; -------------------------------------------------------------------------------- ; @Title: IMX8M On-Chip Peripherals ; @Props: Released ; @Author: FSU, BCA ; @Changelog: 2018-09-20 PCC ; @Manufacturer: NXP Semiconductors ; @Doc:IMX8MDQLQRM_rev0.pdf (Rev. 0, 01/2018) ; @Core: Cortex-A53, Cortex-M4F ; @Chip: IMX8MQ, IMX8MQ-CM4 ; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perimx8m.per 17736 2024-04-08 09:26:07Z kwisniewski $ ; Known problems: ; MODULE REGISTER DESCRIPTION ; HDMI TX ALL Missing information about base address of this registers ; PCIe_PHY ALL Missing base addresses for PCIE_PHY_CMN and PCIE_PHY_TRSV ; NOC ALL Missing information in specification ; TMU TSR[MSITE] Conflict informations ; Pipe 3 ALL Specification couldn't be found width 0x0b sif CORENAME()=="CORTEXM4F" tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end elif CORENAME()=="CORTEXA53" tree "Core Registers (Cortex-A53)" AUTOINDENT.PUSH AUTOINDENT.ON center tree tree.open "AArch64" tree "ID Registers" rgroup.quad spr:0x30000++0x0 line.long 0x0 "MIDR_EL1,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code" bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. "ARCH,Architecture" "Reserved,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme" newline hexmask.long.word 0x0 4.--15. 0x1 "PART,Primary Part Number" bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x30005++0x00 line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register" bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" newline hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" bitfld.quad 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4" elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30005++0x00 line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity level 3. Third highest level affinity field" newline bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" newline hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" endif rgroup.quad SPR:0x30006++0x0 line.long 0x0 "REVIDR_EL1,Revision ID Register" rgroup.quad SPR:0x30014++0x00 line.long 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30015++0x00 line.long 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.quad SPR:0x30016++0x00 line.long 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.quad SPR:0x30017++0x00 line.long 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,Reserved,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.quad spr:0x30026++0x00 line.long 0x00 "ID_MMFR4_EL1,Memory Model Feature Register 4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..." endif if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30071++0x00 line.quad 0x00 "ID_AA64MMFR1_EL1,AArch64 Memory Model Feature Register 1" endif rgroup.quad SPR:0x30020++0x00 line.long 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.quad SPR:0x30021++0x00 line.long 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30022++0x00 line.long 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30023++0x00 line.long 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30024++0x00 line.long 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30025++0x00 line.long 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30060++0x00 line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0" bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions are implemented" "Not implemented,Implemented,?..." bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions are implemented" "Not implemented,Implemented,?..." newline bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..." if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30061++0x00 line.quad 0x00 "ID_AA64ISAR1_EL1,AArch64 Instruction Set Attribute Register 1" endif rgroup.quad SPR:0x30010++0x00 line.long 0x00 "ID_PFR0_EL1,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30011++0x00 line.long 0x00 "ID_PFR1_EL1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,?..." bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,?..." newline bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." newline bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." newline bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." endif if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30041++0x00 line.quad 0x00 "ID_AA64PFR1_EL1,AArch64 Processor Feature Register 1" endif if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x30012++0x00 line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x30012++0x00 line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif rgroup.quad spr:0x30050++0x00 line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0" bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..." bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..." bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." newline bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,Implemented,?..." bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..." bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented,?..." if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30051++0x00 line.quad 0x00 "ID_AA64DFR1_EL1,AArch64 Debug Feature Register 1" rgroup.quad spr:0x30054++0x00 line.quad 0x00 "ID_AA64AFR0_EL1,AArch64 Auxiliary Feature Register 0" rgroup.quad spr:0x30055++0x00 line.quad 0x00 "ID_AA64AFR1_EL1,AArch64 Auxiliary Feature Register 1" endif rgroup.quad SPR:0x30013++0x00 line.long 0x00 "ID_AFR0_EL1,Auxiliary Feature Register 0" rgroup.quad SPR:0x31007++0x00 line.long 0x00 "AIDR_EL1,Auxiliary ID Register" rgroup.quad SPR:0x33007++0x00 line.long 0x00 "DCZID_EL0,Data Cache Zero ID" bitfld.long 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited" bitfld.long 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." tree.end tree "System Control and Configuration" group.quad spr:0x36111++0x00 line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register" bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled" bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled" group.quad SPR:0x30100++0x0 line.long 0x00 "SCTLR_EL1,System Control Register (EL1)" bitfld.long 0x0 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.long 0x0 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.long 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad SPR:0x34100++0x0 line.long 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad SPR:0x36100++0x0 line.long 0x00 "SCTLR_EL3,System Control Register (EL3)" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" rgroup.quad SPR:0x30101++0x0 line.long 0x00 "ACTLR_EL1,Auxiliary Control Register (EL1)" group.quad SPR:0x34101++0x0 line.long 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad SPR:0x36101++0x0 line.long 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad SPR:0x30102++0x00 line.long 0x00 "CPACR_EL1,Architectural Feature Access Control Register" bitfld.long 0x00 28. "TTA,Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1" "Disabled,?..." bitfld.long 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap all,Trap El0,Trap all,Not trapped" group.quad SPR:0x36110++0x0 line.long 0x0 "SCR_EL3,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.long 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled" bitfld.long 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes" newline bitfld.long 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.long 0x00 0. "NS,Secure mode" "Secure,Non-secure" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.quad spr:0x30510++0x00 line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)" group.quad spr:0x30511++0x00 line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)" group.quad spr:0x34510++0x00 line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)" group.quad spr:0x34511++0x00 line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)" group.quad spr:0x36510++0x00 line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)" group.quad spr:0x36511++0x00 line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)" tree.open "Exception Syndrome Registers" if (CORENAME()=="CORTEXA57") if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined" elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif elif (CORENAME()=="CORTEXA53") if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SES,System Error Source" "Processor,System,External," newline hexmask.long.tbyte 0x00 0.--21. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined" elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif endif tree.end newline if (CORENAME()=="CORTEXA57") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif (CORENAME()=="CORTEXA53") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" group.quad spr:0x30C00++0x00 line.quad 0x00 "VBAR_EL1,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" group.quad spr:0x34C00++0x00 line.quad 0x00 "VBAR_EL2,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" group.quad spr:0x36C00++0x00 line.quad 0x00 "VBAR_EL3,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" rgroup.quad spr:0x36C01++0x00 line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register" hexmask.quad 0x00 2.--43. 0x4 "RVBA,Reset Vector Base Address" rgroup.quad SPR:0x30C10++0x00 line.long 0x00 "ISR_EL1,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.quad SPR:0x36C02++0x00 line.long 0x00 "RMR_EL3,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]" elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.tbyte 0x00 18.--39. 1. "PERIPHBASE[39:18],Periphbase[39:18]" endif group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Software Thread ID Register" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Software Thread ID Register" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Software Thread ID Register" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Software Thread ID Register" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Software Thread ID Register" tree.end tree "Memory Management Unit" group.quad spr:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)" bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x30200++0x00 line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x30201++0x00 line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KByte,64 KByte" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB" newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,Reserved,4 KB,64 KB" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 7. "EPD0,Translation table walk disable for translations using TTBR0" "Enabled,Disabled" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x34200++0x00 line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 14. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x36200++0x00 line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 14. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad SPR:0x34300++0x00 line.long 0x00 "DACR32_EL2,Domain Access Control Register" bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (CORENAME()=="CORTEXA57") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif (CORENAME()=="CORTEXA53") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif rgroup.quad SPR:0x30510++0x00 line.long 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)" rgroup.quad SPR:0x34510++0x00 line.long 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)" rgroup.quad SPR:0x36510++0x00 line.long 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)" rgroup.quad SPR:0x30511++0x00 line.long 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)" rgroup.quad SPR:0x34511++0x00 line.long 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)" rgroup.quad SPR:0x36511++0x00 line.long 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)" if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-not nGnRnE,?..." newline hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif (((per.q(spr:0x30740))&0x01)==0x00) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" newline hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" newline bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Reserved,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" group.quad spr:0x30A20++0x00 line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" group.quad spr:0x34A20++0x00 line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" group.quad spr:0x36A20++0x00 line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" rgroup.quad spr:0x30A30++0x00 line.quad 0x00 "AMAIR_EL1,Memory Attribute Indirection Register (EL1)" rgroup.quad spr:0x34A30++0x00 line.quad 0x00 "AMAIR_EL2,Memory Attribute Indirection Register (EL2)" rgroup.quad spr:0x36A30++0x00 line.quad 0x00 "AMAIR_EL3,Memory Attribute Indirection Register (EL3)" tree.end newline group.quad SPR:0x30D01++0x00 line.long 0x0 "CONTEXTIDR_EL1,Context ID Register" tree.end tree "Virtualization Extensions" group.quad SPR:0x34000++0x0 line.long 0x0 "VPIDR_EL2,Virtualization Processor ID Register" if (CORENAME()=="CORTEXA57") group.quad spr:0x34005++0x00 line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" hexmask.quad.long 0x00 0.--31. 1. "VMPIDR_EL2,MPIDR value returned by Non-secure EL1 reads of the MPIDR_EL1" elif (CORENAME()=="CORTEXA53") group.quad spr:0x34005++0x00 line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" endif group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" if (CORENAME()=="CORTEXA57") group.quad SPR:0x34111++0x00 line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x34111++0x00 line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6" endif group.quad SPR:0x34112++0x00 line.long 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad SPR:0x36131++0x00 line.long 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" newline bitfld.long 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes" bitfld.long 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" group.quad SPR:0x36112++0x00 line.long 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad SPR:0x34113++0x00 line.long 0x00 "HSTR_EL2,Hypervisor System Trap Register" bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Not supported,?..." bitfld.long 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped" bitfld.long 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped" newline bitfld.long 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped" bitfld.long 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped" bitfld.long 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped" newline bitfld.long 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped" bitfld.long 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped" bitfld.long 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped" newline bitfld.long 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped" bitfld.long 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped" bitfld.long 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped" newline bitfld.long 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped" bitfld.long 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped" bitfld.long 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped" rgroup.quad SPR:0x34117++0x00 line.long 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register" group.quad spr:0x34210++0x00 line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad SPR:0x34212++0x00 line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..." bitfld.long 0x00 14. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x34212++0x00 line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,?..." bitfld.long 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,?..." bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting IPA bits" tree.end tree "Cache Control and Configuration" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif group.quad SPR:0x32000++0x0 line.long 0x0 "CSSELR_EL1,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x31001++0x0 line.long 0x0 "CLIDR_EL1,Cache Level ID Register" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." newline bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." rgroup.quad SPR:0x31000++0x0 line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..." bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. "RA,Read-Allocate" "Reserved,Supported" newline bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x31001++0x0 line.long 0x0 "CLIDR_EL1,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." rgroup.quad SPR:0x31000++0x0 line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..." bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" newline bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "1Reserved,Reserved,64 bytes,?..." endif tree "Level 1 memory system" if (CORENAME()=="CORTEXA57") group.quad SPR:0x30F10++0x00 line.long 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register" group.quad SPR:0x30F11++0x00 line.long 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register" group.quad SPR:0x30F12++0x00 line.long 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register" group.quad SPR:0x30F13++0x00 line.long 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register" group.quad SPR:0x30F00++0x00 line.long 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register" group.quad SPR:0x30F01++0x00 line.long 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register" group.quad SPR:0x30F02++0x00 line.long 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register" group.quad SPR:0x30F03++0x00 line.long 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register" group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" newline bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled" bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" newline bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" newline bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes" bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" newline bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" newline bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" newline bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" newline bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" newline bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" newline bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines" newline bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..." bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..." elif (CORENAME()=="CORTEXA53") group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 44. "ENDCCASCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes" bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" newline bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes" newline bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes" bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes" bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes" newline bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams" bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled" bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled" newline bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8" bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes" bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache data RAM error injection enable" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" endif if (CORENAME()=="CORTEXA57") group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address" elif (CORENAME()=="CORTEXA53") group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address" endif tree.end tree "Level 2 memory system" if (CORENAME()=="CORTEXA57") group.quad SPR:0x31B02++0x0 line.long 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes" bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" newline bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" bitfld.long 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled" rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not presented,Presented" newline rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not presented,Presented" rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not presented,1,2,?..." bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" newline bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" group.quad SPR:0x31B03++0x0 line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad SPR:0x31F00++0x00 line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" newline bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes" bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled" bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" newline bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" newline bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" newline bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" newline bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x31B02++0x0 line.long 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" newline rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles" group.quad SPR:0x31B03++0x0 line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad SPR:0x31F00++0x00 line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.long 0x00 30.--31. "L2VC,L2 Victim Control" "0,1,2,3" bitfld.long 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled" bitfld.long 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable." "Disabled,Enabled" newline bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address" endif tree.end tree.end tree "System Performance Monitor" group.quad SPR:0x339C0++0x00 line.long 0x0 "PMCR_EL0,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" group.quad SPR:0x339C1++0x00 line.long 0x00 "PMCNTENSET_EL0,Count Enable Set Register" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled" bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled" bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled" bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled" bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled" bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled" bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled" bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled" bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled" bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled" bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled" bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled" bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled" bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled" bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled" bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled" bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled" bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled" bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled" bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.quad SPR:0x339C2++0x00 line.long 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Event Counter 29 clear bit" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Event Counter 28 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 27. "P27,Event Counter 27 clear bit" "Disabled,Enabled" eventfld.long 0x00 26. "P26,Event Counter 26 clear bit" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Event Counter 25 clear bit" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Event Counter 24 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 23. "P23,Event Counter 23 clear bit" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Event Counter 22 clear bit" "Disabled,Enabled" eventfld.long 0x00 21. "P21,Event Counter 21 clear bit" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Event Counter 20 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 19. "P19,Event Counter 19 clear bit" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Event Counter 18 clear bit" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Event Counter 17 clear bit" "Disabled,Enabled" eventfld.long 0x00 16. "P16,Event Counter 16 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled" eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled" group.quad SPR:0x339C3++0x00 line.long 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register" bitfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" eventfld.long 0x00 30. "P30,Event Counter 30 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Event Counter 29 clear bit" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Event Counter 28 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 27. "P27,Event Counter 27 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 26. "P26,Event Counter 26 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Event Counter 25 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Event Counter 24 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 23. "P23,Event Counter 23 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Event Counter 22 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 21. "P21,Event Counter 21 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Event Counter 20 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 19. "P19,Event Counter 19 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Event Counter 18 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Event Counter 17 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 16. "P16,Event Counter 16 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 15. "P15,Event Counter 15 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Event Counter 14 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Event Counter 13 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Event Counter 12 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Event Counter 11 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Event Counter 10 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Event Counter 9 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Event Counter 8 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 7. "P7,Event Counter 7 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 6. "P6,Event Counter 6 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,Event Counter 3 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Event Counter 2 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Event Counter 1 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 overflow clear bit" "Disabled,Enabled" wgroup.quad SPR:0x339C4++0x00 line.long 0x00 "PMSWINC_EL0,Performance Monitor Software Increment" bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment" bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment" bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment" bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment" newline bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment" bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment" bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment" bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment" newline bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment" bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment" bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment" bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment" newline bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment" bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment" bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment" bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment" newline bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment" bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment" bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment" bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment" newline bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment" bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment" bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment" bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment" newline bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment" bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment" newline bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment" bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment" group.quad SPR:0x339C5++0x00 line.long 0x00 "PMSELR_EL0,Performance Monitor Select Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.open "Common Event Identification Registers" if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x339C6++0x0 line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" newline bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" newline bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" newline bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" newline bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" newline bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" newline bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x339C6++0x0 line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" newline bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" newline bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" newline bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" newline bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" newline bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" newline bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" newline bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" newline bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" newline bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" endif rgroup.quad SPR:0x339C7++0x0 line.long 0x00 "PMCEID1_EL0,Common Event Identification Register 1" bitfld.long 0x00 0. "EVENT32,Level 2 cache allocate" "Not implemented,Implemented" tree.end newline group.quad spr:0x339D0++0x00 line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register" group.quad SPR:0x339D1++0x00 line.long 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register" group.quad SPR:0x339D2++0x00 line.long 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register" group.quad SPR:0x339E0++0x00 line.long 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.quad SPR:0x309E1++0x00 line.long 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled" bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.quad SPR:0x309E2++0x00 line.long 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled" group.quad SPR:0x339E3++0x00 line.long 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register" group.quad SPR:(0x33E80+0x0)++0x00 line.long 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" group.quad SPR:(0x33EC0+0x0)++0x00 line.long 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x1)++0x00 line.long 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" group.quad SPR:(0x33EC0+0x1)++0x00 line.long 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x2)++0x00 line.long 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" group.quad SPR:(0x33EC0+0x2)++0x00 line.long 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x3)++0x00 line.long 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" group.quad SPR:(0x33EC0+0x3)++0x00 line.long 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x4)++0x00 line.long 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" group.quad SPR:(0x33EC0+0x4)++0x00 line.long 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x5)++0x00 line.long 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" group.quad SPR:(0x33EC0+0x5)++0x00 line.long 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:0x33EF7++0x00 line.long 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.quad SPR:0x33E00++0x00 line.long 0x00 "CNTFRQ_EL0,Counter Frequency Register" rgroup.quad spr:0x33E01++0x00 line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register" group.quad SPR:0x30E10++0x00 line.long 0x00 "CNTKCTL_EL1,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad SPR:0x33E20++0x00 line.long 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue register" group.quad SPR:0x33E21++0x00 line.long 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad SPR:0x33E30++0x00 line.long 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register" group.quad SPR:0x33E31++0x00 line.long 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E02++0x00 line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register" group.quad spr:0x33E22++0x00 line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register" group.quad spr:0x33E32++0x00 line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register" group.quad spr:0x34E03++0x00 line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register" group.quad SPR:0x34E10++0x00 line.long 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad SPR:0x34E20++0x00 line.long 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register" group.quad SPR:0x34E21++0x00 line.long 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x34E22++0x00 line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register" group.quad SPR:0x37E20++0x00 line.long 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register" group.quad SPR:0x37E21++0x00 line.long 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x37E22++0x00 line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch64 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.quad spr:0x30C84++0x00 line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x30C90++0x00 line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline if (((per.q(spr:0x30CB6))&0x10000000000)==0x00) wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad spr:0x30C83++0x00 line.quad 0x00 "ICC_BPR0_EL1,Interrupt Controller Binary Point Register 0" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.quad spr:0x30CC3++0x00 line.quad 0x00 "ICC_BPR1_EL1,Interrupt Controller Binary Point Register 1" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" group.quad spr:0x30CC4++0x00 line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Zero,Non-zero" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Controls whether the priority mask Register is used as a hint for interrupt distribution" "Disabled,Enabled" bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CBPR,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 interrupts" "Separate registers,Same Register" group.quad spr:0x36CC4++0x00 line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)" rbitfld.quad 0x00 19. "ExtRange,Extended INTID range" "Not supported,Supported" rbitfld.quad 0x00 18. "RSS,Range Selector Support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled" newline bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same Register" bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same Register" if (((per.q(spr:0x30CC4))&0x3800)==0x00) wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" elif (((per.q(spr:0x30CC4))&0x3800)==0x800) wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" endif hgroup.quad spr:0x30C80++0x00 hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0" in hgroup.quad spr:0x30CC0++0x00 hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1" in newline group.quad SPR:0x30CC6++0x00 line.long 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad SPR:0x30CC7++0x00 line.long 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)" bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad SPR:0x36CC7++0x00 line.long 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)" bitfld.long 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled" group.quad SPR:0x30460++0x00 line.long 0x00 "ICC_PMR_EL1,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.quad SPR:0x30CB3++0x00 line.long 0x00 "ICC_RPR_EL1,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" if (((per.q(spr:0x30CB7))&0x10000000000)==0x00) wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated." else wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif if (((per.q(spr:0x30CB5))&0x10000000000)==0x00) wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad SPR:0x30CC5++0x00 line.long 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad SPR:0x34C95++0x00 line.long 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad SPR:0x36CC5++0x00 line.long 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" tree.end tree "AArch64 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.quad SPR:0x34C80++0x00 line.long 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" if (CORENAME()=="CORTEXA53") group.quad SPR:0x34C90++0x00 line.long 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" endif tree.end newline rgroup.quad SPR:0x34CB3++0x00 line.long 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.quad SPR:0x34CB5++0x00 line.long 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.quad SPR:0x34CB0++0x00 line.long 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" if (((d.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif rgroup.quad SPR:0x34CB2++0x00 line.long 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.quad SPR:0x34CB7++0x00 line.long 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.quad SPR:0x34C94++0x00 line.long 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register" rgroup.quad SPR:0x34CB1++0x00 line.long 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" rgroup.quad SPR:0x23010++0x00 line.long 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" group.quad SPR:0x20020++0x00 line.long 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register" bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled" group.quad spr:0x23040++0x00 line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register" rgroup.quad SPR:0x23050++0x00 line.long 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register" wgroup.quad SPR:0x23050++0x00 line.long 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register" group.quad SPR:0x24070++0x00 line.long 0x00 "DBGVCR32_EL2,Vector Catch Register" bitfld.long 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Low,High" newline bitfld.long 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 7. "SF,FIQ vector catch enable in Secure state" "Low,High" bitfld.long 0x00 6. "SI,IRQ vector catch enable in Secure state" "Low,High" newline bitfld.long 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Low,High" bitfld.long 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Low,High" bitfld.long 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Low,High" bitfld.long 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Low,High" group.quad SPR:0x20002++0x00 line.long 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register" group.quad SPR:0x20022++0x00 line.long 0x00 "MDSCR_EL1,Monitor Debug System Control Register" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,Save/restore bit" "Low,High" bitfld.long 0x00 26. "TXU,Save/restore bit" "Low,High" newline bitfld.long 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3" bitfld.long 0x00 21. "TDA,Save/restore bit" "Low,High" bitfld.long 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" bitfld.long 0x00 14. "HDE,Save/restore bit" "Low,High" newline bitfld.long 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.long 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled" bitfld.long 0x00 6. "ERR,Save/restore bit" "Low,High" bitfld.long 0x00 0. "SS,Software step control" "Disabled,Enabled" group.quad SPR:0x20032++0x00 line.long 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register" group.quad SPR:0x20062++0x00 line.long 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register" rgroup.quad spr:0x20100++0x00 line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register" hexmask.quad 0x00 12.--47. 0x1000 "ROMADDR,ROM base physical address" bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid" wgroup.quad SPR:0x20104++0x00 line.long 0x00 "OSLAR_EL1,OS Lock Access Register" bitfld.long 0x00 0. "OSLK,OS lock" "Unlock,Lock" rgroup.quad SPR:0x20114++0x00 line.long 0x00 "OSLSR_EL1,OS Lock Status Register" bitfld.long 0x00 2. "NTT,Not 32-bit access" "Low,High" bitfld.long 0x00 1. "OSLK,OS lock status" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Impelemented,?..." group.quad SPR:0x20134++0x00 line.long 0x00 "OSDLR_EL1,OS Double-lock Register" bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.quad SPR:0x20144++0x00 line.long 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes" group.quad SPR:0x20786++0x00 line.long 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set" bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" newline bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.quad SPR:0x20796++0x00 line.long 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear" bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.quad SPR:0x207E6++0x00 line.long 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" group.quad SPR:0x33450++0x00 line.long 0x00 "DSPSR_EL0,Debug Saved Processor Status Register" group.quad spr:0x33451++0x00 line.quad 0x00 "DLR_EL0,Debug Link Register" tree.end tree "Breakpoint Registers" if (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x0)++0x0 line.long 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x10)++0x0 line.long 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x20)++0x0 line.long 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x30)++0x0 line.long 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x40)++0x0 line.long 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x50)++0x0 line.long 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group.quad spr:(0x20006+0x0)++0x00 "Watchpoint 0" line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x10)++0x00 "Watchpoint 1" line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x20)++0x00 "Watchpoint 2" line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x30)++0x00 "Watchpoint 3" line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree.end tree.open "AArch32" tree "ID Registers" rgroup.long c15:0x0000++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code" bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8" newline hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number" bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (CORENAME()=="CORTEXA57") rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif if corename()=="CORTEXA57" rgroup.long c15:0x0300++0x0 line.long 0x0 "TLBTR,TLB Type Register" endif if corename()=="CORTEXA57" rgroup.long c15:0x0500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline bitfld.long 0x00 0.--1. "CPUID,Indicates the core number in the device" "1,2,3,4" elif corename()=="CORTEXA53" rgroup.long c15:0x0500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,?..." hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" endif rgroup.long c15:0x0600++0x0 line.long 0x0 "REVIDR,Revision ID Register" rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.long c15:0x0620++0x00 line.long 0x00 "ID_MMFR4,ID_MMFR4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." newline bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." if corename()=="CORTEXA57" rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." elif corename()=="CORTEXA53" rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif group.long c15:0x0310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" if corename()=="CORTEXA57" rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" newline bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" newline bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" newline bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" newline bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" rgroup.long c15:0x7C9++0x0 line.long 0x00 "PMCEID1,Common Event Identification Register 1" elif corename()=="CORTEXA53" rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" newline bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" newline bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" newline bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" newline bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" rgroup.long c15:0x7C9++0x0 line.long 0x00 "PMCEID1,Common Event Identification Register 1" bitfld.long 0x00 0. "EVENT32,L2D Cache Allocate" "Not implemented,Implemented" endif group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" tree.end tree "System Control and Configuration" if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,System Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" else group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" endif group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" newline bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled" newline bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" newline bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" newline bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes" newline bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" newline bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" newline bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" newline bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" newline bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" newline bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" newline bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" newline bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" newline bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" newline bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" newline bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" newline bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" newline bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" newline bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address" group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" elif corename()=="CORTEXA53" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes" bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" newline bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" newline bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes" bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes" newline bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes" bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes" newline bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams" bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled" newline bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled" bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address" group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" endif if corename()=="CORTEXA57" group.long c15:0x0201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 28. "TRCDIS,Disable CP14 access to trace registers" "No,Yes" newline bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full" bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full" elif corename()=="CORTEXA53" group.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 only,Reserved,Full" newline bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 only,Reserved,Full" endif group.long c15:0x0011++0x0 line.long 0x00 "SCR,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes" newline bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" newline bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0131++0x00 line.long 0x00 "SDCR,Secure Debug Control Register" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" newline bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" newline bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" if corename()=="CORTEXA57" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" elif corename()=="CORTEXA53" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" endif rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.long c15:0x020C++0x00 line.long 0x00 "RMR,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64" group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" group.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Async. external,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Async. parity/on memory access,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/1st level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/1st level,Permission/1nd level,Sync. external/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..." endif elif corename()=="CORTEXA53" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX/STREX,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/section,Instruction cache maintenance,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/1st level,Permission/section,Sync. external/2nd level,Permission/2nd level,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..." endif endif if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif corename()=="CORTEXA53" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" if corename()=="CORTEXA57" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[42:32],Periphbase[42:32]" elif corename()=="CORTEXA53" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.byte 0x00 0.--7. 1. "PERIPHBASE[39:32],Periphbase[39:32]" endif group.long c15:0x000D++0x00 line.long 0x00 "FCSEIDR,FCSE Process ID register" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register" tree.end tree "Memory Management Unit" if corename()=="CORTEXA57" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" if (((per.l(c15:0x0202))&0x80000000)==0x00000000) // MPIDR[31]==1 case is missing here for TTBR0 and TTBR1 group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. "IMP,Implementation" "Low,High" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTBA,Translation table base address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. "IMP,Implementation" "Low,High" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" else group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" endif if (((per.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" else group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" endif elif corename()=="CORTEXA53" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Register 0" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Register 1" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" else group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base 0 address" bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base 1 address" bitfld.long 0x00 0. 6. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" endif endif if corename()=="CORTEXA57" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" elif corename()=="CORTEXA53" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" else group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" endif tree.open "Memory Attribute Indirection Registers" group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x003A++0x00 line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x013A++0x00 line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 19. "NS1,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" bitfld.long 0x00 18. "NS0,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" newline bitfld.long 0x00 17. "DS1,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. "DS0,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" newline bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline endif tree.end newline if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" else group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier" hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier" endif tree.end tree "Virtualization Extensions" group.long c15:0x4000++0x0 line.long 0x00 "VPIDR,Virtualization Processor ID Register" group.long c15:0x4500++0x00 line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" group.long c15:0x4101++0x00 line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" if corename()=="CORTEXA57" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" newline bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" newline bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" newline bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" newline bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" newline bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" newline bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" newline bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" newline bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3" newline bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted" newline bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed" newline bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" elif corename()=="CORTEXA53" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" newline bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" newline bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" newline bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" newline bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" newline bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3" bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" newline bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "No aborted,Aborted" bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 5. "AMO,A-bit Mask Override" "No override,Override" newline bitfld.long 0x00 4. "IMO,I-bit Mask Override" "No override,Override" bitfld.long 0x00 3. "FMO,F-bit Mask Override" "No override,Override" newline bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" newline bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" endif group.long c15:0x4411++0x00 line.long 0x00 "HCR2,Hypervisor Configuration Register 2" bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hypervisor Debug Control Register" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" newline bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 20. "TTA,Trap Trace Access" "Not trapped,?..." newline bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped" bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped" newline bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hypervisor System Trap Register" bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Disabled,Enabled" bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "Reserved,?..." newline hexmask.long.word 0x00 5.--13. 1. "T4_15,Trap to Hypervisor mode Non-secure priv 5 - 13" bitfld.long 0x00 0.--3. "T0_13,Trap to Hypervisor mode Non-secure priv 0 - 3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4711++0x00 line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register" if corename()=="CORTEXA57" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" elif corename()=="CORTEXA53" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High" bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4015++0x00 line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register" group.long c15:0x4115++0x00 line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Syndrome Register" group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register" group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to c15,Trapped MCRR/MRRC to c15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,Reserved,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome" group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address" tree.open "Hypervisor Memory Attribute Indirection Registers" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" tree.end newline group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address" tree.end tree "Cache Control and Configuration" rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,PIPT" newline bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." if corename()=="CORTEXA57" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." newline bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." elif corename()=="CORTEXA53" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." endif rgroup.long c15:0x1700++0x0 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" newline bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" newline hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "16 bytes,32 bytes,64 bytes,128 bytes,?..." group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" tree "Level 1 memory system" if corename()=="CORTEXA57" group.long c15:0x001F++0x00 line.long 0x00 "DL1DATA0,Data L1 Data 0 Register" group.long c15:0x011F++0x00 line.long 0x00 "DL1DATA1,Data L1 Data 1 Register" group.long c15:0x021F++0x00 line.long 0x00 "DL1DATA2,Data L1 Data 2 Register" group.long c15:0x031F++0x00 line.long 0x00 "DL1DATA3,Data L1 Data 3 Register" group.long c15:0x000F++0x00 line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register" group.long c15:0x010F++0x00 line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register" group.long c15:0x020F++0x00 line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register" group.long c15:0x030F++0x00 line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register" wgroup.long c15:0x04F++0x00 line.long 0x00 "RAMINDEX,RAM Index Operation Register" elif corename()=="CORTEXA53" rgroup.long c15:0x300F++0x00 line.long 0x00 "CDBGDR0,Cache Debug Data Register 0" rgroup.long c15:0x310F++0x00 line.long 0x00 "CDBGDR1,Cache Debug Data Register 1" rgroup.long c15:0x320F++0x00 line.long 0x00 "CDBGDR2,Cache Debug Data Register 2" rgroup.long c15:0x330F++0x00 line.long 0x00 "CDBGDR3,Cache Debug Data Register 3" wgroup.long c15:0x302F++0x00 line.long 0x00 "CDBGDCT,Cache Debug Data Cache Tag Read Operation Register" wgroup.long c15:0x312F++0x00 line.long 0x00 "CDBGICT,Cache Debug Instruction Cache Tag Read Operation Register" wgroup.long c15:0x304F++0x00 line.long 0x00 "CDBGDCD,Cache Debug Cache Debug Data Cache Data Read Operation Register" wgroup.long c15:0x314F++0x00 line.long 0x00 "CDBGICD,Cache Debug Instruction Cache Data Read Operation Register" wgroup.long c15:0x324F++0x00 line.long 0x00 "CDBGTD,Cache Debug TLB Data Read Operation Register" endif tree.end tree "Level 2 memory system" if corename()=="CORTEXA57" group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes" bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4" newline rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Not supported,Supported" bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" newline bitfld.long 0x00 20. "DIECCE,Data in-line ECC enable" "Disabled,Enabled" rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present" newline rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present" rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1,2,Present" newline bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" newline rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle" bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" newline bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" newline bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" newline bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes" bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled" bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" newline bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" newline bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" newline bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" newline bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" newline bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" newline bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" newline bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad c15:0x130F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" elif corename()=="CORTEXA53" group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4" bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" newline rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" newline rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles" group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" newline bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" group.quad c15:0x110F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address" endif tree.end tree.end tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" newline group.long c15:0x1c9++0x00 line.long 0x00 "PMNCNTENSET,Count Enable Set Register " bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled" bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled" bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled" bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled" bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled" bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled" bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled" bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled" bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled" bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled" bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled" bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled" bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled" bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled" bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled" bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled" bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled" bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled" bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled" bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled" bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Event Counter 29 clear bit " "Disabled,Enabled" eventfld.long 0x00 28. "P28,Event Counter 28 clear bit " "Disabled,Enabled" eventfld.long 0x00 27. "P27,Event Counter 27 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 26. "P26,Event Counter 26 clear bit " "Disabled,Enabled" eventfld.long 0x00 25. "P25,Event Counter 25 clear bit " "Disabled,Enabled" eventfld.long 0x00 24. "P24,Event Counter 24 clear bit " "Disabled,Enabled" eventfld.long 0x00 23. "P23,Event Counter 23 clear bit " "Disabled,Enabled" eventfld.long 0x00 22. "P22,Event Counter 22 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 21. "P21,Event Counter 21 clear bit " "Disabled,Enabled" eventfld.long 0x00 20. "P20,Event Counter 20 clear bit " "Disabled,Enabled" eventfld.long 0x00 19. "P19,Event Counter 19 clear bit " "Disabled,Enabled" eventfld.long 0x00 18. "P18,Event Counter 18 clear bit " "Disabled,Enabled" eventfld.long 0x00 17. "P17,Event Counter 17 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 16. "P16,Event Counter 16 clear bit " "Disabled,Enabled" eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled" eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled" eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register" eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" eventfld.long 0x00 30. "P30,PMN30 overflow" "No overflow,Overflow" eventfld.long 0x00 29. "P29,PMN29 overflow" "No overflow,Overflow" eventfld.long 0x00 28. "P28,PMN28 overflow" "No overflow,Overflow" eventfld.long 0x00 27. "P27,PMN27 overflow" "No overflow,Overflow" newline eventfld.long 0x00 26. "P26,PMN26 overflow" "No overflow,Overflow" eventfld.long 0x00 25. "P25,PMN25 overflow" "No overflow,Overflow" eventfld.long 0x00 24. "P24,PMN24 overflow" "No overflow,Overflow" eventfld.long 0x00 23. "P23,PMN23 overflow" "No overflow,Overflow" eventfld.long 0x00 22. "P22,PMN22 overflow" "No overflow,Overflow" newline eventfld.long 0x00 21. "P21,PMN21 overflow" "No overflow,Overflow" eventfld.long 0x00 20. "P20,PMN20 overflow" "No overflow,Overflow" eventfld.long 0x00 19. "P19,PMN19 overflow" "No overflow,Overflow" eventfld.long 0x00 18. "P18,PMN18 overflow" "No overflow,Overflow" eventfld.long 0x00 17. "P17,PMN17 overflow" "No overflow,Overflow" newline eventfld.long 0x00 16. "P16,PMN16 overflow" "No overflow,Overflow" eventfld.long 0x00 15. "P15,PMN15 overflow" "No overflow,Overflow" eventfld.long 0x00 14. "P14,PMN14 overflow" "No overflow,Overflow" eventfld.long 0x00 13. "P13,PMN13 overflow" "No overflow,Overflow" eventfld.long 0x00 12. "P12,PMN12 overflow" "No overflow,Overflow" newline eventfld.long 0x00 11. "P11,PMN11 overflow" "No overflow,Overflow" eventfld.long 0x00 10. "P10,PMN10 overflow" "No overflow,Overflow" eventfld.long 0x00 9. "P9,PMN9 overflow" "No overflow,Overflow" eventfld.long 0x00 8. "P8,PMN8 overflow" "No overflow,Overflow" eventfld.long 0x00 7. "P7,PMN7 overflow" "No overflow,Overflow" newline eventfld.long 0x00 6. "P6,PMN6 overflow" "No overflow,Overflow" eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow" eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow" eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow" newline eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x00 "PMSWINC,Performance Monitor Software Increment" bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment" bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment" bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment" bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment" bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment" newline bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment" bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment" bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment" bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment" bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment" newline bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment" bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment" bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment" bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment" bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment" newline bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment" bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment" bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment" bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment" bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment" newline bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment" bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment" bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment" bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment" bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment" newline bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment" bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment" newline bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Monitor Select Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" group.long c15:0x1d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" group.long c15:0x2d9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled" group.long c15:0x3e9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" group.long c15:0x8E++0x00 line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0" group.long c15:(0x8E+0x40)++0x00 line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x18E++0x00 line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1" group.long c15:(0x18E+0x40)++0x00 line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x28E++0x00 line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2" group.long c15:(0x28E+0x40)++0x00 line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x38E++0x00 line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3" group.long c15:(0x38E+0x40)++0x00 line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x48E++0x00 line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4" group.long c15:(0x48E+0x40)++0x00 line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x58E++0x00 line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5" group.long c15:(0x58E+0x40)++0x00 line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x07FE++0x00 line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" rgroup.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch32 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:0x048C++0x00 line.long 0x00 "ICC_AP0R0,Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x009C++0x00 line.long 0x00 "ICC_AP1R0,Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "SGIID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x038C++0x00 line.long 0x00 "ICC_BPR0,Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x03CC++0x00 line.long 0x00 "ICC_BPR1,Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x04CC++0x00 line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported" rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" newline bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1" group.long c15:0x64CC++0x00 line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3" rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled" bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled" bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled" newline bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register" bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register" if (((per.l(c15:0x4CC))&0x3800)==0x00) wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" elif (((per.l(c15:0x4CC))&0x3800)==0x800) wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" endif hgroup.long c15:0x008C++0x00 hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0" in hgroup.long c15:0x00CC++0x00 hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1" in group.long c15:0x06CC++0x00 line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x07CC++0x00 line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICC_PMR,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" wgroup.quad c15:0x120C0++0x01 line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" wgroup.quad c15:0x100C0++0x01 line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x05CC++0x00 line.long 0x00 "ICC_SRE,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" if corename()=="CORTEXA53" group.long c15:0x459C++0x00 line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" endif group.long c15:0x65CC++0x00 line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x67CC++0x00 line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable" bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled" tree.end tree "AArch32 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.long c15:0x408C++0x00 line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x409C++0x00 line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline rgroup.long c15:0x43BC++0x00 line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.long c15:0x45BC++0x00 line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" group.long c15:(0x40CC+0x0)++0x00 line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x100)++0x00 line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x200)++0x00 line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x300)++0x00 line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" rgroup.long c15:0x42BC++0x00 line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.long c15:0x459C++0x00 line.long 0x00 "ICH_SRE,Hypervisor System Register" group.long c15:0x47BC++0x00 line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.long c15:0x449C++0x00 line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register" rgroup.long c15:0x41BC++0x00 line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" tree "Coresight Management Registers" if corename()=="CORTEXA57" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version" bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented" elif corename()=="CORTEXA53" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version" bitfld.long 0x0 15. "DEVID,Debug Device ID" "Low,High" bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported" newline bitfld.long 0x0 13. "PCSR,PC Sample register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented" hexmask.long.byte 0x0 4.--7. 1. "VARIANT,Implementation-defined Variant Number" newline hexmask.long.byte 0x0 0.--3. 1. "REVISION,Implementation-defined Revision Number" endif rgroup.long c14:0x0060++0x0 line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register" group.long c14:0x0070++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" newline bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled" bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled" group.long c14:0x0020++0x00 line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register" bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled" group.long c14:0x0200++0x0 line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)" group.long c14:0x0220++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled" newline bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled" bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled" newline bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." rgroup.long c14:0x0010++0x0 line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." wgroup.long c14:0x0230++0x0 line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)" group.long c14:0x0050++0x0 line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)" group.long c14:0x0687++0x0 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.long c14:0x0697++0x0 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.long c14:0x06E7++0x0 line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. "SNDFI,Secure non-invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 6. "SNDE,Secure non-invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 5. "SIDFI,Secure invasive debug features implementation" "No effect,Implemented" newline bitfld.long 0x00 4. "SIDE,Secure invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 3. "NSNDFI,Non-secure non-invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNDE,Non-secure non-invasive debug enable" "0,1" newline bitfld.long 0x00 1. "NSIDFI,Non-secure invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 0. "NSIDE,Non-secure invasive debug enable" "0,1" rgroup.long c14:0x0707++0x0 line.long 0x0 "DBGDEVID2,Debug Device ID Register 2" rgroup.long c14:0x0717++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" "0,1,No offset,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c14:0x0727++0x00 line.long 0x00 "DBGDEVID,Debug Device ID Register 0" bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..." bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" "Not implemented,?..." bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..." newline bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..." bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented" newline bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..." tree.end newline rgroup.quad c14:0x10010++0x1 line.quad 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.quad.word 0x0 32.--47. 0x1 "ROMADDR,ROM physical address" hexmask.quad.tbyte 0x0 12.--31. 0x10 "ROMADDR,ROM physical address" bitfld.quad 0x0 1. "VALID1,ROM table address valid" "Not valid,Valid" newline bitfld.quad 0x0 0. "VALID0,ROM table address valid" "Not valid,Valid" rgroup.quad c14:0x10020++0x1 line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" wgroup.long c14:0x0401++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:0x0411++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required" bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..." if (((per.l(c14:0x0411))&0x2)==0x2) group.long c14:0x0260++0x00 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" else hgroup.long c14:0x0260++0x00 hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" endif group.long c14:0x0431++0x00 line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register" bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked" group.long c14:0x0441++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Low,High" tree.end tree "Breakpoint Registers" if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" line.long 0x00 "DBGBVR0,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" hide.long 0x00 "DBGBVR0,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" line.long 0x00 "DBGBVR0,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x0)++0x0 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" line.long 0x00 "DBGBVR1,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" hide.long 0x00 "DBGBVR1,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" line.long 0x00 "DBGBVR1,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x10)++0x0 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" line.long 0x00 "DBGBVR2,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" hide.long 0x00 "DBGBVR2,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" line.long 0x00 "DBGBVR2,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x20)++0x0 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" line.long 0x00 "DBGBVR3,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" hide.long 0x00 "DBGBVR3,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" line.long 0x00 "DBGBVR3,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x30)++0x0 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" line.long 0x00 "DBGBVR4,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" hide.long 0x00 "DBGBVR4,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" line.long 0x00 "DBGBVR4,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x40)++0x0 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" line.long 0x00 "DBGBVR5,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" hide.long 0x00 "DBGBVR5,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" line.long 0x00 "DBGBVR5,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x50)++0x0 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" group.long c14:0x0141++0x0 line.long 0x00 "DBGBXVR4,Debug Breakpoint Extended Value Register 4" hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value" group.long c14:0x0151++0x0 line.long 0x00 "DBGBXVR5,Debug Breakpoint Extended Value Register 5" hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value" tree.end tree "Watchpoint Control Registers" group.long c14:(0x0600+0x0)++0x00 "Breakpoint 0" line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x10)++0x00 "Breakpoint 1" line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x20)++0x00 "Breakpoint 2" line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x30)++0x00 "Breakpoint 3" line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree.end AUTOINDENT.OFF AUTOINDENT.POP tree.open "Interrupt Controller (GIC-500)" base COMP.BASE("GICD",-1.) width 17. tree "Distributor Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 6. " DS ,Disable Security" "No,Yes" textline " " bitfld.long 0x00 5. " ARE_NS ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_S ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLEGRP1S ,Enable Secure Group 1 interrupts" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1NS ,Enable Secure Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_NS ,Affinity Routing Enable" "Reserved,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1A ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" rbitfld.long 0x00 6. " DS ,Disable Security" "Reserved,Yes" textline " " bitfld.long 0x00 4. " ARE ,Affinity Routing Enable" "Reserved,Enabled" bitfld.long 0x00 1. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 25. " NO1N ,Indicates whether 1 of N SPI interrupts are supported" "Supported,Not supported" bitfld.long 0x00 24. " A3V ,Indicates whether the Distributor supports nonzero values of Affinity level 3" "Not supported,Supported" bitfld.long 0x00 19.--23. " IDBITS ,The number of interrupt identifier bits supported" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." textline " " bitfld.long 0x00 17. " LPIS ,Indicates whether the implementation supports LPIs" "Not supported,Supported" bitfld.long 0x00 16. " MBIS ,Indicates whether the implementation supports message-based interrupts by writing to Distributor registers" "Not supported,Supported" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Reports the number of PEs that can be used when affinity routing is not enabled" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0.--4. " ITLN ,Indicates the maximum SPI INTID that the GIC implementation supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved" rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x10000)==0x10000) wgroup.long 0x40++0x03 line.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" wgroup.long 0x48++0x03 line.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50)) wgroup.long 0x50++0x03 line.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x50++0x03 hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Non-secure access)" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58)) wgroup.long 0x58++0x03 line.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x58++0x03 hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)" endif else hgroup.long 0x40++0x03 hide.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register" hgroup.long 0x48++0x03 hide.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register" hgroup.long 0x50++0x03 hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register" hgroup.long 0x58++0x03 hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register" endif width 17. tree "Group Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0080)) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x0080++0x03 hide.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else hgroup.long 0x0084++0x03 hide.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else hgroup.long 0x0088++0x03 hide.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else hgroup.long 0x008C++0x03 hide.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else hgroup.long 0x0090++0x03 hide.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else hgroup.long 0x0094++0x03 hide.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else hgroup.long 0x0098++0x03 hide.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else hgroup.long 0x009C++0x03 hide.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else hgroup.long 0x00A0++0x03 hide.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else hgroup.long 0x00A4++0x03 hide.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else hgroup.long 0x00A8++0x03 hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else hgroup.long 0x00AC++0x03 hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else hgroup.long 0x00B0++0x03 hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else hgroup.long 0x00B4++0x03 hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else hgroup.long 0x00B8++0x03 hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else hgroup.long 0x00BC++0x03 hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else hgroup.long 0x00C0++0x03 hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else hgroup.long 0x00C4++0x03 hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else hgroup.long 0x00C8++0x03 hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else hgroup.long 0x00CC++0x03 hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else hgroup.long 0x00D0++0x03 hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else hgroup.long 0x00D4++0x03 hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else hgroup.long 0x00D8++0x03 hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else hgroup.long 0x00DC++0x03 hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else hgroup.long 0x00E0++0x03 hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else hgroup.long 0x00E4++0x03 hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else hgroup.long 0x00E8++0x03 hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else hgroup.long 0x00EC++0x03 hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else hgroup.long 0x00F0++0x03 hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else hgroup.long 0x00F4++0x03 hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else hgroup.long 0x00F8++0x03 hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" endif tree.end width 24. tree "Set/Clear Enable Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0100++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else hgroup.long 0x0104++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else hgroup.long 0x0108++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else hgroup.long 0x010C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else hgroup.long 0x0110++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else hgroup.long 0x0114++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else hgroup.long 0x0118++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else hgroup.long 0x011C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else hgroup.long 0x0120++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else hgroup.long 0x0124++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else hgroup.long 0x0128++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else hgroup.long 0x012C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else hgroup.long 0x0130++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else hgroup.long 0x0134++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else hgroup.long 0x0138++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else hgroup.long 0x013C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else hgroup.long 0x0140++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else hgroup.long 0x0144++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else hgroup.long 0x0148++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else hgroup.long 0x014C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else hgroup.long 0x0150++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else hgroup.long 0x0154++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else hgroup.long 0x0158++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else hgroup.long 0x015C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else hgroup.long 0x0160++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else hgroup.long 0x0164++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else hgroup.long 0x0168++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else hgroup.long 0x016C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else hgroup.long 0x0170++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else hgroup.long 0x0174++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else hgroup.long 0x0178++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" endif tree.end width 22. tree "Set/Clear Pending Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0200++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else hgroup.long 0x0204++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else hgroup.long 0x0208++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else hgroup.long 0x020C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else hgroup.long 0x0210++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else hgroup.long 0x0214++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else hgroup.long 0x0218++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else hgroup.long 0x021C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else hgroup.long 0x0220++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else hgroup.long 0x0224++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else hgroup.long 0x0228++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else hgroup.long 0x022C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else hgroup.long 0x0230++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else hgroup.long 0x0234++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else hgroup.long 0x0238++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else hgroup.long 0x023C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else hgroup.long 0x0240++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else hgroup.long 0x0244++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else hgroup.long 0x0248++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else hgroup.long 0x024C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else hgroup.long 0x0250++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else hgroup.long 0x0254++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else hgroup.long 0x0258++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else hgroup.long 0x025C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else hgroup.long 0x0260++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else hgroup.long 0x0264++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else hgroup.long 0x0268++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else hgroup.long 0x026C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else hgroup.long 0x0270++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else hgroup.long 0x0274++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else hgroup.long 0x0278++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" endif tree.end width 24. tree "Set/Clear Active Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0300++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else hgroup.long 0x0304++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else hgroup.long 0x0308++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else hgroup.long 0x030C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else hgroup.long 0x0310++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else hgroup.long 0x0314++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else hgroup.long 0x0318++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else hgroup.long 0x031C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else hgroup.long 0x0320++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else hgroup.long 0x0324++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else hgroup.long 0x0328++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else hgroup.long 0x032C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else hgroup.long 0x0330++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else hgroup.long 0x0334++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else hgroup.long 0x0338++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else hgroup.long 0x033C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active" else hgroup.long 0x0340++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active" else hgroup.long 0x0344++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active" else hgroup.long 0x0348++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active" else hgroup.long 0x034C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active" else hgroup.long 0x0350++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active" else hgroup.long 0x0354++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active" else hgroup.long 0x0358++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active" else hgroup.long 0x035C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active" else hgroup.long 0x0360++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active" else hgroup.long 0x0364++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active" else hgroup.long 0x0368++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active" else hgroup.long 0x036C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active" else hgroup.long 0x0370++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active" else hgroup.long 0x0374++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active" else hgroup.long 0x0378++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" endif tree.end width 20. tree "Priority Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x400++0x03 hide.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hgroup.long 0x404++0x03 hide.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hgroup.long 0x408++0x03 hide.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hgroup.long 0x40C++0x03 hide.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hgroup.long 0x410++0x03 hide.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hgroup.long 0x414++0x03 hide.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hgroup.long 0x418++0x03 hide.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hgroup.long 0x41C++0x03 hide.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" else group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else hgroup.long 0x420++0x03 hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hgroup.long 0x424++0x03 hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hgroup.long 0x428++0x03 hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hgroup.long 0x42C++0x03 hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hgroup.long 0x430++0x03 hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hgroup.long 0x434++0x03 hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hgroup.long 0x438++0x03 hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hgroup.long 0x43C++0x03 hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else hgroup.long 0x440++0x03 hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hgroup.long 0x444++0x03 hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hgroup.long 0x448++0x03 hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hgroup.long 0x44C++0x03 hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hgroup.long 0x450++0x03 hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hgroup.long 0x454++0x03 hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hgroup.long 0x458++0x03 hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hgroup.long 0x45C++0x03 hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else hgroup.long 0x460++0x03 hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hgroup.long 0x464++0x03 hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hgroup.long 0x468++0x03 hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hgroup.long 0x46C++0x03 hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hgroup.long 0x470++0x03 hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hgroup.long 0x474++0x03 hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hgroup.long 0x478++0x03 hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hgroup.long 0x47C++0x03 hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else hgroup.long 0x480++0x03 hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hgroup.long 0x484++0x03 hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hgroup.long 0x488++0x03 hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hgroup.long 0x48C++0x03 hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hgroup.long 0x490++0x03 hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hgroup.long 0x494++0x03 hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hgroup.long 0x498++0x03 hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hgroup.long 0x49C++0x03 hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else hgroup.long 0x4A0++0x03 hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hgroup.long 0x4A4++0x03 hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hgroup.long 0x4A8++0x03 hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hgroup.long 0x4AC++0x03 hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hgroup.long 0x4B0++0x03 hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hgroup.long 0x4B4++0x03 hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hgroup.long 0x4B8++0x03 hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hgroup.long 0x4BC++0x03 hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else hgroup.long 0x4C0++0x03 hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hgroup.long 0x4C4++0x03 hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hgroup.long 0x4C8++0x03 hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hgroup.long 0x4CC++0x03 hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hgroup.long 0x4D0++0x03 hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hgroup.long 0x4D4++0x03 hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hgroup.long 0x4D8++0x03 hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hgroup.long 0x4DC++0x03 hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else hgroup.long 0x4E0++0x03 hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hgroup.long 0x4E4++0x03 hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hgroup.long 0x4E8++0x03 hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hgroup.long 0x4EC++0x03 hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hgroup.long 0x4F0++0x03 hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hgroup.long 0x4F4++0x03 hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hgroup.long 0x4F8++0x03 hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hgroup.long 0x4FC++0x03 hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else hgroup.long 0x500++0x03 hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hgroup.long 0x504++0x03 hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hgroup.long 0x508++0x03 hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hgroup.long 0x50C++0x03 hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hgroup.long 0x510++0x03 hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hgroup.long 0x514++0x03 hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hgroup.long 0x518++0x03 hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hgroup.long 0x51C++0x03 hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else hgroup.long 0x520++0x03 hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hgroup.long 0x524++0x03 hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hgroup.long 0x528++0x03 hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hgroup.long 0x52C++0x03 hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hgroup.long 0x530++0x03 hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hgroup.long 0x534++0x03 hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hgroup.long 0x538++0x03 hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hgroup.long 0x53C++0x03 hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else hgroup.long 0x540++0x03 hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hgroup.long 0x544++0x03 hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hgroup.long 0x548++0x03 hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hgroup.long 0x54C++0x03 hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hgroup.long 0x550++0x03 hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hgroup.long 0x554++0x03 hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hgroup.long 0x558++0x03 hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hgroup.long 0x55C++0x03 hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else hgroup.long 0x560++0x03 hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hgroup.long 0x564++0x03 hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hgroup.long 0x568++0x03 hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hgroup.long 0x56C++0x03 hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hgroup.long 0x570++0x03 hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hgroup.long 0x574++0x03 hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hgroup.long 0x578++0x03 hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hgroup.long 0x57C++0x03 hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else hgroup.long 0x580++0x03 hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hgroup.long 0x584++0x03 hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hgroup.long 0x588++0x03 hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hgroup.long 0x58C++0x03 hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hgroup.long 0x590++0x03 hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hgroup.long 0x594++0x03 hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hgroup.long 0x598++0x03 hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hgroup.long 0x59C++0x03 hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else hgroup.long 0x5A0++0x03 hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hgroup.long 0x5A4++0x03 hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hgroup.long 0x5A8++0x03 hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hgroup.long 0x5AC++0x03 hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hgroup.long 0x5B0++0x03 hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hgroup.long 0x5B4++0x03 hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hgroup.long 0x5B8++0x03 hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hgroup.long 0x5BC++0x03 hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else hgroup.long 0x5C0++0x03 hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hgroup.long 0x5C4++0x03 hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hgroup.long 0x5C8++0x03 hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hgroup.long 0x5CC++0x03 hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hgroup.long 0x5D0++0x03 hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hgroup.long 0x5D4++0x03 hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hgroup.long 0x5D8++0x03 hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hgroup.long 0x5DC++0x03 hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else hgroup.long 0x5E0++0x03 hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hgroup.long 0x5E4++0x03 hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hgroup.long 0x5E8++0x03 hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hgroup.long 0x5EC++0x03 hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hgroup.long 0x5F0++0x03 hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hgroup.long 0x5F4++0x03 hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hgroup.long 0x5F8++0x03 hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hgroup.long 0x5FC++0x03 hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else hgroup.long 0x600++0x03 hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hgroup.long 0x604++0x03 hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hgroup.long 0x608++0x03 hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hgroup.long 0x60C++0x03 hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hgroup.long 0x610++0x03 hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hgroup.long 0x614++0x03 hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hgroup.long 0x618++0x03 hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hgroup.long 0x61C++0x03 hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else hgroup.long 0x620++0x03 hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hgroup.long 0x624++0x03 hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hgroup.long 0x628++0x03 hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hgroup.long 0x62C++0x03 hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hgroup.long 0x630++0x03 hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hgroup.long 0x634++0x03 hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hgroup.long 0x638++0x03 hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hgroup.long 0x63C++0x03 hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else hgroup.long 0x640++0x03 hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hgroup.long 0x644++0x03 hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hgroup.long 0x648++0x03 hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hgroup.long 0x64C++0x03 hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hgroup.long 0x650++0x03 hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hgroup.long 0x654++0x03 hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hgroup.long 0x658++0x03 hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hgroup.long 0x65C++0x03 hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else hgroup.long 0x660++0x03 hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hgroup.long 0x664++0x03 hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hgroup.long 0x668++0x03 hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hgroup.long 0x66C++0x03 hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hgroup.long 0x670++0x03 hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hgroup.long 0x674++0x03 hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hgroup.long 0x678++0x03 hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hgroup.long 0x67C++0x03 hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else hgroup.long 0x680++0x03 hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hgroup.long 0x684++0x03 hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hgroup.long 0x688++0x03 hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hgroup.long 0x68C++0x03 hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hgroup.long 0x690++0x03 hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hgroup.long 0x694++0x03 hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hgroup.long 0x698++0x03 hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hgroup.long 0x69C++0x03 hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else hgroup.long 0x6A0++0x03 hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hgroup.long 0x6A4++0x03 hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hgroup.long 0x6A8++0x03 hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hgroup.long 0x6AC++0x03 hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hgroup.long 0x6B0++0x03 hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hgroup.long 0x6B4++0x03 hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hgroup.long 0x6B8++0x03 hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hgroup.long 0x6BC++0x03 hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else hgroup.long 0x6C0++0x03 hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hgroup.long 0x6C4++0x03 hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hgroup.long 0x6C8++0x03 hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hgroup.long 0x6CC++0x03 hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hgroup.long 0x6D0++0x03 hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hgroup.long 0x6D4++0x03 hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hgroup.long 0x6D8++0x03 hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hgroup.long 0x6DC++0x03 hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else hgroup.long 0x6E0++0x03 hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hgroup.long 0x6E4++0x03 hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hgroup.long 0x6E8++0x03 hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hgroup.long 0x6EC++0x03 hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hgroup.long 0x6F0++0x03 hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hgroup.long 0x6F4++0x03 hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hgroup.long 0x6F8++0x03 hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hgroup.long 0x6FC++0x03 hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else hgroup.long 0x700++0x03 hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hgroup.long 0x704++0x03 hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hgroup.long 0x708++0x03 hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hgroup.long 0x70C++0x03 hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hgroup.long 0x710++0x03 hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hgroup.long 0x714++0x03 hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hgroup.long 0x718++0x03 hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hgroup.long 0x71C++0x03 hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else hgroup.long 0x720++0x03 hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hgroup.long 0x724++0x03 hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hgroup.long 0x728++0x03 hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hgroup.long 0x72C++0x03 hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hgroup.long 0x730++0x03 hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hgroup.long 0x734++0x03 hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hgroup.long 0x738++0x03 hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hgroup.long 0x73C++0x03 hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else hgroup.long 0x740++0x03 hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hgroup.long 0x744++0x03 hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hgroup.long 0x748++0x03 hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hgroup.long 0x74C++0x03 hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hgroup.long 0x750++0x03 hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hgroup.long 0x754++0x03 hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hgroup.long 0x758++0x03 hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hgroup.long 0x75C++0x03 hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else hgroup.long 0x760++0x03 hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hgroup.long 0x764++0x03 hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hgroup.long 0x768++0x03 hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hgroup.long 0x76C++0x03 hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hgroup.long 0x770++0x03 hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hgroup.long 0x774++0x03 hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hgroup.long 0x778++0x03 hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hgroup.long 0x77C++0x03 hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else hgroup.long 0x780++0x03 hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hgroup.long 0x784++0x03 hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hgroup.long 0x788++0x03 hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hgroup.long 0x78C++0x03 hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hgroup.long 0x790++0x03 hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hgroup.long 0x794++0x03 hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hgroup.long 0x798++0x03 hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hgroup.long 0x79C++0x03 hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else hgroup.long 0x7A0++0x03 hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hgroup.long 0x7A4++0x03 hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hgroup.long 0x7A8++0x03 hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hgroup.long 0x7AC++0x03 hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hgroup.long 0x7B0++0x03 hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hgroup.long 0x7B4++0x03 hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hgroup.long 0x7B8++0x03 hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hgroup.long 0x7BC++0x03 hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else hgroup.long 0x7C0++0x03 hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hgroup.long 0x7C4++0x03 hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hgroup.long 0x7C8++0x03 hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hgroup.long 0x7CC++0x03 hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hgroup.long 0x7D0++0x03 hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hgroup.long 0x7D4++0x03 hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hgroup.long 0x7D8++0x03 hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hgroup.long 0x7DC++0x03 hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif tree.end width 19. tree "Interrupt Targets Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x000000E0)>0x1) hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif else hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif tree.end width 14. tree "Configuration Registers" rgroup.long 0xC00++0x03 line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SGI)" "Level,Edge" group.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (PPI)" "Level,Edge" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC08++0x03 hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" hgroup.long 0xC0C++0x03 hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC10++0x03 hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" hgroup.long 0xC14++0x03 hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC18++0x03 hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" hgroup.long 0xC1C++0x03 hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC20++0x03 hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" hgroup.long 0xC24++0x03 hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC28++0x03 hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" hgroup.long 0xC2C++0x03 hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC30++0x03 hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" hgroup.long 0xC34++0x03 hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC38++0x03 hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" hgroup.long 0xC3C++0x03 hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC40++0x03 hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" hgroup.long 0xC44++0x03 hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC48++0x03 hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" hgroup.long 0xC4C++0x03 hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC50++0x03 hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" hgroup.long 0xC54++0x03 hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC58++0x03 hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" hgroup.long 0xC5C++0x03 hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC60++0x03 hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" hgroup.long 0xC64++0x03 hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC68++0x03 hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" hgroup.long 0xC6C++0x03 hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC70++0x03 hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" hgroup.long 0xC74++0x03 hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC78++0x03 hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" hgroup.long 0xC7C++0x03 hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC80++0x03 hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" hgroup.long 0xC84++0x03 hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC88++0x03 hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" hgroup.long 0xC8C++0x03 hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC90++0x03 hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" hgroup.long 0xC94++0x03 hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC98++0x03 hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" hgroup.long 0xC9C++0x03 hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA0++0x03 hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" hgroup.long 0xCA4++0x03 hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA8++0x03 hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" hgroup.long 0xCAC++0x03 hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB0++0x03 hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" hgroup.long 0xCB4++0x03 hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB8++0x03 hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" hgroup.long 0xCBC++0x03 hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC0++0x03 hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" hgroup.long 0xCC4++0x03 hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC8++0x03 hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" hgroup.long 0xCCC++0x03 hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD0++0x03 hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" hgroup.long 0xCD4++0x03 hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD8++0x03 hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" hgroup.long 0xCDC++0x03 hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE0++0x03 hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" hgroup.long 0xCE4++0x03 hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE8++0x03 hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" hgroup.long 0xCEC++0x03 hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCF0++0x03 hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" hgroup.long 0xCF4++0x03 hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif tree.end width 17. tree "Interrupt Group Modifier Registers" hgroup.long 0x0D00++0x03 hide.long 0x0 "GICD_IGRPMODR0,Interrupt Group Modifier Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D00))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)) group.long 0x0D04++0x03 line.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" bitfld.long 0x00 31. " GMB63 ,Group Modifier Bit 63" "0,1" bitfld.long 0x00 30. " GMB62 ,Group Modifier Bit 62" "0,1" bitfld.long 0x00 29. " GMB61 ,Group Modifier Bit 61" "0,1" textline " " bitfld.long 0x00 28. " GMB60 ,Group Modifier Bit 60" "0,1" bitfld.long 0x00 27. " GMB59 ,Group Modifier Bit 59" "0,1" bitfld.long 0x00 26. " GMB58 ,Group Modifier Bit 58" "0,1" textline " " bitfld.long 0x00 25. " GMB57 ,Group Modifier Bit 57" "0,1" bitfld.long 0x00 24. " GMB56 ,Group Modifier Bit 56" "0,1" bitfld.long 0x00 23. " GMB55 ,Group Modifier Bit 55" "0,1" textline " " bitfld.long 0x00 22. " GMB54 ,Group Modifier Bit 54" "0,1" bitfld.long 0x00 21. " GMB53 ,Group Modifier Bit 53" "0,1" bitfld.long 0x00 20. " GMB52 ,Group Modifier Bit 52" "0,1" textline " " bitfld.long 0x00 19. " GMB51 ,Group Modifier Bit 51" "0,1" bitfld.long 0x00 18. " GMB50 ,Group Modifier Bit 50" "0,1" bitfld.long 0x00 17. " GMB49 ,Group Modifier Bit 49" "0,1" textline " " bitfld.long 0x00 16. " GMB48 ,Group Modifier Bit 48" "0,1" bitfld.long 0x00 15. " GMB47 ,Group Modifier Bit 47" "0,1" bitfld.long 0x00 14. " GMB46 ,Group Modifier Bit 46" "0,1" textline " " bitfld.long 0x00 13. " GMB45 ,Group Modifier Bit 45" "0,1" bitfld.long 0x00 12. " GMB44 ,Group Modifier Bit 44" "0,1" bitfld.long 0x00 11. " GMB43 ,Group Modifier Bit 43" "0,1" textline " " bitfld.long 0x00 10. " GMB42 ,Group Modifier Bit 42" "0,1" bitfld.long 0x00 9. " GMB41 ,Group Modifier Bit 41" "0,1" bitfld.long 0x00 8. " GMB40 ,Group Modifier Bit 40" "0,1" textline " " bitfld.long 0x00 7. " GMB39 ,Group Modifier Bit 39" "0,1" bitfld.long 0x00 6. " GMB38 ,Group Modifier Bit 38" "0,1" bitfld.long 0x00 5. " GMB37 ,Group Modifier Bit 37" "0,1" textline " " bitfld.long 0x00 4. " GMB36 ,Group Modifier Bit 36" "0,1" bitfld.long 0x00 3. " GMB35 ,Group Modifier Bit 35" "0,1" bitfld.long 0x00 2. " GMB34 ,Group Modifier Bit 34" "0,1" textline " " bitfld.long 0x00 1. " GMB33 ,Group Modifier Bit 33" "0,1" bitfld.long 0x00 0. " GMB32 ,Group Modifier Bit 32" "0,1" else hgroup.long 0x0D04++0x03 hide.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D08))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)) group.long 0x0D08++0x03 line.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" bitfld.long 0x00 31. " GMB95 ,Group Modifier Bit 95" "0,1" bitfld.long 0x00 30. " GMB94 ,Group Modifier Bit 94" "0,1" bitfld.long 0x00 29. " GMB93 ,Group Modifier Bit 93" "0,1" textline " " bitfld.long 0x00 28. " GMB92 ,Group Modifier Bit 92" "0,1" bitfld.long 0x00 27. " GMB91 ,Group Modifier Bit 91" "0,1" bitfld.long 0x00 26. " GMB90 ,Group Modifier Bit 90" "0,1" textline " " bitfld.long 0x00 25. " GMB89 ,Group Modifier Bit 89" "0,1" bitfld.long 0x00 24. " GMB88 ,Group Modifier Bit 88" "0,1" bitfld.long 0x00 23. " GMB87 ,Group Modifier Bit 87" "0,1" textline " " bitfld.long 0x00 22. " GMB86 ,Group Modifier Bit 86" "0,1" bitfld.long 0x00 21. " GMB85 ,Group Modifier Bit 85" "0,1" bitfld.long 0x00 20. " GMB84 ,Group Modifier Bit 84" "0,1" textline " " bitfld.long 0x00 19. " GMB83 ,Group Modifier Bit 83" "0,1" bitfld.long 0x00 18. " GMB82 ,Group Modifier Bit 82" "0,1" bitfld.long 0x00 17. " GMB81 ,Group Modifier Bit 81" "0,1" textline " " bitfld.long 0x00 16. " GMB80 ,Group Modifier Bit 80" "0,1" bitfld.long 0x00 15. " GMB79 ,Group Modifier Bit 79" "0,1" bitfld.long 0x00 14. " GMB78 ,Group Modifier Bit 78" "0,1" textline " " bitfld.long 0x00 13. " GMB77 ,Group Modifier Bit 77" "0,1" bitfld.long 0x00 12. " GMB76 ,Group Modifier Bit 76" "0,1" bitfld.long 0x00 11. " GMB75 ,Group Modifier Bit 75" "0,1" textline " " bitfld.long 0x00 10. " GMB74 ,Group Modifier Bit 74" "0,1" bitfld.long 0x00 9. " GMB73 ,Group Modifier Bit 73" "0,1" bitfld.long 0x00 8. " GMB72 ,Group Modifier Bit 72" "0,1" textline " " bitfld.long 0x00 7. " GMB71 ,Group Modifier Bit 71" "0,1" bitfld.long 0x00 6. " GMB70 ,Group Modifier Bit 70" "0,1" bitfld.long 0x00 5. " GMB69 ,Group Modifier Bit 69" "0,1" textline " " bitfld.long 0x00 4. " GMB68 ,Group Modifier Bit 68" "0,1" bitfld.long 0x00 3. " GMB67 ,Group Modifier Bit 67" "0,1" bitfld.long 0x00 2. " GMB66 ,Group Modifier Bit 66" "0,1" textline " " bitfld.long 0x00 1. " GMB65 ,Group Modifier Bit 65" "0,1" bitfld.long 0x00 0. " GMB64 ,Group Modifier Bit 64" "0,1" else hgroup.long 0x0D08++0x03 hide.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D0C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)) group.long 0x0D0C++0x03 line.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" bitfld.long 0x00 31. " GMB127 ,Group Modifier Bit 127" "0,1" bitfld.long 0x00 30. " GMB126 ,Group Modifier Bit 126" "0,1" bitfld.long 0x00 29. " GMB125 ,Group Modifier Bit 125" "0,1" textline " " bitfld.long 0x00 28. " GMB124 ,Group Modifier Bit 124" "0,1" bitfld.long 0x00 27. " GMB123 ,Group Modifier Bit 123" "0,1" bitfld.long 0x00 26. " GMB122 ,Group Modifier Bit 122" "0,1" textline " " bitfld.long 0x00 25. " GMB121 ,Group Modifier Bit 121" "0,1" bitfld.long 0x00 24. " GMB120 ,Group Modifier Bit 120" "0,1" bitfld.long 0x00 23. " GMB119 ,Group Modifier Bit 119" "0,1" textline " " bitfld.long 0x00 22. " GMB118 ,Group Modifier Bit 118" "0,1" bitfld.long 0x00 21. " GMB117 ,Group Modifier Bit 117" "0,1" bitfld.long 0x00 20. " GMB116 ,Group Modifier Bit 116" "0,1" textline " " bitfld.long 0x00 19. " GMB115 ,Group Modifier Bit 115" "0,1" bitfld.long 0x00 18. " GMB114 ,Group Modifier Bit 114" "0,1" bitfld.long 0x00 17. " GMB113 ,Group Modifier Bit 113" "0,1" textline " " bitfld.long 0x00 16. " GMB112 ,Group Modifier Bit 112" "0,1" bitfld.long 0x00 15. " GMB111 ,Group Modifier Bit 111" "0,1" bitfld.long 0x00 14. " GMB110 ,Group Modifier Bit 110" "0,1" textline " " bitfld.long 0x00 13. " GMB109 ,Group Modifier Bit 109" "0,1" bitfld.long 0x00 12. " GMB108 ,Group Modifier Bit 108" "0,1" bitfld.long 0x00 11. " GMB107 ,Group Modifier Bit 107" "0,1" textline " " bitfld.long 0x00 10. " GMB106 ,Group Modifier Bit 106" "0,1" bitfld.long 0x00 9. " GMB105 ,Group Modifier Bit 105" "0,1" bitfld.long 0x00 8. " GMB104 ,Group Modifier Bit 104" "0,1" textline " " bitfld.long 0x00 7. " GMB103 ,Group Modifier Bit 103" "0,1" bitfld.long 0x00 6. " GMB102 ,Group Modifier Bit 102" "0,1" bitfld.long 0x00 5. " GMB101 ,Group Modifier Bit 101" "0,1" textline " " bitfld.long 0x00 4. " GMB100 ,Group Modifier Bit 100" "0,1" bitfld.long 0x00 3. " GMB99 ,Group Modifier Bit 99" "0,1" bitfld.long 0x00 2. " GMB98 ,Group Modifier Bit 98" "0,1" textline " " bitfld.long 0x00 1. " GMB97 ,Group Modifier Bit 97" "0,1" bitfld.long 0x00 0. " GMB96 ,Group Modifier Bit 96" "0,1" else hgroup.long 0x0D0C++0x03 hide.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D10))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)) group.long 0x0D10++0x03 line.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" bitfld.long 0x00 31. " GMB159 ,Group Modifier Bit 159" "0,1" bitfld.long 0x00 30. " GMB158 ,Group Modifier Bit 158" "0,1" bitfld.long 0x00 29. " GMB157 ,Group Modifier Bit 157" "0,1" textline " " bitfld.long 0x00 28. " GMB156 ,Group Modifier Bit 156" "0,1" bitfld.long 0x00 27. " GMB155 ,Group Modifier Bit 155" "0,1" bitfld.long 0x00 26. " GMB154 ,Group Modifier Bit 154" "0,1" textline " " bitfld.long 0x00 25. " GMB153 ,Group Modifier Bit 153" "0,1" bitfld.long 0x00 24. " GMB152 ,Group Modifier Bit 152" "0,1" bitfld.long 0x00 23. " GMB151 ,Group Modifier Bit 151" "0,1" textline " " bitfld.long 0x00 22. " GMB150 ,Group Modifier Bit 150" "0,1" bitfld.long 0x00 21. " GMB149 ,Group Modifier Bit 149" "0,1" bitfld.long 0x00 20. " GMB148 ,Group Modifier Bit 148" "0,1" textline " " bitfld.long 0x00 19. " GMB147 ,Group Modifier Bit 147" "0,1" bitfld.long 0x00 18. " GMB146 ,Group Modifier Bit 146" "0,1" bitfld.long 0x00 17. " GMB145 ,Group Modifier Bit 145" "0,1" textline " " bitfld.long 0x00 16. " GMB144 ,Group Modifier Bit 144" "0,1" bitfld.long 0x00 15. " GMB143 ,Group Modifier Bit 143" "0,1" bitfld.long 0x00 14. " GMB142 ,Group Modifier Bit 142" "0,1" textline " " bitfld.long 0x00 13. " GMB141 ,Group Modifier Bit 141" "0,1" bitfld.long 0x00 12. " GMB140 ,Group Modifier Bit 140" "0,1" bitfld.long 0x00 11. " GMB139 ,Group Modifier Bit 139" "0,1" textline " " bitfld.long 0x00 10. " GMB138 ,Group Modifier Bit 138" "0,1" bitfld.long 0x00 9. " GMB137 ,Group Modifier Bit 137" "0,1" bitfld.long 0x00 8. " GMB136 ,Group Modifier Bit 136" "0,1" textline " " bitfld.long 0x00 7. " GMB135 ,Group Modifier Bit 135" "0,1" bitfld.long 0x00 6. " GMB134 ,Group Modifier Bit 134" "0,1" bitfld.long 0x00 5. " GMB133 ,Group Modifier Bit 133" "0,1" textline " " bitfld.long 0x00 4. " GMB132 ,Group Modifier Bit 132" "0,1" bitfld.long 0x00 3. " GMB131 ,Group Modifier Bit 131" "0,1" bitfld.long 0x00 2. " GMB130 ,Group Modifier Bit 130" "0,1" textline " " bitfld.long 0x00 1. " GMB129 ,Group Modifier Bit 129" "0,1" bitfld.long 0x00 0. " GMB128 ,Group Modifier Bit 128" "0,1" else hgroup.long 0x0D10++0x03 hide.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D14))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)) group.long 0x0D14++0x03 line.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" bitfld.long 0x00 31. " GMB191 ,Group Modifier Bit 191" "0,1" bitfld.long 0x00 30. " GMB190 ,Group Modifier Bit 190" "0,1" bitfld.long 0x00 29. " GMB189 ,Group Modifier Bit 189" "0,1" textline " " bitfld.long 0x00 28. " GMB188 ,Group Modifier Bit 188" "0,1" bitfld.long 0x00 27. " GMB187 ,Group Modifier Bit 187" "0,1" bitfld.long 0x00 26. " GMB186 ,Group Modifier Bit 186" "0,1" textline " " bitfld.long 0x00 25. " GMB185 ,Group Modifier Bit 185" "0,1" bitfld.long 0x00 24. " GMB184 ,Group Modifier Bit 184" "0,1" bitfld.long 0x00 23. " GMB183 ,Group Modifier Bit 183" "0,1" textline " " bitfld.long 0x00 22. " GMB182 ,Group Modifier Bit 182" "0,1" bitfld.long 0x00 21. " GMB181 ,Group Modifier Bit 181" "0,1" bitfld.long 0x00 20. " GMB180 ,Group Modifier Bit 180" "0,1" textline " " bitfld.long 0x00 19. " GMB179 ,Group Modifier Bit 179" "0,1" bitfld.long 0x00 18. " GMB178 ,Group Modifier Bit 178" "0,1" bitfld.long 0x00 17. " GMB177 ,Group Modifier Bit 177" "0,1" textline " " bitfld.long 0x00 16. " GMB176 ,Group Modifier Bit 176" "0,1" bitfld.long 0x00 15. " GMB175 ,Group Modifier Bit 175" "0,1" bitfld.long 0x00 14. " GMB174 ,Group Modifier Bit 174" "0,1" textline " " bitfld.long 0x00 13. " GMB173 ,Group Modifier Bit 173" "0,1" bitfld.long 0x00 12. " GMB172 ,Group Modifier Bit 172" "0,1" bitfld.long 0x00 11. " GMB171 ,Group Modifier Bit 171" "0,1" textline " " bitfld.long 0x00 10. " GMB170 ,Group Modifier Bit 170" "0,1" bitfld.long 0x00 9. " GMB169 ,Group Modifier Bit 169" "0,1" bitfld.long 0x00 8. " GMB168 ,Group Modifier Bit 168" "0,1" textline " " bitfld.long 0x00 7. " GMB167 ,Group Modifier Bit 167" "0,1" bitfld.long 0x00 6. " GMB166 ,Group Modifier Bit 166" "0,1" bitfld.long 0x00 5. " GMB165 ,Group Modifier Bit 165" "0,1" textline " " bitfld.long 0x00 4. " GMB164 ,Group Modifier Bit 164" "0,1" bitfld.long 0x00 3. " GMB163 ,Group Modifier Bit 163" "0,1" bitfld.long 0x00 2. " GMB162 ,Group Modifier Bit 162" "0,1" textline " " bitfld.long 0x00 1. " GMB161 ,Group Modifier Bit 161" "0,1" bitfld.long 0x00 0. " GMB160 ,Group Modifier Bit 160" "0,1" else hgroup.long 0x0D14++0x03 hide.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D18))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)) group.long 0x0D18++0x03 line.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" bitfld.long 0x00 31. " GMB223 ,Group Modifier Bit 223" "0,1" bitfld.long 0x00 30. " GMB222 ,Group Modifier Bit 222" "0,1" bitfld.long 0x00 29. " GMB221 ,Group Modifier Bit 221" "0,1" textline " " bitfld.long 0x00 28. " GMB220 ,Group Modifier Bit 220" "0,1" bitfld.long 0x00 27. " GMB219 ,Group Modifier Bit 219" "0,1" bitfld.long 0x00 26. " GMB218 ,Group Modifier Bit 218" "0,1" textline " " bitfld.long 0x00 25. " GMB217 ,Group Modifier Bit 217" "0,1" bitfld.long 0x00 24. " GMB216 ,Group Modifier Bit 216" "0,1" bitfld.long 0x00 23. " GMB215 ,Group Modifier Bit 215" "0,1" textline " " bitfld.long 0x00 22. " GMB214 ,Group Modifier Bit 214" "0,1" bitfld.long 0x00 21. " GMB213 ,Group Modifier Bit 213" "0,1" bitfld.long 0x00 20. " GMB212 ,Group Modifier Bit 212" "0,1" textline " " bitfld.long 0x00 19. " GMB211 ,Group Modifier Bit 211" "0,1" bitfld.long 0x00 18. " GMB210 ,Group Modifier Bit 210" "0,1" bitfld.long 0x00 17. " GMB209 ,Group Modifier Bit 209" "0,1" textline " " bitfld.long 0x00 16. " GMB208 ,Group Modifier Bit 208" "0,1" bitfld.long 0x00 15. " GMB207 ,Group Modifier Bit 207" "0,1" bitfld.long 0x00 14. " GMB206 ,Group Modifier Bit 206" "0,1" textline " " bitfld.long 0x00 13. " GMB205 ,Group Modifier Bit 205" "0,1" bitfld.long 0x00 12. " GMB204 ,Group Modifier Bit 204" "0,1" bitfld.long 0x00 11. " GMB203 ,Group Modifier Bit 203" "0,1" textline " " bitfld.long 0x00 10. " GMB202 ,Group Modifier Bit 202" "0,1" bitfld.long 0x00 9. " GMB201 ,Group Modifier Bit 201" "0,1" bitfld.long 0x00 8. " GMB200 ,Group Modifier Bit 200" "0,1" textline " " bitfld.long 0x00 7. " GMB199 ,Group Modifier Bit 199" "0,1" bitfld.long 0x00 6. " GMB198 ,Group Modifier Bit 198" "0,1" bitfld.long 0x00 5. " GMB197 ,Group Modifier Bit 197" "0,1" textline " " bitfld.long 0x00 4. " GMB196 ,Group Modifier Bit 196" "0,1" bitfld.long 0x00 3. " GMB195 ,Group Modifier Bit 195" "0,1" bitfld.long 0x00 2. " GMB194 ,Group Modifier Bit 194" "0,1" textline " " bitfld.long 0x00 1. " GMB193 ,Group Modifier Bit 193" "0,1" bitfld.long 0x00 0. " GMB192 ,Group Modifier Bit 192" "0,1" else hgroup.long 0x0D18++0x03 hide.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D1C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)) group.long 0x0D1C++0x03 line.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" bitfld.long 0x00 31. " GMB255 ,Group Modifier Bit 255" "0,1" bitfld.long 0x00 30. " GMB254 ,Group Modifier Bit 254" "0,1" bitfld.long 0x00 29. " GMB253 ,Group Modifier Bit 253" "0,1" textline " " bitfld.long 0x00 28. " GMB252 ,Group Modifier Bit 252" "0,1" bitfld.long 0x00 27. " GMB251 ,Group Modifier Bit 251" "0,1" bitfld.long 0x00 26. " GMB250 ,Group Modifier Bit 250" "0,1" textline " " bitfld.long 0x00 25. " GMB249 ,Group Modifier Bit 249" "0,1" bitfld.long 0x00 24. " GMB248 ,Group Modifier Bit 248" "0,1" bitfld.long 0x00 23. " GMB247 ,Group Modifier Bit 247" "0,1" textline " " bitfld.long 0x00 22. " GMB246 ,Group Modifier Bit 246" "0,1" bitfld.long 0x00 21. " GMB245 ,Group Modifier Bit 245" "0,1" bitfld.long 0x00 20. " GMB244 ,Group Modifier Bit 244" "0,1" textline " " bitfld.long 0x00 19. " GMB243 ,Group Modifier Bit 243" "0,1" bitfld.long 0x00 18. " GMB242 ,Group Modifier Bit 242" "0,1" bitfld.long 0x00 17. " GMB241 ,Group Modifier Bit 241" "0,1" textline " " bitfld.long 0x00 16. " GMB240 ,Group Modifier Bit 240" "0,1" bitfld.long 0x00 15. " GMB239 ,Group Modifier Bit 239" "0,1" bitfld.long 0x00 14. " GMB238 ,Group Modifier Bit 238" "0,1" textline " " bitfld.long 0x00 13. " GMB237 ,Group Modifier Bit 237" "0,1" bitfld.long 0x00 12. " GMB236 ,Group Modifier Bit 236" "0,1" bitfld.long 0x00 11. " GMB235 ,Group Modifier Bit 235" "0,1" textline " " bitfld.long 0x00 10. " GMB234 ,Group Modifier Bit 234" "0,1" bitfld.long 0x00 9. " GMB233 ,Group Modifier Bit 233" "0,1" bitfld.long 0x00 8. " GMB232 ,Group Modifier Bit 232" "0,1" textline " " bitfld.long 0x00 7. " GMB231 ,Group Modifier Bit 231" "0,1" bitfld.long 0x00 6. " GMB230 ,Group Modifier Bit 230" "0,1" bitfld.long 0x00 5. " GMB229 ,Group Modifier Bit 229" "0,1" textline " " bitfld.long 0x00 4. " GMB228 ,Group Modifier Bit 228" "0,1" bitfld.long 0x00 3. " GMB227 ,Group Modifier Bit 227" "0,1" bitfld.long 0x00 2. " GMB226 ,Group Modifier Bit 226" "0,1" textline " " bitfld.long 0x00 1. " GMB225 ,Group Modifier Bit 225" "0,1" bitfld.long 0x00 0. " GMB224 ,Group Modifier Bit 224" "0,1" else hgroup.long 0x0D1C++0x03 hide.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D20))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)) group.long 0x0D20++0x03 line.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" bitfld.long 0x00 31. " GMB287 ,Group Modifier Bit 287" "0,1" bitfld.long 0x00 30. " GMB286 ,Group Modifier Bit 286" "0,1" bitfld.long 0x00 29. " GMB285 ,Group Modifier Bit 285" "0,1" textline " " bitfld.long 0x00 28. " GMB284 ,Group Modifier Bit 284" "0,1" bitfld.long 0x00 27. " GMB283 ,Group Modifier Bit 283" "0,1" bitfld.long 0x00 26. " GMB282 ,Group Modifier Bit 282" "0,1" textline " " bitfld.long 0x00 25. " GMB281 ,Group Modifier Bit 281" "0,1" bitfld.long 0x00 24. " GMB280 ,Group Modifier Bit 280" "0,1" bitfld.long 0x00 23. " GMB279 ,Group Modifier Bit 279" "0,1" textline " " bitfld.long 0x00 22. " GMB278 ,Group Modifier Bit 278" "0,1" bitfld.long 0x00 21. " GMB277 ,Group Modifier Bit 277" "0,1" bitfld.long 0x00 20. " GMB276 ,Group Modifier Bit 276" "0,1" textline " " bitfld.long 0x00 19. " GMB275 ,Group Modifier Bit 275" "0,1" bitfld.long 0x00 18. " GMB274 ,Group Modifier Bit 274" "0,1" bitfld.long 0x00 17. " GMB273 ,Group Modifier Bit 273" "0,1" textline " " bitfld.long 0x00 16. " GMB272 ,Group Modifier Bit 272" "0,1" bitfld.long 0x00 15. " GMB271 ,Group Modifier Bit 271" "0,1" bitfld.long 0x00 14. " GMB270 ,Group Modifier Bit 270" "0,1" textline " " bitfld.long 0x00 13. " GMB269 ,Group Modifier Bit 269" "0,1" bitfld.long 0x00 12. " GMB268 ,Group Modifier Bit 268" "0,1" bitfld.long 0x00 11. " GMB267 ,Group Modifier Bit 267" "0,1" textline " " bitfld.long 0x00 10. " GMB266 ,Group Modifier Bit 266" "0,1" bitfld.long 0x00 9. " GMB265 ,Group Modifier Bit 265" "0,1" bitfld.long 0x00 8. " GMB264 ,Group Modifier Bit 264" "0,1" textline " " bitfld.long 0x00 7. " GMB263 ,Group Modifier Bit 263" "0,1" bitfld.long 0x00 6. " GMB262 ,Group Modifier Bit 262" "0,1" bitfld.long 0x00 5. " GMB261 ,Group Modifier Bit 261" "0,1" textline " " bitfld.long 0x00 4. " GMB260 ,Group Modifier Bit 260" "0,1" bitfld.long 0x00 3. " GMB259 ,Group Modifier Bit 259" "0,1" bitfld.long 0x00 2. " GMB258 ,Group Modifier Bit 258" "0,1" textline " " bitfld.long 0x00 1. " GMB257 ,Group Modifier Bit 257" "0,1" bitfld.long 0x00 0. " GMB256 ,Group Modifier Bit 256" "0,1" else hgroup.long 0x0D20++0x03 hide.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D24))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)) group.long 0x0D24++0x03 line.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" bitfld.long 0x00 31. " GMB319 ,Group Modifier Bit 319" "0,1" bitfld.long 0x00 30. " GMB318 ,Group Modifier Bit 318" "0,1" bitfld.long 0x00 29. " GMB317 ,Group Modifier Bit 317" "0,1" textline " " bitfld.long 0x00 28. " GMB316 ,Group Modifier Bit 316" "0,1" bitfld.long 0x00 27. " GMB315 ,Group Modifier Bit 315" "0,1" bitfld.long 0x00 26. " GMB314 ,Group Modifier Bit 314" "0,1" textline " " bitfld.long 0x00 25. " GMB313 ,Group Modifier Bit 313" "0,1" bitfld.long 0x00 24. " GMB312 ,Group Modifier Bit 312" "0,1" bitfld.long 0x00 23. " GMB311 ,Group Modifier Bit 311" "0,1" textline " " bitfld.long 0x00 22. " GMB310 ,Group Modifier Bit 310" "0,1" bitfld.long 0x00 21. " GMB309 ,Group Modifier Bit 309" "0,1" bitfld.long 0x00 20. " GMB308 ,Group Modifier Bit 308" "0,1" textline " " bitfld.long 0x00 19. " GMB307 ,Group Modifier Bit 307" "0,1" bitfld.long 0x00 18. " GMB306 ,Group Modifier Bit 306" "0,1" bitfld.long 0x00 17. " GMB305 ,Group Modifier Bit 305" "0,1" textline " " bitfld.long 0x00 16. " GMB304 ,Group Modifier Bit 304" "0,1" bitfld.long 0x00 15. " GMB303 ,Group Modifier Bit 303" "0,1" bitfld.long 0x00 14. " GMB302 ,Group Modifier Bit 302" "0,1" textline " " bitfld.long 0x00 13. " GMB301 ,Group Modifier Bit 301" "0,1" bitfld.long 0x00 12. " GMB300 ,Group Modifier Bit 300" "0,1" bitfld.long 0x00 11. " GMB299 ,Group Modifier Bit 299" "0,1" textline " " bitfld.long 0x00 10. " GMB298 ,Group Modifier Bit 298" "0,1" bitfld.long 0x00 9. " GMB297 ,Group Modifier Bit 297" "0,1" bitfld.long 0x00 8. " GMB296 ,Group Modifier Bit 296" "0,1" textline " " bitfld.long 0x00 7. " GMB295 ,Group Modifier Bit 295" "0,1" bitfld.long 0x00 6. " GMB294 ,Group Modifier Bit 294" "0,1" bitfld.long 0x00 5. " GMB293 ,Group Modifier Bit 293" "0,1" textline " " bitfld.long 0x00 4. " GMB292 ,Group Modifier Bit 292" "0,1" bitfld.long 0x00 3. " GMB291 ,Group Modifier Bit 291" "0,1" bitfld.long 0x00 2. " GMB290 ,Group Modifier Bit 290" "0,1" textline " " bitfld.long 0x00 1. " GMB289 ,Group Modifier Bit 289" "0,1" bitfld.long 0x00 0. " GMB288 ,Group Modifier Bit 288" "0,1" else hgroup.long 0x0D24++0x03 hide.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D28))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)) group.long 0x0D28++0x03 line.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" bitfld.long 0x00 31. " GMB351 ,Group Modifier Bit 351" "0,1" bitfld.long 0x00 30. " GMB350 ,Group Modifier Bit 350" "0,1" bitfld.long 0x00 29. " GMB349 ,Group Modifier Bit 349" "0,1" textline " " bitfld.long 0x00 28. " GMB348 ,Group Modifier Bit 348" "0,1" bitfld.long 0x00 27. " GMB347 ,Group Modifier Bit 347" "0,1" bitfld.long 0x00 26. " GMB346 ,Group Modifier Bit 346" "0,1" textline " " bitfld.long 0x00 25. " GMB345 ,Group Modifier Bit 345" "0,1" bitfld.long 0x00 24. " GMB344 ,Group Modifier Bit 344" "0,1" bitfld.long 0x00 23. " GMB343 ,Group Modifier Bit 343" "0,1" textline " " bitfld.long 0x00 22. " GMB342 ,Group Modifier Bit 342" "0,1" bitfld.long 0x00 21. " GMB341 ,Group Modifier Bit 341" "0,1" bitfld.long 0x00 20. " GMB340 ,Group Modifier Bit 340" "0,1" textline " " bitfld.long 0x00 19. " GMB339 ,Group Modifier Bit 339" "0,1" bitfld.long 0x00 18. " GMB338 ,Group Modifier Bit 338" "0,1" bitfld.long 0x00 17. " GMB337 ,Group Modifier Bit 337" "0,1" textline " " bitfld.long 0x00 16. " GMB336 ,Group Modifier Bit 336" "0,1" bitfld.long 0x00 15. " GMB335 ,Group Modifier Bit 335" "0,1" bitfld.long 0x00 14. " GMB334 ,Group Modifier Bit 334" "0,1" textline " " bitfld.long 0x00 13. " GMB333 ,Group Modifier Bit 333" "0,1" bitfld.long 0x00 12. " GMB332 ,Group Modifier Bit 332" "0,1" bitfld.long 0x00 11. " GMB331 ,Group Modifier Bit 331" "0,1" textline " " bitfld.long 0x00 10. " GMB330 ,Group Modifier Bit 330" "0,1" bitfld.long 0x00 9. " GMB329 ,Group Modifier Bit 329" "0,1" bitfld.long 0x00 8. " GMB328 ,Group Modifier Bit 328" "0,1" textline " " bitfld.long 0x00 7. " GMB327 ,Group Modifier Bit 327" "0,1" bitfld.long 0x00 6. " GMB326 ,Group Modifier Bit 326" "0,1" bitfld.long 0x00 5. " GMB325 ,Group Modifier Bit 325" "0,1" textline " " bitfld.long 0x00 4. " GMB324 ,Group Modifier Bit 324" "0,1" bitfld.long 0x00 3. " GMB323 ,Group Modifier Bit 323" "0,1" bitfld.long 0x00 2. " GMB322 ,Group Modifier Bit 322" "0,1" textline " " bitfld.long 0x00 1. " GMB321 ,Group Modifier Bit 321" "0,1" bitfld.long 0x00 0. " GMB320 ,Group Modifier Bit 320" "0,1" else hgroup.long 0x0D28++0x03 hide.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D2C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)) group.long 0x0D2C++0x03 line.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" bitfld.long 0x00 31. " GMB383 ,Group Modifier Bit 383" "0,1" bitfld.long 0x00 30. " GMB382 ,Group Modifier Bit 382" "0,1" bitfld.long 0x00 29. " GMB381 ,Group Modifier Bit 381" "0,1" textline " " bitfld.long 0x00 28. " GMB380 ,Group Modifier Bit 380" "0,1" bitfld.long 0x00 27. " GMB379 ,Group Modifier Bit 379" "0,1" bitfld.long 0x00 26. " GMB378 ,Group Modifier Bit 378" "0,1" textline " " bitfld.long 0x00 25. " GMB377 ,Group Modifier Bit 377" "0,1" bitfld.long 0x00 24. " GMB376 ,Group Modifier Bit 376" "0,1" bitfld.long 0x00 23. " GMB375 ,Group Modifier Bit 375" "0,1" textline " " bitfld.long 0x00 22. " GMB374 ,Group Modifier Bit 374" "0,1" bitfld.long 0x00 21. " GMB373 ,Group Modifier Bit 373" "0,1" bitfld.long 0x00 20. " GMB372 ,Group Modifier Bit 372" "0,1" textline " " bitfld.long 0x00 19. " GMB371 ,Group Modifier Bit 371" "0,1" bitfld.long 0x00 18. " GMB370 ,Group Modifier Bit 370" "0,1" bitfld.long 0x00 17. " GMB369 ,Group Modifier Bit 369" "0,1" textline " " bitfld.long 0x00 16. " GMB368 ,Group Modifier Bit 368" "0,1" bitfld.long 0x00 15. " GMB367 ,Group Modifier Bit 367" "0,1" bitfld.long 0x00 14. " GMB366 ,Group Modifier Bit 366" "0,1" textline " " bitfld.long 0x00 13. " GMB365 ,Group Modifier Bit 365" "0,1" bitfld.long 0x00 12. " GMB364 ,Group Modifier Bit 364" "0,1" bitfld.long 0x00 11. " GMB363 ,Group Modifier Bit 363" "0,1" textline " " bitfld.long 0x00 10. " GMB362 ,Group Modifier Bit 362" "0,1" bitfld.long 0x00 9. " GMB361 ,Group Modifier Bit 361" "0,1" bitfld.long 0x00 8. " GMB360 ,Group Modifier Bit 360" "0,1" textline " " bitfld.long 0x00 7. " GMB359 ,Group Modifier Bit 359" "0,1" bitfld.long 0x00 6. " GMB358 ,Group Modifier Bit 358" "0,1" bitfld.long 0x00 5. " GMB357 ,Group Modifier Bit 357" "0,1" textline " " bitfld.long 0x00 4. " GMB356 ,Group Modifier Bit 356" "0,1" bitfld.long 0x00 3. " GMB355 ,Group Modifier Bit 355" "0,1" bitfld.long 0x00 2. " GMB354 ,Group Modifier Bit 354" "0,1" textline " " bitfld.long 0x00 1. " GMB353 ,Group Modifier Bit 353" "0,1" bitfld.long 0x00 0. " GMB352 ,Group Modifier Bit 352" "0,1" else hgroup.long 0x0D2C++0x03 hide.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D30))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)) group.long 0x0D30++0x03 line.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" bitfld.long 0x00 31. " GMB415 ,Group Modifier Bit 415" "0,1" bitfld.long 0x00 30. " GMB414 ,Group Modifier Bit 414" "0,1" bitfld.long 0x00 29. " GMB413 ,Group Modifier Bit 413" "0,1" textline " " bitfld.long 0x00 28. " GMB412 ,Group Modifier Bit 412" "0,1" bitfld.long 0x00 27. " GMB411 ,Group Modifier Bit 411" "0,1" bitfld.long 0x00 26. " GMB410 ,Group Modifier Bit 410" "0,1" textline " " bitfld.long 0x00 25. " GMB409 ,Group Modifier Bit 409" "0,1" bitfld.long 0x00 24. " GMB408 ,Group Modifier Bit 408" "0,1" bitfld.long 0x00 23. " GMB407 ,Group Modifier Bit 407" "0,1" textline " " bitfld.long 0x00 22. " GMB406 ,Group Modifier Bit 406" "0,1" bitfld.long 0x00 21. " GMB405 ,Group Modifier Bit 405" "0,1" bitfld.long 0x00 20. " GMB404 ,Group Modifier Bit 404" "0,1" textline " " bitfld.long 0x00 19. " GMB403 ,Group Modifier Bit 403" "0,1" bitfld.long 0x00 18. " GMB402 ,Group Modifier Bit 402" "0,1" bitfld.long 0x00 17. " GMB401 ,Group Modifier Bit 401" "0,1" textline " " bitfld.long 0x00 16. " GMB400 ,Group Modifier Bit 400" "0,1" bitfld.long 0x00 15. " GMB399 ,Group Modifier Bit 399" "0,1" bitfld.long 0x00 14. " GMB398 ,Group Modifier Bit 398" "0,1" textline " " bitfld.long 0x00 13. " GMB397 ,Group Modifier Bit 397" "0,1" bitfld.long 0x00 12. " GMB396 ,Group Modifier Bit 396" "0,1" bitfld.long 0x00 11. " GMB395 ,Group Modifier Bit 395" "0,1" textline " " bitfld.long 0x00 10. " GMB394 ,Group Modifier Bit 394" "0,1" bitfld.long 0x00 9. " GMB393 ,Group Modifier Bit 393" "0,1" bitfld.long 0x00 8. " GMB392 ,Group Modifier Bit 392" "0,1" textline " " bitfld.long 0x00 7. " GMB391 ,Group Modifier Bit 391" "0,1" bitfld.long 0x00 6. " GMB390 ,Group Modifier Bit 390" "0,1" bitfld.long 0x00 5. " GMB389 ,Group Modifier Bit 389" "0,1" textline " " bitfld.long 0x00 4. " GMB388 ,Group Modifier Bit 388" "0,1" bitfld.long 0x00 3. " GMB387 ,Group Modifier Bit 387" "0,1" bitfld.long 0x00 2. " GMB386 ,Group Modifier Bit 386" "0,1" textline " " bitfld.long 0x00 1. " GMB385 ,Group Modifier Bit 385" "0,1" bitfld.long 0x00 0. " GMB384 ,Group Modifier Bit 384" "0,1" else hgroup.long 0x0D30++0x03 hide.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D34))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)) group.long 0x0D34++0x03 line.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" bitfld.long 0x00 31. " GMB447 ,Group Modifier Bit 447" "0,1" bitfld.long 0x00 30. " GMB446 ,Group Modifier Bit 446" "0,1" bitfld.long 0x00 29. " GMB445 ,Group Modifier Bit 445" "0,1" textline " " bitfld.long 0x00 28. " GMB444 ,Group Modifier Bit 444" "0,1" bitfld.long 0x00 27. " GMB443 ,Group Modifier Bit 443" "0,1" bitfld.long 0x00 26. " GMB442 ,Group Modifier Bit 442" "0,1" textline " " bitfld.long 0x00 25. " GMB441 ,Group Modifier Bit 441" "0,1" bitfld.long 0x00 24. " GMB440 ,Group Modifier Bit 440" "0,1" bitfld.long 0x00 23. " GMB439 ,Group Modifier Bit 439" "0,1" textline " " bitfld.long 0x00 22. " GMB438 ,Group Modifier Bit 438" "0,1" bitfld.long 0x00 21. " GMB437 ,Group Modifier Bit 437" "0,1" bitfld.long 0x00 20. " GMB436 ,Group Modifier Bit 436" "0,1" textline " " bitfld.long 0x00 19. " GMB435 ,Group Modifier Bit 435" "0,1" bitfld.long 0x00 18. " GMB434 ,Group Modifier Bit 434" "0,1" bitfld.long 0x00 17. " GMB433 ,Group Modifier Bit 433" "0,1" textline " " bitfld.long 0x00 16. " GMB432 ,Group Modifier Bit 432" "0,1" bitfld.long 0x00 15. " GMB431 ,Group Modifier Bit 431" "0,1" bitfld.long 0x00 14. " GMB430 ,Group Modifier Bit 430" "0,1" textline " " bitfld.long 0x00 13. " GMB429 ,Group Modifier Bit 429" "0,1" bitfld.long 0x00 12. " GMB428 ,Group Modifier Bit 428" "0,1" bitfld.long 0x00 11. " GMB427 ,Group Modifier Bit 427" "0,1" textline " " bitfld.long 0x00 10. " GMB426 ,Group Modifier Bit 426" "0,1" bitfld.long 0x00 9. " GMB425 ,Group Modifier Bit 425" "0,1" bitfld.long 0x00 8. " GMB424 ,Group Modifier Bit 424" "0,1" textline " " bitfld.long 0x00 7. " GMB423 ,Group Modifier Bit 423" "0,1" bitfld.long 0x00 6. " GMB422 ,Group Modifier Bit 422" "0,1" bitfld.long 0x00 5. " GMB421 ,Group Modifier Bit 421" "0,1" textline " " bitfld.long 0x00 4. " GMB420 ,Group Modifier Bit 420" "0,1" bitfld.long 0x00 3. " GMB419 ,Group Modifier Bit 419" "0,1" bitfld.long 0x00 2. " GMB418 ,Group Modifier Bit 418" "0,1" textline " " bitfld.long 0x00 1. " GMB417 ,Group Modifier Bit 417" "0,1" bitfld.long 0x00 0. " GMB416 ,Group Modifier Bit 416" "0,1" else hgroup.long 0x0D34++0x03 hide.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D38))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)) group.long 0x0D38++0x03 line.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" bitfld.long 0x00 31. " GMB479 ,Group Modifier Bit 479" "0,1" bitfld.long 0x00 30. " GMB478 ,Group Modifier Bit 478" "0,1" bitfld.long 0x00 29. " GMB477 ,Group Modifier Bit 477" "0,1" textline " " bitfld.long 0x00 28. " GMB476 ,Group Modifier Bit 476" "0,1" bitfld.long 0x00 27. " GMB475 ,Group Modifier Bit 475" "0,1" bitfld.long 0x00 26. " GMB474 ,Group Modifier Bit 474" "0,1" textline " " bitfld.long 0x00 25. " GMB473 ,Group Modifier Bit 473" "0,1" bitfld.long 0x00 24. " GMB472 ,Group Modifier Bit 472" "0,1" bitfld.long 0x00 23. " GMB471 ,Group Modifier Bit 471" "0,1" textline " " bitfld.long 0x00 22. " GMB470 ,Group Modifier Bit 470" "0,1" bitfld.long 0x00 21. " GMB469 ,Group Modifier Bit 469" "0,1" bitfld.long 0x00 20. " GMB468 ,Group Modifier Bit 468" "0,1" textline " " bitfld.long 0x00 19. " GMB467 ,Group Modifier Bit 467" "0,1" bitfld.long 0x00 18. " GMB466 ,Group Modifier Bit 466" "0,1" bitfld.long 0x00 17. " GMB465 ,Group Modifier Bit 465" "0,1" textline " " bitfld.long 0x00 16. " GMB464 ,Group Modifier Bit 464" "0,1" bitfld.long 0x00 15. " GMB463 ,Group Modifier Bit 463" "0,1" bitfld.long 0x00 14. " GMB462 ,Group Modifier Bit 462" "0,1" textline " " bitfld.long 0x00 13. " GMB461 ,Group Modifier Bit 461" "0,1" bitfld.long 0x00 12. " GMB460 ,Group Modifier Bit 460" "0,1" bitfld.long 0x00 11. " GMB459 ,Group Modifier Bit 459" "0,1" textline " " bitfld.long 0x00 10. " GMB458 ,Group Modifier Bit 458" "0,1" bitfld.long 0x00 9. " GMB457 ,Group Modifier Bit 457" "0,1" bitfld.long 0x00 8. " GMB456 ,Group Modifier Bit 456" "0,1" textline " " bitfld.long 0x00 7. " GMB455 ,Group Modifier Bit 455" "0,1" bitfld.long 0x00 6. " GMB454 ,Group Modifier Bit 454" "0,1" bitfld.long 0x00 5. " GMB453 ,Group Modifier Bit 453" "0,1" textline " " bitfld.long 0x00 4. " GMB452 ,Group Modifier Bit 452" "0,1" bitfld.long 0x00 3. " GMB451 ,Group Modifier Bit 451" "0,1" bitfld.long 0x00 2. " GMB450 ,Group Modifier Bit 450" "0,1" textline " " bitfld.long 0x00 1. " GMB449 ,Group Modifier Bit 449" "0,1" bitfld.long 0x00 0. " GMB448 ,Group Modifier Bit 448" "0,1" else hgroup.long 0x0D38++0x03 hide.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D3C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)) group.long 0x0D3C++0x03 line.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" bitfld.long 0x00 31. " GMB511 ,Group Modifier Bit 511" "0,1" bitfld.long 0x00 30. " GMB510 ,Group Modifier Bit 510" "0,1" bitfld.long 0x00 29. " GMB509 ,Group Modifier Bit 509" "0,1" textline " " bitfld.long 0x00 28. " GMB508 ,Group Modifier Bit 508" "0,1" bitfld.long 0x00 27. " GMB507 ,Group Modifier Bit 507" "0,1" bitfld.long 0x00 26. " GMB506 ,Group Modifier Bit 506" "0,1" textline " " bitfld.long 0x00 25. " GMB505 ,Group Modifier Bit 505" "0,1" bitfld.long 0x00 24. " GMB504 ,Group Modifier Bit 504" "0,1" bitfld.long 0x00 23. " GMB503 ,Group Modifier Bit 503" "0,1" textline " " bitfld.long 0x00 22. " GMB502 ,Group Modifier Bit 502" "0,1" bitfld.long 0x00 21. " GMB501 ,Group Modifier Bit 501" "0,1" bitfld.long 0x00 20. " GMB500 ,Group Modifier Bit 500" "0,1" textline " " bitfld.long 0x00 19. " GMB499 ,Group Modifier Bit 499" "0,1" bitfld.long 0x00 18. " GMB498 ,Group Modifier Bit 498" "0,1" bitfld.long 0x00 17. " GMB497 ,Group Modifier Bit 497" "0,1" textline " " bitfld.long 0x00 16. " GMB496 ,Group Modifier Bit 496" "0,1" bitfld.long 0x00 15. " GMB495 ,Group Modifier Bit 495" "0,1" bitfld.long 0x00 14. " GMB494 ,Group Modifier Bit 494" "0,1" textline " " bitfld.long 0x00 13. " GMB493 ,Group Modifier Bit 493" "0,1" bitfld.long 0x00 12. " GMB492 ,Group Modifier Bit 492" "0,1" bitfld.long 0x00 11. " GMB491 ,Group Modifier Bit 491" "0,1" textline " " bitfld.long 0x00 10. " GMB490 ,Group Modifier Bit 490" "0,1" bitfld.long 0x00 9. " GMB489 ,Group Modifier Bit 489" "0,1" bitfld.long 0x00 8. " GMB488 ,Group Modifier Bit 488" "0,1" textline " " bitfld.long 0x00 7. " GMB487 ,Group Modifier Bit 487" "0,1" bitfld.long 0x00 6. " GMB486 ,Group Modifier Bit 486" "0,1" bitfld.long 0x00 5. " GMB485 ,Group Modifier Bit 485" "0,1" textline " " bitfld.long 0x00 4. " GMB484 ,Group Modifier Bit 484" "0,1" bitfld.long 0x00 3. " GMB483 ,Group Modifier Bit 483" "0,1" bitfld.long 0x00 2. " GMB482 ,Group Modifier Bit 482" "0,1" textline " " bitfld.long 0x00 1. " GMB481 ,Group Modifier Bit 481" "0,1" bitfld.long 0x00 0. " GMB480 ,Group Modifier Bit 480" "0,1" else hgroup.long 0x0D3C++0x03 hide.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D40))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x0D40++0x03 line.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" bitfld.long 0x00 31. " GMB543 ,Group Modifier Bit 543" "0,1" bitfld.long 0x00 30. " GMB542 ,Group Modifier Bit 542" "0,1" bitfld.long 0x00 29. " GMB541 ,Group Modifier Bit 541" "0,1" textline " " bitfld.long 0x00 28. " GMB540 ,Group Modifier Bit 540" "0,1" bitfld.long 0x00 27. " GMB539 ,Group Modifier Bit 539" "0,1" bitfld.long 0x00 26. " GMB538 ,Group Modifier Bit 538" "0,1" textline " " bitfld.long 0x00 25. " GMB537 ,Group Modifier Bit 537" "0,1" bitfld.long 0x00 24. " GMB536 ,Group Modifier Bit 536" "0,1" bitfld.long 0x00 23. " GMB535 ,Group Modifier Bit 535" "0,1" textline " " bitfld.long 0x00 22. " GMB534 ,Group Modifier Bit 534" "0,1" bitfld.long 0x00 21. " GMB533 ,Group Modifier Bit 533" "0,1" bitfld.long 0x00 20. " GMB532 ,Group Modifier Bit 532" "0,1" textline " " bitfld.long 0x00 19. " GMB531 ,Group Modifier Bit 531" "0,1" bitfld.long 0x00 18. " GMB530 ,Group Modifier Bit 530" "0,1" bitfld.long 0x00 17. " GMB529 ,Group Modifier Bit 529" "0,1" textline " " bitfld.long 0x00 16. " GMB528 ,Group Modifier Bit 528" "0,1" bitfld.long 0x00 15. " GMB527 ,Group Modifier Bit 527" "0,1" bitfld.long 0x00 14. " GMB526 ,Group Modifier Bit 526" "0,1" textline " " bitfld.long 0x00 13. " GMB525 ,Group Modifier Bit 525" "0,1" bitfld.long 0x00 12. " GMB524 ,Group Modifier Bit 524" "0,1" bitfld.long 0x00 11. " GMB523 ,Group Modifier Bit 523" "0,1" textline " " bitfld.long 0x00 10. " GMB522 ,Group Modifier Bit 522" "0,1" bitfld.long 0x00 9. " GMB521 ,Group Modifier Bit 521" "0,1" bitfld.long 0x00 8. " GMB520 ,Group Modifier Bit 520" "0,1" textline " " bitfld.long 0x00 7. " GMB519 ,Group Modifier Bit 519" "0,1" bitfld.long 0x00 6. " GMB518 ,Group Modifier Bit 518" "0,1" bitfld.long 0x00 5. " GMB517 ,Group Modifier Bit 517" "0,1" textline " " bitfld.long 0x00 4. " GMB516 ,Group Modifier Bit 516" "0,1" bitfld.long 0x00 3. " GMB515 ,Group Modifier Bit 515" "0,1" bitfld.long 0x00 2. " GMB514 ,Group Modifier Bit 514" "0,1" textline " " bitfld.long 0x00 1. " GMB513 ,Group Modifier Bit 513" "0,1" bitfld.long 0x00 0. " GMB512 ,Group Modifier Bit 512" "0,1" else hgroup.long 0x0D40++0x03 hide.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D44))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x0D44++0x03 line.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" bitfld.long 0x00 31. " GMB575 ,Group Modifier Bit 575" "0,1" bitfld.long 0x00 30. " GMB574 ,Group Modifier Bit 574" "0,1" bitfld.long 0x00 29. " GMB573 ,Group Modifier Bit 573" "0,1" textline " " bitfld.long 0x00 28. " GMB572 ,Group Modifier Bit 572" "0,1" bitfld.long 0x00 27. " GMB571 ,Group Modifier Bit 571" "0,1" bitfld.long 0x00 26. " GMB570 ,Group Modifier Bit 570" "0,1" textline " " bitfld.long 0x00 25. " GMB569 ,Group Modifier Bit 569" "0,1" bitfld.long 0x00 24. " GMB568 ,Group Modifier Bit 568" "0,1" bitfld.long 0x00 23. " GMB567 ,Group Modifier Bit 567" "0,1" textline " " bitfld.long 0x00 22. " GMB566 ,Group Modifier Bit 566" "0,1" bitfld.long 0x00 21. " GMB565 ,Group Modifier Bit 565" "0,1" bitfld.long 0x00 20. " GMB564 ,Group Modifier Bit 564" "0,1" textline " " bitfld.long 0x00 19. " GMB563 ,Group Modifier Bit 563" "0,1" bitfld.long 0x00 18. " GMB562 ,Group Modifier Bit 562" "0,1" bitfld.long 0x00 17. " GMB561 ,Group Modifier Bit 561" "0,1" textline " " bitfld.long 0x00 16. " GMB560 ,Group Modifier Bit 560" "0,1" bitfld.long 0x00 15. " GMB559 ,Group Modifier Bit 559" "0,1" bitfld.long 0x00 14. " GMB558 ,Group Modifier Bit 558" "0,1" textline " " bitfld.long 0x00 13. " GMB557 ,Group Modifier Bit 557" "0,1" bitfld.long 0x00 12. " GMB556 ,Group Modifier Bit 556" "0,1" bitfld.long 0x00 11. " GMB555 ,Group Modifier Bit 555" "0,1" textline " " bitfld.long 0x00 10. " GMB554 ,Group Modifier Bit 554" "0,1" bitfld.long 0x00 9. " GMB553 ,Group Modifier Bit 553" "0,1" bitfld.long 0x00 8. " GMB552 ,Group Modifier Bit 552" "0,1" textline " " bitfld.long 0x00 7. " GMB551 ,Group Modifier Bit 551" "0,1" bitfld.long 0x00 6. " GMB550 ,Group Modifier Bit 550" "0,1" bitfld.long 0x00 5. " GMB549 ,Group Modifier Bit 549" "0,1" textline " " bitfld.long 0x00 4. " GMB548 ,Group Modifier Bit 548" "0,1" bitfld.long 0x00 3. " GMB547 ,Group Modifier Bit 547" "0,1" bitfld.long 0x00 2. " GMB546 ,Group Modifier Bit 546" "0,1" textline " " bitfld.long 0x00 1. " GMB545 ,Group Modifier Bit 545" "0,1" bitfld.long 0x00 0. " GMB544 ,Group Modifier Bit 544" "0,1" else hgroup.long 0x0D44++0x03 hide.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D48))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x0D48++0x03 line.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" bitfld.long 0x00 31. " GMB607 ,Group Modifier Bit 607" "0,1" bitfld.long 0x00 30. " GMB606 ,Group Modifier Bit 606" "0,1" bitfld.long 0x00 29. " GMB605 ,Group Modifier Bit 605" "0,1" textline " " bitfld.long 0x00 28. " GMB604 ,Group Modifier Bit 604" "0,1" bitfld.long 0x00 27. " GMB603 ,Group Modifier Bit 603" "0,1" bitfld.long 0x00 26. " GMB602 ,Group Modifier Bit 602" "0,1" textline " " bitfld.long 0x00 25. " GMB601 ,Group Modifier Bit 601" "0,1" bitfld.long 0x00 24. " GMB600 ,Group Modifier Bit 600" "0,1" bitfld.long 0x00 23. " GMB599 ,Group Modifier Bit 599" "0,1" textline " " bitfld.long 0x00 22. " GMB598 ,Group Modifier Bit 598" "0,1" bitfld.long 0x00 21. " GMB597 ,Group Modifier Bit 597" "0,1" bitfld.long 0x00 20. " GMB596 ,Group Modifier Bit 596" "0,1" textline " " bitfld.long 0x00 19. " GMB595 ,Group Modifier Bit 595" "0,1" bitfld.long 0x00 18. " GMB594 ,Group Modifier Bit 594" "0,1" bitfld.long 0x00 17. " GMB593 ,Group Modifier Bit 593" "0,1" textline " " bitfld.long 0x00 16. " GMB592 ,Group Modifier Bit 592" "0,1" bitfld.long 0x00 15. " GMB591 ,Group Modifier Bit 591" "0,1" bitfld.long 0x00 14. " GMB590 ,Group Modifier Bit 590" "0,1" textline " " bitfld.long 0x00 13. " GMB589 ,Group Modifier Bit 589" "0,1" bitfld.long 0x00 12. " GMB588 ,Group Modifier Bit 588" "0,1" bitfld.long 0x00 11. " GMB587 ,Group Modifier Bit 587" "0,1" textline " " bitfld.long 0x00 10. " GMB586 ,Group Modifier Bit 586" "0,1" bitfld.long 0x00 9. " GMB585 ,Group Modifier Bit 585" "0,1" bitfld.long 0x00 8. " GMB584 ,Group Modifier Bit 584" "0,1" textline " " bitfld.long 0x00 7. " GMB583 ,Group Modifier Bit 583" "0,1" bitfld.long 0x00 6. " GMB582 ,Group Modifier Bit 582" "0,1" bitfld.long 0x00 5. " GMB581 ,Group Modifier Bit 581" "0,1" textline " " bitfld.long 0x00 4. " GMB580 ,Group Modifier Bit 580" "0,1" bitfld.long 0x00 3. " GMB579 ,Group Modifier Bit 579" "0,1" bitfld.long 0x00 2. " GMB578 ,Group Modifier Bit 578" "0,1" textline " " bitfld.long 0x00 1. " GMB577 ,Group Modifier Bit 577" "0,1" bitfld.long 0x00 0. " GMB576 ,Group Modifier Bit 576" "0,1" else hgroup.long 0x0D48++0x03 hide.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D4C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x0D4C++0x03 line.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" bitfld.long 0x00 31. " GMB639 ,Group Modifier Bit 639" "0,1" bitfld.long 0x00 30. " GMB638 ,Group Modifier Bit 638" "0,1" bitfld.long 0x00 29. " GMB637 ,Group Modifier Bit 637" "0,1" textline " " bitfld.long 0x00 28. " GMB636 ,Group Modifier Bit 636" "0,1" bitfld.long 0x00 27. " GMB635 ,Group Modifier Bit 635" "0,1" bitfld.long 0x00 26. " GMB634 ,Group Modifier Bit 634" "0,1" textline " " bitfld.long 0x00 25. " GMB633 ,Group Modifier Bit 633" "0,1" bitfld.long 0x00 24. " GMB632 ,Group Modifier Bit 632" "0,1" bitfld.long 0x00 23. " GMB631 ,Group Modifier Bit 631" "0,1" textline " " bitfld.long 0x00 22. " GMB630 ,Group Modifier Bit 630" "0,1" bitfld.long 0x00 21. " GMB629 ,Group Modifier Bit 629" "0,1" bitfld.long 0x00 20. " GMB628 ,Group Modifier Bit 628" "0,1" textline " " bitfld.long 0x00 19. " GMB627 ,Group Modifier Bit 627" "0,1" bitfld.long 0x00 18. " GMB626 ,Group Modifier Bit 626" "0,1" bitfld.long 0x00 17. " GMB625 ,Group Modifier Bit 625" "0,1" textline " " bitfld.long 0x00 16. " GMB624 ,Group Modifier Bit 624" "0,1" bitfld.long 0x00 15. " GMB623 ,Group Modifier Bit 623" "0,1" bitfld.long 0x00 14. " GMB622 ,Group Modifier Bit 622" "0,1" textline " " bitfld.long 0x00 13. " GMB621 ,Group Modifier Bit 621" "0,1" bitfld.long 0x00 12. " GMB620 ,Group Modifier Bit 620" "0,1" bitfld.long 0x00 11. " GMB619 ,Group Modifier Bit 619" "0,1" textline " " bitfld.long 0x00 10. " GMB618 ,Group Modifier Bit 618" "0,1" bitfld.long 0x00 9. " GMB617 ,Group Modifier Bit 617" "0,1" bitfld.long 0x00 8. " GMB616 ,Group Modifier Bit 616" "0,1" textline " " bitfld.long 0x00 7. " GMB615 ,Group Modifier Bit 615" "0,1" bitfld.long 0x00 6. " GMB614 ,Group Modifier Bit 614" "0,1" bitfld.long 0x00 5. " GMB613 ,Group Modifier Bit 613" "0,1" textline " " bitfld.long 0x00 4. " GMB612 ,Group Modifier Bit 612" "0,1" bitfld.long 0x00 3. " GMB611 ,Group Modifier Bit 611" "0,1" bitfld.long 0x00 2. " GMB610 ,Group Modifier Bit 610" "0,1" textline " " bitfld.long 0x00 1. " GMB609 ,Group Modifier Bit 609" "0,1" bitfld.long 0x00 0. " GMB608 ,Group Modifier Bit 608" "0,1" else hgroup.long 0x0D4C++0x03 hide.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D50))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x0D50++0x03 line.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" bitfld.long 0x00 31. " GMB671 ,Group Modifier Bit 671" "0,1" bitfld.long 0x00 30. " GMB670 ,Group Modifier Bit 670" "0,1" bitfld.long 0x00 29. " GMB669 ,Group Modifier Bit 669" "0,1" textline " " bitfld.long 0x00 28. " GMB668 ,Group Modifier Bit 668" "0,1" bitfld.long 0x00 27. " GMB667 ,Group Modifier Bit 667" "0,1" bitfld.long 0x00 26. " GMB666 ,Group Modifier Bit 666" "0,1" textline " " bitfld.long 0x00 25. " GMB665 ,Group Modifier Bit 665" "0,1" bitfld.long 0x00 24. " GMB664 ,Group Modifier Bit 664" "0,1" bitfld.long 0x00 23. " GMB663 ,Group Modifier Bit 663" "0,1" textline " " bitfld.long 0x00 22. " GMB662 ,Group Modifier Bit 662" "0,1" bitfld.long 0x00 21. " GMB661 ,Group Modifier Bit 661" "0,1" bitfld.long 0x00 20. " GMB660 ,Group Modifier Bit 660" "0,1" textline " " bitfld.long 0x00 19. " GMB659 ,Group Modifier Bit 659" "0,1" bitfld.long 0x00 18. " GMB658 ,Group Modifier Bit 658" "0,1" bitfld.long 0x00 17. " GMB657 ,Group Modifier Bit 657" "0,1" textline " " bitfld.long 0x00 16. " GMB656 ,Group Modifier Bit 656" "0,1" bitfld.long 0x00 15. " GMB655 ,Group Modifier Bit 655" "0,1" bitfld.long 0x00 14. " GMB654 ,Group Modifier Bit 654" "0,1" textline " " bitfld.long 0x00 13. " GMB653 ,Group Modifier Bit 653" "0,1" bitfld.long 0x00 12. " GMB652 ,Group Modifier Bit 652" "0,1" bitfld.long 0x00 11. " GMB651 ,Group Modifier Bit 651" "0,1" textline " " bitfld.long 0x00 10. " GMB650 ,Group Modifier Bit 650" "0,1" bitfld.long 0x00 9. " GMB649 ,Group Modifier Bit 649" "0,1" bitfld.long 0x00 8. " GMB648 ,Group Modifier Bit 648" "0,1" textline " " bitfld.long 0x00 7. " GMB647 ,Group Modifier Bit 647" "0,1" bitfld.long 0x00 6. " GMB646 ,Group Modifier Bit 646" "0,1" bitfld.long 0x00 5. " GMB645 ,Group Modifier Bit 645" "0,1" textline " " bitfld.long 0x00 4. " GMB644 ,Group Modifier Bit 644" "0,1" bitfld.long 0x00 3. " GMB643 ,Group Modifier Bit 643" "0,1" bitfld.long 0x00 2. " GMB642 ,Group Modifier Bit 642" "0,1" textline " " bitfld.long 0x00 1. " GMB641 ,Group Modifier Bit 641" "0,1" bitfld.long 0x00 0. " GMB640 ,Group Modifier Bit 640" "0,1" else hgroup.long 0x0D50++0x03 hide.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D54))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x0D54++0x03 line.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" bitfld.long 0x00 31. " GMB703 ,Group Modifier Bit 703" "0,1" bitfld.long 0x00 30. " GMB702 ,Group Modifier Bit 702" "0,1" bitfld.long 0x00 29. " GMB701 ,Group Modifier Bit 701" "0,1" textline " " bitfld.long 0x00 28. " GMB700 ,Group Modifier Bit 700" "0,1" bitfld.long 0x00 27. " GMB699 ,Group Modifier Bit 699" "0,1" bitfld.long 0x00 26. " GMB698 ,Group Modifier Bit 698" "0,1" textline " " bitfld.long 0x00 25. " GMB697 ,Group Modifier Bit 697" "0,1" bitfld.long 0x00 24. " GMB696 ,Group Modifier Bit 696" "0,1" bitfld.long 0x00 23. " GMB695 ,Group Modifier Bit 695" "0,1" textline " " bitfld.long 0x00 22. " GMB694 ,Group Modifier Bit 694" "0,1" bitfld.long 0x00 21. " GMB693 ,Group Modifier Bit 693" "0,1" bitfld.long 0x00 20. " GMB692 ,Group Modifier Bit 692" "0,1" textline " " bitfld.long 0x00 19. " GMB691 ,Group Modifier Bit 691" "0,1" bitfld.long 0x00 18. " GMB690 ,Group Modifier Bit 690" "0,1" bitfld.long 0x00 17. " GMB689 ,Group Modifier Bit 689" "0,1" textline " " bitfld.long 0x00 16. " GMB688 ,Group Modifier Bit 688" "0,1" bitfld.long 0x00 15. " GMB687 ,Group Modifier Bit 687" "0,1" bitfld.long 0x00 14. " GMB686 ,Group Modifier Bit 686" "0,1" textline " " bitfld.long 0x00 13. " GMB685 ,Group Modifier Bit 685" "0,1" bitfld.long 0x00 12. " GMB684 ,Group Modifier Bit 684" "0,1" bitfld.long 0x00 11. " GMB683 ,Group Modifier Bit 683" "0,1" textline " " bitfld.long 0x00 10. " GMB682 ,Group Modifier Bit 682" "0,1" bitfld.long 0x00 9. " GMB681 ,Group Modifier Bit 681" "0,1" bitfld.long 0x00 8. " GMB680 ,Group Modifier Bit 680" "0,1" textline " " bitfld.long 0x00 7. " GMB679 ,Group Modifier Bit 679" "0,1" bitfld.long 0x00 6. " GMB678 ,Group Modifier Bit 678" "0,1" bitfld.long 0x00 5. " GMB677 ,Group Modifier Bit 677" "0,1" textline " " bitfld.long 0x00 4. " GMB676 ,Group Modifier Bit 676" "0,1" bitfld.long 0x00 3. " GMB675 ,Group Modifier Bit 675" "0,1" bitfld.long 0x00 2. " GMB674 ,Group Modifier Bit 674" "0,1" textline " " bitfld.long 0x00 1. " GMB673 ,Group Modifier Bit 673" "0,1" bitfld.long 0x00 0. " GMB672 ,Group Modifier Bit 672" "0,1" else hgroup.long 0x0D54++0x03 hide.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D58))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x0D58++0x03 line.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" bitfld.long 0x00 31. " GMB735 ,Group Modifier Bit 735" "0,1" bitfld.long 0x00 30. " GMB734 ,Group Modifier Bit 734" "0,1" bitfld.long 0x00 29. " GMB733 ,Group Modifier Bit 733" "0,1" textline " " bitfld.long 0x00 28. " GMB732 ,Group Modifier Bit 732" "0,1" bitfld.long 0x00 27. " GMB731 ,Group Modifier Bit 731" "0,1" bitfld.long 0x00 26. " GMB730 ,Group Modifier Bit 730" "0,1" textline " " bitfld.long 0x00 25. " GMB729 ,Group Modifier Bit 729" "0,1" bitfld.long 0x00 24. " GMB728 ,Group Modifier Bit 728" "0,1" bitfld.long 0x00 23. " GMB727 ,Group Modifier Bit 727" "0,1" textline " " bitfld.long 0x00 22. " GMB726 ,Group Modifier Bit 726" "0,1" bitfld.long 0x00 21. " GMB725 ,Group Modifier Bit 725" "0,1" bitfld.long 0x00 20. " GMB724 ,Group Modifier Bit 724" "0,1" textline " " bitfld.long 0x00 19. " GMB723 ,Group Modifier Bit 723" "0,1" bitfld.long 0x00 18. " GMB722 ,Group Modifier Bit 722" "0,1" bitfld.long 0x00 17. " GMB721 ,Group Modifier Bit 721" "0,1" textline " " bitfld.long 0x00 16. " GMB720 ,Group Modifier Bit 720" "0,1" bitfld.long 0x00 15. " GMB719 ,Group Modifier Bit 719" "0,1" bitfld.long 0x00 14. " GMB718 ,Group Modifier Bit 718" "0,1" textline " " bitfld.long 0x00 13. " GMB717 ,Group Modifier Bit 717" "0,1" bitfld.long 0x00 12. " GMB716 ,Group Modifier Bit 716" "0,1" bitfld.long 0x00 11. " GMB715 ,Group Modifier Bit 715" "0,1" textline " " bitfld.long 0x00 10. " GMB714 ,Group Modifier Bit 714" "0,1" bitfld.long 0x00 9. " GMB713 ,Group Modifier Bit 713" "0,1" bitfld.long 0x00 8. " GMB712 ,Group Modifier Bit 712" "0,1" textline " " bitfld.long 0x00 7. " GMB711 ,Group Modifier Bit 711" "0,1" bitfld.long 0x00 6. " GMB710 ,Group Modifier Bit 710" "0,1" bitfld.long 0x00 5. " GMB709 ,Group Modifier Bit 709" "0,1" textline " " bitfld.long 0x00 4. " GMB708 ,Group Modifier Bit 708" "0,1" bitfld.long 0x00 3. " GMB707 ,Group Modifier Bit 707" "0,1" bitfld.long 0x00 2. " GMB706 ,Group Modifier Bit 706" "0,1" textline " " bitfld.long 0x00 1. " GMB705 ,Group Modifier Bit 705" "0,1" bitfld.long 0x00 0. " GMB704 ,Group Modifier Bit 704" "0,1" else hgroup.long 0x0D58++0x03 hide.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D5C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x0D5C++0x03 line.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" bitfld.long 0x00 31. " GMB767 ,Group Modifier Bit 767" "0,1" bitfld.long 0x00 30. " GMB766 ,Group Modifier Bit 766" "0,1" bitfld.long 0x00 29. " GMB765 ,Group Modifier Bit 765" "0,1" textline " " bitfld.long 0x00 28. " GMB764 ,Group Modifier Bit 764" "0,1" bitfld.long 0x00 27. " GMB763 ,Group Modifier Bit 763" "0,1" bitfld.long 0x00 26. " GMB762 ,Group Modifier Bit 762" "0,1" textline " " bitfld.long 0x00 25. " GMB761 ,Group Modifier Bit 761" "0,1" bitfld.long 0x00 24. " GMB760 ,Group Modifier Bit 760" "0,1" bitfld.long 0x00 23. " GMB759 ,Group Modifier Bit 759" "0,1" textline " " bitfld.long 0x00 22. " GMB758 ,Group Modifier Bit 758" "0,1" bitfld.long 0x00 21. " GMB757 ,Group Modifier Bit 757" "0,1" bitfld.long 0x00 20. " GMB756 ,Group Modifier Bit 756" "0,1" textline " " bitfld.long 0x00 19. " GMB755 ,Group Modifier Bit 755" "0,1" bitfld.long 0x00 18. " GMB754 ,Group Modifier Bit 754" "0,1" bitfld.long 0x00 17. " GMB753 ,Group Modifier Bit 753" "0,1" textline " " bitfld.long 0x00 16. " GMB752 ,Group Modifier Bit 752" "0,1" bitfld.long 0x00 15. " GMB751 ,Group Modifier Bit 751" "0,1" bitfld.long 0x00 14. " GMB750 ,Group Modifier Bit 750" "0,1" textline " " bitfld.long 0x00 13. " GMB749 ,Group Modifier Bit 749" "0,1" bitfld.long 0x00 12. " GMB748 ,Group Modifier Bit 748" "0,1" bitfld.long 0x00 11. " GMB747 ,Group Modifier Bit 747" "0,1" textline " " bitfld.long 0x00 10. " GMB746 ,Group Modifier Bit 746" "0,1" bitfld.long 0x00 9. " GMB745 ,Group Modifier Bit 745" "0,1" bitfld.long 0x00 8. " GMB744 ,Group Modifier Bit 744" "0,1" textline " " bitfld.long 0x00 7. " GMB743 ,Group Modifier Bit 743" "0,1" bitfld.long 0x00 6. " GMB742 ,Group Modifier Bit 742" "0,1" bitfld.long 0x00 5. " GMB741 ,Group Modifier Bit 741" "0,1" textline " " bitfld.long 0x00 4. " GMB740 ,Group Modifier Bit 740" "0,1" bitfld.long 0x00 3. " GMB739 ,Group Modifier Bit 739" "0,1" bitfld.long 0x00 2. " GMB738 ,Group Modifier Bit 738" "0,1" textline " " bitfld.long 0x00 1. " GMB737 ,Group Modifier Bit 737" "0,1" bitfld.long 0x00 0. " GMB736 ,Group Modifier Bit 736" "0,1" else hgroup.long 0x0D5C++0x03 hide.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D60))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x0D60++0x03 line.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" bitfld.long 0x00 31. " GMB799 ,Group Modifier Bit 799" "0,1" bitfld.long 0x00 30. " GMB798 ,Group Modifier Bit 798" "0,1" bitfld.long 0x00 29. " GMB797 ,Group Modifier Bit 797" "0,1" textline " " bitfld.long 0x00 28. " GMB796 ,Group Modifier Bit 796" "0,1" bitfld.long 0x00 27. " GMB795 ,Group Modifier Bit 795" "0,1" bitfld.long 0x00 26. " GMB794 ,Group Modifier Bit 794" "0,1" textline " " bitfld.long 0x00 25. " GMB793 ,Group Modifier Bit 793" "0,1" bitfld.long 0x00 24. " GMB792 ,Group Modifier Bit 792" "0,1" bitfld.long 0x00 23. " GMB791 ,Group Modifier Bit 791" "0,1" textline " " bitfld.long 0x00 22. " GMB790 ,Group Modifier Bit 790" "0,1" bitfld.long 0x00 21. " GMB789 ,Group Modifier Bit 789" "0,1" bitfld.long 0x00 20. " GMB788 ,Group Modifier Bit 788" "0,1" textline " " bitfld.long 0x00 19. " GMB787 ,Group Modifier Bit 787" "0,1" bitfld.long 0x00 18. " GMB786 ,Group Modifier Bit 786" "0,1" bitfld.long 0x00 17. " GMB785 ,Group Modifier Bit 785" "0,1" textline " " bitfld.long 0x00 16. " GMB784 ,Group Modifier Bit 784" "0,1" bitfld.long 0x00 15. " GMB783 ,Group Modifier Bit 783" "0,1" bitfld.long 0x00 14. " GMB782 ,Group Modifier Bit 782" "0,1" textline " " bitfld.long 0x00 13. " GMB781 ,Group Modifier Bit 781" "0,1" bitfld.long 0x00 12. " GMB780 ,Group Modifier Bit 780" "0,1" bitfld.long 0x00 11. " GMB779 ,Group Modifier Bit 779" "0,1" textline " " bitfld.long 0x00 10. " GMB778 ,Group Modifier Bit 778" "0,1" bitfld.long 0x00 9. " GMB777 ,Group Modifier Bit 777" "0,1" bitfld.long 0x00 8. " GMB776 ,Group Modifier Bit 776" "0,1" textline " " bitfld.long 0x00 7. " GMB775 ,Group Modifier Bit 775" "0,1" bitfld.long 0x00 6. " GMB774 ,Group Modifier Bit 774" "0,1" bitfld.long 0x00 5. " GMB773 ,Group Modifier Bit 773" "0,1" textline " " bitfld.long 0x00 4. " GMB772 ,Group Modifier Bit 772" "0,1" bitfld.long 0x00 3. " GMB771 ,Group Modifier Bit 771" "0,1" bitfld.long 0x00 2. " GMB770 ,Group Modifier Bit 770" "0,1" textline " " bitfld.long 0x00 1. " GMB769 ,Group Modifier Bit 769" "0,1" bitfld.long 0x00 0. " GMB768 ,Group Modifier Bit 768" "0,1" else hgroup.long 0x0D60++0x03 hide.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D64))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x0D64++0x03 line.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" bitfld.long 0x00 31. " GMB831 ,Group Modifier Bit 831" "0,1" bitfld.long 0x00 30. " GMB830 ,Group Modifier Bit 830" "0,1" bitfld.long 0x00 29. " GMB829 ,Group Modifier Bit 829" "0,1" textline " " bitfld.long 0x00 28. " GMB828 ,Group Modifier Bit 828" "0,1" bitfld.long 0x00 27. " GMB827 ,Group Modifier Bit 827" "0,1" bitfld.long 0x00 26. " GMB826 ,Group Modifier Bit 826" "0,1" textline " " bitfld.long 0x00 25. " GMB825 ,Group Modifier Bit 825" "0,1" bitfld.long 0x00 24. " GMB824 ,Group Modifier Bit 824" "0,1" bitfld.long 0x00 23. " GMB823 ,Group Modifier Bit 823" "0,1" textline " " bitfld.long 0x00 22. " GMB822 ,Group Modifier Bit 822" "0,1" bitfld.long 0x00 21. " GMB821 ,Group Modifier Bit 821" "0,1" bitfld.long 0x00 20. " GMB820 ,Group Modifier Bit 820" "0,1" textline " " bitfld.long 0x00 19. " GMB819 ,Group Modifier Bit 819" "0,1" bitfld.long 0x00 18. " GMB818 ,Group Modifier Bit 818" "0,1" bitfld.long 0x00 17. " GMB817 ,Group Modifier Bit 817" "0,1" textline " " bitfld.long 0x00 16. " GMB816 ,Group Modifier Bit 816" "0,1" bitfld.long 0x00 15. " GMB815 ,Group Modifier Bit 815" "0,1" bitfld.long 0x00 14. " GMB814 ,Group Modifier Bit 814" "0,1" textline " " bitfld.long 0x00 13. " GMB813 ,Group Modifier Bit 813" "0,1" bitfld.long 0x00 12. " GMB812 ,Group Modifier Bit 812" "0,1" bitfld.long 0x00 11. " GMB811 ,Group Modifier Bit 811" "0,1" textline " " bitfld.long 0x00 10. " GMB810 ,Group Modifier Bit 810" "0,1" bitfld.long 0x00 9. " GMB809 ,Group Modifier Bit 809" "0,1" bitfld.long 0x00 8. " GMB808 ,Group Modifier Bit 808" "0,1" textline " " bitfld.long 0x00 7. " GMB807 ,Group Modifier Bit 807" "0,1" bitfld.long 0x00 6. " GMB806 ,Group Modifier Bit 806" "0,1" bitfld.long 0x00 5. " GMB805 ,Group Modifier Bit 805" "0,1" textline " " bitfld.long 0x00 4. " GMB804 ,Group Modifier Bit 804" "0,1" bitfld.long 0x00 3. " GMB803 ,Group Modifier Bit 803" "0,1" bitfld.long 0x00 2. " GMB802 ,Group Modifier Bit 802" "0,1" textline " " bitfld.long 0x00 1. " GMB801 ,Group Modifier Bit 801" "0,1" bitfld.long 0x00 0. " GMB800 ,Group Modifier Bit 800" "0,1" else hgroup.long 0x0D64++0x03 hide.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D68))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01A)) group.long 0x0D68++0x03 line.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" bitfld.long 0x00 31. " GMB863 ,Group Modifier Bit 863" "0,1" bitfld.long 0x00 30. " GMB862 ,Group Modifier Bit 862" "0,1" bitfld.long 0x00 29. " GMB861 ,Group Modifier Bit 861" "0,1" textline " " bitfld.long 0x00 28. " GMB860 ,Group Modifier Bit 860" "0,1" bitfld.long 0x00 27. " GMB859 ,Group Modifier Bit 859" "0,1" bitfld.long 0x00 26. " GMB858 ,Group Modifier Bit 858" "0,1" textline " " bitfld.long 0x00 25. " GMB857 ,Group Modifier Bit 857" "0,1" bitfld.long 0x00 24. " GMB856 ,Group Modifier Bit 856" "0,1" bitfld.long 0x00 23. " GMB855 ,Group Modifier Bit 855" "0,1" textline " " bitfld.long 0x00 22. " GMB854 ,Group Modifier Bit 854" "0,1" bitfld.long 0x00 21. " GMB853 ,Group Modifier Bit 853" "0,1" bitfld.long 0x00 20. " GMB852 ,Group Modifier Bit 852" "0,1" textline " " bitfld.long 0x00 19. " GMB851 ,Group Modifier Bit 851" "0,1" bitfld.long 0x00 18. " GMB850 ,Group Modifier Bit 850" "0,1" bitfld.long 0x00 17. " GMB849 ,Group Modifier Bit 849" "0,1" textline " " bitfld.long 0x00 16. " GMB848 ,Group Modifier Bit 848" "0,1" bitfld.long 0x00 15. " GMB847 ,Group Modifier Bit 847" "0,1" bitfld.long 0x00 14. " GMB846 ,Group Modifier Bit 846" "0,1" textline " " bitfld.long 0x00 13. " GMB845 ,Group Modifier Bit 845" "0,1" bitfld.long 0x00 12. " GMB844 ,Group Modifier Bit 844" "0,1" bitfld.long 0x00 11. " GMB843 ,Group Modifier Bit 843" "0,1" textline " " bitfld.long 0x00 10. " GMB842 ,Group Modifier Bit 842" "0,1" bitfld.long 0x00 9. " GMB841 ,Group Modifier Bit 841" "0,1" bitfld.long 0x00 8. " GMB840 ,Group Modifier Bit 840" "0,1" textline " " bitfld.long 0x00 7. " GMB839 ,Group Modifier Bit 839" "0,1" bitfld.long 0x00 6. " GMB838 ,Group Modifier Bit 838" "0,1" bitfld.long 0x00 5. " GMB837 ,Group Modifier Bit 837" "0,1" textline " " bitfld.long 0x00 4. " GMB836 ,Group Modifier Bit 836" "0,1" bitfld.long 0x00 3. " GMB835 ,Group Modifier Bit 835" "0,1" bitfld.long 0x00 2. " GMB834 ,Group Modifier Bit 834" "0,1" textline " " bitfld.long 0x00 1. " GMB833 ,Group Modifier Bit 833" "0,1" bitfld.long 0x00 0. " GMB832 ,Group Modifier Bit 832" "0,1" else hgroup.long 0x0D68++0x03 hide.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D6C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x0D6C++0x03 line.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" bitfld.long 0x00 31. " GMB895 ,Group Modifier Bit 895" "0,1" bitfld.long 0x00 30. " GMB894 ,Group Modifier Bit 894" "0,1" bitfld.long 0x00 29. " GMB893 ,Group Modifier Bit 893" "0,1" textline " " bitfld.long 0x00 28. " GMB892 ,Group Modifier Bit 892" "0,1" bitfld.long 0x00 27. " GMB891 ,Group Modifier Bit 891" "0,1" bitfld.long 0x00 26. " GMB890 ,Group Modifier Bit 890" "0,1" textline " " bitfld.long 0x00 25. " GMB889 ,Group Modifier Bit 889" "0,1" bitfld.long 0x00 24. " GMB888 ,Group Modifier Bit 888" "0,1" bitfld.long 0x00 23. " GMB887 ,Group Modifier Bit 887" "0,1" textline " " bitfld.long 0x00 22. " GMB886 ,Group Modifier Bit 886" "0,1" bitfld.long 0x00 21. " GMB885 ,Group Modifier Bit 885" "0,1" bitfld.long 0x00 20. " GMB884 ,Group Modifier Bit 884" "0,1" textline " " bitfld.long 0x00 19. " GMB883 ,Group Modifier Bit 883" "0,1" bitfld.long 0x00 18. " GMB882 ,Group Modifier Bit 882" "0,1" bitfld.long 0x00 17. " GMB881 ,Group Modifier Bit 881" "0,1" textline " " bitfld.long 0x00 16. " GMB880 ,Group Modifier Bit 880" "0,1" bitfld.long 0x00 15. " GMB879 ,Group Modifier Bit 879" "0,1" bitfld.long 0x00 14. " GMB878 ,Group Modifier Bit 878" "0,1" textline " " bitfld.long 0x00 13. " GMB877 ,Group Modifier Bit 877" "0,1" bitfld.long 0x00 12. " GMB876 ,Group Modifier Bit 876" "0,1" bitfld.long 0x00 11. " GMB875 ,Group Modifier Bit 875" "0,1" textline " " bitfld.long 0x00 10. " GMB874 ,Group Modifier Bit 874" "0,1" bitfld.long 0x00 9. " GMB873 ,Group Modifier Bit 873" "0,1" bitfld.long 0x00 8. " GMB872 ,Group Modifier Bit 872" "0,1" textline " " bitfld.long 0x00 7. " GMB871 ,Group Modifier Bit 871" "0,1" bitfld.long 0x00 6. " GMB870 ,Group Modifier Bit 870" "0,1" bitfld.long 0x00 5. " GMB869 ,Group Modifier Bit 869" "0,1" textline " " bitfld.long 0x00 4. " GMB868 ,Group Modifier Bit 868" "0,1" bitfld.long 0x00 3. " GMB867 ,Group Modifier Bit 867" "0,1" bitfld.long 0x00 2. " GMB866 ,Group Modifier Bit 866" "0,1" textline " " bitfld.long 0x00 1. " GMB865 ,Group Modifier Bit 865" "0,1" bitfld.long 0x00 0. " GMB864 ,Group Modifier Bit 864" "0,1" else hgroup.long 0x0D6C++0x03 hide.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D70))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x0D70++0x03 line.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" bitfld.long 0x00 31. " GMB927 ,Group Modifier Bit 927" "0,1" bitfld.long 0x00 30. " GMB926 ,Group Modifier Bit 926" "0,1" bitfld.long 0x00 29. " GMB925 ,Group Modifier Bit 925" "0,1" textline " " bitfld.long 0x00 28. " GMB924 ,Group Modifier Bit 924" "0,1" bitfld.long 0x00 27. " GMB923 ,Group Modifier Bit 923" "0,1" bitfld.long 0x00 26. " GMB922 ,Group Modifier Bit 922" "0,1" textline " " bitfld.long 0x00 25. " GMB921 ,Group Modifier Bit 921" "0,1" bitfld.long 0x00 24. " GMB920 ,Group Modifier Bit 920" "0,1" bitfld.long 0x00 23. " GMB919 ,Group Modifier Bit 919" "0,1" textline " " bitfld.long 0x00 22. " GMB918 ,Group Modifier Bit 918" "0,1" bitfld.long 0x00 21. " GMB917 ,Group Modifier Bit 917" "0,1" bitfld.long 0x00 20. " GMB916 ,Group Modifier Bit 916" "0,1" textline " " bitfld.long 0x00 19. " GMB915 ,Group Modifier Bit 915" "0,1" bitfld.long 0x00 18. " GMB914 ,Group Modifier Bit 914" "0,1" bitfld.long 0x00 17. " GMB913 ,Group Modifier Bit 913" "0,1" textline " " bitfld.long 0x00 16. " GMB912 ,Group Modifier Bit 912" "0,1" bitfld.long 0x00 15. " GMB911 ,Group Modifier Bit 911" "0,1" bitfld.long 0x00 14. " GMB910 ,Group Modifier Bit 910" "0,1" textline " " bitfld.long 0x00 13. " GMB909 ,Group Modifier Bit 909" "0,1" bitfld.long 0x00 12. " GMB908 ,Group Modifier Bit 908" "0,1" bitfld.long 0x00 11. " GMB907 ,Group Modifier Bit 907" "0,1" textline " " bitfld.long 0x00 10. " GMB906 ,Group Modifier Bit 906" "0,1" bitfld.long 0x00 9. " GMB905 ,Group Modifier Bit 905" "0,1" bitfld.long 0x00 8. " GMB904 ,Group Modifier Bit 904" "0,1" textline " " bitfld.long 0x00 7. " GMB903 ,Group Modifier Bit 903" "0,1" bitfld.long 0x00 6. " GMB902 ,Group Modifier Bit 902" "0,1" bitfld.long 0x00 5. " GMB901 ,Group Modifier Bit 901" "0,1" textline " " bitfld.long 0x00 4. " GMB900 ,Group Modifier Bit 900" "0,1" bitfld.long 0x00 3. " GMB899 ,Group Modifier Bit 899" "0,1" bitfld.long 0x00 2. " GMB898 ,Group Modifier Bit 898" "0,1" textline " " bitfld.long 0x00 1. " GMB897 ,Group Modifier Bit 897" "0,1" bitfld.long 0x00 0. " GMB896 ,Group Modifier Bit 896" "0,1" else hgroup.long 0x0D70++0x03 hide.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D74))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x0D74++0x03 line.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" bitfld.long 0x00 31. " GMB959 ,Group Modifier Bit 959" "0,1" bitfld.long 0x00 30. " GMB958 ,Group Modifier Bit 958" "0,1" bitfld.long 0x00 29. " GMB957 ,Group Modifier Bit 957" "0,1" textline " " bitfld.long 0x00 28. " GMB956 ,Group Modifier Bit 956" "0,1" bitfld.long 0x00 27. " GMB955 ,Group Modifier Bit 955" "0,1" bitfld.long 0x00 26. " GMB954 ,Group Modifier Bit 954" "0,1" textline " " bitfld.long 0x00 25. " GMB953 ,Group Modifier Bit 953" "0,1" bitfld.long 0x00 24. " GMB952 ,Group Modifier Bit 952" "0,1" bitfld.long 0x00 23. " GMB951 ,Group Modifier Bit 951" "0,1" textline " " bitfld.long 0x00 22. " GMB950 ,Group Modifier Bit 950" "0,1" bitfld.long 0x00 21. " GMB949 ,Group Modifier Bit 949" "0,1" bitfld.long 0x00 20. " GMB948 ,Group Modifier Bit 948" "0,1" textline " " bitfld.long 0x00 19. " GMB947 ,Group Modifier Bit 947" "0,1" bitfld.long 0x00 18. " GMB946 ,Group Modifier Bit 946" "0,1" bitfld.long 0x00 17. " GMB945 ,Group Modifier Bit 945" "0,1" textline " " bitfld.long 0x00 16. " GMB944 ,Group Modifier Bit 944" "0,1" bitfld.long 0x00 15. " GMB943 ,Group Modifier Bit 943" "0,1" bitfld.long 0x00 14. " GMB942 ,Group Modifier Bit 942" "0,1" textline " " bitfld.long 0x00 13. " GMB941 ,Group Modifier Bit 941" "0,1" bitfld.long 0x00 12. " GMB940 ,Group Modifier Bit 940" "0,1" bitfld.long 0x00 11. " GMB939 ,Group Modifier Bit 939" "0,1" textline " " bitfld.long 0x00 10. " GMB938 ,Group Modifier Bit 938" "0,1" bitfld.long 0x00 9. " GMB937 ,Group Modifier Bit 937" "0,1" bitfld.long 0x00 8. " GMB936 ,Group Modifier Bit 936" "0,1" textline " " bitfld.long 0x00 7. " GMB935 ,Group Modifier Bit 935" "0,1" bitfld.long 0x00 6. " GMB934 ,Group Modifier Bit 934" "0,1" bitfld.long 0x00 5. " GMB933 ,Group Modifier Bit 933" "0,1" textline " " bitfld.long 0x00 4. " GMB932 ,Group Modifier Bit 932" "0,1" bitfld.long 0x00 3. " GMB931 ,Group Modifier Bit 931" "0,1" bitfld.long 0x00 2. " GMB930 ,Group Modifier Bit 930" "0,1" textline " " bitfld.long 0x00 1. " GMB929 ,Group Modifier Bit 929" "0,1" bitfld.long 0x00 0. " GMB928 ,Group Modifier Bit 928" "0,1" else hgroup.long 0x0D74++0x03 hide.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D78))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x0D78++0x03 line.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" bitfld.long 0x00 31. " GMB991 ,Group Modifier Bit 991" "0,1" bitfld.long 0x00 30. " GMB990 ,Group Modifier Bit 990" "0,1" bitfld.long 0x00 29. " GMB989 ,Group Modifier Bit 989" "0,1" textline " " bitfld.long 0x00 28. " GMB988 ,Group Modifier Bit 988" "0,1" bitfld.long 0x00 27. " GMB987 ,Group Modifier Bit 987" "0,1" bitfld.long 0x00 26. " GMB986 ,Group Modifier Bit 986" "0,1" textline " " bitfld.long 0x00 25. " GMB985 ,Group Modifier Bit 985" "0,1" bitfld.long 0x00 24. " GMB984 ,Group Modifier Bit 984" "0,1" bitfld.long 0x00 23. " GMB983 ,Group Modifier Bit 983" "0,1" textline " " bitfld.long 0x00 22. " GMB982 ,Group Modifier Bit 982" "0,1" bitfld.long 0x00 21. " GMB981 ,Group Modifier Bit 981" "0,1" bitfld.long 0x00 20. " GMB980 ,Group Modifier Bit 980" "0,1" textline " " bitfld.long 0x00 19. " GMB979 ,Group Modifier Bit 979" "0,1" bitfld.long 0x00 18. " GMB978 ,Group Modifier Bit 978" "0,1" bitfld.long 0x00 17. " GMB977 ,Group Modifier Bit 977" "0,1" textline " " bitfld.long 0x00 16. " GMB976 ,Group Modifier Bit 976" "0,1" bitfld.long 0x00 15. " GMB975 ,Group Modifier Bit 975" "0,1" bitfld.long 0x00 14. " GMB974 ,Group Modifier Bit 974" "0,1" textline " " bitfld.long 0x00 13. " GMB973 ,Group Modifier Bit 973" "0,1" bitfld.long 0x00 12. " GMB972 ,Group Modifier Bit 972" "0,1" bitfld.long 0x00 11. " GMB971 ,Group Modifier Bit 971" "0,1" textline " " bitfld.long 0x00 10. " GMB970 ,Group Modifier Bit 970" "0,1" bitfld.long 0x00 9. " GMB969 ,Group Modifier Bit 969" "0,1" bitfld.long 0x00 8. " GMB968 ,Group Modifier Bit 968" "0,1" textline " " bitfld.long 0x00 7. " GMB967 ,Group Modifier Bit 967" "0,1" bitfld.long 0x00 6. " GMB966 ,Group Modifier Bit 966" "0,1" bitfld.long 0x00 5. " GMB965 ,Group Modifier Bit 965" "0,1" textline " " bitfld.long 0x00 4. " GMB964 ,Group Modifier Bit 964" "0,1" bitfld.long 0x00 3. " GMB963 ,Group Modifier Bit 963" "0,1" bitfld.long 0x00 2. " GMB962 ,Group Modifier Bit 962" "0,1" textline " " bitfld.long 0x00 1. " GMB961 ,Group Modifier Bit 961" "0,1" bitfld.long 0x00 0. " GMB960 ,Group Modifier Bit 960" "0,1" else hgroup.long 0x0D78++0x03 hide.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" endif tree.end width 14. tree "Non-secure Access Control Registers" hgroup.long 0x0E00++0x03 hide.long 0x00 "GICD_NSACR0,Non-secure Access Control Register 0" hgroup.long 0xE04++0x03 hide.long 0x00 "GICD_NSACR1,Non-secure Access Control Register 1" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE08))) group.long 0xE08++0x03 line.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" bitfld.long 0x00 30.--31. " NS_ACCESS47 ,Controls Non-secure access of the interrupt with ID47 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS46 ,Controls Non-secure access of the interrupt with ID46 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS45 ,Controls Non-secure access of the interrupt with ID45 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS44 ,Controls Non-secure access of the interrupt with ID44 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS43 ,Controls Non-secure access of the interrupt with ID43 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS42 ,Controls Non-secure access of the interrupt with ID42 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS41 ,Controls Non-secure access of the interrupt with ID41 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS40 ,Controls Non-secure access of the interrupt with ID40 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS39 ,Controls Non-secure access of the interrupt with ID39 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS38 ,Controls Non-secure access of the interrupt with ID38 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS37 ,Controls Non-secure access of the interrupt with ID37 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS36 ,Controls Non-secure access of the interrupt with ID36 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS35 ,Controls Non-secure access of the interrupt with ID35 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS34 ,Controls Non-secure access of the interrupt with ID34 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS33 ,Controls Non-secure access of the interrupt with ID33 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS32 ,Controls Non-secure access of the interrupt with ID32 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE08++0x03 hide.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0C))) group.long 0xE0C++0x03 line.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" bitfld.long 0x00 30.--31. " NS_ACCESS63 ,Controls Non-secure access of the interrupt with ID63 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS62 ,Controls Non-secure access of the interrupt with ID62 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS61 ,Controls Non-secure access of the interrupt with ID61 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS60 ,Controls Non-secure access of the interrupt with ID60 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS59 ,Controls Non-secure access of the interrupt with ID59 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS58 ,Controls Non-secure access of the interrupt with ID58 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS57 ,Controls Non-secure access of the interrupt with ID57 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS56 ,Controls Non-secure access of the interrupt with ID56 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS55 ,Controls Non-secure access of the interrupt with ID55 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS54 ,Controls Non-secure access of the interrupt with ID54 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS53 ,Controls Non-secure access of the interrupt with ID53 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS52 ,Controls Non-secure access of the interrupt with ID52 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS51 ,Controls Non-secure access of the interrupt with ID51 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS50 ,Controls Non-secure access of the interrupt with ID50 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS49 ,Controls Non-secure access of the interrupt with ID49 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS48 ,Controls Non-secure access of the interrupt with ID48 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE0C++0x03 hide.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE10))) group.long 0xE10++0x03 line.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" bitfld.long 0x00 30.--31. " NS_ACCESS79 ,Controls Non-secure access of the interrupt with ID79 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS78 ,Controls Non-secure access of the interrupt with ID78 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS77 ,Controls Non-secure access of the interrupt with ID77 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS76 ,Controls Non-secure access of the interrupt with ID76 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS75 ,Controls Non-secure access of the interrupt with ID75 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS74 ,Controls Non-secure access of the interrupt with ID74 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS73 ,Controls Non-secure access of the interrupt with ID73 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS72 ,Controls Non-secure access of the interrupt with ID72 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS71 ,Controls Non-secure access of the interrupt with ID71 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS70 ,Controls Non-secure access of the interrupt with ID70 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS69 ,Controls Non-secure access of the interrupt with ID69 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS68 ,Controls Non-secure access of the interrupt with ID68 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS67 ,Controls Non-secure access of the interrupt with ID67 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS66 ,Controls Non-secure access of the interrupt with ID66 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS65 ,Controls Non-secure access of the interrupt with ID65 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS64 ,Controls Non-secure access of the interrupt with ID64 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE10++0x03 hide.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE14))) group.long 0xE14++0x03 line.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" bitfld.long 0x00 30.--31. " NS_ACCESS95 ,Controls Non-secure access of the interrupt with ID95 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS94 ,Controls Non-secure access of the interrupt with ID94 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS93 ,Controls Non-secure access of the interrupt with ID93 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS92 ,Controls Non-secure access of the interrupt with ID92 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS91 ,Controls Non-secure access of the interrupt with ID91 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS90 ,Controls Non-secure access of the interrupt with ID90 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS89 ,Controls Non-secure access of the interrupt with ID89 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS88 ,Controls Non-secure access of the interrupt with ID88 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS87 ,Controls Non-secure access of the interrupt with ID87 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS86 ,Controls Non-secure access of the interrupt with ID86 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS85 ,Controls Non-secure access of the interrupt with ID85 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS84 ,Controls Non-secure access of the interrupt with ID84 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS83 ,Controls Non-secure access of the interrupt with ID83 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS82 ,Controls Non-secure access of the interrupt with ID82 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS81 ,Controls Non-secure access of the interrupt with ID81 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS80 ,Controls Non-secure access of the interrupt with ID80 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE14++0x03 hide.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE18))) group.long 0xE18++0x03 line.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" bitfld.long 0x00 30.--31. " NS_ACCESS111 ,Controls Non-secure access of the interrupt with ID111" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS110 ,Controls Non-secure access of the interrupt with ID110" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS109 ,Controls Non-secure access of the interrupt with ID109" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS108 ,Controls Non-secure access of the interrupt with ID108" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS107 ,Controls Non-secure access of the interrupt with ID107" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS106 ,Controls Non-secure access of the interrupt with ID106" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS105 ,Controls Non-secure access of the interrupt with ID105" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS104 ,Controls Non-secure access of the interrupt with ID104" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS103 ,Controls Non-secure access of the interrupt with ID103" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS102 ,Controls Non-secure access of the interrupt with ID102" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS101 ,Controls Non-secure access of the interrupt with ID101" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS100 ,Controls Non-secure access of the interrupt with ID100" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS99 ,Controls Non-secure access of the interrupt with ID99 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS98 ,Controls Non-secure access of the interrupt with ID98 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS97 ,Controls Non-secure access of the interrupt with ID97 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS96 ,Controls Non-secure access of the interrupt with ID96 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE18++0x03 hide.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE1C))) group.long 0xE1C++0x03 line.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" bitfld.long 0x00 30.--31. " NS_ACCESS127 ,Controls Non-secure access of the interrupt with ID127" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS126 ,Controls Non-secure access of the interrupt with ID126" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS125 ,Controls Non-secure access of the interrupt with ID125" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS124 ,Controls Non-secure access of the interrupt with ID124" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS123 ,Controls Non-secure access of the interrupt with ID123" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS122 ,Controls Non-secure access of the interrupt with ID122" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS121 ,Controls Non-secure access of the interrupt with ID121" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS120 ,Controls Non-secure access of the interrupt with ID120" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS119 ,Controls Non-secure access of the interrupt with ID119" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS118 ,Controls Non-secure access of the interrupt with ID118" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS117 ,Controls Non-secure access of the interrupt with ID117" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS116 ,Controls Non-secure access of the interrupt with ID116" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS115 ,Controls Non-secure access of the interrupt with ID115" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS114 ,Controls Non-secure access of the interrupt with ID114" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS113 ,Controls Non-secure access of the interrupt with ID113" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS112 ,Controls Non-secure access of the interrupt with ID112" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE1C++0x03 hide.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE20))) group.long 0xE20++0x03 line.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" bitfld.long 0x00 30.--31. " NS_ACCESS143 ,Controls Non-secure access of the interrupt with ID143" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS142 ,Controls Non-secure access of the interrupt with ID142" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS141 ,Controls Non-secure access of the interrupt with ID141" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS140 ,Controls Non-secure access of the interrupt with ID140" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS139 ,Controls Non-secure access of the interrupt with ID139" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS138 ,Controls Non-secure access of the interrupt with ID138" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS137 ,Controls Non-secure access of the interrupt with ID137" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS136 ,Controls Non-secure access of the interrupt with ID136" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS135 ,Controls Non-secure access of the interrupt with ID135" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS134 ,Controls Non-secure access of the interrupt with ID134" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS133 ,Controls Non-secure access of the interrupt with ID133" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS132 ,Controls Non-secure access of the interrupt with ID132" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS131 ,Controls Non-secure access of the interrupt with ID131" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS130 ,Controls Non-secure access of the interrupt with ID130" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS129 ,Controls Non-secure access of the interrupt with ID129" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS128 ,Controls Non-secure access of the interrupt with ID128" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE20++0x03 hide.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE24))) group.long 0xE24++0x03 line.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" bitfld.long 0x00 30.--31. " NS_ACCESS159 ,Controls Non-secure access of the interrupt with ID159" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS158 ,Controls Non-secure access of the interrupt with ID158" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS157 ,Controls Non-secure access of the interrupt with ID157" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS156 ,Controls Non-secure access of the interrupt with ID156" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS155 ,Controls Non-secure access of the interrupt with ID155" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS154 ,Controls Non-secure access of the interrupt with ID154" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS153 ,Controls Non-secure access of the interrupt with ID153" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS152 ,Controls Non-secure access of the interrupt with ID152" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS151 ,Controls Non-secure access of the interrupt with ID151" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS150 ,Controls Non-secure access of the interrupt with ID150" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS149 ,Controls Non-secure access of the interrupt with ID149" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS148 ,Controls Non-secure access of the interrupt with ID148" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS147 ,Controls Non-secure access of the interrupt with ID147" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS146 ,Controls Non-secure access of the interrupt with ID146" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS145 ,Controls Non-secure access of the interrupt with ID145" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS144 ,Controls Non-secure access of the interrupt with ID144" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE24++0x03 hide.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE28))) group.long 0xE28++0x03 line.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" bitfld.long 0x00 30.--31. " NS_ACCESS175 ,Controls Non-secure access of the interrupt with ID175" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS174 ,Controls Non-secure access of the interrupt with ID174" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS173 ,Controls Non-secure access of the interrupt with ID173" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS172 ,Controls Non-secure access of the interrupt with ID172" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS171 ,Controls Non-secure access of the interrupt with ID171" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS170 ,Controls Non-secure access of the interrupt with ID170" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS169 ,Controls Non-secure access of the interrupt with ID169" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS168 ,Controls Non-secure access of the interrupt with ID168" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS167 ,Controls Non-secure access of the interrupt with ID167" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS166 ,Controls Non-secure access of the interrupt with ID166" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS165 ,Controls Non-secure access of the interrupt with ID165" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS164 ,Controls Non-secure access of the interrupt with ID164" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS163 ,Controls Non-secure access of the interrupt with ID163" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS162 ,Controls Non-secure access of the interrupt with ID162" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS161 ,Controls Non-secure access of the interrupt with ID161" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS160 ,Controls Non-secure access of the interrupt with ID160" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE28++0x03 hide.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE2C))) group.long 0xE2C++0x03 line.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" bitfld.long 0x00 30.--31. " NS_ACCESS191 ,Controls Non-secure access of the interrupt with ID191" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS190 ,Controls Non-secure access of the interrupt with ID190" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS189 ,Controls Non-secure access of the interrupt with ID189" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS188 ,Controls Non-secure access of the interrupt with ID188" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS187 ,Controls Non-secure access of the interrupt with ID187" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS186 ,Controls Non-secure access of the interrupt with ID186" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS185 ,Controls Non-secure access of the interrupt with ID185" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS184 ,Controls Non-secure access of the interrupt with ID184" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS183 ,Controls Non-secure access of the interrupt with ID183" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS182 ,Controls Non-secure access of the interrupt with ID182" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS181 ,Controls Non-secure access of the interrupt with ID181" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS180 ,Controls Non-secure access of the interrupt with ID180" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS179 ,Controls Non-secure access of the interrupt with ID179" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS178 ,Controls Non-secure access of the interrupt with ID178" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS177 ,Controls Non-secure access of the interrupt with ID177" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS176 ,Controls Non-secure access of the interrupt with ID176" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE2C++0x03 hide.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE30))) group.long 0xE30++0x03 line.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" bitfld.long 0x00 30.--31. " NS_ACCESS207 ,Controls Non-secure access of the interrupt with ID207" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS206 ,Controls Non-secure access of the interrupt with ID206" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS205 ,Controls Non-secure access of the interrupt with ID205" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS204 ,Controls Non-secure access of the interrupt with ID204" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS203 ,Controls Non-secure access of the interrupt with ID203" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS202 ,Controls Non-secure access of the interrupt with ID202" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS201 ,Controls Non-secure access of the interrupt with ID201" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS200 ,Controls Non-secure access of the interrupt with ID200" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS199 ,Controls Non-secure access of the interrupt with ID199" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS198 ,Controls Non-secure access of the interrupt with ID198" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS197 ,Controls Non-secure access of the interrupt with ID197" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS196 ,Controls Non-secure access of the interrupt with ID196" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS195 ,Controls Non-secure access of the interrupt with ID195" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS194 ,Controls Non-secure access of the interrupt with ID194" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS193 ,Controls Non-secure access of the interrupt with ID193" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS192 ,Controls Non-secure access of the interrupt with ID192" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE30++0x03 hide.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE34))) group.long 0xE34++0x03 line.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" bitfld.long 0x00 30.--31. " NS_ACCESS223 ,Controls Non-secure access of the interrupt with ID223" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS222 ,Controls Non-secure access of the interrupt with ID222" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS221 ,Controls Non-secure access of the interrupt with ID221" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS220 ,Controls Non-secure access of the interrupt with ID220" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS219 ,Controls Non-secure access of the interrupt with ID219" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS218 ,Controls Non-secure access of the interrupt with ID218" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS217 ,Controls Non-secure access of the interrupt with ID217" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS216 ,Controls Non-secure access of the interrupt with ID216" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS215 ,Controls Non-secure access of the interrupt with ID215" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS214 ,Controls Non-secure access of the interrupt with ID214" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS213 ,Controls Non-secure access of the interrupt with ID213" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS212 ,Controls Non-secure access of the interrupt with ID212" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS211 ,Controls Non-secure access of the interrupt with ID211" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS210 ,Controls Non-secure access of the interrupt with ID210" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS209 ,Controls Non-secure access of the interrupt with ID209" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS208 ,Controls Non-secure access of the interrupt with ID208" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE34++0x03 hide.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE38))) group.long 0xE38++0x03 line.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" bitfld.long 0x00 30.--31. " NS_ACCESS239 ,Controls Non-secure access of the interrupt with ID239" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS238 ,Controls Non-secure access of the interrupt with ID238" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS237 ,Controls Non-secure access of the interrupt with ID237" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS236 ,Controls Non-secure access of the interrupt with ID236" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS235 ,Controls Non-secure access of the interrupt with ID235" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS234 ,Controls Non-secure access of the interrupt with ID234" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS233 ,Controls Non-secure access of the interrupt with ID233" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS232 ,Controls Non-secure access of the interrupt with ID232" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS231 ,Controls Non-secure access of the interrupt with ID231" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS230 ,Controls Non-secure access of the interrupt with ID230" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS229 ,Controls Non-secure access of the interrupt with ID229" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS228 ,Controls Non-secure access of the interrupt with ID228" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS227 ,Controls Non-secure access of the interrupt with ID227" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS226 ,Controls Non-secure access of the interrupt with ID226" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS225 ,Controls Non-secure access of the interrupt with ID225" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS224 ,Controls Non-secure access of the interrupt with ID224" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE38++0x03 hide.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE3C))) group.long 0xE3C++0x03 line.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" bitfld.long 0x00 30.--31. " NS_ACCESS255 ,Controls Non-secure access of the interrupt with ID255" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS254 ,Controls Non-secure access of the interrupt with ID254" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS253 ,Controls Non-secure access of the interrupt with ID253" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS252 ,Controls Non-secure access of the interrupt with ID252" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS251 ,Controls Non-secure access of the interrupt with ID251" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS250 ,Controls Non-secure access of the interrupt with ID250" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS249 ,Controls Non-secure access of the interrupt with ID249" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS248 ,Controls Non-secure access of the interrupt with ID248" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS247 ,Controls Non-secure access of the interrupt with ID247" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS246 ,Controls Non-secure access of the interrupt with ID246" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS245 ,Controls Non-secure access of the interrupt with ID245" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS244 ,Controls Non-secure access of the interrupt with ID244" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS243 ,Controls Non-secure access of the interrupt with ID243" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS242 ,Controls Non-secure access of the interrupt with ID242" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS241 ,Controls Non-secure access of the interrupt with ID241" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS240 ,Controls Non-secure access of the interrupt with ID240" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE3C++0x03 hide.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE40))) group.long 0xE40++0x03 line.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" bitfld.long 0x00 30.--31. " NS_ACCESS271 ,Controls Non-secure access of the interrupt with ID271" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS270 ,Controls Non-secure access of the interrupt with ID270" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS269 ,Controls Non-secure access of the interrupt with ID269" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS268 ,Controls Non-secure access of the interrupt with ID268" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS267 ,Controls Non-secure access of the interrupt with ID267" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS266 ,Controls Non-secure access of the interrupt with ID266" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS265 ,Controls Non-secure access of the interrupt with ID265" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS264 ,Controls Non-secure access of the interrupt with ID264" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS263 ,Controls Non-secure access of the interrupt with ID263" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS262 ,Controls Non-secure access of the interrupt with ID262" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS261 ,Controls Non-secure access of the interrupt with ID261" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS260 ,Controls Non-secure access of the interrupt with ID260" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS259 ,Controls Non-secure access of the interrupt with ID259" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS258 ,Controls Non-secure access of the interrupt with ID258" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS257 ,Controls Non-secure access of the interrupt with ID257" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS256 ,Controls Non-secure access of the interrupt with ID256" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE40++0x03 hide.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE44))) group.long 0xE44++0x03 line.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" bitfld.long 0x00 30.--31. " NS_ACCESS287 ,Controls Non-secure access of the interrupt with ID287" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS286 ,Controls Non-secure access of the interrupt with ID286" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS285 ,Controls Non-secure access of the interrupt with ID285" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS284 ,Controls Non-secure access of the interrupt with ID284" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS283 ,Controls Non-secure access of the interrupt with ID283" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS282 ,Controls Non-secure access of the interrupt with ID282" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS281 ,Controls Non-secure access of the interrupt with ID281" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS280 ,Controls Non-secure access of the interrupt with ID280" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS279 ,Controls Non-secure access of the interrupt with ID279" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS278 ,Controls Non-secure access of the interrupt with ID278" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS277 ,Controls Non-secure access of the interrupt with ID277" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS276 ,Controls Non-secure access of the interrupt with ID276" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS275 ,Controls Non-secure access of the interrupt with ID275" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS274 ,Controls Non-secure access of the interrupt with ID274" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS273 ,Controls Non-secure access of the interrupt with ID273" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS272 ,Controls Non-secure access of the interrupt with ID272" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE44++0x03 hide.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE48))) group.long 0xE48++0x03 line.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" bitfld.long 0x00 30.--31. " NS_ACCESS303 ,Controls Non-secure access of the interrupt with ID303" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS302 ,Controls Non-secure access of the interrupt with ID302" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS301 ,Controls Non-secure access of the interrupt with ID301" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS300 ,Controls Non-secure access of the interrupt with ID300" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS299 ,Controls Non-secure access of the interrupt with ID299" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS298 ,Controls Non-secure access of the interrupt with ID298" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS297 ,Controls Non-secure access of the interrupt with ID297" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS296 ,Controls Non-secure access of the interrupt with ID296" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS295 ,Controls Non-secure access of the interrupt with ID295" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS294 ,Controls Non-secure access of the interrupt with ID294" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS293 ,Controls Non-secure access of the interrupt with ID293" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS292 ,Controls Non-secure access of the interrupt with ID292" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS291 ,Controls Non-secure access of the interrupt with ID291" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS290 ,Controls Non-secure access of the interrupt with ID290" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS289 ,Controls Non-secure access of the interrupt with ID289" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS288 ,Controls Non-secure access of the interrupt with ID288" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE48++0x03 hide.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4C))) group.long 0xE4C++0x03 line.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" bitfld.long 0x00 30.--31. " NS_ACCESS319 ,Controls Non-secure access of the interrupt with ID319" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS318 ,Controls Non-secure access of the interrupt with ID318" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS317 ,Controls Non-secure access of the interrupt with ID317" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS316 ,Controls Non-secure access of the interrupt with ID316" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS315 ,Controls Non-secure access of the interrupt with ID315" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS314 ,Controls Non-secure access of the interrupt with ID314" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS313 ,Controls Non-secure access of the interrupt with ID313" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS312 ,Controls Non-secure access of the interrupt with ID312" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS311 ,Controls Non-secure access of the interrupt with ID311" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS310 ,Controls Non-secure access of the interrupt with ID310" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS309 ,Controls Non-secure access of the interrupt with ID309" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS308 ,Controls Non-secure access of the interrupt with ID308" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS307 ,Controls Non-secure access of the interrupt with ID307" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS306 ,Controls Non-secure access of the interrupt with ID306" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS305 ,Controls Non-secure access of the interrupt with ID305" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS304 ,Controls Non-secure access of the interrupt with ID304" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE4C++0x03 hide.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE50))) group.long 0xE50++0x03 line.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" bitfld.long 0x00 30.--31. " NS_ACCESS335 ,Controls Non-secure access of the interrupt with ID335" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS334 ,Controls Non-secure access of the interrupt with ID334" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS333 ,Controls Non-secure access of the interrupt with ID333" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS332 ,Controls Non-secure access of the interrupt with ID332" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS331 ,Controls Non-secure access of the interrupt with ID331" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS330 ,Controls Non-secure access of the interrupt with ID330" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS329 ,Controls Non-secure access of the interrupt with ID329" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS328 ,Controls Non-secure access of the interrupt with ID328" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS327 ,Controls Non-secure access of the interrupt with ID327" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS326 ,Controls Non-secure access of the interrupt with ID326" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS325 ,Controls Non-secure access of the interrupt with ID325" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS324 ,Controls Non-secure access of the interrupt with ID324" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS323 ,Controls Non-secure access of the interrupt with ID323" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS322 ,Controls Non-secure access of the interrupt with ID322" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS321 ,Controls Non-secure access of the interrupt with ID321" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS320 ,Controls Non-secure access of the interrupt with ID320" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE50++0x03 hide.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE54))) group.long 0xE54++0x03 line.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" bitfld.long 0x00 30.--31. " NS_ACCESS351 ,Controls Non-secure access of the interrupt with ID351" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS350 ,Controls Non-secure access of the interrupt with ID350" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS349 ,Controls Non-secure access of the interrupt with ID349" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS348 ,Controls Non-secure access of the interrupt with ID348" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS347 ,Controls Non-secure access of the interrupt with ID347" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS346 ,Controls Non-secure access of the interrupt with ID346" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS345 ,Controls Non-secure access of the interrupt with ID345" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS344 ,Controls Non-secure access of the interrupt with ID344" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS343 ,Controls Non-secure access of the interrupt with ID343" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS342 ,Controls Non-secure access of the interrupt with ID342" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS341 ,Controls Non-secure access of the interrupt with ID341" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS340 ,Controls Non-secure access of the interrupt with ID340" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS339 ,Controls Non-secure access of the interrupt with ID339" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS338 ,Controls Non-secure access of the interrupt with ID338" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS337 ,Controls Non-secure access of the interrupt with ID337" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS336 ,Controls Non-secure access of the interrupt with ID336" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE54++0x03 hide.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE58))) group.long 0xE58++0x03 line.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" bitfld.long 0x00 30.--31. " NS_ACCESS367 ,Controls Non-secure access of the interrupt with ID367" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS366 ,Controls Non-secure access of the interrupt with ID366" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS365 ,Controls Non-secure access of the interrupt with ID365" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS364 ,Controls Non-secure access of the interrupt with ID364" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS363 ,Controls Non-secure access of the interrupt with ID363" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS362 ,Controls Non-secure access of the interrupt with ID362" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS361 ,Controls Non-secure access of the interrupt with ID361" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS360 ,Controls Non-secure access of the interrupt with ID360" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS359 ,Controls Non-secure access of the interrupt with ID359" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS358 ,Controls Non-secure access of the interrupt with ID358" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS357 ,Controls Non-secure access of the interrupt with ID357" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS356 ,Controls Non-secure access of the interrupt with ID356" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS355 ,Controls Non-secure access of the interrupt with ID355" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS354 ,Controls Non-secure access of the interrupt with ID354" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS353 ,Controls Non-secure access of the interrupt with ID353" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS352 ,Controls Non-secure access of the interrupt with ID352" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE58++0x03 hide.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE5C))) group.long 0xE5C++0x03 line.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" bitfld.long 0x00 30.--31. " NS_ACCESS383 ,Controls Non-secure access of the interrupt with ID383" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS382 ,Controls Non-secure access of the interrupt with ID382" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS381 ,Controls Non-secure access of the interrupt with ID381" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS380 ,Controls Non-secure access of the interrupt with ID380" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS379 ,Controls Non-secure access of the interrupt with ID379" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS378 ,Controls Non-secure access of the interrupt with ID378" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS377 ,Controls Non-secure access of the interrupt with ID377" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS376 ,Controls Non-secure access of the interrupt with ID376" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS375 ,Controls Non-secure access of the interrupt with ID375" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS374 ,Controls Non-secure access of the interrupt with ID374" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS373 ,Controls Non-secure access of the interrupt with ID373" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS372 ,Controls Non-secure access of the interrupt with ID372" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS371 ,Controls Non-secure access of the interrupt with ID371" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS370 ,Controls Non-secure access of the interrupt with ID370" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS369 ,Controls Non-secure access of the interrupt with ID369" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS368 ,Controls Non-secure access of the interrupt with ID368" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE5C++0x03 hide.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE60))) group.long 0xE60++0x03 line.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" bitfld.long 0x00 30.--31. " NS_ACCESS399 ,Controls Non-secure access of the interrupt with ID399" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS398 ,Controls Non-secure access of the interrupt with ID398" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS397 ,Controls Non-secure access of the interrupt with ID397" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS396 ,Controls Non-secure access of the interrupt with ID396" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS395 ,Controls Non-secure access of the interrupt with ID395" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS394 ,Controls Non-secure access of the interrupt with ID394" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS393 ,Controls Non-secure access of the interrupt with ID393" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS392 ,Controls Non-secure access of the interrupt with ID392" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS391 ,Controls Non-secure access of the interrupt with ID391" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS390 ,Controls Non-secure access of the interrupt with ID390" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS389 ,Controls Non-secure access of the interrupt with ID389" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS388 ,Controls Non-secure access of the interrupt with ID388" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS387 ,Controls Non-secure access of the interrupt with ID387" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS386 ,Controls Non-secure access of the interrupt with ID386" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS385 ,Controls Non-secure access of the interrupt with ID385" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS384 ,Controls Non-secure access of the interrupt with ID384" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE60++0x03 hide.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE64))) group.long 0xE64++0x03 line.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" bitfld.long 0x00 30.--31. " NS_ACCESS415 ,Controls Non-secure access of the interrupt with ID415" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS414 ,Controls Non-secure access of the interrupt with ID414" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS413 ,Controls Non-secure access of the interrupt with ID413" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS412 ,Controls Non-secure access of the interrupt with ID412" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS411 ,Controls Non-secure access of the interrupt with ID411" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS410 ,Controls Non-secure access of the interrupt with ID410" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS409 ,Controls Non-secure access of the interrupt with ID409" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS408 ,Controls Non-secure access of the interrupt with ID408" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS407 ,Controls Non-secure access of the interrupt with ID407" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS406 ,Controls Non-secure access of the interrupt with ID406" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS405 ,Controls Non-secure access of the interrupt with ID405" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS404 ,Controls Non-secure access of the interrupt with ID404" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS403 ,Controls Non-secure access of the interrupt with ID403" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS402 ,Controls Non-secure access of the interrupt with ID402" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS401 ,Controls Non-secure access of the interrupt with ID401" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS400 ,Controls Non-secure access of the interrupt with ID400" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE64++0x03 hide.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE68))) group.long 0xE68++0x03 line.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" bitfld.long 0x00 30.--31. " NS_ACCESS431 ,Controls Non-secure access of the interrupt with ID431" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS430 ,Controls Non-secure access of the interrupt with ID430" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS429 ,Controls Non-secure access of the interrupt with ID429" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS428 ,Controls Non-secure access of the interrupt with ID428" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS427 ,Controls Non-secure access of the interrupt with ID427" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS426 ,Controls Non-secure access of the interrupt with ID426" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS425 ,Controls Non-secure access of the interrupt with ID425" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS424 ,Controls Non-secure access of the interrupt with ID424" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS423 ,Controls Non-secure access of the interrupt with ID423" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS422 ,Controls Non-secure access of the interrupt with ID422" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS421 ,Controls Non-secure access of the interrupt with ID421" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS420 ,Controls Non-secure access of the interrupt with ID420" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS419 ,Controls Non-secure access of the interrupt with ID419" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS418 ,Controls Non-secure access of the interrupt with ID418" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS417 ,Controls Non-secure access of the interrupt with ID417" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS416 ,Controls Non-secure access of the interrupt with ID416" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE68++0x03 hide.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE6C))) group.long 0xE6C++0x03 line.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" bitfld.long 0x00 30.--31. " NS_ACCESS447 ,Controls Non-secure access of the interrupt with ID447" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS446 ,Controls Non-secure access of the interrupt with ID446" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS445 ,Controls Non-secure access of the interrupt with ID445" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS444 ,Controls Non-secure access of the interrupt with ID444" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS443 ,Controls Non-secure access of the interrupt with ID443" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS442 ,Controls Non-secure access of the interrupt with ID442" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS441 ,Controls Non-secure access of the interrupt with ID441" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS440 ,Controls Non-secure access of the interrupt with ID440" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS439 ,Controls Non-secure access of the interrupt with ID439" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS438 ,Controls Non-secure access of the interrupt with ID438" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS437 ,Controls Non-secure access of the interrupt with ID437" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS436 ,Controls Non-secure access of the interrupt with ID436" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS435 ,Controls Non-secure access of the interrupt with ID435" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS434 ,Controls Non-secure access of the interrupt with ID434" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS433 ,Controls Non-secure access of the interrupt with ID433" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS432 ,Controls Non-secure access of the interrupt with ID432" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE6C++0x03 hide.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE70))) group.long 0xE70++0x03 line.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" bitfld.long 0x00 30.--31. " NS_ACCESS463 ,Controls Non-secure access of the interrupt with ID463" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS462 ,Controls Non-secure access of the interrupt with ID462" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS461 ,Controls Non-secure access of the interrupt with ID461" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS460 ,Controls Non-secure access of the interrupt with ID460" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS459 ,Controls Non-secure access of the interrupt with ID459" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS458 ,Controls Non-secure access of the interrupt with ID458" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS457 ,Controls Non-secure access of the interrupt with ID457" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS456 ,Controls Non-secure access of the interrupt with ID456" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS455 ,Controls Non-secure access of the interrupt with ID455" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS454 ,Controls Non-secure access of the interrupt with ID454" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS453 ,Controls Non-secure access of the interrupt with ID453" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS452 ,Controls Non-secure access of the interrupt with ID452" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS451 ,Controls Non-secure access of the interrupt with ID451" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS450 ,Controls Non-secure access of the interrupt with ID450" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS449 ,Controls Non-secure access of the interrupt with ID449" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS448 ,Controls Non-secure access of the interrupt with ID448" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE70++0x03 hide.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE74))) group.long 0xE74++0x03 line.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" bitfld.long 0x00 30.--31. " NS_ACCESS479 ,Controls Non-secure access of the interrupt with ID479" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS478 ,Controls Non-secure access of the interrupt with ID478" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS477 ,Controls Non-secure access of the interrupt with ID477" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS476 ,Controls Non-secure access of the interrupt with ID476" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS475 ,Controls Non-secure access of the interrupt with ID475" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS474 ,Controls Non-secure access of the interrupt with ID474" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS473 ,Controls Non-secure access of the interrupt with ID473" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS472 ,Controls Non-secure access of the interrupt with ID472" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS471 ,Controls Non-secure access of the interrupt with ID471" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS470 ,Controls Non-secure access of the interrupt with ID470" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS469 ,Controls Non-secure access of the interrupt with ID469" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS468 ,Controls Non-secure access of the interrupt with ID468" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS467 ,Controls Non-secure access of the interrupt with ID467" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS466 ,Controls Non-secure access of the interrupt with ID466" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS465 ,Controls Non-secure access of the interrupt with ID465" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS464 ,Controls Non-secure access of the interrupt with ID464" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE74++0x03 hide.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE78))) group.long 0xE78++0x03 line.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" bitfld.long 0x00 30.--31. " NS_ACCESS495 ,Controls Non-secure access of the interrupt with ID495" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS494 ,Controls Non-secure access of the interrupt with ID494" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS493 ,Controls Non-secure access of the interrupt with ID493" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS492 ,Controls Non-secure access of the interrupt with ID492" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS491 ,Controls Non-secure access of the interrupt with ID491" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS490 ,Controls Non-secure access of the interrupt with ID490" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS489 ,Controls Non-secure access of the interrupt with ID489" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS488 ,Controls Non-secure access of the interrupt with ID488" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS487 ,Controls Non-secure access of the interrupt with ID487" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS486 ,Controls Non-secure access of the interrupt with ID486" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS485 ,Controls Non-secure access of the interrupt with ID485" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS484 ,Controls Non-secure access of the interrupt with ID484" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS483 ,Controls Non-secure access of the interrupt with ID483" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS482 ,Controls Non-secure access of the interrupt with ID482" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS481 ,Controls Non-secure access of the interrupt with ID481" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS480 ,Controls Non-secure access of the interrupt with ID480" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE78++0x03 hide.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE7C))) group.long 0xE7C++0x03 line.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" bitfld.long 0x00 30.--31. " NS_ACCESS511 ,Controls Non-secure access of the interrupt with ID511" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS510 ,Controls Non-secure access of the interrupt with ID510" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS509 ,Controls Non-secure access of the interrupt with ID509" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS508 ,Controls Non-secure access of the interrupt with ID508" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS507 ,Controls Non-secure access of the interrupt with ID507" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS506 ,Controls Non-secure access of the interrupt with ID506" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS505 ,Controls Non-secure access of the interrupt with ID505" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS504 ,Controls Non-secure access of the interrupt with ID504" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS503 ,Controls Non-secure access of the interrupt with ID503" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS502 ,Controls Non-secure access of the interrupt with ID502" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS501 ,Controls Non-secure access of the interrupt with ID501" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS500 ,Controls Non-secure access of the interrupt with ID500" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS499 ,Controls Non-secure access of the interrupt with ID499" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS498 ,Controls Non-secure access of the interrupt with ID498" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS497 ,Controls Non-secure access of the interrupt with ID497" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS496 ,Controls Non-secure access of the interrupt with ID496" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE7C++0x03 hide.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE80))) group.long 0xE80++0x03 line.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" bitfld.long 0x00 30.--31. " NS_ACCESS527 ,Controls Non-secure access of the interrupt with ID527" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS526 ,Controls Non-secure access of the interrupt with ID526" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS525 ,Controls Non-secure access of the interrupt with ID525" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS524 ,Controls Non-secure access of the interrupt with ID524" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS523 ,Controls Non-secure access of the interrupt with ID523" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS522 ,Controls Non-secure access of the interrupt with ID522" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS521 ,Controls Non-secure access of the interrupt with ID521" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS520 ,Controls Non-secure access of the interrupt with ID520" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS519 ,Controls Non-secure access of the interrupt with ID519" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS518 ,Controls Non-secure access of the interrupt with ID518" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS517 ,Controls Non-secure access of the interrupt with ID517" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS516 ,Controls Non-secure access of the interrupt with ID516" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS515 ,Controls Non-secure access of the interrupt with ID515" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS514 ,Controls Non-secure access of the interrupt with ID514" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS513 ,Controls Non-secure access of the interrupt with ID513" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS512 ,Controls Non-secure access of the interrupt with ID512" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE80++0x03 hide.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE84))) group.long 0xE84++0x03 line.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" bitfld.long 0x00 30.--31. " NS_ACCESS543 ,Controls Non-secure access of the interrupt with ID543" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS542 ,Controls Non-secure access of the interrupt with ID542" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS541 ,Controls Non-secure access of the interrupt with ID541" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS540 ,Controls Non-secure access of the interrupt with ID540" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS539 ,Controls Non-secure access of the interrupt with ID539" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS538 ,Controls Non-secure access of the interrupt with ID538" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS537 ,Controls Non-secure access of the interrupt with ID537" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS536 ,Controls Non-secure access of the interrupt with ID536" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS535 ,Controls Non-secure access of the interrupt with ID535" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS534 ,Controls Non-secure access of the interrupt with ID534" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS533 ,Controls Non-secure access of the interrupt with ID533" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS532 ,Controls Non-secure access of the interrupt with ID532" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS531 ,Controls Non-secure access of the interrupt with ID531" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS530 ,Controls Non-secure access of the interrupt with ID530" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS529 ,Controls Non-secure access of the interrupt with ID529" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS528 ,Controls Non-secure access of the interrupt with ID528" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE84++0x03 hide.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE88))) group.long 0xE88++0x03 line.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" bitfld.long 0x00 30.--31. " NS_ACCESS559 ,Controls Non-secure access of the interrupt with ID559" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS558 ,Controls Non-secure access of the interrupt with ID558" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS557 ,Controls Non-secure access of the interrupt with ID557" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS556 ,Controls Non-secure access of the interrupt with ID556" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS555 ,Controls Non-secure access of the interrupt with ID555" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS554 ,Controls Non-secure access of the interrupt with ID554" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS553 ,Controls Non-secure access of the interrupt with ID553" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS552 ,Controls Non-secure access of the interrupt with ID552" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS551 ,Controls Non-secure access of the interrupt with ID551" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS550 ,Controls Non-secure access of the interrupt with ID550" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS549 ,Controls Non-secure access of the interrupt with ID549" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS548 ,Controls Non-secure access of the interrupt with ID548" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS547 ,Controls Non-secure access of the interrupt with ID547" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS546 ,Controls Non-secure access of the interrupt with ID546" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS545 ,Controls Non-secure access of the interrupt with ID545" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS544 ,Controls Non-secure access of the interrupt with ID544" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE88++0x03 hide.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8C))) group.long 0xE8C++0x03 line.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" bitfld.long 0x00 30.--31. " NS_ACCESS575 ,Controls Non-secure access of the interrupt with ID575" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS574 ,Controls Non-secure access of the interrupt with ID574" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS573 ,Controls Non-secure access of the interrupt with ID573" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS572 ,Controls Non-secure access of the interrupt with ID572" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS571 ,Controls Non-secure access of the interrupt with ID571" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS570 ,Controls Non-secure access of the interrupt with ID570" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS569 ,Controls Non-secure access of the interrupt with ID569" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS568 ,Controls Non-secure access of the interrupt with ID568" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS567 ,Controls Non-secure access of the interrupt with ID567" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS566 ,Controls Non-secure access of the interrupt with ID566" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS565 ,Controls Non-secure access of the interrupt with ID565" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS564 ,Controls Non-secure access of the interrupt with ID564" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS563 ,Controls Non-secure access of the interrupt with ID563" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS562 ,Controls Non-secure access of the interrupt with ID562" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS561 ,Controls Non-secure access of the interrupt with ID561" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS560 ,Controls Non-secure access of the interrupt with ID560" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE8C++0x03 hide.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE90))) group.long 0xE90++0x03 line.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" bitfld.long 0x00 30.--31. " NS_ACCESS591 ,Controls Non-secure access of the interrupt with ID591" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS590 ,Controls Non-secure access of the interrupt with ID590" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS589 ,Controls Non-secure access of the interrupt with ID589" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS588 ,Controls Non-secure access of the interrupt with ID588" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS587 ,Controls Non-secure access of the interrupt with ID587" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS586 ,Controls Non-secure access of the interrupt with ID586" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS585 ,Controls Non-secure access of the interrupt with ID585" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS584 ,Controls Non-secure access of the interrupt with ID584" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS583 ,Controls Non-secure access of the interrupt with ID583" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS582 ,Controls Non-secure access of the interrupt with ID582" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS581 ,Controls Non-secure access of the interrupt with ID581" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS580 ,Controls Non-secure access of the interrupt with ID580" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS579 ,Controls Non-secure access of the interrupt with ID579" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS578 ,Controls Non-secure access of the interrupt with ID578" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS577 ,Controls Non-secure access of the interrupt with ID577" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS576 ,Controls Non-secure access of the interrupt with ID576" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE90++0x03 hide.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE94))) group.long 0xE94++0x03 line.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" bitfld.long 0x00 30.--31. " NS_ACCESS607 ,Controls Non-secure access of the interrupt with ID607" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS606 ,Controls Non-secure access of the interrupt with ID606" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS605 ,Controls Non-secure access of the interrupt with ID605" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS604 ,Controls Non-secure access of the interrupt with ID604" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS603 ,Controls Non-secure access of the interrupt with ID603" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS602 ,Controls Non-secure access of the interrupt with ID602" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS601 ,Controls Non-secure access of the interrupt with ID601" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS600 ,Controls Non-secure access of the interrupt with ID600" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS599 ,Controls Non-secure access of the interrupt with ID599" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS598 ,Controls Non-secure access of the interrupt with ID598" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS597 ,Controls Non-secure access of the interrupt with ID597" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS596 ,Controls Non-secure access of the interrupt with ID596" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS595 ,Controls Non-secure access of the interrupt with ID595" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS594 ,Controls Non-secure access of the interrupt with ID594" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS593 ,Controls Non-secure access of the interrupt with ID593" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS592 ,Controls Non-secure access of the interrupt with ID592" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE94++0x03 hide.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE98))) group.long 0xE98++0x03 line.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" bitfld.long 0x00 30.--31. " NS_ACCESS623 ,Controls Non-secure access of the interrupt with ID623" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS622 ,Controls Non-secure access of the interrupt with ID622" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS621 ,Controls Non-secure access of the interrupt with ID621" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS620 ,Controls Non-secure access of the interrupt with ID620" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS619 ,Controls Non-secure access of the interrupt with ID619" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS618 ,Controls Non-secure access of the interrupt with ID618" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS617 ,Controls Non-secure access of the interrupt with ID617" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS616 ,Controls Non-secure access of the interrupt with ID616" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS615 ,Controls Non-secure access of the interrupt with ID615" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS614 ,Controls Non-secure access of the interrupt with ID614" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS613 ,Controls Non-secure access of the interrupt with ID613" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS612 ,Controls Non-secure access of the interrupt with ID612" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS611 ,Controls Non-secure access of the interrupt with ID611" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS610 ,Controls Non-secure access of the interrupt with ID610" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS609 ,Controls Non-secure access of the interrupt with ID609" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS608 ,Controls Non-secure access of the interrupt with ID608" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE98++0x03 hide.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE9C))) group.long 0xE9C++0x03 line.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" bitfld.long 0x00 30.--31. " NS_ACCESS639 ,Controls Non-secure access of the interrupt with ID639" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS638 ,Controls Non-secure access of the interrupt with ID638" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS637 ,Controls Non-secure access of the interrupt with ID637" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS636 ,Controls Non-secure access of the interrupt with ID636" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS635 ,Controls Non-secure access of the interrupt with ID635" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS634 ,Controls Non-secure access of the interrupt with ID634" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS633 ,Controls Non-secure access of the interrupt with ID633" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS632 ,Controls Non-secure access of the interrupt with ID632" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS631 ,Controls Non-secure access of the interrupt with ID631" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS630 ,Controls Non-secure access of the interrupt with ID630" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS629 ,Controls Non-secure access of the interrupt with ID629" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS628 ,Controls Non-secure access of the interrupt with ID628" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS627 ,Controls Non-secure access of the interrupt with ID627" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS626 ,Controls Non-secure access of the interrupt with ID626" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS625 ,Controls Non-secure access of the interrupt with ID625" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS624 ,Controls Non-secure access of the interrupt with ID624" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE9C++0x03 hide.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA0))) group.long 0xEA0++0x03 line.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" bitfld.long 0x00 30.--31. " NS_ACCESS655 ,Controls Non-secure access of the interrupt with ID655" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS654 ,Controls Non-secure access of the interrupt with ID654" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS653 ,Controls Non-secure access of the interrupt with ID653" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS652 ,Controls Non-secure access of the interrupt with ID652" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS651 ,Controls Non-secure access of the interrupt with ID651" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS650 ,Controls Non-secure access of the interrupt with ID650" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS649 ,Controls Non-secure access of the interrupt with ID649" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS648 ,Controls Non-secure access of the interrupt with ID648" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS647 ,Controls Non-secure access of the interrupt with ID647" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS646 ,Controls Non-secure access of the interrupt with ID646" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS645 ,Controls Non-secure access of the interrupt with ID645" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS644 ,Controls Non-secure access of the interrupt with ID644" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS643 ,Controls Non-secure access of the interrupt with ID643" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS642 ,Controls Non-secure access of the interrupt with ID642" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS641 ,Controls Non-secure access of the interrupt with ID641" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS640 ,Controls Non-secure access of the interrupt with ID640" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA0++0x03 hide.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA4))) group.long 0xEA4++0x03 line.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" bitfld.long 0x00 30.--31. " NS_ACCESS671 ,Controls Non-secure access of the interrupt with ID671" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS670 ,Controls Non-secure access of the interrupt with ID670" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS669 ,Controls Non-secure access of the interrupt with ID669" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS668 ,Controls Non-secure access of the interrupt with ID668" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS667 ,Controls Non-secure access of the interrupt with ID667" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS666 ,Controls Non-secure access of the interrupt with ID666" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS665 ,Controls Non-secure access of the interrupt with ID665" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS664 ,Controls Non-secure access of the interrupt with ID664" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS663 ,Controls Non-secure access of the interrupt with ID663" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS662 ,Controls Non-secure access of the interrupt with ID662" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS661 ,Controls Non-secure access of the interrupt with ID661" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS660 ,Controls Non-secure access of the interrupt with ID660" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS659 ,Controls Non-secure access of the interrupt with ID659" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS658 ,Controls Non-secure access of the interrupt with ID658" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS657 ,Controls Non-secure access of the interrupt with ID657" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS656 ,Controls Non-secure access of the interrupt with ID656" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA4++0x03 hide.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA8))) group.long 0xEA8++0x03 line.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" bitfld.long 0x00 30.--31. " NS_ACCESS687 ,Controls Non-secure access of the interrupt with ID687" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS686 ,Controls Non-secure access of the interrupt with ID686" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS685 ,Controls Non-secure access of the interrupt with ID685" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS684 ,Controls Non-secure access of the interrupt with ID684" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS683 ,Controls Non-secure access of the interrupt with ID683" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS682 ,Controls Non-secure access of the interrupt with ID682" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS681 ,Controls Non-secure access of the interrupt with ID681" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS680 ,Controls Non-secure access of the interrupt with ID680" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS679 ,Controls Non-secure access of the interrupt with ID679" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS678 ,Controls Non-secure access of the interrupt with ID678" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS677 ,Controls Non-secure access of the interrupt with ID677" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS676 ,Controls Non-secure access of the interrupt with ID676" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS675 ,Controls Non-secure access of the interrupt with ID675" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS674 ,Controls Non-secure access of the interrupt with ID674" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS673 ,Controls Non-secure access of the interrupt with ID673" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS672 ,Controls Non-secure access of the interrupt with ID672" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA8++0x03 hide.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEAC))) group.long 0xEAC++0x03 line.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" bitfld.long 0x00 30.--31. " NS_ACCESS703 ,Controls Non-secure access of the interrupt with ID703" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS702 ,Controls Non-secure access of the interrupt with ID702" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS701 ,Controls Non-secure access of the interrupt with ID701" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS700 ,Controls Non-secure access of the interrupt with ID700" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS699 ,Controls Non-secure access of the interrupt with ID699" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS698 ,Controls Non-secure access of the interrupt with ID698" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS697 ,Controls Non-secure access of the interrupt with ID697" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS696 ,Controls Non-secure access of the interrupt with ID696" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS695 ,Controls Non-secure access of the interrupt with ID695" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS694 ,Controls Non-secure access of the interrupt with ID694" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS693 ,Controls Non-secure access of the interrupt with ID693" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS692 ,Controls Non-secure access of the interrupt with ID692" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS691 ,Controls Non-secure access of the interrupt with ID691" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS690 ,Controls Non-secure access of the interrupt with ID690" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS689 ,Controls Non-secure access of the interrupt with ID689" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS688 ,Controls Non-secure access of the interrupt with ID688" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEAC++0x03 hide.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB0))) group.long 0xEB0++0x03 line.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" bitfld.long 0x00 30.--31. " NS_ACCESS719 ,Controls Non-secure access of the interrupt with ID719" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS718 ,Controls Non-secure access of the interrupt with ID718" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS717 ,Controls Non-secure access of the interrupt with ID717" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS716 ,Controls Non-secure access of the interrupt with ID716" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS715 ,Controls Non-secure access of the interrupt with ID715" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS714 ,Controls Non-secure access of the interrupt with ID714" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS713 ,Controls Non-secure access of the interrupt with ID713" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS712 ,Controls Non-secure access of the interrupt with ID712" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS711 ,Controls Non-secure access of the interrupt with ID711" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS710 ,Controls Non-secure access of the interrupt with ID710" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS709 ,Controls Non-secure access of the interrupt with ID709" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS708 ,Controls Non-secure access of the interrupt with ID708" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS707 ,Controls Non-secure access of the interrupt with ID707" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS706 ,Controls Non-secure access of the interrupt with ID706" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS705 ,Controls Non-secure access of the interrupt with ID705" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS704 ,Controls Non-secure access of the interrupt with ID704" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB0++0x03 hide.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB4))) group.long 0xEB4++0x03 line.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" bitfld.long 0x00 30.--31. " NS_ACCESS735 ,Controls Non-secure access of the interrupt with ID735" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS734 ,Controls Non-secure access of the interrupt with ID734" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS733 ,Controls Non-secure access of the interrupt with ID733" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS732 ,Controls Non-secure access of the interrupt with ID732" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS731 ,Controls Non-secure access of the interrupt with ID731" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS730 ,Controls Non-secure access of the interrupt with ID730" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS729 ,Controls Non-secure access of the interrupt with ID729" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS728 ,Controls Non-secure access of the interrupt with ID728" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS727 ,Controls Non-secure access of the interrupt with ID727" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS726 ,Controls Non-secure access of the interrupt with ID726" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS725 ,Controls Non-secure access of the interrupt with ID725" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS724 ,Controls Non-secure access of the interrupt with ID724" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS723 ,Controls Non-secure access of the interrupt with ID723" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS722 ,Controls Non-secure access of the interrupt with ID722" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS721 ,Controls Non-secure access of the interrupt with ID721" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS720 ,Controls Non-secure access of the interrupt with ID720" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB4++0x03 hide.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB8))) group.long 0xEB8++0x03 line.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" bitfld.long 0x00 30.--31. " NS_ACCESS751 ,Controls Non-secure access of the interrupt with ID751" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS750 ,Controls Non-secure access of the interrupt with ID750" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS749 ,Controls Non-secure access of the interrupt with ID749" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS748 ,Controls Non-secure access of the interrupt with ID748" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS747 ,Controls Non-secure access of the interrupt with ID747" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS746 ,Controls Non-secure access of the interrupt with ID746" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS745 ,Controls Non-secure access of the interrupt with ID745" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS744 ,Controls Non-secure access of the interrupt with ID744" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS743 ,Controls Non-secure access of the interrupt with ID743" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS742 ,Controls Non-secure access of the interrupt with ID742" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS741 ,Controls Non-secure access of the interrupt with ID741" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS740 ,Controls Non-secure access of the interrupt with ID740" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS739 ,Controls Non-secure access of the interrupt with ID739" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS738 ,Controls Non-secure access of the interrupt with ID738" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS737 ,Controls Non-secure access of the interrupt with ID737" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS736 ,Controls Non-secure access of the interrupt with ID736" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB8++0x03 hide.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEBC))) group.long 0xEBC++0x03 line.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" bitfld.long 0x00 30.--31. " NS_ACCESS767 ,Controls Non-secure access of the interrupt with ID767" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS766 ,Controls Non-secure access of the interrupt with ID766" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS765 ,Controls Non-secure access of the interrupt with ID765" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS764 ,Controls Non-secure access of the interrupt with ID764" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS763 ,Controls Non-secure access of the interrupt with ID763" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS762 ,Controls Non-secure access of the interrupt with ID762" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS761 ,Controls Non-secure access of the interrupt with ID761" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS760 ,Controls Non-secure access of the interrupt with ID760" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS759 ,Controls Non-secure access of the interrupt with ID759" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS758 ,Controls Non-secure access of the interrupt with ID758" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS757 ,Controls Non-secure access of the interrupt with ID757" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS756 ,Controls Non-secure access of the interrupt with ID756" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS755 ,Controls Non-secure access of the interrupt with ID755" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS754 ,Controls Non-secure access of the interrupt with ID754" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS753 ,Controls Non-secure access of the interrupt with ID753" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS752 ,Controls Non-secure access of the interrupt with ID752" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEBC++0x03 hide.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC0))) group.long 0xEC0++0x03 line.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" bitfld.long 0x00 30.--31. " NS_ACCESS783 ,Controls Non-secure access of the interrupt with ID783" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS782 ,Controls Non-secure access of the interrupt with ID782" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS781 ,Controls Non-secure access of the interrupt with ID781" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS780 ,Controls Non-secure access of the interrupt with ID780" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS779 ,Controls Non-secure access of the interrupt with ID779" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS778 ,Controls Non-secure access of the interrupt with ID778" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS777 ,Controls Non-secure access of the interrupt with ID777" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS776 ,Controls Non-secure access of the interrupt with ID776" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS775 ,Controls Non-secure access of the interrupt with ID775" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS774 ,Controls Non-secure access of the interrupt with ID774" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS773 ,Controls Non-secure access of the interrupt with ID773" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS772 ,Controls Non-secure access of the interrupt with ID772" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS771 ,Controls Non-secure access of the interrupt with ID771" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS770 ,Controls Non-secure access of the interrupt with ID770" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS769 ,Controls Non-secure access of the interrupt with ID769" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS768 ,Controls Non-secure access of the interrupt with ID768" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC0++0x03 hide.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC4))) group.long 0xEC4++0x03 line.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" bitfld.long 0x00 30.--31. " NS_ACCESS799 ,Controls Non-secure access of the interrupt with ID799" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS798 ,Controls Non-secure access of the interrupt with ID798" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS797 ,Controls Non-secure access of the interrupt with ID797" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS796 ,Controls Non-secure access of the interrupt with ID796" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS795 ,Controls Non-secure access of the interrupt with ID795" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS794 ,Controls Non-secure access of the interrupt with ID794" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS793 ,Controls Non-secure access of the interrupt with ID793" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS792 ,Controls Non-secure access of the interrupt with ID792" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS791 ,Controls Non-secure access of the interrupt with ID791" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS790 ,Controls Non-secure access of the interrupt with ID790" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS789 ,Controls Non-secure access of the interrupt with ID789" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS788 ,Controls Non-secure access of the interrupt with ID788" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS787 ,Controls Non-secure access of the interrupt with ID787" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS786 ,Controls Non-secure access of the interrupt with ID786" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS785 ,Controls Non-secure access of the interrupt with ID785" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS784 ,Controls Non-secure access of the interrupt with ID784" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC4++0x03 hide.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC8))) group.long 0xEC8++0x03 line.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" bitfld.long 0x00 30.--31. " NS_ACCESS815 ,Controls Non-secure access of the interrupt with ID815" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS814 ,Controls Non-secure access of the interrupt with ID814" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS813 ,Controls Non-secure access of the interrupt with ID813" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS812 ,Controls Non-secure access of the interrupt with ID812" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS811 ,Controls Non-secure access of the interrupt with ID811" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS810 ,Controls Non-secure access of the interrupt with ID810" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS809 ,Controls Non-secure access of the interrupt with ID809" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS808 ,Controls Non-secure access of the interrupt with ID808" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS807 ,Controls Non-secure access of the interrupt with ID807" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS806 ,Controls Non-secure access of the interrupt with ID806" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS805 ,Controls Non-secure access of the interrupt with ID805" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS804 ,Controls Non-secure access of the interrupt with ID804" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS803 ,Controls Non-secure access of the interrupt with ID803" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS802 ,Controls Non-secure access of the interrupt with ID802" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS801 ,Controls Non-secure access of the interrupt with ID801" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS800 ,Controls Non-secure access of the interrupt with ID800" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC8++0x03 hide.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xECC))) group.long 0xECC++0x03 line.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" bitfld.long 0x00 30.--31. " NS_ACCESS831 ,Controls Non-secure access of the interrupt with ID831" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS830 ,Controls Non-secure access of the interrupt with ID830" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS829 ,Controls Non-secure access of the interrupt with ID829" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS828 ,Controls Non-secure access of the interrupt with ID828" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS827 ,Controls Non-secure access of the interrupt with ID827" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS826 ,Controls Non-secure access of the interrupt with ID826" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS825 ,Controls Non-secure access of the interrupt with ID825" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS824 ,Controls Non-secure access of the interrupt with ID824" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS823 ,Controls Non-secure access of the interrupt with ID823" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS822 ,Controls Non-secure access of the interrupt with ID822" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS821 ,Controls Non-secure access of the interrupt with ID821" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS820 ,Controls Non-secure access of the interrupt with ID820" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS819 ,Controls Non-secure access of the interrupt with ID819" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS818 ,Controls Non-secure access of the interrupt with ID818" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS817 ,Controls Non-secure access of the interrupt with ID817" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS816 ,Controls Non-secure access of the interrupt with ID816" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xECC++0x03 hide.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED0))) group.long 0xED0++0x03 line.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" bitfld.long 0x00 30.--31. " NS_ACCESS847 ,Controls Non-secure access of the interrupt with ID847" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS846 ,Controls Non-secure access of the interrupt with ID846" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS845 ,Controls Non-secure access of the interrupt with ID845" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS844 ,Controls Non-secure access of the interrupt with ID844" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS843 ,Controls Non-secure access of the interrupt with ID843" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS842 ,Controls Non-secure access of the interrupt with ID842" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS841 ,Controls Non-secure access of the interrupt with ID841" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS840 ,Controls Non-secure access of the interrupt with ID840" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS839 ,Controls Non-secure access of the interrupt with ID839" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS838 ,Controls Non-secure access of the interrupt with ID838" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS837 ,Controls Non-secure access of the interrupt with ID837" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS836 ,Controls Non-secure access of the interrupt with ID836" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS835 ,Controls Non-secure access of the interrupt with ID835" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS834 ,Controls Non-secure access of the interrupt with ID834" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS833 ,Controls Non-secure access of the interrupt with ID833" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS832 ,Controls Non-secure access of the interrupt with ID832" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED0++0x03 hide.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED4))) group.long 0xED4++0x03 line.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" bitfld.long 0x00 30.--31. " NS_ACCESS863 ,Controls Non-secure access of the interrupt with ID863" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS862 ,Controls Non-secure access of the interrupt with ID862" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS861 ,Controls Non-secure access of the interrupt with ID861" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS860 ,Controls Non-secure access of the interrupt with ID860" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS859 ,Controls Non-secure access of the interrupt with ID859" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS858 ,Controls Non-secure access of the interrupt with ID858" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS857 ,Controls Non-secure access of the interrupt with ID857" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS856 ,Controls Non-secure access of the interrupt with ID856" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS855 ,Controls Non-secure access of the interrupt with ID855" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS854 ,Controls Non-secure access of the interrupt with ID854" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS853 ,Controls Non-secure access of the interrupt with ID853" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS852 ,Controls Non-secure access of the interrupt with ID852" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS851 ,Controls Non-secure access of the interrupt with ID851" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS850 ,Controls Non-secure access of the interrupt with ID850" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS849 ,Controls Non-secure access of the interrupt with ID849" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS848 ,Controls Non-secure access of the interrupt with ID848" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED4++0x03 hide.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED8))) group.long 0xED8++0x03 line.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" bitfld.long 0x00 30.--31. " NS_ACCESS879 ,Controls Non-secure access of the interrupt with ID879" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS878 ,Controls Non-secure access of the interrupt with ID878" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS877 ,Controls Non-secure access of the interrupt with ID877" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS876 ,Controls Non-secure access of the interrupt with ID876" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS875 ,Controls Non-secure access of the interrupt with ID875" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS874 ,Controls Non-secure access of the interrupt with ID874" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS873 ,Controls Non-secure access of the interrupt with ID873" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS872 ,Controls Non-secure access of the interrupt with ID872" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS871 ,Controls Non-secure access of the interrupt with ID871" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS870 ,Controls Non-secure access of the interrupt with ID870" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS869 ,Controls Non-secure access of the interrupt with ID869" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS868 ,Controls Non-secure access of the interrupt with ID868" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS867 ,Controls Non-secure access of the interrupt with ID867" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS866 ,Controls Non-secure access of the interrupt with ID866" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS865 ,Controls Non-secure access of the interrupt with ID865" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS864 ,Controls Non-secure access of the interrupt with ID864" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED8++0x03 hide.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEDC))) group.long 0xEDC++0x03 line.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" bitfld.long 0x00 30.--31. " NS_ACCESS895 ,Controls Non-secure access of the interrupt with ID895" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS894 ,Controls Non-secure access of the interrupt with ID894" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS893 ,Controls Non-secure access of the interrupt with ID893" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS892 ,Controls Non-secure access of the interrupt with ID892" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS891 ,Controls Non-secure access of the interrupt with ID891" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS890 ,Controls Non-secure access of the interrupt with ID890" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS889 ,Controls Non-secure access of the interrupt with ID889" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS888 ,Controls Non-secure access of the interrupt with ID888" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS887 ,Controls Non-secure access of the interrupt with ID887" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS886 ,Controls Non-secure access of the interrupt with ID886" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS885 ,Controls Non-secure access of the interrupt with ID885" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS884 ,Controls Non-secure access of the interrupt with ID884" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS883 ,Controls Non-secure access of the interrupt with ID883" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS882 ,Controls Non-secure access of the interrupt with ID882" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS881 ,Controls Non-secure access of the interrupt with ID881" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS880 ,Controls Non-secure access of the interrupt with ID880" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEDC++0x03 hide.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE0))) group.long 0xEE0++0x03 line.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" bitfld.long 0x00 30.--31. " NS_ACCESS911 ,Controls Non-secure access of the interrupt with ID911" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS910 ,Controls Non-secure access of the interrupt with ID910" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS909 ,Controls Non-secure access of the interrupt with ID909" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS908 ,Controls Non-secure access of the interrupt with ID908" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS907 ,Controls Non-secure access of the interrupt with ID907" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS906 ,Controls Non-secure access of the interrupt with ID906" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS905 ,Controls Non-secure access of the interrupt with ID905" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS904 ,Controls Non-secure access of the interrupt with ID904" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS903 ,Controls Non-secure access of the interrupt with ID903" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS902 ,Controls Non-secure access of the interrupt with ID902" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS901 ,Controls Non-secure access of the interrupt with ID901" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS900 ,Controls Non-secure access of the interrupt with ID900" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS899 ,Controls Non-secure access of the interrupt with ID899" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS898 ,Controls Non-secure access of the interrupt with ID898" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS897 ,Controls Non-secure access of the interrupt with ID897" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS896 ,Controls Non-secure access of the interrupt with ID896" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE0++0x03 hide.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE4))) group.long 0xEE4++0x03 line.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" bitfld.long 0x00 30.--31. " NS_ACCESS927 ,Controls Non-secure access of the interrupt with ID927" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS926 ,Controls Non-secure access of the interrupt with ID926" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS925 ,Controls Non-secure access of the interrupt with ID925" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS924 ,Controls Non-secure access of the interrupt with ID924" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS923 ,Controls Non-secure access of the interrupt with ID923" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS922 ,Controls Non-secure access of the interrupt with ID922" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS921 ,Controls Non-secure access of the interrupt with ID921" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS920 ,Controls Non-secure access of the interrupt with ID920" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS919 ,Controls Non-secure access of the interrupt with ID919" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS918 ,Controls Non-secure access of the interrupt with ID918" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS917 ,Controls Non-secure access of the interrupt with ID917" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS916 ,Controls Non-secure access of the interrupt with ID916" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS915 ,Controls Non-secure access of the interrupt with ID915" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS914 ,Controls Non-secure access of the interrupt with ID914" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS913 ,Controls Non-secure access of the interrupt with ID913" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS912 ,Controls Non-secure access of the interrupt with ID912" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE4++0x03 hide.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE8))) group.long 0xEE8++0x03 line.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" bitfld.long 0x00 30.--31. " NS_ACCESS943 ,Controls Non-secure access of the interrupt with ID943" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS942 ,Controls Non-secure access of the interrupt with ID942" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS941 ,Controls Non-secure access of the interrupt with ID941" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS940 ,Controls Non-secure access of the interrupt with ID940" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS939 ,Controls Non-secure access of the interrupt with ID939" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS938 ,Controls Non-secure access of the interrupt with ID938" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS937 ,Controls Non-secure access of the interrupt with ID937" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS936 ,Controls Non-secure access of the interrupt with ID936" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS935 ,Controls Non-secure access of the interrupt with ID935" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS934 ,Controls Non-secure access of the interrupt with ID934" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS933 ,Controls Non-secure access of the interrupt with ID933" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS932 ,Controls Non-secure access of the interrupt with ID932" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS931 ,Controls Non-secure access of the interrupt with ID931" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS930 ,Controls Non-secure access of the interrupt with ID930" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS929 ,Controls Non-secure access of the interrupt with ID929" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS928 ,Controls Non-secure access of the interrupt with ID928" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE8++0x03 hide.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEEC))) group.long 0xEEC++0x03 line.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" bitfld.long 0x00 30.--31. " NS_ACCESS959 ,Controls Non-secure access of the interrupt with ID959" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS958 ,Controls Non-secure access of the interrupt with ID958" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS957 ,Controls Non-secure access of the interrupt with ID957" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS956 ,Controls Non-secure access of the interrupt with ID956" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS955 ,Controls Non-secure access of the interrupt with ID955" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS954 ,Controls Non-secure access of the interrupt with ID954" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS953 ,Controls Non-secure access of the interrupt with ID953" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS952 ,Controls Non-secure access of the interrupt with ID952" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS951 ,Controls Non-secure access of the interrupt with ID951" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS950 ,Controls Non-secure access of the interrupt with ID950" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS949 ,Controls Non-secure access of the interrupt with ID949" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS948 ,Controls Non-secure access of the interrupt with ID948" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS947 ,Controls Non-secure access of the interrupt with ID947" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS946 ,Controls Non-secure access of the interrupt with ID946" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS945 ,Controls Non-secure access of the interrupt with ID945" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS944 ,Controls Non-secure access of the interrupt with ID944" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEEC++0x03 hide.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF0))) group.long 0xEF0++0x03 line.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" bitfld.long 0x00 30.--31. " NS_ACCESS975 ,Controls Non-secure access of the interrupt with ID975" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS974 ,Controls Non-secure access of the interrupt with ID974" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS973 ,Controls Non-secure access of the interrupt with ID973" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS972 ,Controls Non-secure access of the interrupt with ID972" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS971 ,Controls Non-secure access of the interrupt with ID971" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS970 ,Controls Non-secure access of the interrupt with ID970" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS969 ,Controls Non-secure access of the interrupt with ID969" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS968 ,Controls Non-secure access of the interrupt with ID968" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS967 ,Controls Non-secure access of the interrupt with ID967" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS966 ,Controls Non-secure access of the interrupt with ID966" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS965 ,Controls Non-secure access of the interrupt with ID965" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS964 ,Controls Non-secure access of the interrupt with ID964" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS963 ,Controls Non-secure access of the interrupt with ID963" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS962 ,Controls Non-secure access of the interrupt with ID962" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS961 ,Controls Non-secure access of the interrupt with ID961" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS960 ,Controls Non-secure access of the interrupt with ID960" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF0++0x03 hide.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF4))) group.long 0xEF4++0x03 line.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" bitfld.long 0x00 30.--31. " NS_ACCESS991 ,Controls Non-secure access of the interrupt with ID991" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS990 ,Controls Non-secure access of the interrupt with ID990" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS989 ,Controls Non-secure access of the interrupt with ID989" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS988 ,Controls Non-secure access of the interrupt with ID988" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS987 ,Controls Non-secure access of the interrupt with ID987" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS986 ,Controls Non-secure access of the interrupt with ID986" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS985 ,Controls Non-secure access of the interrupt with ID985" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS984 ,Controls Non-secure access of the interrupt with ID984" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS983 ,Controls Non-secure access of the interrupt with ID983" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS982 ,Controls Non-secure access of the interrupt with ID982" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS981 ,Controls Non-secure access of the interrupt with ID981" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS980 ,Controls Non-secure access of the interrupt with ID980" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS979 ,Controls Non-secure access of the interrupt with ID979" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS978 ,Controls Non-secure access of the interrupt with ID978" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS977 ,Controls Non-secure access of the interrupt with ID977" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS976 ,Controls Non-secure access of the interrupt with ID976" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF4++0x03 hide.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" endif tree.end width 25. tree "Software Generated Interrupt" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0F00++0x03 hide.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" hgroup.long 0xF10++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" hgroup.long 0xF14++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" hgroup.long 0xF18++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" hgroup.long 0xF1C++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" hgroup.long 0xF20++0x03 hide.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" hgroup.long 0xF24++0x03 hide.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" hgroup.long 0xF28++0x03 hide.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" hgroup.long 0xF2C++0x03 hide.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" group.long 0xF10++0x03 line.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" group.long 0xF14++0x03 line.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" group.long 0xF18++0x03 line.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" group.long 0xF1C++0x03 line.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" group.long 0xF20++0x03 line.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" group.long 0xF24++0x03 line.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" group.long 0xF28++0x03 line.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" group.long 0xF2C++0x03 line.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" endif tree.end width 24. tree "Interrupt Routing Registers" group.quad 0x6100++0x07 line.quad 0x00 "GICD_IROUTER32 ,Interrupt Routing Register 32 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6108++0x07 line.quad 0x00 "GICD_IROUTER33 ,Interrupt Routing Register 33 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6110++0x07 line.quad 0x00 "GICD_IROUTER34 ,Interrupt Routing Register 34 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6118++0x07 line.quad 0x00 "GICD_IROUTER35 ,Interrupt Routing Register 35 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6120++0x07 line.quad 0x00 "GICD_IROUTER36 ,Interrupt Routing Register 36 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6128++0x07 line.quad 0x00 "GICD_IROUTER37 ,Interrupt Routing Register 37 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6130++0x07 line.quad 0x00 "GICD_IROUTER38 ,Interrupt Routing Register 38 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6138++0x07 line.quad 0x00 "GICD_IROUTER39 ,Interrupt Routing Register 39 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6140++0x07 line.quad 0x00 "GICD_IROUTER40 ,Interrupt Routing Register 40 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6148++0x07 line.quad 0x00 "GICD_IROUTER41 ,Interrupt Routing Register 41 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6150++0x07 line.quad 0x00 "GICD_IROUTER42 ,Interrupt Routing Register 42 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6158++0x07 line.quad 0x00 "GICD_IROUTER43 ,Interrupt Routing Register 43 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6160++0x07 line.quad 0x00 "GICD_IROUTER44 ,Interrupt Routing Register 44 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6168++0x07 line.quad 0x00 "GICD_IROUTER45 ,Interrupt Routing Register 45 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6170++0x07 line.quad 0x00 "GICD_IROUTER46 ,Interrupt Routing Register 46 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6178++0x07 line.quad 0x00 "GICD_IROUTER47 ,Interrupt Routing Register 47 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6180++0x07 line.quad 0x00 "GICD_IROUTER48 ,Interrupt Routing Register 48 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6188++0x07 line.quad 0x00 "GICD_IROUTER49 ,Interrupt Routing Register 49 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6190++0x07 line.quad 0x00 "GICD_IROUTER50 ,Interrupt Routing Register 50 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6198++0x07 line.quad 0x00 "GICD_IROUTER51 ,Interrupt Routing Register 51 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A0++0x07 line.quad 0x00 "GICD_IROUTER52 ,Interrupt Routing Register 52 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A8++0x07 line.quad 0x00 "GICD_IROUTER53 ,Interrupt Routing Register 53 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B0++0x07 line.quad 0x00 "GICD_IROUTER54 ,Interrupt Routing Register 54 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B8++0x07 line.quad 0x00 "GICD_IROUTER55 ,Interrupt Routing Register 55 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C0++0x07 line.quad 0x00 "GICD_IROUTER56 ,Interrupt Routing Register 56 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C8++0x07 line.quad 0x00 "GICD_IROUTER57 ,Interrupt Routing Register 57 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D0++0x07 line.quad 0x00 "GICD_IROUTER58 ,Interrupt Routing Register 58 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D8++0x07 line.quad 0x00 "GICD_IROUTER59 ,Interrupt Routing Register 59 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E0++0x07 line.quad 0x00 "GICD_IROUTER60 ,Interrupt Routing Register 60 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E8++0x07 line.quad 0x00 "GICD_IROUTER61 ,Interrupt Routing Register 61 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F0++0x07 line.quad 0x00 "GICD_IROUTER62 ,Interrupt Routing Register 62 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F8++0x07 line.quad 0x00 "GICD_IROUTER63 ,Interrupt Routing Register 63 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6200++0x07 line.quad 0x00 "GICD_IROUTER64 ,Interrupt Routing Register 64 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6208++0x07 line.quad 0x00 "GICD_IROUTER65 ,Interrupt Routing Register 65 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6210++0x07 line.quad 0x00 "GICD_IROUTER66 ,Interrupt Routing Register 66 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6218++0x07 line.quad 0x00 "GICD_IROUTER67 ,Interrupt Routing Register 67 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6220++0x07 line.quad 0x00 "GICD_IROUTER68 ,Interrupt Routing Register 68 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6228++0x07 line.quad 0x00 "GICD_IROUTER69 ,Interrupt Routing Register 69 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6230++0x07 line.quad 0x00 "GICD_IROUTER70 ,Interrupt Routing Register 70 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6238++0x07 line.quad 0x00 "GICD_IROUTER71 ,Interrupt Routing Register 71 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6240++0x07 line.quad 0x00 "GICD_IROUTER72 ,Interrupt Routing Register 72 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6248++0x07 line.quad 0x00 "GICD_IROUTER73 ,Interrupt Routing Register 73 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6250++0x07 line.quad 0x00 "GICD_IROUTER74 ,Interrupt Routing Register 74 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6258++0x07 line.quad 0x00 "GICD_IROUTER75 ,Interrupt Routing Register 75 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6260++0x07 line.quad 0x00 "GICD_IROUTER76 ,Interrupt Routing Register 76 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6268++0x07 line.quad 0x00 "GICD_IROUTER77 ,Interrupt Routing Register 77 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6270++0x07 line.quad 0x00 "GICD_IROUTER78 ,Interrupt Routing Register 78 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6278++0x07 line.quad 0x00 "GICD_IROUTER79 ,Interrupt Routing Register 79 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6280++0x07 line.quad 0x00 "GICD_IROUTER80 ,Interrupt Routing Register 80 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6288++0x07 line.quad 0x00 "GICD_IROUTER81 ,Interrupt Routing Register 81 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6290++0x07 line.quad 0x00 "GICD_IROUTER82 ,Interrupt Routing Register 82 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6298++0x07 line.quad 0x00 "GICD_IROUTER83 ,Interrupt Routing Register 83 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A0++0x07 line.quad 0x00 "GICD_IROUTER84 ,Interrupt Routing Register 84 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A8++0x07 line.quad 0x00 "GICD_IROUTER85 ,Interrupt Routing Register 85 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B0++0x07 line.quad 0x00 "GICD_IROUTER86 ,Interrupt Routing Register 86 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B8++0x07 line.quad 0x00 "GICD_IROUTER87 ,Interrupt Routing Register 87 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C0++0x07 line.quad 0x00 "GICD_IROUTER88 ,Interrupt Routing Register 88 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C8++0x07 line.quad 0x00 "GICD_IROUTER89 ,Interrupt Routing Register 89 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D0++0x07 line.quad 0x00 "GICD_IROUTER90 ,Interrupt Routing Register 90 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D8++0x07 line.quad 0x00 "GICD_IROUTER91 ,Interrupt Routing Register 91 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E0++0x07 line.quad 0x00 "GICD_IROUTER92 ,Interrupt Routing Register 92 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E8++0x07 line.quad 0x00 "GICD_IROUTER93 ,Interrupt Routing Register 93 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F0++0x07 line.quad 0x00 "GICD_IROUTER94 ,Interrupt Routing Register 94 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F8++0x07 line.quad 0x00 "GICD_IROUTER95 ,Interrupt Routing Register 95 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6300++0x07 line.quad 0x00 "GICD_IROUTER96 ,Interrupt Routing Register 96 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6308++0x07 line.quad 0x00 "GICD_IROUTER97 ,Interrupt Routing Register 97 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6310++0x07 line.quad 0x00 "GICD_IROUTER98 ,Interrupt Routing Register 98 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6318++0x07 line.quad 0x00 "GICD_IROUTER99 ,Interrupt Routing Register 99 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6320++0x07 line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6328++0x07 line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6330++0x07 line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6338++0x07 line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6340++0x07 line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6348++0x07 line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6350++0x07 line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6358++0x07 line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6360++0x07 line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6368++0x07 line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6370++0x07 line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6378++0x07 line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6380++0x07 line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6388++0x07 line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6390++0x07 line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6398++0x07 line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A0++0x07 line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A8++0x07 line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B0++0x07 line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B8++0x07 line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C0++0x07 line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C8++0x07 line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D0++0x07 line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D8++0x07 line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E0++0x07 line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E8++0x07 line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F0++0x07 line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F8++0x07 line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6400++0x07 line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6408++0x07 line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6410++0x07 line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6418++0x07 line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6420++0x07 line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6428++0x07 line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6430++0x07 line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6438++0x07 line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6440++0x07 line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6448++0x07 line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6450++0x07 line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6458++0x07 line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6460++0x07 line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6468++0x07 line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6470++0x07 line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6478++0x07 line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6480++0x07 line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6488++0x07 line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6490++0x07 line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6498++0x07 line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A0++0x07 line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A8++0x07 line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B0++0x07 line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B8++0x07 line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C0++0x07 line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C8++0x07 line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D0++0x07 line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D8++0x07 line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E0++0x07 line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E8++0x07 line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F0++0x07 line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F8++0x07 line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6500++0x07 line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6508++0x07 line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6510++0x07 line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6518++0x07 line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6520++0x07 line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6528++0x07 line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6530++0x07 line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6538++0x07 line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6540++0x07 line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6548++0x07 line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6550++0x07 line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6558++0x07 line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6560++0x07 line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6568++0x07 line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6570++0x07 line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6578++0x07 line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6580++0x07 line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6588++0x07 line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6590++0x07 line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6598++0x07 line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A0++0x07 line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A8++0x07 line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B0++0x07 line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B8++0x07 line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C0++0x07 line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C8++0x07 line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D0++0x07 line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D8++0x07 line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E0++0x07 line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E8++0x07 line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F0++0x07 line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F8++0x07 line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6600++0x07 line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6608++0x07 line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6610++0x07 line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6618++0x07 line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6620++0x07 line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6628++0x07 line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6630++0x07 line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6638++0x07 line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6640++0x07 line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6648++0x07 line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6650++0x07 line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6658++0x07 line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6660++0x07 line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6668++0x07 line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6670++0x07 line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6678++0x07 line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6680++0x07 line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6688++0x07 line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6690++0x07 line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6698++0x07 line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A0++0x07 line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A8++0x07 line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B0++0x07 line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B8++0x07 line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C0++0x07 line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C8++0x07 line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D0++0x07 line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D8++0x07 line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E0++0x07 line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E8++0x07 line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F0++0x07 line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F8++0x07 line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6700++0x07 line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6708++0x07 line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6710++0x07 line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6718++0x07 line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6720++0x07 line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6728++0x07 line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6730++0x07 line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6738++0x07 line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6740++0x07 line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6748++0x07 line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6750++0x07 line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6758++0x07 line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6760++0x07 line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6768++0x07 line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6770++0x07 line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6778++0x07 line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6780++0x07 line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6788++0x07 line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6790++0x07 line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6798++0x07 line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A0++0x07 line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A8++0x07 line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B0++0x07 line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B8++0x07 line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C0++0x07 line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C8++0x07 line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D0++0x07 line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D8++0x07 line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E0++0x07 line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E8++0x07 line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F0++0x07 line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F8++0x07 line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6800++0x07 line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6808++0x07 line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6810++0x07 line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6818++0x07 line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6820++0x07 line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6828++0x07 line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6830++0x07 line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6838++0x07 line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6840++0x07 line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6848++0x07 line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6850++0x07 line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6858++0x07 line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6860++0x07 line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6868++0x07 line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6870++0x07 line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6878++0x07 line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6880++0x07 line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6888++0x07 line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6890++0x07 line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6898++0x07 line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A0++0x07 line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A8++0x07 line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B0++0x07 line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B8++0x07 line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C0++0x07 line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C8++0x07 line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D0++0x07 line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D8++0x07 line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E0++0x07 line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E8++0x07 line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F0++0x07 line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F8++0x07 line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6900++0x07 line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6908++0x07 line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6910++0x07 line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6918++0x07 line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6920++0x07 line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6928++0x07 line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6930++0x07 line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6938++0x07 line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6940++0x07 line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6948++0x07 line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6950++0x07 line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6958++0x07 line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6960++0x07 line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6968++0x07 line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6970++0x07 line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6978++0x07 line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6980++0x07 line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6988++0x07 line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6990++0x07 line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6998++0x07 line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A0++0x07 line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A8++0x07 line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B0++0x07 line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B8++0x07 line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C0++0x07 line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C8++0x07 line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D0++0x07 line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D8++0x07 line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E0++0x07 line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E8++0x07 line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F0++0x07 line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F8++0x07 line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A00++0x07 line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A08++0x07 line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A10++0x07 line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A18++0x07 line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A20++0x07 line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A28++0x07 line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A30++0x07 line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A38++0x07 line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A40++0x07 line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A48++0x07 line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A50++0x07 line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A58++0x07 line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A60++0x07 line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A68++0x07 line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A70++0x07 line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A78++0x07 line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A80++0x07 line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A88++0x07 line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A90++0x07 line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A98++0x07 line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA0++0x07 line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA8++0x07 line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB0++0x07 line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB8++0x07 line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC0++0x07 line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC8++0x07 line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD0++0x07 line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD8++0x07 line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE0++0x07 line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE8++0x07 line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF0++0x07 line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF8++0x07 line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B00++0x07 line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B08++0x07 line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B10++0x07 line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B18++0x07 line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B20++0x07 line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B28++0x07 line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B30++0x07 line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B38++0x07 line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B40++0x07 line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B48++0x07 line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B50++0x07 line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B58++0x07 line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B60++0x07 line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B68++0x07 line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B70++0x07 line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B78++0x07 line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B80++0x07 line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B88++0x07 line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B90++0x07 line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B98++0x07 line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA0++0x07 line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA8++0x07 line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB0++0x07 line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB8++0x07 line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC0++0x07 line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC8++0x07 line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD0++0x07 line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD8++0x07 line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE0++0x07 line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE8++0x07 line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF0++0x07 line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF8++0x07 line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C00++0x07 line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C08++0x07 line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C10++0x07 line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C18++0x07 line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C20++0x07 line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C28++0x07 line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C30++0x07 line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C38++0x07 line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C40++0x07 line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C48++0x07 line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C50++0x07 line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C58++0x07 line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C60++0x07 line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C68++0x07 line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C70++0x07 line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C78++0x07 line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C80++0x07 line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C88++0x07 line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C90++0x07 line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C98++0x07 line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA0++0x07 line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA8++0x07 line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB0++0x07 line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB8++0x07 line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC0++0x07 line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC8++0x07 line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD0++0x07 line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD8++0x07 line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE0++0x07 line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE8++0x07 line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF0++0x07 line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF8++0x07 line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D00++0x07 line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D08++0x07 line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D10++0x07 line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D18++0x07 line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D20++0x07 line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D28++0x07 line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D30++0x07 line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D38++0x07 line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D40++0x07 line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D48++0x07 line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D50++0x07 line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D58++0x07 line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D60++0x07 line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D68++0x07 line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D70++0x07 line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D78++0x07 line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D80++0x07 line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D88++0x07 line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D90++0x07 line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D98++0x07 line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA0++0x07 line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA8++0x07 line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB0++0x07 line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB8++0x07 line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC0++0x07 line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC8++0x07 line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD0++0x07 line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD8++0x07 line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE0++0x07 line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE8++0x07 line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF0++0x07 line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF8++0x07 line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E00++0x07 line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E08++0x07 line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E10++0x07 line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E18++0x07 line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E20++0x07 line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E28++0x07 line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E30++0x07 line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E38++0x07 line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E40++0x07 line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E48++0x07 line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E50++0x07 line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E58++0x07 line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E60++0x07 line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E68++0x07 line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E70++0x07 line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E78++0x07 line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E80++0x07 line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E88++0x07 line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E90++0x07 line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E98++0x07 line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA0++0x07 line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA8++0x07 line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB0++0x07 line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB8++0x07 line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC0++0x07 line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC8++0x07 line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED0++0x07 line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED8++0x07 line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE0++0x07 line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE8++0x07 line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF0++0x07 line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF8++0x07 line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F00++0x07 line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F08++0x07 line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F10++0x07 line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F18++0x07 line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F20++0x07 line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F28++0x07 line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F30++0x07 line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F38++0x07 line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F40++0x07 line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F48++0x07 line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F50++0x07 line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F58++0x07 line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F60++0x07 line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F68++0x07 line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F70++0x07 line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F78++0x07 line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F80++0x07 line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F88++0x07 line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F90++0x07 line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F98++0x07 line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA0++0x07 line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA8++0x07 line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB0++0x07 line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB8++0x07 line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC0++0x07 line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC8++0x07 line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD0++0x07 line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD8++0x07 line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE0++0x07 line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE8++0x07 line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF0++0x07 line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF8++0x07 line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7000++0x07 line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7008++0x07 line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7010++0x07 line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7018++0x07 line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7020++0x07 line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7028++0x07 line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7030++0x07 line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7038++0x07 line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7040++0x07 line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7048++0x07 line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7050++0x07 line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7058++0x07 line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7060++0x07 line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7068++0x07 line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7070++0x07 line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7078++0x07 line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7080++0x07 line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7088++0x07 line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7090++0x07 line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7098++0x07 line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A0++0x07 line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A8++0x07 line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B0++0x07 line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B8++0x07 line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C0++0x07 line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C8++0x07 line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D0++0x07 line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D8++0x07 line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E0++0x07 line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E8++0x07 line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F0++0x07 line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F8++0x07 line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7100++0x07 line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7108++0x07 line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7110++0x07 line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7118++0x07 line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7120++0x07 line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7128++0x07 line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7130++0x07 line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7138++0x07 line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7140++0x07 line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7148++0x07 line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7150++0x07 line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7158++0x07 line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7160++0x07 line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7168++0x07 line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7170++0x07 line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7178++0x07 line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7180++0x07 line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7188++0x07 line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7190++0x07 line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7198++0x07 line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A0++0x07 line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A8++0x07 line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B0++0x07 line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B8++0x07 line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C0++0x07 line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C8++0x07 line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D0++0x07 line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D8++0x07 line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E0++0x07 line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E8++0x07 line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F0++0x07 line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F8++0x07 line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7200++0x07 line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7208++0x07 line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7210++0x07 line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7218++0x07 line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7220++0x07 line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7228++0x07 line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7230++0x07 line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7238++0x07 line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7240++0x07 line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7248++0x07 line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7250++0x07 line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7258++0x07 line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7260++0x07 line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7268++0x07 line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7270++0x07 line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7278++0x07 line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7280++0x07 line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7288++0x07 line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7290++0x07 line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7298++0x07 line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A0++0x07 line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A8++0x07 line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B0++0x07 line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B8++0x07 line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C0++0x07 line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C8++0x07 line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D0++0x07 line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D8++0x07 line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E0++0x07 line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E8++0x07 line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F0++0x07 line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F8++0x07 line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7300++0x07 line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7308++0x07 line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7310++0x07 line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7318++0x07 line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7320++0x07 line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7328++0x07 line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7330++0x07 line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7338++0x07 line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7340++0x07 line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7348++0x07 line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7350++0x07 line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7358++0x07 line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7360++0x07 line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7368++0x07 line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7370++0x07 line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7378++0x07 line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7380++0x07 line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7388++0x07 line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7390++0x07 line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7398++0x07 line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A0++0x07 line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A8++0x07 line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B0++0x07 line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B8++0x07 line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C0++0x07 line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C8++0x07 line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D0++0x07 line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D8++0x07 line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E0++0x07 line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E8++0x07 line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F0++0x07 line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F8++0x07 line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7400++0x07 line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7408++0x07 line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7410++0x07 line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7418++0x07 line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7420++0x07 line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7428++0x07 line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7430++0x07 line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7438++0x07 line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7440++0x07 line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7448++0x07 line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7450++0x07 line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7458++0x07 line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7460++0x07 line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7468++0x07 line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7470++0x07 line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7478++0x07 line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7480++0x07 line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7488++0x07 line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7490++0x07 line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7498++0x07 line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A0++0x07 line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A8++0x07 line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B0++0x07 line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B8++0x07 line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C0++0x07 line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C8++0x07 line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D0++0x07 line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D8++0x07 line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E0++0x07 line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E8++0x07 line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F0++0x07 line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F8++0x07 line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7500++0x07 line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7508++0x07 line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7510++0x07 line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7518++0x07 line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7520++0x07 line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7528++0x07 line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7530++0x07 line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7538++0x07 line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7540++0x07 line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7548++0x07 line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7550++0x07 line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7558++0x07 line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7560++0x07 line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7568++0x07 line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7570++0x07 line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7578++0x07 line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7580++0x07 line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7588++0x07 line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7590++0x07 line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7598++0x07 line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A0++0x07 line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A8++0x07 line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B0++0x07 line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B8++0x07 line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C0++0x07 line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C8++0x07 line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D0++0x07 line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D8++0x07 line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E0++0x07 line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E8++0x07 line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F0++0x07 line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F8++0x07 line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7600++0x07 line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7608++0x07 line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7610++0x07 line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7618++0x07 line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7620++0x07 line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7628++0x07 line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7630++0x07 line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7638++0x07 line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7640++0x07 line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7648++0x07 line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7650++0x07 line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7658++0x07 line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7660++0x07 line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7668++0x07 line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7670++0x07 line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7678++0x07 line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7680++0x07 line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7688++0x07 line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7690++0x07 line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7698++0x07 line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A0++0x07 line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A8++0x07 line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B0++0x07 line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B8++0x07 line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C0++0x07 line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C8++0x07 line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D0++0x07 line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D8++0x07 line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E0++0x07 line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E8++0x07 line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F0++0x07 line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F8++0x07 line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7700++0x07 line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7708++0x07 line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7710++0x07 line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7718++0x07 line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7720++0x07 line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7728++0x07 line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7730++0x07 line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7738++0x07 line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7740++0x07 line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7748++0x07 line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7750++0x07 line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7758++0x07 line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7760++0x07 line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7768++0x07 line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7770++0x07 line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7778++0x07 line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7780++0x07 line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7788++0x07 line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7790++0x07 line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7798++0x07 line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A0++0x07 line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A8++0x07 line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B0++0x07 line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B8++0x07 line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C0++0x07 line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C8++0x07 line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D0++0x07 line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D8++0x07 line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E0++0x07 line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E8++0x07 line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F0++0x07 line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F8++0x07 line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7800++0x07 line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7808++0x07 line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7810++0x07 line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7818++0x07 line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7820++0x07 line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7828++0x07 line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7830++0x07 line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7838++0x07 line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7840++0x07 line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7848++0x07 line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7850++0x07 line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7858++0x07 line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7860++0x07 line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7868++0x07 line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7870++0x07 line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7878++0x07 line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7880++0x07 line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7888++0x07 line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7890++0x07 line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7898++0x07 line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A0++0x07 line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A8++0x07 line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B0++0x07 line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B8++0x07 line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C0++0x07 line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C8++0x07 line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D0++0x07 line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D8++0x07 line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E0++0x07 line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E8++0x07 line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F0++0x07 line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F8++0x07 line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7900++0x07 line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7908++0x07 line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7910++0x07 line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7918++0x07 line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7920++0x07 line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7928++0x07 line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7930++0x07 line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7938++0x07 line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7940++0x07 line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7948++0x07 line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7950++0x07 line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7958++0x07 line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7960++0x07 line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7968++0x07 line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7970++0x07 line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7978++0x07 line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7980++0x07 line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7988++0x07 line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7990++0x07 line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7998++0x07 line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A0++0x07 line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A8++0x07 line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B0++0x07 line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B8++0x07 line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C0++0x07 line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C8++0x07 line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D0++0x07 line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D8++0x07 line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E0++0x07 line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E8++0x07 line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F0++0x07 line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F8++0x07 line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A00++0x07 line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A08++0x07 line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A10++0x07 line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A18++0x07 line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A20++0x07 line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A28++0x07 line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A30++0x07 line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A38++0x07 line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A40++0x07 line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A48++0x07 line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A50++0x07 line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A58++0x07 line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A60++0x07 line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A68++0x07 line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A70++0x07 line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A78++0x07 line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A80++0x07 line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A88++0x07 line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A90++0x07 line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A98++0x07 line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA0++0x07 line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA8++0x07 line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB0++0x07 line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB8++0x07 line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC0++0x07 line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC8++0x07 line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD0++0x07 line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD8++0x07 line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE0++0x07 line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE8++0x07 line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF0++0x07 line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF8++0x07 line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B00++0x07 line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B08++0x07 line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B10++0x07 line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B18++0x07 line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B20++0x07 line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B28++0x07 line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B30++0x07 line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B38++0x07 line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B40++0x07 line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B48++0x07 line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B50++0x07 line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B58++0x07 line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B60++0x07 line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B68++0x07 line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B70++0x07 line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B78++0x07 line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B80++0x07 line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B88++0x07 line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B90++0x07 line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B98++0x07 line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA0++0x07 line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA8++0x07 line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB0++0x07 line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB8++0x07 line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC0++0x07 line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC8++0x07 line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD0++0x07 line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD8++0x07 line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE0++0x07 line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE8++0x07 line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF0++0x07 line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF8++0x07 line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C00++0x07 line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C08++0x07 line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C10++0x07 line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C18++0x07 line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C20++0x07 line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C28++0x07 line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C30++0x07 line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C38++0x07 line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C40++0x07 line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C48++0x07 line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C50++0x07 line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C58++0x07 line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C60++0x07 line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C68++0x07 line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C70++0x07 line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C78++0x07 line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C80++0x07 line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C88++0x07 line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C90++0x07 line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C98++0x07 line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA0++0x07 line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA8++0x07 line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB0++0x07 line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB8++0x07 line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC0++0x07 line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC8++0x07 line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD0++0x07 line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD8++0x07 line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE0++0x07 line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE8++0x07 line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF0++0x07 line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF8++0x07 line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D00++0x07 line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D08++0x07 line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D10++0x07 line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D18++0x07 line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D20++0x07 line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D28++0x07 line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D30++0x07 line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D38++0x07 line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D40++0x07 line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D48++0x07 line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D50++0x07 line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D58++0x07 line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D60++0x07 line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D68++0x07 line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D70++0x07 line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D78++0x07 line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D80++0x07 line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D88++0x07 line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D90++0x07 line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D98++0x07 line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA0++0x07 line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA8++0x07 line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB0++0x07 line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB8++0x07 line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC0++0x07 line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC8++0x07 line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD0++0x07 line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD8++0x07 line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE0++0x07 line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE8++0x07 line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF0++0x07 line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF8++0x07 line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E00++0x07 line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E08++0x07 line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E10++0x07 line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E18++0x07 line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E20++0x07 line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E28++0x07 line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E30++0x07 line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E38++0x07 line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E40++0x07 line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E48++0x07 line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E50++0x07 line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E58++0x07 line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E60++0x07 line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E68++0x07 line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E70++0x07 line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E78++0x07 line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E80++0x07 line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E88++0x07 line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E90++0x07 line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E98++0x07 line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA0++0x07 line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA8++0x07 line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB0++0x07 line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB8++0x07 line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC0++0x07 line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC8++0x07 line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED0++0x07 line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED8++0x07 line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE0++0x07 line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE8++0x07 line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF0++0x07 line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF8++0x07 line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" tree.end width 22. tree "Implementation Defined Test Registers" rgroup.long 0xC000++0x03 line.long 0x00 "GICD_ESTATUSR,GICD_ESTATUSR" bitfld.long 0x00 31. " SRWP ,Super Register Write Pending" "Not pending,Pending" wgroup.long 0xC004++0x03 line.long 0x00 "GICD_ERRTESTR,Error Test Register" bitfld.long 0x00 1. " AXIM_ERR ,Drives the axim_err pin to 0b1 for 1 cycle" "Low,High" bitfld.long 0x00 0. " ECC_FATAL ,Drives the ecc_fatal pin to 0b1 for 1 cycle" "Low,High" textline " " if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) rgroup.long 0xC084++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " SPIS63 ,SPI Status Bit 63" "Low,High" bitfld.long 0x00 30. " SPIS62 ,SPI Status Bit 62" "Low,High" bitfld.long 0x00 29. " SPIS61 ,SPI Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " SPIS60 ,SPI Status Bit 60" "Low,High" bitfld.long 0x00 27. " SPIS59 ,SPI Status Bit 59" "Low,High" bitfld.long 0x00 26. " SPIS58 ,SPI Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " SPIS57 ,SPI Status Bit 57" "Low,High" bitfld.long 0x00 24. " SPIS56 ,SPI Status Bit 56" "Low,High" bitfld.long 0x00 23. " SPIS55 ,SPI Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " SPIS54 ,SPI Status Bit 54" "Low,High" bitfld.long 0x00 21. " SPIS53 ,SPI Status Bit 53" "Low,High" bitfld.long 0x00 20. " SPIS52 ,SPI Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " SPIS51 ,SPI Status Bit 51" "Low,High" bitfld.long 0x00 18. " SPIS50 ,SPI Status Bit 50" "Low,High" bitfld.long 0x00 17. " SPIS49 ,SPI Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " SPIS48 ,SPI Status Bit 48" "Low,High" bitfld.long 0x00 15. " SPIS47 ,SPI Status Bit 47" "Low,High" bitfld.long 0x00 14. " SPIS46 ,SPI Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " SPIS45 ,SPI Status Bit 45" "Low,High" bitfld.long 0x00 12. " SPIS44 ,SPI Status Bit 44" "Low,High" bitfld.long 0x00 11. " SPIS43 ,SPI Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " SPIS42 ,SPI Status Bit 42" "Low,High" bitfld.long 0x00 9. " SPIS41 ,SPI Status Bit 41" "Low,High" bitfld.long 0x00 8. " SPIS40 ,SPI Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " SPIS39 ,SPI Status Bit 39" "Low,High" bitfld.long 0x00 6. " SPIS38 ,SPI Status Bit 38" "Low,High" bitfld.long 0x00 5. " SPIS37 ,SPI Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " SPIS36 ,SPI Status Bit 36" "Low,High" bitfld.long 0x00 3. " SPIS35 ,SPI Status Bit 35" "Low,High" bitfld.long 0x00 2. " SPIS34 ,SPI Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " SPIS33 ,SPI Status Bit 33" "Low,High" bitfld.long 0x00 0. " SPIS32 ,SPI Status Bit 32" "Low,High" else hgroup.long 0xC084++0x03 hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) rgroup.long 0xC088++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " SPIS95 ,SPI Status Bit 95" "Low,High" bitfld.long 0x00 30. " SPIS94 ,SPI Status Bit 94" "Low,High" bitfld.long 0x00 29. " SPIS93 ,SPI Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " SPIS92 ,SPI Status Bit 92" "Low,High" bitfld.long 0x00 27. " SPIS91 ,SPI Status Bit 91" "Low,High" bitfld.long 0x00 26. " SPIS90 ,SPI Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " SPIS89 ,SPI Status Bit 89" "Low,High" bitfld.long 0x00 24. " SPIS88 ,SPI Status Bit 88" "Low,High" bitfld.long 0x00 23. " SPIS87 ,SPI Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " SPIS86 ,SPI Status Bit 86" "Low,High" bitfld.long 0x00 21. " SPIS85 ,SPI Status Bit 85" "Low,High" bitfld.long 0x00 20. " SPIS84 ,SPI Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " SPIS83 ,SPI Status Bit 83" "Low,High" bitfld.long 0x00 18. " SPIS82 ,SPI Status Bit 82" "Low,High" bitfld.long 0x00 17. " SPIS81 ,SPI Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " SPIS80 ,SPI Status Bit 80" "Low,High" bitfld.long 0x00 15. " SPIS79 ,SPI Status Bit 79" "Low,High" bitfld.long 0x00 14. " SPIS78 ,SPI Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " SPIS77 ,SPI Status Bit 77" "Low,High" bitfld.long 0x00 12. " SPIS76 ,SPI Status Bit 76" "Low,High" bitfld.long 0x00 11. " SPIS75 ,SPI Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " SPIS74 ,SPI Status Bit 74" "Low,High" bitfld.long 0x00 9. " SPIS73 ,SPI Status Bit 73" "Low,High" bitfld.long 0x00 8. " SPIS72 ,SPI Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " SPIS71 ,SPI Status Bit 71" "Low,High" bitfld.long 0x00 6. " SPIS70 ,SPI Status Bit 70" "Low,High" bitfld.long 0x00 5. " SPIS69 ,SPI Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " SPIS68 ,SPI Status Bit 68" "Low,High" bitfld.long 0x00 3. " SPIS67 ,SPI Status Bit 67" "Low,High" bitfld.long 0x00 2. " SPIS66 ,SPI Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " SPIS65 ,SPI Status Bit 65" "Low,High" bitfld.long 0x00 0. " SPIS64 ,SPI Status Bit 64" "Low,High" else hgroup.long 0xC088++0x03 hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) rgroup.long 0xC08C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " SPIS127 ,SPI Status Bit 127" "Low,High" bitfld.long 0x00 30. " SPIS126 ,SPI Status Bit 126" "Low,High" bitfld.long 0x00 29. " SPIS125 ,SPI Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " SPIS124 ,SPI Status Bit 124" "Low,High" bitfld.long 0x00 27. " SPIS123 ,SPI Status Bit 123" "Low,High" bitfld.long 0x00 26. " SPIS122 ,SPI Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " SPIS121 ,SPI Status Bit 121" "Low,High" bitfld.long 0x00 24. " SPIS120 ,SPI Status Bit 120" "Low,High" bitfld.long 0x00 23. " SPIS119 ,SPI Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " SPIS118 ,SPI Status Bit 118" "Low,High" bitfld.long 0x00 21. " SPIS117 ,SPI Status Bit 117" "Low,High" bitfld.long 0x00 20. " SPIS116 ,SPI Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " SPIS115 ,SPI Status Bit 115" "Low,High" bitfld.long 0x00 18. " SPIS114 ,SPI Status Bit 114" "Low,High" bitfld.long 0x00 17. " SPIS113 ,SPI Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " SPIS112 ,SPI Status Bit 112" "Low,High" bitfld.long 0x00 15. " SPIS111 ,SPI Status Bit 111" "Low,High" bitfld.long 0x00 14. " SPIS110 ,SPI Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " SPIS109 ,SPI Status Bit 109" "Low,High" bitfld.long 0x00 12. " SPIS108 ,SPI Status Bit 108" "Low,High" bitfld.long 0x00 11. " SPIS107 ,SPI Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " SPIS106 ,SPI Status Bit 106" "Low,High" bitfld.long 0x00 9. " SPIS105 ,SPI Status Bit 105" "Low,High" bitfld.long 0x00 8. " SPIS104 ,SPI Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " SPIS103 ,SPI Status Bit 103" "Low,High" bitfld.long 0x00 6. " SPIS102 ,SPI Status Bit 102" "Low,High" bitfld.long 0x00 5. " SPIS101 ,SPI Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " SPIS100 ,SPI Status Bit 100" "Low,High" bitfld.long 0x00 3. " SPIS99 ,SPI Status Bit 99" "Low,High" bitfld.long 0x00 2. " SPIS98 ,SPI Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " SPIS97 ,SPI Status Bit 97" "Low,High" bitfld.long 0x00 0. " SPIS96 ,SPI Status Bit 96" "Low,High" else hgroup.long 0xC08C++0x03 hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) rgroup.long 0xC090++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " SPIS159 ,SPI Status Bit 159" "Low,High" bitfld.long 0x00 30. " SPIS158 ,SPI Status Bit 158" "Low,High" bitfld.long 0x00 29. " SPIS157 ,SPI Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " SPIS156 ,SPI Status Bit 156" "Low,High" bitfld.long 0x00 27. " SPIS155 ,SPI Status Bit 155" "Low,High" bitfld.long 0x00 26. " SPIS154 ,SPI Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " SPIS153 ,SPI Status Bit 153" "Low,High" bitfld.long 0x00 24. " SPIS152 ,SPI Status Bit 152" "Low,High" bitfld.long 0x00 23. " SPIS151 ,SPI Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " SPIS150 ,SPI Status Bit 150" "Low,High" bitfld.long 0x00 21. " SPIS149 ,SPI Status Bit 149" "Low,High" bitfld.long 0x00 20. " SPIS148 ,SPI Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " SPIS147 ,SPI Status Bit 147" "Low,High" bitfld.long 0x00 18. " SPIS146 ,SPI Status Bit 146" "Low,High" bitfld.long 0x00 17. " SPIS145 ,SPI Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " SPIS144 ,SPI Status Bit 144" "Low,High" bitfld.long 0x00 15. " SPIS143 ,SPI Status Bit 143" "Low,High" bitfld.long 0x00 14. " SPIS142 ,SPI Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " SPIS141 ,SPI Status Bit 141" "Low,High" bitfld.long 0x00 12. " SPIS140 ,SPI Status Bit 140" "Low,High" bitfld.long 0x00 11. " SPIS139 ,SPI Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " SPIS138 ,SPI Status Bit 138" "Low,High" bitfld.long 0x00 9. " SPIS137 ,SPI Status Bit 137" "Low,High" bitfld.long 0x00 8. " SPIS136 ,SPI Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " SPIS135 ,SPI Status Bit 135" "Low,High" bitfld.long 0x00 6. " SPIS134 ,SPI Status Bit 134" "Low,High" bitfld.long 0x00 5. " SPIS133 ,SPI Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " SPIS132 ,SPI Status Bit 132" "Low,High" bitfld.long 0x00 3. " SPIS131 ,SPI Status Bit 131" "Low,High" bitfld.long 0x00 2. " SPIS130 ,SPI Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " SPIS129 ,SPI Status Bit 129" "Low,High" bitfld.long 0x00 0. " SPIS128 ,SPI Status Bit 128" "Low,High" else hgroup.long 0xC090++0x03 hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) rgroup.long 0xC094++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " SPIS191 ,SPI Status Bit 191" "Low,High" bitfld.long 0x00 30. " SPIS190 ,SPI Status Bit 190" "Low,High" bitfld.long 0x00 29. " SPIS189 ,SPI Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " SPIS188 ,SPI Status Bit 188" "Low,High" bitfld.long 0x00 27. " SPIS187 ,SPI Status Bit 187" "Low,High" bitfld.long 0x00 26. " SPIS186 ,SPI Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " SPIS185 ,SPI Status Bit 185" "Low,High" bitfld.long 0x00 24. " SPIS184 ,SPI Status Bit 184" "Low,High" bitfld.long 0x00 23. " SPIS183 ,SPI Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " SPIS182 ,SPI Status Bit 182" "Low,High" bitfld.long 0x00 21. " SPIS181 ,SPI Status Bit 181" "Low,High" bitfld.long 0x00 20. " SPIS180 ,SPI Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " SPIS179 ,SPI Status Bit 179" "Low,High" bitfld.long 0x00 18. " SPIS178 ,SPI Status Bit 178" "Low,High" bitfld.long 0x00 17. " SPIS177 ,SPI Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " SPIS176 ,SPI Status Bit 176" "Low,High" bitfld.long 0x00 15. " SPIS175 ,SPI Status Bit 175" "Low,High" bitfld.long 0x00 14. " SPIS174 ,SPI Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " SPIS173 ,SPI Status Bit 173" "Low,High" bitfld.long 0x00 12. " SPIS172 ,SPI Status Bit 172" "Low,High" bitfld.long 0x00 11. " SPIS171 ,SPI Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " SPIS170 ,SPI Status Bit 170" "Low,High" bitfld.long 0x00 9. " SPIS169 ,SPI Status Bit 169" "Low,High" bitfld.long 0x00 8. " SPIS168 ,SPI Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " SPIS167 ,SPI Status Bit 167" "Low,High" bitfld.long 0x00 6. " SPIS166 ,SPI Status Bit 166" "Low,High" bitfld.long 0x00 5. " SPIS165 ,SPI Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " SPIS164 ,SPI Status Bit 164" "Low,High" bitfld.long 0x00 3. " SPIS163 ,SPI Status Bit 163" "Low,High" bitfld.long 0x00 2. " SPIS162 ,SPI Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " SPIS161 ,SPI Status Bit 161" "Low,High" bitfld.long 0x00 0. " SPIS160 ,SPI Status Bit 160" "Low,High" else hgroup.long 0xC094++0x03 hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) rgroup.long 0xC098++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " SPIS223 ,SPI Status Bit 223" "Low,High" bitfld.long 0x00 30. " SPIS222 ,SPI Status Bit 222" "Low,High" bitfld.long 0x00 29. " SPIS221 ,SPI Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " SPIS220 ,SPI Status Bit 220" "Low,High" bitfld.long 0x00 27. " SPIS219 ,SPI Status Bit 219" "Low,High" bitfld.long 0x00 26. " SPIS218 ,SPI Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " SPIS217 ,SPI Status Bit 217" "Low,High" bitfld.long 0x00 24. " SPIS216 ,SPI Status Bit 216" "Low,High" bitfld.long 0x00 23. " SPIS215 ,SPI Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " SPIS214 ,SPI Status Bit 214" "Low,High" bitfld.long 0x00 21. " SPIS213 ,SPI Status Bit 213" "Low,High" bitfld.long 0x00 20. " SPIS212 ,SPI Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " SPIS211 ,SPI Status Bit 211" "Low,High" bitfld.long 0x00 18. " SPIS210 ,SPI Status Bit 210" "Low,High" bitfld.long 0x00 17. " SPIS209 ,SPI Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " SPIS208 ,SPI Status Bit 208" "Low,High" bitfld.long 0x00 15. " SPIS207 ,SPI Status Bit 207" "Low,High" bitfld.long 0x00 14. " SPIS206 ,SPI Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " SPIS205 ,SPI Status Bit 205" "Low,High" bitfld.long 0x00 12. " SPIS204 ,SPI Status Bit 204" "Low,High" bitfld.long 0x00 11. " SPIS203 ,SPI Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " SPIS202 ,SPI Status Bit 202" "Low,High" bitfld.long 0x00 9. " SPIS201 ,SPI Status Bit 201" "Low,High" bitfld.long 0x00 8. " SPIS200 ,SPI Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " SPIS199 ,SPI Status Bit 199" "Low,High" bitfld.long 0x00 6. " SPIS198 ,SPI Status Bit 198" "Low,High" bitfld.long 0x00 5. " SPIS197 ,SPI Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " SPIS196 ,SPI Status Bit 196" "Low,High" bitfld.long 0x00 3. " SPIS195 ,SPI Status Bit 195" "Low,High" bitfld.long 0x00 2. " SPIS194 ,SPI Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " SPIS193 ,SPI Status Bit 193" "Low,High" bitfld.long 0x00 0. " SPIS192 ,SPI Status Bit 192" "Low,High" else hgroup.long 0xC098++0x03 hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) rgroup.long 0xC09C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " SPIS255 ,SPI Status Bit 255" "Low,High" bitfld.long 0x00 30. " SPIS254 ,SPI Status Bit 254" "Low,High" bitfld.long 0x00 29. " SPIS253 ,SPI Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " SPIS252 ,SPI Status Bit 252" "Low,High" bitfld.long 0x00 27. " SPIS251 ,SPI Status Bit 251" "Low,High" bitfld.long 0x00 26. " SPIS250 ,SPI Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " SPIS249 ,SPI Status Bit 249" "Low,High" bitfld.long 0x00 24. " SPIS248 ,SPI Status Bit 248" "Low,High" bitfld.long 0x00 23. " SPIS247 ,SPI Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " SPIS246 ,SPI Status Bit 246" "Low,High" bitfld.long 0x00 21. " SPIS245 ,SPI Status Bit 245" "Low,High" bitfld.long 0x00 20. " SPIS244 ,SPI Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " SPIS243 ,SPI Status Bit 243" "Low,High" bitfld.long 0x00 18. " SPIS242 ,SPI Status Bit 242" "Low,High" bitfld.long 0x00 17. " SPIS241 ,SPI Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " SPIS240 ,SPI Status Bit 240" "Low,High" bitfld.long 0x00 15. " SPIS239 ,SPI Status Bit 239" "Low,High" bitfld.long 0x00 14. " SPIS238 ,SPI Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " SPIS237 ,SPI Status Bit 237" "Low,High" bitfld.long 0x00 12. " SPIS236 ,SPI Status Bit 236" "Low,High" bitfld.long 0x00 11. " SPIS235 ,SPI Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " SPIS234 ,SPI Status Bit 234" "Low,High" bitfld.long 0x00 9. " SPIS233 ,SPI Status Bit 233" "Low,High" bitfld.long 0x00 8. " SPIS232 ,SPI Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " SPIS231 ,SPI Status Bit 231" "Low,High" bitfld.long 0x00 6. " SPIS230 ,SPI Status Bit 230" "Low,High" bitfld.long 0x00 5. " SPIS229 ,SPI Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " SPIS228 ,SPI Status Bit 228" "Low,High" bitfld.long 0x00 3. " SPIS227 ,SPI Status Bit 227" "Low,High" bitfld.long 0x00 2. " SPIS226 ,SPI Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " SPIS225 ,SPI Status Bit 225" "Low,High" bitfld.long 0x00 0. " SPIS224 ,SPI Status Bit 224" "Low,High" else hgroup.long 0xC09C++0x03 hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) rgroup.long 0xC0A0++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " SPIS287 ,SPI Status Bit 287" "Low,High" bitfld.long 0x00 30. " SPIS286 ,SPI Status Bit 286" "Low,High" bitfld.long 0x00 29. " SPIS285 ,SPI Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " SPIS284 ,SPI Status Bit 284" "Low,High" bitfld.long 0x00 27. " SPIS283 ,SPI Status Bit 283" "Low,High" bitfld.long 0x00 26. " SPIS282 ,SPI Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " SPIS281 ,SPI Status Bit 281" "Low,High" bitfld.long 0x00 24. " SPIS280 ,SPI Status Bit 280" "Low,High" bitfld.long 0x00 23. " SPIS279 ,SPI Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " SPIS278 ,SPI Status Bit 278" "Low,High" bitfld.long 0x00 21. " SPIS277 ,SPI Status Bit 277" "Low,High" bitfld.long 0x00 20. " SPIS276 ,SPI Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " SPIS275 ,SPI Status Bit 275" "Low,High" bitfld.long 0x00 18. " SPIS274 ,SPI Status Bit 274" "Low,High" bitfld.long 0x00 17. " SPIS273 ,SPI Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " SPIS272 ,SPI Status Bit 272" "Low,High" bitfld.long 0x00 15. " SPIS271 ,SPI Status Bit 271" "Low,High" bitfld.long 0x00 14. " SPIS270 ,SPI Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " SPIS269 ,SPI Status Bit 269" "Low,High" bitfld.long 0x00 12. " SPIS268 ,SPI Status Bit 268" "Low,High" bitfld.long 0x00 11. " SPIS267 ,SPI Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " SPIS266 ,SPI Status Bit 266" "Low,High" bitfld.long 0x00 9. " SPIS265 ,SPI Status Bit 265" "Low,High" bitfld.long 0x00 8. " SPIS264 ,SPI Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " SPIS263 ,SPI Status Bit 263" "Low,High" bitfld.long 0x00 6. " SPIS262 ,SPI Status Bit 262" "Low,High" bitfld.long 0x00 5. " SPIS261 ,SPI Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " SPIS260 ,SPI Status Bit 260" "Low,High" bitfld.long 0x00 3. " SPIS259 ,SPI Status Bit 259" "Low,High" bitfld.long 0x00 2. " SPIS258 ,SPI Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " SPIS257 ,SPI Status Bit 257" "Low,High" bitfld.long 0x00 0. " SPIS256 ,SPI Status Bit 256" "Low,High" else hgroup.long 0xC0A0++0x03 hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) rgroup.long 0xC0A4++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " SPIS319 ,SPI Status Bit 319" "Low,High" bitfld.long 0x00 30. " SPIS318 ,SPI Status Bit 318" "Low,High" bitfld.long 0x00 29. " SPIS317 ,SPI Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " SPIS316 ,SPI Status Bit 316" "Low,High" bitfld.long 0x00 27. " SPIS315 ,SPI Status Bit 315" "Low,High" bitfld.long 0x00 26. " SPIS314 ,SPI Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " SPIS313 ,SPI Status Bit 313" "Low,High" bitfld.long 0x00 24. " SPIS312 ,SPI Status Bit 312" "Low,High" bitfld.long 0x00 23. " SPIS311 ,SPI Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " SPIS310 ,SPI Status Bit 310" "Low,High" bitfld.long 0x00 21. " SPIS309 ,SPI Status Bit 309" "Low,High" bitfld.long 0x00 20. " SPIS308 ,SPI Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " SPIS307 ,SPI Status Bit 307" "Low,High" bitfld.long 0x00 18. " SPIS306 ,SPI Status Bit 306" "Low,High" bitfld.long 0x00 17. " SPIS305 ,SPI Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " SPIS304 ,SPI Status Bit 304" "Low,High" bitfld.long 0x00 15. " SPIS303 ,SPI Status Bit 303" "Low,High" bitfld.long 0x00 14. " SPIS302 ,SPI Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " SPIS301 ,SPI Status Bit 301" "Low,High" bitfld.long 0x00 12. " SPIS300 ,SPI Status Bit 300" "Low,High" bitfld.long 0x00 11. " SPIS299 ,SPI Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " SPIS298 ,SPI Status Bit 298" "Low,High" bitfld.long 0x00 9. " SPIS297 ,SPI Status Bit 297" "Low,High" bitfld.long 0x00 8. " SPIS296 ,SPI Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " SPIS295 ,SPI Status Bit 295" "Low,High" bitfld.long 0x00 6. " SPIS294 ,SPI Status Bit 294" "Low,High" bitfld.long 0x00 5. " SPIS293 ,SPI Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " SPIS292 ,SPI Status Bit 292" "Low,High" bitfld.long 0x00 3. " SPIS291 ,SPI Status Bit 291" "Low,High" bitfld.long 0x00 2. " SPIS290 ,SPI Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " SPIS289 ,SPI Status Bit 289" "Low,High" bitfld.long 0x00 0. " SPIS288 ,SPI Status Bit 288" "Low,High" else hgroup.long 0xC0A4++0x03 hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) rgroup.long 0xC0A8++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " SPIS351 ,SPI Status Bit 351" "Low,High" bitfld.long 0x00 30. " SPIS350 ,SPI Status Bit 350" "Low,High" bitfld.long 0x00 29. " SPIS349 ,SPI Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " SPIS348 ,SPI Status Bit 348" "Low,High" bitfld.long 0x00 27. " SPIS347 ,SPI Status Bit 347" "Low,High" bitfld.long 0x00 26. " SPIS346 ,SPI Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " SPIS345 ,SPI Status Bit 345" "Low,High" bitfld.long 0x00 24. " SPIS344 ,SPI Status Bit 344" "Low,High" bitfld.long 0x00 23. " SPIS343 ,SPI Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " SPIS342 ,SPI Status Bit 342" "Low,High" bitfld.long 0x00 21. " SPIS341 ,SPI Status Bit 341" "Low,High" bitfld.long 0x00 20. " SPIS340 ,SPI Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " SPIS339 ,SPI Status Bit 339" "Low,High" bitfld.long 0x00 18. " SPIS338 ,SPI Status Bit 338" "Low,High" bitfld.long 0x00 17. " SPIS337 ,SPI Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " SPIS336 ,SPI Status Bit 336" "Low,High" bitfld.long 0x00 15. " SPIS335 ,SPI Status Bit 335" "Low,High" bitfld.long 0x00 14. " SPIS334 ,SPI Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " SPIS333 ,SPI Status Bit 333" "Low,High" bitfld.long 0x00 12. " SPIS332 ,SPI Status Bit 332" "Low,High" bitfld.long 0x00 11. " SPIS331 ,SPI Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " SPIS330 ,SPI Status Bit 330" "Low,High" bitfld.long 0x00 9. " SPIS329 ,SPI Status Bit 329" "Low,High" bitfld.long 0x00 8. " SPIS328 ,SPI Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " SPIS327 ,SPI Status Bit 327" "Low,High" bitfld.long 0x00 6. " SPIS326 ,SPI Status Bit 326" "Low,High" bitfld.long 0x00 5. " SPIS325 ,SPI Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " SPIS324 ,SPI Status Bit 324" "Low,High" bitfld.long 0x00 3. " SPIS323 ,SPI Status Bit 323" "Low,High" bitfld.long 0x00 2. " SPIS322 ,SPI Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " SPIS321 ,SPI Status Bit 321" "Low,High" bitfld.long 0x00 0. " SPIS320 ,SPI Status Bit 320" "Low,High" else hgroup.long 0xC0A8++0x03 hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) rgroup.long 0xC0AC++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " SPIS383 ,SPI Status Bit 383" "Low,High" bitfld.long 0x00 30. " SPIS382 ,SPI Status Bit 382" "Low,High" bitfld.long 0x00 29. " SPIS381 ,SPI Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " SPIS380 ,SPI Status Bit 380" "Low,High" bitfld.long 0x00 27. " SPIS379 ,SPI Status Bit 379" "Low,High" bitfld.long 0x00 26. " SPIS378 ,SPI Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " SPIS377 ,SPI Status Bit 377" "Low,High" bitfld.long 0x00 24. " SPIS376 ,SPI Status Bit 376" "Low,High" bitfld.long 0x00 23. " SPIS375 ,SPI Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " SPIS374 ,SPI Status Bit 374" "Low,High" bitfld.long 0x00 21. " SPIS373 ,SPI Status Bit 373" "Low,High" bitfld.long 0x00 20. " SPIS372 ,SPI Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " SPIS371 ,SPI Status Bit 371" "Low,High" bitfld.long 0x00 18. " SPIS370 ,SPI Status Bit 370" "Low,High" bitfld.long 0x00 17. " SPIS369 ,SPI Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " SPIS368 ,SPI Status Bit 368" "Low,High" bitfld.long 0x00 15. " SPIS367 ,SPI Status Bit 367" "Low,High" bitfld.long 0x00 14. " SPIS366 ,SPI Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " SPIS365 ,SPI Status Bit 365" "Low,High" bitfld.long 0x00 12. " SPIS364 ,SPI Status Bit 364" "Low,High" bitfld.long 0x00 11. " SPIS363 ,SPI Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " SPIS362 ,SPI Status Bit 362" "Low,High" bitfld.long 0x00 9. " SPIS361 ,SPI Status Bit 361" "Low,High" bitfld.long 0x00 8. " SPIS360 ,SPI Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " SPIS359 ,SPI Status Bit 359" "Low,High" bitfld.long 0x00 6. " SPIS358 ,SPI Status Bit 358" "Low,High" bitfld.long 0x00 5. " SPIS357 ,SPI Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " SPIS356 ,SPI Status Bit 356" "Low,High" bitfld.long 0x00 3. " SPIS355 ,SPI Status Bit 355" "Low,High" bitfld.long 0x00 2. " SPIS354 ,SPI Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " SPIS353 ,SPI Status Bit 353" "Low,High" bitfld.long 0x00 0. " SPIS352 ,SPI Status Bit 352" "Low,High" else hgroup.long 0xC0AC++0x03 hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) rgroup.long 0xC0B0++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " SPIS415 ,SPI Status Bit 415" "Low,High" bitfld.long 0x00 30. " SPIS414 ,SPI Status Bit 414" "Low,High" bitfld.long 0x00 29. " SPIS413 ,SPI Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " SPIS412 ,SPI Status Bit 412" "Low,High" bitfld.long 0x00 27. " SPIS411 ,SPI Status Bit 411" "Low,High" bitfld.long 0x00 26. " SPIS410 ,SPI Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " SPIS409 ,SPI Status Bit 409" "Low,High" bitfld.long 0x00 24. " SPIS408 ,SPI Status Bit 408" "Low,High" bitfld.long 0x00 23. " SPIS407 ,SPI Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " SPIS406 ,SPI Status Bit 406" "Low,High" bitfld.long 0x00 21. " SPIS405 ,SPI Status Bit 405" "Low,High" bitfld.long 0x00 20. " SPIS404 ,SPI Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " SPIS403 ,SPI Status Bit 403" "Low,High" bitfld.long 0x00 18. " SPIS402 ,SPI Status Bit 402" "Low,High" bitfld.long 0x00 17. " SPIS401 ,SPI Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " SPIS400 ,SPI Status Bit 400" "Low,High" bitfld.long 0x00 15. " SPIS399 ,SPI Status Bit 399" "Low,High" bitfld.long 0x00 14. " SPIS398 ,SPI Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " SPIS397 ,SPI Status Bit 397" "Low,High" bitfld.long 0x00 12. " SPIS396 ,SPI Status Bit 396" "Low,High" bitfld.long 0x00 11. " SPIS395 ,SPI Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " SPIS394 ,SPI Status Bit 394" "Low,High" bitfld.long 0x00 9. " SPIS393 ,SPI Status Bit 393" "Low,High" bitfld.long 0x00 8. " SPIS392 ,SPI Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " SPIS391 ,SPI Status Bit 391" "Low,High" bitfld.long 0x00 6. " SPIS390 ,SPI Status Bit 390" "Low,High" bitfld.long 0x00 5. " SPIS389 ,SPI Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " SPIS388 ,SPI Status Bit 388" "Low,High" bitfld.long 0x00 3. " SPIS387 ,SPI Status Bit 387" "Low,High" bitfld.long 0x00 2. " SPIS386 ,SPI Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " SPIS385 ,SPI Status Bit 385" "Low,High" bitfld.long 0x00 0. " SPIS384 ,SPI Status Bit 384" "Low,High" else hgroup.long 0xC0B0++0x03 hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) rgroup.long 0xC0B4++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " SPIS447 ,SPI Status Bit 447" "Low,High" bitfld.long 0x00 30. " SPIS446 ,SPI Status Bit 446" "Low,High" bitfld.long 0x00 29. " SPIS445 ,SPI Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " SPIS444 ,SPI Status Bit 444" "Low,High" bitfld.long 0x00 27. " SPIS443 ,SPI Status Bit 443" "Low,High" bitfld.long 0x00 26. " SPIS442 ,SPI Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " SPIS441 ,SPI Status Bit 441" "Low,High" bitfld.long 0x00 24. " SPIS440 ,SPI Status Bit 440" "Low,High" bitfld.long 0x00 23. " SPIS439 ,SPI Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " SPIS438 ,SPI Status Bit 438" "Low,High" bitfld.long 0x00 21. " SPIS437 ,SPI Status Bit 437" "Low,High" bitfld.long 0x00 20. " SPIS436 ,SPI Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " SPIS435 ,SPI Status Bit 435" "Low,High" bitfld.long 0x00 18. " SPIS434 ,SPI Status Bit 434" "Low,High" bitfld.long 0x00 17. " SPIS433 ,SPI Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " SPIS432 ,SPI Status Bit 432" "Low,High" bitfld.long 0x00 15. " SPIS431 ,SPI Status Bit 431" "Low,High" bitfld.long 0x00 14. " SPIS430 ,SPI Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " SPIS429 ,SPI Status Bit 429" "Low,High" bitfld.long 0x00 12. " SPIS428 ,SPI Status Bit 428" "Low,High" bitfld.long 0x00 11. " SPIS427 ,SPI Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " SPIS426 ,SPI Status Bit 426" "Low,High" bitfld.long 0x00 9. " SPIS425 ,SPI Status Bit 425" "Low,High" bitfld.long 0x00 8. " SPIS424 ,SPI Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " SPIS423 ,SPI Status Bit 423" "Low,High" bitfld.long 0x00 6. " SPIS422 ,SPI Status Bit 422" "Low,High" bitfld.long 0x00 5. " SPIS421 ,SPI Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " SPIS420 ,SPI Status Bit 420" "Low,High" bitfld.long 0x00 3. " SPIS419 ,SPI Status Bit 419" "Low,High" bitfld.long 0x00 2. " SPIS418 ,SPI Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " SPIS417 ,SPI Status Bit 417" "Low,High" bitfld.long 0x00 0. " SPIS416 ,SPI Status Bit 416" "Low,High" else hgroup.long 0xC0B4++0x03 hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) rgroup.long 0xC0B8++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " SPIS479 ,SPI Status Bit 479" "Low,High" bitfld.long 0x00 30. " SPIS478 ,SPI Status Bit 478" "Low,High" bitfld.long 0x00 29. " SPIS477 ,SPI Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " SPIS476 ,SPI Status Bit 476" "Low,High" bitfld.long 0x00 27. " SPIS475 ,SPI Status Bit 475" "Low,High" bitfld.long 0x00 26. " SPIS474 ,SPI Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " SPIS473 ,SPI Status Bit 473" "Low,High" bitfld.long 0x00 24. " SPIS472 ,SPI Status Bit 472" "Low,High" bitfld.long 0x00 23. " SPIS471 ,SPI Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " SPIS470 ,SPI Status Bit 470" "Low,High" bitfld.long 0x00 21. " SPIS469 ,SPI Status Bit 469" "Low,High" bitfld.long 0x00 20. " SPIS468 ,SPI Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " SPIS467 ,SPI Status Bit 467" "Low,High" bitfld.long 0x00 18. " SPIS466 ,SPI Status Bit 466" "Low,High" bitfld.long 0x00 17. " SPIS465 ,SPI Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " SPIS464 ,SPI Status Bit 464" "Low,High" bitfld.long 0x00 15. " SPIS463 ,SPI Status Bit 463" "Low,High" bitfld.long 0x00 14. " SPIS462 ,SPI Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " SPIS461 ,SPI Status Bit 461" "Low,High" bitfld.long 0x00 12. " SPIS460 ,SPI Status Bit 460" "Low,High" bitfld.long 0x00 11. " SPIS459 ,SPI Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " SPIS458 ,SPI Status Bit 458" "Low,High" bitfld.long 0x00 9. " SPIS457 ,SPI Status Bit 457" "Low,High" bitfld.long 0x00 8. " SPIS456 ,SPI Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " SPIS455 ,SPI Status Bit 455" "Low,High" bitfld.long 0x00 6. " SPIS454 ,SPI Status Bit 454" "Low,High" bitfld.long 0x00 5. " SPIS453 ,SPI Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " SPIS452 ,SPI Status Bit 452" "Low,High" bitfld.long 0x00 3. " SPIS451 ,SPI Status Bit 451" "Low,High" bitfld.long 0x00 2. " SPIS450 ,SPI Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " SPIS449 ,SPI Status Bit 449" "Low,High" bitfld.long 0x00 0. " SPIS448 ,SPI Status Bit 448" "Low,High" else hgroup.long 0xC0B8++0x03 hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) rgroup.long 0xC0BC++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " SPIS511 ,SPI Status Bit 511" "Low,High" bitfld.long 0x00 30. " SPIS510 ,SPI Status Bit 510" "Low,High" bitfld.long 0x00 29. " SPIS509 ,SPI Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " SPIS508 ,SPI Status Bit 508" "Low,High" bitfld.long 0x00 27. " SPIS507 ,SPI Status Bit 507" "Low,High" bitfld.long 0x00 26. " SPIS506 ,SPI Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " SPIS505 ,SPI Status Bit 505" "Low,High" bitfld.long 0x00 24. " SPIS504 ,SPI Status Bit 504" "Low,High" bitfld.long 0x00 23. " SPIS503 ,SPI Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " SPIS502 ,SPI Status Bit 502" "Low,High" bitfld.long 0x00 21. " SPIS501 ,SPI Status Bit 501" "Low,High" bitfld.long 0x00 20. " SPIS500 ,SPI Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " SPIS499 ,SPI Status Bit 499" "Low,High" bitfld.long 0x00 18. " SPIS498 ,SPI Status Bit 498" "Low,High" bitfld.long 0x00 17. " SPIS497 ,SPI Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " SPIS496 ,SPI Status Bit 496" "Low,High" bitfld.long 0x00 15. " SPIS495 ,SPI Status Bit 495" "Low,High" bitfld.long 0x00 14. " SPIS494 ,SPI Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " SPIS493 ,SPI Status Bit 493" "Low,High" bitfld.long 0x00 12. " SPIS492 ,SPI Status Bit 492" "Low,High" bitfld.long 0x00 11. " SPIS491 ,SPI Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " SPIS490 ,SPI Status Bit 490" "Low,High" bitfld.long 0x00 9. " SPIS489 ,SPI Status Bit 489" "Low,High" bitfld.long 0x00 8. " SPIS488 ,SPI Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " SPIS487 ,SPI Status Bit 487" "Low,High" bitfld.long 0x00 6. " SPIS486 ,SPI Status Bit 486" "Low,High" bitfld.long 0x00 5. " SPIS485 ,SPI Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " SPIS484 ,SPI Status Bit 484" "Low,High" bitfld.long 0x00 3. " SPIS483 ,SPI Status Bit 483" "Low,High" bitfld.long 0x00 2. " SPIS482 ,SPI Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " SPIS481 ,SPI Status Bit 481" "Low,High" bitfld.long 0x00 0. " SPIS480 ,SPI Status Bit 480" "Low,High" else hgroup.long 0xC0BC++0x03 hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) rgroup.long 0xC0C0++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " SPIS543 ,SPI Status Bit 543" "Low,High" bitfld.long 0x00 30. " SPIS542 ,SPI Status Bit 542" "Low,High" bitfld.long 0x00 29. " SPIS541 ,SPI Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " SPIS540 ,SPI Status Bit 540" "Low,High" bitfld.long 0x00 27. " SPIS539 ,SPI Status Bit 539" "Low,High" bitfld.long 0x00 26. " SPIS538 ,SPI Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " SPIS537 ,SPI Status Bit 537" "Low,High" bitfld.long 0x00 24. " SPIS536 ,SPI Status Bit 536" "Low,High" bitfld.long 0x00 23. " SPIS535 ,SPI Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " SPIS534 ,SPI Status Bit 534" "Low,High" bitfld.long 0x00 21. " SPIS533 ,SPI Status Bit 533" "Low,High" bitfld.long 0x00 20. " SPIS532 ,SPI Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " SPIS531 ,SPI Status Bit 531" "Low,High" bitfld.long 0x00 18. " SPIS530 ,SPI Status Bit 530" "Low,High" bitfld.long 0x00 17. " SPIS529 ,SPI Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " SPIS528 ,SPI Status Bit 528" "Low,High" bitfld.long 0x00 15. " SPIS527 ,SPI Status Bit 527" "Low,High" bitfld.long 0x00 14. " SPIS526 ,SPI Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " SPIS525 ,SPI Status Bit 525" "Low,High" bitfld.long 0x00 12. " SPIS524 ,SPI Status Bit 524" "Low,High" bitfld.long 0x00 11. " SPIS523 ,SPI Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " SPIS522 ,SPI Status Bit 522" "Low,High" bitfld.long 0x00 9. " SPIS521 ,SPI Status Bit 521" "Low,High" bitfld.long 0x00 8. " SPIS520 ,SPI Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " SPIS519 ,SPI Status Bit 519" "Low,High" bitfld.long 0x00 6. " SPIS518 ,SPI Status Bit 518" "Low,High" bitfld.long 0x00 5. " SPIS517 ,SPI Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " SPIS516 ,SPI Status Bit 516" "Low,High" bitfld.long 0x00 3. " SPIS515 ,SPI Status Bit 515" "Low,High" bitfld.long 0x00 2. " SPIS514 ,SPI Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " SPIS513 ,SPI Status Bit 513" "Low,High" bitfld.long 0x00 0. " SPIS512 ,SPI Status Bit 512" "Low,High" else hgroup.long 0xC0C0++0x03 hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) rgroup.long 0xC0C4++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " SPIS575 ,SPI Status Bit 575" "Low,High" bitfld.long 0x00 30. " SPIS574 ,SPI Status Bit 574" "Low,High" bitfld.long 0x00 29. " SPIS573 ,SPI Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " SPIS572 ,SPI Status Bit 572" "Low,High" bitfld.long 0x00 27. " SPIS571 ,SPI Status Bit 571" "Low,High" bitfld.long 0x00 26. " SPIS570 ,SPI Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " SPIS569 ,SPI Status Bit 569" "Low,High" bitfld.long 0x00 24. " SPIS568 ,SPI Status Bit 568" "Low,High" bitfld.long 0x00 23. " SPIS567 ,SPI Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " SPIS566 ,SPI Status Bit 566" "Low,High" bitfld.long 0x00 21. " SPIS565 ,SPI Status Bit 565" "Low,High" bitfld.long 0x00 20. " SPIS564 ,SPI Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " SPIS563 ,SPI Status Bit 563" "Low,High" bitfld.long 0x00 18. " SPIS562 ,SPI Status Bit 562" "Low,High" bitfld.long 0x00 17. " SPIS561 ,SPI Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " SPIS560 ,SPI Status Bit 560" "Low,High" bitfld.long 0x00 15. " SPIS559 ,SPI Status Bit 559" "Low,High" bitfld.long 0x00 14. " SPIS558 ,SPI Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " SPIS557 ,SPI Status Bit 557" "Low,High" bitfld.long 0x00 12. " SPIS556 ,SPI Status Bit 556" "Low,High" bitfld.long 0x00 11. " SPIS555 ,SPI Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " SPIS554 ,SPI Status Bit 554" "Low,High" bitfld.long 0x00 9. " SPIS553 ,SPI Status Bit 553" "Low,High" bitfld.long 0x00 8. " SPIS552 ,SPI Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " SPIS551 ,SPI Status Bit 551" "Low,High" bitfld.long 0x00 6. " SPIS550 ,SPI Status Bit 550" "Low,High" bitfld.long 0x00 5. " SPIS549 ,SPI Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " SPIS548 ,SPI Status Bit 548" "Low,High" bitfld.long 0x00 3. " SPIS547 ,SPI Status Bit 547" "Low,High" bitfld.long 0x00 2. " SPIS546 ,SPI Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " SPIS545 ,SPI Status Bit 545" "Low,High" bitfld.long 0x00 0. " SPIS544 ,SPI Status Bit 544" "Low,High" else hgroup.long 0xC0C4++0x03 hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) rgroup.long 0xC0C8++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " SPIS607 ,SPI Status Bit 607" "Low,High" bitfld.long 0x00 30. " SPIS606 ,SPI Status Bit 606" "Low,High" bitfld.long 0x00 29. " SPIS605 ,SPI Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " SPIS604 ,SPI Status Bit 604" "Low,High" bitfld.long 0x00 27. " SPIS603 ,SPI Status Bit 603" "Low,High" bitfld.long 0x00 26. " SPIS602 ,SPI Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " SPIS601 ,SPI Status Bit 601" "Low,High" bitfld.long 0x00 24. " SPIS600 ,SPI Status Bit 600" "Low,High" bitfld.long 0x00 23. " SPIS599 ,SPI Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " SPIS598 ,SPI Status Bit 598" "Low,High" bitfld.long 0x00 21. " SPIS597 ,SPI Status Bit 597" "Low,High" bitfld.long 0x00 20. " SPIS596 ,SPI Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " SPIS595 ,SPI Status Bit 595" "Low,High" bitfld.long 0x00 18. " SPIS594 ,SPI Status Bit 594" "Low,High" bitfld.long 0x00 17. " SPIS593 ,SPI Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " SPIS592 ,SPI Status Bit 592" "Low,High" bitfld.long 0x00 15. " SPIS591 ,SPI Status Bit 591" "Low,High" bitfld.long 0x00 14. " SPIS590 ,SPI Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " SPIS589 ,SPI Status Bit 589" "Low,High" bitfld.long 0x00 12. " SPIS588 ,SPI Status Bit 588" "Low,High" bitfld.long 0x00 11. " SPIS587 ,SPI Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " SPIS586 ,SPI Status Bit 586" "Low,High" bitfld.long 0x00 9. " SPIS585 ,SPI Status Bit 585" "Low,High" bitfld.long 0x00 8. " SPIS584 ,SPI Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " SPIS583 ,SPI Status Bit 583" "Low,High" bitfld.long 0x00 6. " SPIS582 ,SPI Status Bit 582" "Low,High" bitfld.long 0x00 5. " SPIS581 ,SPI Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " SPIS580 ,SPI Status Bit 580" "Low,High" bitfld.long 0x00 3. " SPIS579 ,SPI Status Bit 579" "Low,High" bitfld.long 0x00 2. " SPIS578 ,SPI Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " SPIS577 ,SPI Status Bit 577" "Low,High" bitfld.long 0x00 0. " SPIS576 ,SPI Status Bit 576" "Low,High" else hgroup.long 0xC0C8++0x03 hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) rgroup.long 0xC0CC++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " SPIS639 ,SPI Status Bit 639" "Low,High" bitfld.long 0x00 30. " SPIS638 ,SPI Status Bit 638" "Low,High" bitfld.long 0x00 29. " SPIS637 ,SPI Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " SPIS636 ,SPI Status Bit 636" "Low,High" bitfld.long 0x00 27. " SPIS635 ,SPI Status Bit 635" "Low,High" bitfld.long 0x00 26. " SPIS634 ,SPI Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " SPIS633 ,SPI Status Bit 633" "Low,High" bitfld.long 0x00 24. " SPIS632 ,SPI Status Bit 632" "Low,High" bitfld.long 0x00 23. " SPIS631 ,SPI Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " SPIS630 ,SPI Status Bit 630" "Low,High" bitfld.long 0x00 21. " SPIS629 ,SPI Status Bit 629" "Low,High" bitfld.long 0x00 20. " SPIS628 ,SPI Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " SPIS627 ,SPI Status Bit 627" "Low,High" bitfld.long 0x00 18. " SPIS626 ,SPI Status Bit 626" "Low,High" bitfld.long 0x00 17. " SPIS625 ,SPI Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " SPIS624 ,SPI Status Bit 624" "Low,High" bitfld.long 0x00 15. " SPIS623 ,SPI Status Bit 623" "Low,High" bitfld.long 0x00 14. " SPIS622 ,SPI Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " SPIS621 ,SPI Status Bit 621" "Low,High" bitfld.long 0x00 12. " SPIS620 ,SPI Status Bit 620" "Low,High" bitfld.long 0x00 11. " SPIS619 ,SPI Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " SPIS618 ,SPI Status Bit 618" "Low,High" bitfld.long 0x00 9. " SPIS617 ,SPI Status Bit 617" "Low,High" bitfld.long 0x00 8. " SPIS616 ,SPI Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " SPIS615 ,SPI Status Bit 615" "Low,High" bitfld.long 0x00 6. " SPIS614 ,SPI Status Bit 614" "Low,High" bitfld.long 0x00 5. " SPIS613 ,SPI Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " SPIS612 ,SPI Status Bit 612" "Low,High" bitfld.long 0x00 3. " SPIS611 ,SPI Status Bit 611" "Low,High" bitfld.long 0x00 2. " SPIS610 ,SPI Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " SPIS609 ,SPI Status Bit 609" "Low,High" bitfld.long 0x00 0. " SPIS608 ,SPI Status Bit 608" "Low,High" else hgroup.long 0xC0CC++0x03 hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) rgroup.long 0xC0D0++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " SPIS671 ,SPI Status Bit 671" "Low,High" bitfld.long 0x00 30. " SPIS670 ,SPI Status Bit 670" "Low,High" bitfld.long 0x00 29. " SPIS669 ,SPI Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " SPIS668 ,SPI Status Bit 668" "Low,High" bitfld.long 0x00 27. " SPIS667 ,SPI Status Bit 667" "Low,High" bitfld.long 0x00 26. " SPIS666 ,SPI Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " SPIS665 ,SPI Status Bit 665" "Low,High" bitfld.long 0x00 24. " SPIS664 ,SPI Status Bit 664" "Low,High" bitfld.long 0x00 23. " SPIS663 ,SPI Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " SPIS662 ,SPI Status Bit 662" "Low,High" bitfld.long 0x00 21. " SPIS661 ,SPI Status Bit 661" "Low,High" bitfld.long 0x00 20. " SPIS660 ,SPI Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " SPIS659 ,SPI Status Bit 659" "Low,High" bitfld.long 0x00 18. " SPIS658 ,SPI Status Bit 658" "Low,High" bitfld.long 0x00 17. " SPIS657 ,SPI Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " SPIS656 ,SPI Status Bit 656" "Low,High" bitfld.long 0x00 15. " SPIS655 ,SPI Status Bit 655" "Low,High" bitfld.long 0x00 14. " SPIS654 ,SPI Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " SPIS653 ,SPI Status Bit 653" "Low,High" bitfld.long 0x00 12. " SPIS652 ,SPI Status Bit 652" "Low,High" bitfld.long 0x00 11. " SPIS651 ,SPI Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " SPIS650 ,SPI Status Bit 650" "Low,High" bitfld.long 0x00 9. " SPIS649 ,SPI Status Bit 649" "Low,High" bitfld.long 0x00 8. " SPIS648 ,SPI Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " SPIS647 ,SPI Status Bit 647" "Low,High" bitfld.long 0x00 6. " SPIS646 ,SPI Status Bit 646" "Low,High" bitfld.long 0x00 5. " SPIS645 ,SPI Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " SPIS644 ,SPI Status Bit 644" "Low,High" bitfld.long 0x00 3. " SPIS643 ,SPI Status Bit 643" "Low,High" bitfld.long 0x00 2. " SPIS642 ,SPI Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " SPIS641 ,SPI Status Bit 641" "Low,High" bitfld.long 0x00 0. " SPIS640 ,SPI Status Bit 640" "Low,High" else hgroup.long 0xC0D0++0x03 hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) rgroup.long 0xC0D4++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " SPIS703 ,SPI Status Bit 703" "Low,High" bitfld.long 0x00 30. " SPIS702 ,SPI Status Bit 702" "Low,High" bitfld.long 0x00 29. " SPIS701 ,SPI Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " SPIS700 ,SPI Status Bit 700" "Low,High" bitfld.long 0x00 27. " SPIS699 ,SPI Status Bit 699" "Low,High" bitfld.long 0x00 26. " SPIS698 ,SPI Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " SPIS697 ,SPI Status Bit 697" "Low,High" bitfld.long 0x00 24. " SPIS696 ,SPI Status Bit 696" "Low,High" bitfld.long 0x00 23. " SPIS695 ,SPI Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " SPIS694 ,SPI Status Bit 694" "Low,High" bitfld.long 0x00 21. " SPIS693 ,SPI Status Bit 693" "Low,High" bitfld.long 0x00 20. " SPIS692 ,SPI Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " SPIS691 ,SPI Status Bit 691" "Low,High" bitfld.long 0x00 18. " SPIS690 ,SPI Status Bit 690" "Low,High" bitfld.long 0x00 17. " SPIS689 ,SPI Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " SPIS688 ,SPI Status Bit 688" "Low,High" bitfld.long 0x00 15. " SPIS687 ,SPI Status Bit 687" "Low,High" bitfld.long 0x00 14. " SPIS686 ,SPI Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " SPIS685 ,SPI Status Bit 685" "Low,High" bitfld.long 0x00 12. " SPIS684 ,SPI Status Bit 684" "Low,High" bitfld.long 0x00 11. " SPIS683 ,SPI Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " SPIS682 ,SPI Status Bit 682" "Low,High" bitfld.long 0x00 9. " SPIS681 ,SPI Status Bit 681" "Low,High" bitfld.long 0x00 8. " SPIS680 ,SPI Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " SPIS679 ,SPI Status Bit 679" "Low,High" bitfld.long 0x00 6. " SPIS678 ,SPI Status Bit 678" "Low,High" bitfld.long 0x00 5. " SPIS677 ,SPI Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " SPIS676 ,SPI Status Bit 676" "Low,High" bitfld.long 0x00 3. " SPIS675 ,SPI Status Bit 675" "Low,High" bitfld.long 0x00 2. " SPIS674 ,SPI Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " SPIS673 ,SPI Status Bit 673" "Low,High" bitfld.long 0x00 0. " SPIS672 ,SPI Status Bit 672" "Low,High" else hgroup.long 0xC0D4++0x03 hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) rgroup.long 0xC0D8++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " SPIS735 ,SPI Status Bit 735" "Low,High" bitfld.long 0x00 30. " SPIS734 ,SPI Status Bit 734" "Low,High" bitfld.long 0x00 29. " SPIS733 ,SPI Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " SPIS732 ,SPI Status Bit 732" "Low,High" bitfld.long 0x00 27. " SPIS731 ,SPI Status Bit 731" "Low,High" bitfld.long 0x00 26. " SPIS730 ,SPI Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " SPIS729 ,SPI Status Bit 729" "Low,High" bitfld.long 0x00 24. " SPIS728 ,SPI Status Bit 728" "Low,High" bitfld.long 0x00 23. " SPIS727 ,SPI Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " SPIS726 ,SPI Status Bit 726" "Low,High" bitfld.long 0x00 21. " SPIS725 ,SPI Status Bit 725" "Low,High" bitfld.long 0x00 20. " SPIS724 ,SPI Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " SPIS723 ,SPI Status Bit 723" "Low,High" bitfld.long 0x00 18. " SPIS722 ,SPI Status Bit 722" "Low,High" bitfld.long 0x00 17. " SPIS721 ,SPI Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " SPIS720 ,SPI Status Bit 720" "Low,High" bitfld.long 0x00 15. " SPIS719 ,SPI Status Bit 719" "Low,High" bitfld.long 0x00 14. " SPIS718 ,SPI Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " SPIS717 ,SPI Status Bit 717" "Low,High" bitfld.long 0x00 12. " SPIS716 ,SPI Status Bit 716" "Low,High" bitfld.long 0x00 11. " SPIS715 ,SPI Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " SPIS714 ,SPI Status Bit 714" "Low,High" bitfld.long 0x00 9. " SPIS713 ,SPI Status Bit 713" "Low,High" bitfld.long 0x00 8. " SPIS712 ,SPI Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " SPIS711 ,SPI Status Bit 711" "Low,High" bitfld.long 0x00 6. " SPIS710 ,SPI Status Bit 710" "Low,High" bitfld.long 0x00 5. " SPIS709 ,SPI Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " SPIS708 ,SPI Status Bit 708" "Low,High" bitfld.long 0x00 3. " SPIS707 ,SPI Status Bit 707" "Low,High" bitfld.long 0x00 2. " SPIS706 ,SPI Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " SPIS705 ,SPI Status Bit 705" "Low,High" bitfld.long 0x00 0. " SPIS704 ,SPI Status Bit 704" "Low,High" else hgroup.long 0xC0D8++0x03 hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) rgroup.long 0xC0DC++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " SPIS767 ,SPI Status Bit 767" "Low,High" bitfld.long 0x00 30. " SPIS766 ,SPI Status Bit 766" "Low,High" bitfld.long 0x00 29. " SPIS765 ,SPI Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " SPIS764 ,SPI Status Bit 764" "Low,High" bitfld.long 0x00 27. " SPIS763 ,SPI Status Bit 763" "Low,High" bitfld.long 0x00 26. " SPIS762 ,SPI Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " SPIS761 ,SPI Status Bit 761" "Low,High" bitfld.long 0x00 24. " SPIS760 ,SPI Status Bit 760" "Low,High" bitfld.long 0x00 23. " SPIS759 ,SPI Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " SPIS758 ,SPI Status Bit 758" "Low,High" bitfld.long 0x00 21. " SPIS757 ,SPI Status Bit 757" "Low,High" bitfld.long 0x00 20. " SPIS756 ,SPI Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " SPIS755 ,SPI Status Bit 755" "Low,High" bitfld.long 0x00 18. " SPIS754 ,SPI Status Bit 754" "Low,High" bitfld.long 0x00 17. " SPIS753 ,SPI Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " SPIS752 ,SPI Status Bit 752" "Low,High" bitfld.long 0x00 15. " SPIS751 ,SPI Status Bit 751" "Low,High" bitfld.long 0x00 14. " SPIS750 ,SPI Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " SPIS749 ,SPI Status Bit 749" "Low,High" bitfld.long 0x00 12. " SPIS748 ,SPI Status Bit 748" "Low,High" bitfld.long 0x00 11. " SPIS747 ,SPI Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " SPIS746 ,SPI Status Bit 746" "Low,High" bitfld.long 0x00 9. " SPIS745 ,SPI Status Bit 745" "Low,High" bitfld.long 0x00 8. " SPIS744 ,SPI Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " SPIS743 ,SPI Status Bit 743" "Low,High" bitfld.long 0x00 6. " SPIS742 ,SPI Status Bit 742" "Low,High" bitfld.long 0x00 5. " SPIS741 ,SPI Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " SPIS740 ,SPI Status Bit 740" "Low,High" bitfld.long 0x00 3. " SPIS739 ,SPI Status Bit 739" "Low,High" bitfld.long 0x00 2. " SPIS738 ,SPI Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " SPIS737 ,SPI Status Bit 737" "Low,High" bitfld.long 0x00 0. " SPIS736 ,SPI Status Bit 736" "Low,High" else hgroup.long 0xC0DC++0x03 hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) rgroup.long 0xC0E0++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " SPIS799 ,SPI Status Bit 799" "Low,High" bitfld.long 0x00 30. " SPIS798 ,SPI Status Bit 798" "Low,High" bitfld.long 0x00 29. " SPIS797 ,SPI Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " SPIS796 ,SPI Status Bit 796" "Low,High" bitfld.long 0x00 27. " SPIS795 ,SPI Status Bit 795" "Low,High" bitfld.long 0x00 26. " SPIS794 ,SPI Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " SPIS793 ,SPI Status Bit 793" "Low,High" bitfld.long 0x00 24. " SPIS792 ,SPI Status Bit 792" "Low,High" bitfld.long 0x00 23. " SPIS791 ,SPI Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " SPIS790 ,SPI Status Bit 790" "Low,High" bitfld.long 0x00 21. " SPIS789 ,SPI Status Bit 789" "Low,High" bitfld.long 0x00 20. " SPIS788 ,SPI Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " SPIS787 ,SPI Status Bit 787" "Low,High" bitfld.long 0x00 18. " SPIS786 ,SPI Status Bit 786" "Low,High" bitfld.long 0x00 17. " SPIS785 ,SPI Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " SPIS784 ,SPI Status Bit 784" "Low,High" bitfld.long 0x00 15. " SPIS783 ,SPI Status Bit 783" "Low,High" bitfld.long 0x00 14. " SPIS782 ,SPI Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " SPIS781 ,SPI Status Bit 781" "Low,High" bitfld.long 0x00 12. " SPIS780 ,SPI Status Bit 780" "Low,High" bitfld.long 0x00 11. " SPIS779 ,SPI Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " SPIS778 ,SPI Status Bit 778" "Low,High" bitfld.long 0x00 9. " SPIS777 ,SPI Status Bit 777" "Low,High" bitfld.long 0x00 8. " SPIS776 ,SPI Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " SPIS775 ,SPI Status Bit 775" "Low,High" bitfld.long 0x00 6. " SPIS774 ,SPI Status Bit 774" "Low,High" bitfld.long 0x00 5. " SPIS773 ,SPI Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " SPIS772 ,SPI Status Bit 772" "Low,High" bitfld.long 0x00 3. " SPIS771 ,SPI Status Bit 771" "Low,High" bitfld.long 0x00 2. " SPIS770 ,SPI Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " SPIS769 ,SPI Status Bit 769" "Low,High" bitfld.long 0x00 0. " SPIS768 ,SPI Status Bit 768" "Low,High" else hgroup.long 0xC0E0++0x03 hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) rgroup.long 0xC0E4++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " SPIS831 ,SPI Status Bit 831" "Low,High" bitfld.long 0x00 30. " SPIS830 ,SPI Status Bit 830" "Low,High" bitfld.long 0x00 29. " SPIS829 ,SPI Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " SPIS828 ,SPI Status Bit 828" "Low,High" bitfld.long 0x00 27. " SPIS827 ,SPI Status Bit 827" "Low,High" bitfld.long 0x00 26. " SPIS826 ,SPI Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " SPIS825 ,SPI Status Bit 825" "Low,High" bitfld.long 0x00 24. " SPIS824 ,SPI Status Bit 824" "Low,High" bitfld.long 0x00 23. " SPIS823 ,SPI Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " SPIS822 ,SPI Status Bit 822" "Low,High" bitfld.long 0x00 21. " SPIS821 ,SPI Status Bit 821" "Low,High" bitfld.long 0x00 20. " SPIS820 ,SPI Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " SPIS819 ,SPI Status Bit 819" "Low,High" bitfld.long 0x00 18. " SPIS818 ,SPI Status Bit 818" "Low,High" bitfld.long 0x00 17. " SPIS817 ,SPI Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " SPIS816 ,SPI Status Bit 816" "Low,High" bitfld.long 0x00 15. " SPIS815 ,SPI Status Bit 815" "Low,High" bitfld.long 0x00 14. " SPIS814 ,SPI Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " SPIS813 ,SPI Status Bit 813" "Low,High" bitfld.long 0x00 12. " SPIS812 ,SPI Status Bit 812" "Low,High" bitfld.long 0x00 11. " SPIS811 ,SPI Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " SPIS810 ,SPI Status Bit 810" "Low,High" bitfld.long 0x00 9. " SPIS809 ,SPI Status Bit 809" "Low,High" bitfld.long 0x00 8. " SPIS808 ,SPI Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " SPIS807 ,SPI Status Bit 807" "Low,High" bitfld.long 0x00 6. " SPIS806 ,SPI Status Bit 806" "Low,High" bitfld.long 0x00 5. " SPIS805 ,SPI Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " SPIS804 ,SPI Status Bit 804" "Low,High" bitfld.long 0x00 3. " SPIS803 ,SPI Status Bit 803" "Low,High" bitfld.long 0x00 2. " SPIS802 ,SPI Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " SPIS801 ,SPI Status Bit 801" "Low,High" bitfld.long 0x00 0. " SPIS800 ,SPI Status Bit 800" "Low,High" else hgroup.long 0xC0E4++0x03 hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) rgroup.long 0xC0E8++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " SPIS863 ,SPI Status Bit 863" "Low,High" bitfld.long 0x00 30. " SPIS862 ,SPI Status Bit 862" "Low,High" bitfld.long 0x00 29. " SPIS861 ,SPI Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " SPIS860 ,SPI Status Bit 860" "Low,High" bitfld.long 0x00 27. " SPIS859 ,SPI Status Bit 859" "Low,High" bitfld.long 0x00 26. " SPIS858 ,SPI Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " SPIS857 ,SPI Status Bit 857" "Low,High" bitfld.long 0x00 24. " SPIS856 ,SPI Status Bit 856" "Low,High" bitfld.long 0x00 23. " SPIS855 ,SPI Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " SPIS854 ,SPI Status Bit 854" "Low,High" bitfld.long 0x00 21. " SPIS853 ,SPI Status Bit 853" "Low,High" bitfld.long 0x00 20. " SPIS852 ,SPI Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " SPIS851 ,SPI Status Bit 851" "Low,High" bitfld.long 0x00 18. " SPIS850 ,SPI Status Bit 850" "Low,High" bitfld.long 0x00 17. " SPIS849 ,SPI Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " SPIS848 ,SPI Status Bit 848" "Low,High" bitfld.long 0x00 15. " SPIS847 ,SPI Status Bit 847" "Low,High" bitfld.long 0x00 14. " SPIS846 ,SPI Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " SPIS845 ,SPI Status Bit 845" "Low,High" bitfld.long 0x00 12. " SPIS844 ,SPI Status Bit 844" "Low,High" bitfld.long 0x00 11. " SPIS843 ,SPI Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " SPIS842 ,SPI Status Bit 842" "Low,High" bitfld.long 0x00 9. " SPIS841 ,SPI Status Bit 841" "Low,High" bitfld.long 0x00 8. " SPIS840 ,SPI Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " SPIS839 ,SPI Status Bit 839" "Low,High" bitfld.long 0x00 6. " SPIS838 ,SPI Status Bit 838" "Low,High" bitfld.long 0x00 5. " SPIS837 ,SPI Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " SPIS836 ,SPI Status Bit 836" "Low,High" bitfld.long 0x00 3. " SPIS835 ,SPI Status Bit 835" "Low,High" bitfld.long 0x00 2. " SPIS834 ,SPI Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " SPIS833 ,SPI Status Bit 833" "Low,High" bitfld.long 0x00 0. " SPIS832 ,SPI Status Bit 832" "Low,High" else hgroup.long 0xC0E8++0x03 hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) rgroup.long 0xC0EC++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " SPIS895 ,SPI Status Bit 895" "Low,High" bitfld.long 0x00 30. " SPIS894 ,SPI Status Bit 894" "Low,High" bitfld.long 0x00 29. " SPIS893 ,SPI Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " SPIS892 ,SPI Status Bit 892" "Low,High" bitfld.long 0x00 27. " SPIS891 ,SPI Status Bit 891" "Low,High" bitfld.long 0x00 26. " SPIS890 ,SPI Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " SPIS889 ,SPI Status Bit 889" "Low,High" bitfld.long 0x00 24. " SPIS888 ,SPI Status Bit 888" "Low,High" bitfld.long 0x00 23. " SPIS887 ,SPI Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " SPIS886 ,SPI Status Bit 886" "Low,High" bitfld.long 0x00 21. " SPIS885 ,SPI Status Bit 885" "Low,High" bitfld.long 0x00 20. " SPIS884 ,SPI Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " SPIS883 ,SPI Status Bit 883" "Low,High" bitfld.long 0x00 18. " SPIS882 ,SPI Status Bit 882" "Low,High" bitfld.long 0x00 17. " SPIS881 ,SPI Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " SPIS880 ,SPI Status Bit 880" "Low,High" bitfld.long 0x00 15. " SPIS879 ,SPI Status Bit 879" "Low,High" bitfld.long 0x00 14. " SPIS878 ,SPI Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " SPIS877 ,SPI Status Bit 877" "Low,High" bitfld.long 0x00 12. " SPIS876 ,SPI Status Bit 876" "Low,High" bitfld.long 0x00 11. " SPIS875 ,SPI Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " SPIS874 ,SPI Status Bit 874" "Low,High" bitfld.long 0x00 9. " SPIS873 ,SPI Status Bit 873" "Low,High" bitfld.long 0x00 8. " SPIS872 ,SPI Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " SPIS871 ,SPI Status Bit 871" "Low,High" bitfld.long 0x00 6. " SPIS870 ,SPI Status Bit 870" "Low,High" bitfld.long 0x00 5. " SPIS869 ,SPI Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " SPIS868 ,SPI Status Bit 868" "Low,High" bitfld.long 0x00 3. " SPIS867 ,SPI Status Bit 867" "Low,High" bitfld.long 0x00 2. " SPIS866 ,SPI Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " SPIS865 ,SPI Status Bit 865" "Low,High" bitfld.long 0x00 0. " SPIS864 ,SPI Status Bit 864" "Low,High" else hgroup.long 0xC0EC++0x03 hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) rgroup.long 0xC0F0++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " SPIS927 ,SPI Status Bit 927" "Low,High" bitfld.long 0x00 30. " SPIS926 ,SPI Status Bit 926" "Low,High" bitfld.long 0x00 29. " SPIS925 ,SPI Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " SPIS924 ,SPI Status Bit 924" "Low,High" bitfld.long 0x00 27. " SPIS923 ,SPI Status Bit 923" "Low,High" bitfld.long 0x00 26. " SPIS922 ,SPI Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " SPIS921 ,SPI Status Bit 921" "Low,High" bitfld.long 0x00 24. " SPIS920 ,SPI Status Bit 920" "Low,High" bitfld.long 0x00 23. " SPIS919 ,SPI Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " SPIS918 ,SPI Status Bit 918" "Low,High" bitfld.long 0x00 21. " SPIS917 ,SPI Status Bit 917" "Low,High" bitfld.long 0x00 20. " SPIS916 ,SPI Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " SPIS915 ,SPI Status Bit 915" "Low,High" bitfld.long 0x00 18. " SPIS914 ,SPI Status Bit 914" "Low,High" bitfld.long 0x00 17. " SPIS913 ,SPI Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " SPIS912 ,SPI Status Bit 912" "Low,High" bitfld.long 0x00 15. " SPIS911 ,SPI Status Bit 911" "Low,High" bitfld.long 0x00 14. " SPIS910 ,SPI Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " SPIS909 ,SPI Status Bit 909" "Low,High" bitfld.long 0x00 12. " SPIS908 ,SPI Status Bit 908" "Low,High" bitfld.long 0x00 11. " SPIS907 ,SPI Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " SPIS906 ,SPI Status Bit 906" "Low,High" bitfld.long 0x00 9. " SPIS905 ,SPI Status Bit 905" "Low,High" bitfld.long 0x00 8. " SPIS904 ,SPI Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " SPIS903 ,SPI Status Bit 903" "Low,High" bitfld.long 0x00 6. " SPIS902 ,SPI Status Bit 902" "Low,High" bitfld.long 0x00 5. " SPIS901 ,SPI Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " SPIS900 ,SPI Status Bit 900" "Low,High" bitfld.long 0x00 3. " SPIS899 ,SPI Status Bit 899" "Low,High" bitfld.long 0x00 2. " SPIS898 ,SPI Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " SPIS897 ,SPI Status Bit 897" "Low,High" bitfld.long 0x00 0. " SPIS896 ,SPI Status Bit 896" "Low,High" else hgroup.long 0xC0F0++0x03 hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) rgroup.long 0xC0F4++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " SPIS959 ,SPI Status Bit 959" "Low,High" bitfld.long 0x00 30. " SPIS958 ,SPI Status Bit 958" "Low,High" bitfld.long 0x00 29. " SPIS957 ,SPI Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " SPIS956 ,SPI Status Bit 956" "Low,High" bitfld.long 0x00 27. " SPIS955 ,SPI Status Bit 955" "Low,High" bitfld.long 0x00 26. " SPIS954 ,SPI Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " SPIS953 ,SPI Status Bit 953" "Low,High" bitfld.long 0x00 24. " SPIS952 ,SPI Status Bit 952" "Low,High" bitfld.long 0x00 23. " SPIS951 ,SPI Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " SPIS950 ,SPI Status Bit 950" "Low,High" bitfld.long 0x00 21. " SPIS949 ,SPI Status Bit 949" "Low,High" bitfld.long 0x00 20. " SPIS948 ,SPI Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " SPIS947 ,SPI Status Bit 947" "Low,High" bitfld.long 0x00 18. " SPIS946 ,SPI Status Bit 946" "Low,High" bitfld.long 0x00 17. " SPIS945 ,SPI Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " SPIS944 ,SPI Status Bit 944" "Low,High" bitfld.long 0x00 15. " SPIS943 ,SPI Status Bit 943" "Low,High" bitfld.long 0x00 14. " SPIS942 ,SPI Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " SPIS941 ,SPI Status Bit 941" "Low,High" bitfld.long 0x00 12. " SPIS940 ,SPI Status Bit 940" "Low,High" bitfld.long 0x00 11. " SPIS939 ,SPI Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " SPIS938 ,SPI Status Bit 938" "Low,High" bitfld.long 0x00 9. " SPIS937 ,SPI Status Bit 937" "Low,High" bitfld.long 0x00 8. " SPIS936 ,SPI Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " SPIS935 ,SPI Status Bit 935" "Low,High" bitfld.long 0x00 6. " SPIS934 ,SPI Status Bit 934" "Low,High" bitfld.long 0x00 5. " SPIS933 ,SPI Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " SPIS932 ,SPI Status Bit 932" "Low,High" bitfld.long 0x00 3. " SPIS931 ,SPI Status Bit 931" "Low,High" bitfld.long 0x00 2. " SPIS930 ,SPI Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " SPIS929 ,SPI Status Bit 929" "Low,High" bitfld.long 0x00 0. " SPIS928 ,SPI Status Bit 928" "Low,High" else hgroup.long 0xC0F4++0x03 hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) rgroup.long 0xC0F8++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " SPIS991 ,SPI Status Bit 991" "Low,High" bitfld.long 0x00 30. " SPIS990 ,SPI Status Bit 990" "Low,High" bitfld.long 0x00 29. " SPIS989 ,SPI Status Bit 989" "Low,High" textline " " bitfld.long 0x00 28. " SPIS988 ,SPI Status Bit 988" "Low,High" bitfld.long 0x00 27. " SPIS987 ,SPI Status Bit 987" "Low,High" bitfld.long 0x00 26. " SPIS986 ,SPI Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " SPIS985 ,SPI Status Bit 985" "Low,High" bitfld.long 0x00 24. " SPIS984 ,SPI Status Bit 984" "Low,High" bitfld.long 0x00 23. " SPIS983 ,SPI Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " SPIS982 ,SPI Status Bit 982" "Low,High" bitfld.long 0x00 21. " SPIS981 ,SPI Status Bit 981" "Low,High" bitfld.long 0x00 20. " SPIS980 ,SPI Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " SPIS979 ,SPI Status Bit 979" "Low,High" bitfld.long 0x00 18. " SPIS978 ,SPI Status Bit 978" "Low,High" bitfld.long 0x00 17. " SPIS977 ,SPI Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " SPIS976 ,SPI Status Bit 976" "Low,High" bitfld.long 0x00 15. " SPIS975 ,SPI Status Bit 975" "Low,High" bitfld.long 0x00 14. " SPIS974 ,SPI Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " SPIS973 ,SPI Status Bit 973" "Low,High" bitfld.long 0x00 12. " SPIS972 ,SPI Status Bit 972" "Low,High" bitfld.long 0x00 11. " SPIS971 ,SPI Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " SPIS970 ,SPI Status Bit 970" "Low,High" bitfld.long 0x00 9. " SPIS969 ,SPI Status Bit 969" "Low,High" bitfld.long 0x00 8. " SPIS968 ,SPI Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " SPIS967 ,SPI Status Bit 967" "Low,High" bitfld.long 0x00 6. " SPIS966 ,SPI Status Bit 966" "Low,High" bitfld.long 0x00 5. " SPIS965 ,SPI Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " SPIS964 ,SPI Status Bit 964" "Low,High" bitfld.long 0x00 3. " SPIS963 ,SPI Status Bit 963" "Low,High" bitfld.long 0x00 2. " SPIS962 ,SPI Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " SPIS961 ,SPI Status Bit 961" "Low,High" bitfld.long 0x00 0. " SPIS960 ,SPI Status Bit 960" "Low,High" else hgroup.long 0xC0F8++0x03 hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" endif tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Not Used,Used" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end width 0x0B base (COMP.BASE("GICD",-1.)+0x20000) width 24. tree "Interrupt Translation Service" group.long 0x00++0x03 line.long 0x00 "GITS_CTLR,ITS Control Register" rbitfld.long 0x00 31. " QUIESCENT ,Indicates completion of all ITS operations" "Not quiescent,Quiescent" bitfld.long 0x00 0. " ENABLED ,Controls whether the ITS is enabled" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GITS_IIDR,ITS Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)&&(((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" textline " " bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" textline " " bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" textline " " bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" textline " " bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" textline " " bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" else rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" textline " " bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.quad 0x80++0x07 line.quad 0x00 "GITS_CBASER,The command queue control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the command queue" "Not allocated,Allocated" bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the command queue" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the command queue" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the base physical address of the command queue" textline " " bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the command queue" "Non-shareable,Inner Shareable,Outer Shareable,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of 4KB pages of physical memory allocated to the command queue minus one" group.quad 0x88++0x7 line.quad 0x00 "GITS_CWRITER,The command queue write pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " RETRY ,Restarts the processing of commands by the ITS if it stalled because of a command error" "No effect,Restarted" group.quad 0x90++0x07 line.quad 0x00 "GITS_CREADR,The command queue read pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " STALLED ,Reports whether the processing of commands is stalled because of a command error" "Not stalled,Stalled" if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0100))&0x700000000000000)==0x00) group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" textline " " bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.quad 0x00 12.--47. 1. " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." else group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" textline " " bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.quad 0x00 12.--47. 0x10 " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of pages of physical memory allocated to the table minus one" endif textline " " wgroup.long 0xC000++0x03 line.long 0x00 "GITS_TRKCTLR,Tracking Control Register" bitfld.long 0x00 1. " LPI_TRACK ,Write 0b1 to capture information about the next interrupt that the ITS generated or failed to generate because of misprogramming" "No effect,Capture" bitfld.long 0x00 0. " CACHE_COUNT_RESET ,Write 0b1 to reset the cache hit and miss counters in GITS_TRKICR and GITS_TRKLCR" "No effect,Reset" if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x1F)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 6. " PID_OUT_OF_RANGE ,Indicates that the LPI PID is larger than that allowed by the IDbits field in the GICR_PROPBASER" "0,1" bitfld.long 0x00 5. " TARGET_OUT_OF_RANGE ,Indicates that target collection has not been successfully mapped using MAPC or that the target core does not have LPIs enabled in GICR_CTLR" "0,1" textline " " bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" textline " " bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0xF)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" textline " " bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" textline " " bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x3)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" else rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01) rgroup.long 0xC008++0x03 line.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register" hexmask.long.tbyte 0x00 0.--19. 1. " LPI_DID ,The Device ID for the interrupt that was tracked" else hgroup.long 0xC008++0x03 hide.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01) rgroup.long 0xC00C++0x03 line.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register" hexmask.long.word 0x00 0.--15. 1. " LPI_PID ,The ID after translation for an interrupt that was tracked and generated an LPI successfully" else hgroup.long 0xC00C++0x03 hide.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01) rgroup.long 0xC010++0x03 line.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register" hexmask.long.word 0x00 0.--15. 1. " LPI_ID ,The ID before translation of the interrupt that was tracked" else hgroup.long 0xC010++0x03 hide.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01) rgroup.long 0xC014++0x03 line.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register" hexmask.long.byte 0x00 0.--6. 1. " LPI_TARGET_CORE ,The target core for an interrupt that was tracked and generated an LPI successfully" else hgroup.long 0xC014++0x03 hide.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register" endif rgroup.long 0xC018++0x03 line.long 0x00 "GITS_TRKICR,Debug ITE Cache Statistics" hexmask.long.word 0x00 16.--31. 1. " ITE_CACHE_HITS ,Number of hits in the ITE cache" hexmask.long.word 0x00 0.--15. 1. " ITE_CACHE_MISSES ,Number of misses in the ITE cache" rgroup.long 0xC01C++0x03 line.long 0x00 "GITS_TRKLCR,Debug LPI Cache Statistics" hexmask.long.word 0x00 16.--31. 1. " LPI_CACHE_HITS ,Number of hits in the LPI cache" hexmask.long.word 0x00 0.--15. 1. " LPI_CACHE_MISSES ,Number of misses in the LPI cache" rgroup.long 0xFFE0++0x03 line.long 0x00 "GITS_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GITS_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GITS_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" textline " " bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GITS_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GITS_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GITS_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GITS_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GITS_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GITS_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GITS_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GITS_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GITS_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " base (COMP.BASE("GICD",-1.)+0x20000)+0x10000 if (((per.l((COMP.BASE("GICD",-1.)+0x20000)))&0x01)==0x01) wgroup.long 0x40++0x03 line.long 0x00 "GITS_TRANSLATER,ITS Translation Register" else hgroup.long 0x40++0x03 hide.long 0x00 "GITS_TRANSLATER,ITS Translation Register" endif tree.end width 0x0B base COMP.BASE("GICR",-1.) width 17. tree "Redistributor Interface" tree "Control Registers" if (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x21) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" textline " " bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x20) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" textline " " bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x01) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" rgroup.quad 0x0008++0x07 line.quad 0x00 "GICR_TYPER,Interrupt Controller Type Register" hexmask.quad.byte 0x00 56.--63. 1. " AFF3 ,Affinity level 3 value for the Redistributor" hexmask.quad.byte 0x00 48.--55. 1. " AFF2 ,Affinity level 2 value for the Redistributor" hexmask.quad.byte 0x00 40.--47. 1. " AFF1 ,Affinity level 1 value for the Redistributor" textline " " hexmask.quad.byte 0x00 32.--39. 1. " AFF0 ,Affinity level 0 value for the Redistributor" bitfld.quad 0x00 24.--25. " COMMONLPIAFF ,The affinity level at which Redistributors share a LPI Configuration table" "All levels,AFF3,AFF3/AFF2,AFF3/AFF2/AFF1" hexmask.quad.word 0x00 8.--23. 1. " PROCESSOR_NUMBER ,A unique identifier for the PE" textline " " bitfld.quad 0x00 5. " DPGS ,Sets support for GICR_CTLR.DPG* bits" "Not supported,Supported" bitfld.quad 0x00 4. " LAST ,Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages" "Not highest,Highest" bitfld.quad 0x00 3. " DIRECTLPI ,Indicates whether this Redistributor supports direct injection of LPIs" "Not supported,Supported" textline " " bitfld.quad 0x00 0. " PLPIS ,Indicates whether the GIC implementation supports physical LPIs" "Not supported,Supported" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x0014)))) group.long 0x0014++0x03 line.long 0x00 "GICR_WAKER,Power Management Control Register" bitfld.long 0x00 31. " QUIESCENT ,This bit shows that the GIC-500 is idle and can be powered down if required" "Not quiescent,Quiescent" bitfld.long 0x00 2. " CHILDRENASLEEP ,Indicates the bus between the CPU interface and this Redistributor is quiescent" "Not quiescent,Quiescent" bitfld.long 0x00 1. " PROCESSORASLEEP ,Indicates if this Redistributor must assert a WakeRequest if there is a pending interrupt targeted at the connected core" "No,Yes" textline " " bitfld.long 0x00 0. " SLEEP ,Indicates if GIC-500 ensures that all the caches are consistent with external memory and that it is safe to power off" "No,Yes" textline " " else hgroup.long 0x0014++0x03 hide.long 0x00 "GICR_WAKER,Power Management Control Register" endif group.quad 0x070++0x07 line.quad 0x00 "GICR_PROPBASER,Common LPI configuration table base register" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the physical address containing the LPI Configuration table" textline " " bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Configuration table" "Non-shareable,Inner Shareable,Outer Shareable,?..." bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " bitfld.quad 0x00 0.--4. " IDBITS ,The number of bits of LPI INTID supported minus one by the LPI Configuration table starting at Physical_Address" group.quad 0x78++0x07 line.quad 0x00 "GICR_PENDBASER,LPI pending table base register" bitfld.quad 0x00 62. " PTZ ,Pending Table Zero" "Not zero,Zero" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Pending table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" textline " " hexmask.quad 0x00 16.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:16] of the physical address containing the LPI Pending table" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Pending table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Pending table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " tree.end tree "SGI and PPI Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10080)) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x000) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x10080++0x03 hide.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif textline " " width 24. group.long 0x10100++0x03 line.long 0x0 "GICR_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" group.long 0x10200++0x03 line.long 0x0 "GICR_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" group.long 0x10300++0x03 line.long 0x0 "GICR_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" textline " " width 18. group.long 0x10400++0x03 line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x10404++0x03 line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x10408++0x03 line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x1040C++0x03 line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x10410++0x03 line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x10414++0x03 line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x10418++0x03 line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x1041C++0x03 line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " textline " " rgroup.long 0x10C00++0x03 line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" group.long 0x10C04++0x03 line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" textline " " width 18. if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10D00)) group.long 0x10D00++0x03 line.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" bitfld.long 0x00 31. " GMB31 ,Group Modifier Bit 31" "0,1" bitfld.long 0x00 30. " GMB30 ,Group Modifier Bit 30" "0,1" bitfld.long 0x00 29. " GMB29 ,Group Modifier Bit 29" "0,1" textline " " bitfld.long 0x00 28. " GMB28 ,Group Modifier Bit 28" "0,1" bitfld.long 0x00 27. " GMB27 ,Group Modifier Bit 27" "0,1" bitfld.long 0x00 26. " GMB26 ,Group Modifier Bit 26" "0,1" textline " " bitfld.long 0x00 25. " GMB25 ,Group Modifier Bit 25" "0,1" bitfld.long 0x00 24. " GMB24 ,Group Modifier Bit 24" "0,1" bitfld.long 0x00 23. " GMB23 ,Group Modifier Bit 23" "0,1" textline " " bitfld.long 0x00 22. " GMB22 ,Group Modifier Bit 22" "0,1" bitfld.long 0x00 21. " GMB21 ,Group Modifier Bit 21" "0,1" bitfld.long 0x00 20. " GMB20 ,Group Modifier Bit 20" "0,1" textline " " bitfld.long 0x00 19. " GMB19 ,Group Modifier Bit 19" "0,1" bitfld.long 0x00 18. " GMB18 ,Group Modifier Bit 18" "0,1" bitfld.long 0x00 17. " GMB17 ,Group Modifier Bit 17" "0,1" textline " " bitfld.long 0x00 16. " GMB16 ,Group Modifier Bit 16" "0,1" bitfld.long 0x00 15. " GMB15 ,Group Modifier Bit 15" "0,1" bitfld.long 0x00 14. " GMB14 ,Group Modifier Bit 14" "0,1" textline " " bitfld.long 0x00 13. " GMB13 ,Group Modifier Bit 13" "0,1" bitfld.long 0x00 12. " GMB12 ,Group Modifier Bit 12" "0,1" bitfld.long 0x00 11. " GMB11 ,Group Modifier Bit 11" "0,1" textline " " bitfld.long 0x00 10. " GMB10 ,Group Modifier Bit 10" "0,1" bitfld.long 0x00 9. " GMB9 ,Group Modifier Bit 9" "0,1" bitfld.long 0x00 8. " GMB8 ,Group Modifier Bit 8" "0,1" textline " " bitfld.long 0x00 7. " GMB7 ,Group Modifier Bit 7" "0,1" bitfld.long 0x00 6. " GMB6 ,Group Modifier Bit 6" "0,1" bitfld.long 0x00 5. " GMB5 ,Group Modifier Bit 5" "0,1" textline " " bitfld.long 0x00 4. " GMB4 ,Group Modifier Bit 4" "0,1" bitfld.long 0x00 3. " GMB3 ,Group Modifier Bit 3" "0,1" bitfld.long 0x00 2. " GMB2 ,Group Modifier Bit 2" "0,1" textline " " bitfld.long 0x00 1. " GMB1 ,Group Modifier Bit 1" "0,1" bitfld.long 0x00 0. " GMB0 ,Group Modifier Bit 0" "0,1" textline " " else hgroup.long 0x10D00++0x03 hide.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10E00)) group.long 0x10E00++0x03 line.long 0x00 "GICR_NSACR,Non-secure Access Control Register" bitfld.long 0x00 30.--31. " NS_ACCESS15 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID15" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 28.--29. " NS_ACCESS14 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID14" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 26.--27. " NS_ACCESS13 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID13" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 24.--25. " NS_ACCESS12 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID12" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 22.--23. " NS_ACCESS11 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID11" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 20.--21. " NS_ACCESS10 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID10" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 18.--19. " NS_ACCESS9 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID9" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 16.--17. " NS_ACCESS8 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID8" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 14.--15. " NS_ACCESS7 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID7" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 12.--13. " NS_ACCESS6 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID6" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 10.--11. " NS_ACCESS5 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID5" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 8.--9. " NS_ACCESS4 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID4" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 6.--7. " NS_ACCESS3 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID3" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 4.--5. " NS_ACCESS2 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID2" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 2.--3. " NS_ACCESS1 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID1" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 0.--1. " NS_ACCESS0 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID0" "No access,G0S,G0S/G1S,?..." textline " " else hgroup.long 0x10E00++0x03 hide.long 0x00 "GICR_NSACR,Non-secure Access Control Register" textline " " textline " " textline " " textline " " textline " " endif rgroup.long 0x1C000++0x03 line.long 0x00 "GICR_MISCSTATUSR,Miscellaneous Status Register" bitfld.long 0x00 31. " CPU_AS ,CPU active state. This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read" "Low,High" bitfld.long 0x00 2. " ENABLEGRP1_S ,EnableGrp1 Secure" "0,1" bitfld.long 0x00 1. " ENABLEGRP1_NS ,EnableGrp1 Non-secure" "0,1" textline " " bitfld.long 0x00 0. " ENABLEGRP0 ,EnableGrp0" "0,1" rgroup.long 0x1C080++0x03 line.long 0x00 "GICR_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 31. " PPI31S ,Actual status of the PPI31 input signal" "Low,High" bitfld.long 0x00 30. " PPI30S ,Actual status of the PPI30 input signal" "Low,High" bitfld.long 0x00 29. " PPI29S ,Actual status of the PPI29 input signal" "Low,High" textline " " bitfld.long 0x00 28. " PPI28S ,Actual status of the PPI28 input signal" "Low,High" bitfld.long 0x00 27. " PPI27S ,Actual status of the PPI27 input signal" "Low,High" bitfld.long 0x00 26. " PPI26S ,Actual status of the PPI26 input signal" "Low,High" textline " " bitfld.long 0x00 25. " PPI25S ,Actual status of the PPI25 input signal" "Low,High" bitfld.long 0x00 24. " PPI24S ,Actual status of the PPI24 input signal" "Low,High" bitfld.long 0x00 23. " PPI23S ,Actual status of the PPI23 input signal" "Low,High" textline " " bitfld.long 0x00 22. " PPI22S ,Actual status of the PPI22 input signal" "Low,High" bitfld.long 0x00 21. " PPI21S ,Actual status of the PPI21 input signal" "Low,High" bitfld.long 0x00 20. " PPI20S ,Actual status of the PPI20 input signal" "Low,High" textline " " bitfld.long 0x00 19. " PPI19S ,Actual status of the PPI19 input signal" "Low,High" bitfld.long 0x00 18. " PPI18S ,Actual status of the PPI18 input signal" "Low,High" bitfld.long 0x00 17. " PPI17S ,Actual status of the PPI17 input signal" "Low,High" textline " " bitfld.long 0x00 16. " PPI16S ,Actual status of the PPI16 input signal" "Low,High" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICR_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICR_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICR_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICR_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICR_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICR_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICR_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICR_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICR_CIDR0,Component ID0 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICR_CIDR1,Component ID1 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICR_CIDR2,Component ID2 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICR_CIDR3,Component ID3 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end width 0x0B sif COMP.AVAILABLE("GICC") base COMP.BASE("GICC",-1.) width 14. tree "CPU Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICC",-1.))) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 10. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 9. " EOIMODES ,Controls the behavior of Secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" textline " " bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behavior of accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" textline " " bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" endif textline " " group.long 0x04++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" group.long 0x08++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x0C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x10++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICC_HPPIR,Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x20++0x03 hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register" in wgroup.long 0x24++0x03 line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x2C++0x03 line.long 0x00 "GICC_STATUSR,CPU Interface Status Register" bitfld.long 0x00 4. " ASV ,Attempted security violation" "Not detected,Detected" bitfld.long 0x00 3. " WROD ,Write to an RO location" "Not detected,Detected" bitfld.long 0x00 2. " RWOD ,Read of a WO location" "Not detected,Detected" textline " " bitfld.long 0x00 1. " WRD ,Write to a reserved location" "Not detected,Detected" bitfld.long 0x00 0. " RRD ,Read of a reserved location" "Not detected,Detected" group.long 0xD0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register 0" group.long 0xD4++0x03 line.long 0x00 "GICC_APR1,Active Priorities Register 1" group.long 0xD8++0x03 line.long 0x00 "GICC_APR2,Active Priorities Register 2" group.long 0xDC++0x03 line.long 0x00 "GICC_APR3,Active Priorities Register 3" group.long 0xE0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register 0" group.long 0xE4++0x03 line.long 0x00 "GICC_NSAPR1,Non-Secure Active Priorities Register 1" group.long 0xE8++0x03 line.long 0x00 "GICC_NSAPR2,Non-Secure Active Priorities Register 2" group.long 0xEC++0x03 line.long 0x00 "GICC_NSAPR3,Non-Secure Active Priorities Register 3" rgroup.long 0xFC++0x03 line.long 0x00 "GICC_IIDR,CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" ",,,GICv3,?..." bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICH") base COMP.BASE("GICH",-1.) width 13. tree "Virtual CPU Control Interface" group.long 0x00++0x03 line.long 0x00 "GICH_HCR,Hypervisor Control Register" bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " VGRP1DIE ,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " VGRP1EIE ,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " VGRP0DIE ,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " VGRP0EIE ,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,Virtual CPU interface Enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GICH_VTR,Virtual Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 23.--25. " IDBITS ,The number of virtual interrupt identifier bits supported" "16 bits,24 bits,?..." textline " " bitfld.long 0x00 22. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. " A3V ,Affinity 3 valid" "Invalid,Valid" bitfld.long 0x00 0.--4. " LISTREGS ,List regs number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0x08++0x03 line.long 0x00 "GICH_VMCR,Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. " VPMR ,Virtual priority mask" bitfld.long 0x00 21.--23. " VBPR0 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 0)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VBPR1 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 1)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9. " VEOIM ,Virtual EOImode. DP - Drop the priority / ID - interrupt deactivate" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" textline " " bitfld.long 0x00 4. " VCBPR ,Virtual Common Binary Point Register" "ABPR,BPR" bitfld.long 0x00 3. " VFIQEN ,Virtual FIQ enable" "Disabled,Enabled" bitfld.long 0x00 2. " VACKCTL ,Virtual AckCtl" "INTID=1022,INTID=corresponding" bitfld.long 0x00 1. " VENG1 ,Virtual interrupt enable for group 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " VENG0 ,Virtual interrupt enable for group 0" "Disabled,Enabled" rgroup.long 0x10++0x03 line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register" bitfld.long 0x00 7. " VGRP1D ,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 6. " VGRP1E ,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 5. " VGRP0D ,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 4. " VGRP0E ,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted" textline " " bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 1. " U ,Underflow maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 0. " EOI ,End Of Interrupt maintenance interrupt assertion" "Not asserted,Asserted" rgroup.long 0x20++0x03 line.long 0x00 "GICH_EISR0,End of Interrupt Status Register" bitfld.long 0x00 15. " STATUS15 ,EOI maintenance interrupt status for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,EOI maintenance interrupt status for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,EOI maintenance interrupt status for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,EOI maintenance interrupt status for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,EOI maintenance interrupt status for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,EOI maintenance interrupt status for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,EOI maintenance interrupt status for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,EOI maintenance interrupt status for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,EOI maintenance interrupt status for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,EOI maintenance interrupt status for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,EOI maintenance interrupt status for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,EOI maintenance interrupt status for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt" rgroup.long 0x30++0x03 line.long 0x00 "GICH_ELRSR0,Empty List register Status Register" bitfld.long 0x00 15. " STATUS15 ,Status bit for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,Status bit for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,Status bit for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,Status bit for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,Status bit for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,Status bit for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,Status bit for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,Status bit for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,Status bit for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,Status bit for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,Status bit for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,Status bit for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,Status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,Status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,Status bit for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,Status bit for List register 0" "No interrupt,Interrupt" textline " " group.long 0xF0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF4++0x03 line.long 0x00 "GICH_APR1,Active Priorities Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF8++0x03 line.long 0x00 "GICH_APR2,Active Priorities Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "GICH_APR3,Active Priorities Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x110++0x03 line.long 0x00 "GICH_LR4,List Register 4" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x114++0x03 line.long 0x00 "GICH_LR5,List Register 5" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x118++0x03 line.long 0x00 "GICH_LR6,List Register 6" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x11C++0x03 line.long 0x00 "GICH_LR7,List Register 7" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x120++0x03 line.long 0x00 "GICH_LR8,List Register 8" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x124++0x03 line.long 0x00 "GICH_LR9,List Register 9" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x128++0x03 line.long 0x00 "GICH_LR10,List Register 10" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x12C++0x03 line.long 0x00 "GICH_LR11,List Register 11" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x130++0x03 line.long 0x00 "GICH_LR12,List Register 12" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x134++0x03 line.long 0x00 "GICH_LR13,List Register 13" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x138++0x03 line.long 0x00 "GICH_LR14,List Register 14" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICV") base COMP.BASE("GICV",-1.) width 14. tree "Virtual CPU Interface" group.long 0x00++0x03 line.long 0x00 "GICV_CTLR,VM Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behaviour of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 4. " CBPR ,Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,FIQ Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ACKCTL ,Acknowledge control. Return ID of the corresponding interrupt" "1022,Corresponding" textline " " bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signalling of Group 1 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signalling of Group 0 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" group.long 0x04++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for the virtual CPU interface" group.long 0x08++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x0C++0x03 line.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x10++0x03 line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x20++0x03 line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x24++0x03 line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" textline "" group.long 0xD0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD4++0x03 line.long 0x00 "GICV_APR1,VM Active Priority Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD8++0x03 line.long 0x00 "GICV_APR2,VM Active Priority Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "GICV_APR3,VM Active Priority Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " rgroup.long 0xFC++0x03 line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" ",,,GICv3,?..." hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif width 0x0B tree.end tree.end endif config 16. 8. tree.open "Security" tree "RDC (Resources Domain Controller)" base ad:0x303D0000 width 9. rgroup.long 0x00++0x03 line.long 0x00 "VIR,Version Information" hexmask.long.byte 0x00 20.--27. 1. " NRGN ,Number of memory regions" hexmask.long.byte 0x00 12.--19. 1. " NPER ,Number of peripherals" newline hexmask.long.byte 0x00 4.--11. 1. " NMSTR ,Number of masters" bitfld.long 0x00 0.--3. " NDID ,Number of domains" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x24++0x0B line.long 0x00 "STAT,Status" bitfld.long 0x00 8. " PDS ,Power domain status" "Off,On" bitfld.long 0x00 0.--3. " DID ,Domain ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "INTCTRL,Interrupt and Control" bitfld.long 0x04 0. " RCI ,Restoration complete interrupt" "Disabled,Enabled" line.long 0x08 "INSTANT,Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt status" "No Interrupt,Interrupt" group.long 0x200++0x03 line.long 0x00 "MDA0x200,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x204++0x03 line.long 0x00 "MDA0x204,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x208++0x03 line.long 0x00 "MDA0x208,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x20C++0x03 line.long 0x00 "MDA0x20C,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x210++0x03 line.long 0x00 "MDA0x210,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x214++0x03 line.long 0x00 "MDA0x214,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x218++0x03 line.long 0x00 "MDA0x218,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x21C++0x03 line.long 0x00 "MDA0x21C,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x220++0x03 line.long 0x00 "MDA0x220,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x224++0x03 line.long 0x00 "MDA0x224,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x228++0x03 line.long 0x00 "MDA0x228,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x22C++0x03 line.long 0x00 "MDA0x22C,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x230++0x03 line.long 0x00 "MDA0x230,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x234++0x03 line.long 0x00 "MDA0x234,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x238++0x03 line.long 0x00 "MDA0x238,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x23C++0x03 line.long 0x00 "MDA0x23C,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x240++0x03 line.long 0x00 "MDA0x240,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x244++0x03 line.long 0x00 "MDA0x244,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x248++0x03 line.long 0x00 "MDA0x248,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x24C++0x03 line.long 0x00 "MDA0x24C,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x250++0x03 line.long 0x00 "MDA0x250,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x254++0x03 line.long 0x00 "MDA0x254,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x258++0x03 line.long 0x00 "MDA0x258,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x25C++0x03 line.long 0x00 "MDA0x25C,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x260++0x03 line.long 0x00 "MDA0x260,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x264++0x03 line.long 0x00 "MDA0x264,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x268++0x03 line.long 0x00 "MDA0x268,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "0,1,2,3" group.long 0x400++0x03 line.long 0x00 "PDAP,Peripheral Domain Access Permissions" button "PDAP" "d (ad:0x303D0000+0x400)--(ad:0x303D0000+0x85F) /long" group.long 0x800++0x0F line.long 0x00 "MRSA0x800,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x800,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x800,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x800,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x810++0x0F line.long 0x00 "MRSA0x810,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x810,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x810,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x810,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x820++0x0F line.long 0x00 "MRSA0x820,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x820,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x820,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x820,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x830++0x0F line.long 0x00 "MRSA0x830,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x830,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x830,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x830,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x840++0x0F line.long 0x00 "MRSA0x840,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x840,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x840,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x840,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x850++0x0F line.long 0x00 "MRSA0x850,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x850,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x850,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x850,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x860++0x0F line.long 0x00 "MRSA0x860,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x860,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x860,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x860,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x870++0x0F line.long 0x00 "MRSA0x870,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x870,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x870,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x870,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x880++0x0F line.long 0x00 "MRSA0x880,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x880,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x880,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x880,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x890++0x0F line.long 0x00 "MRSA0x890,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x890,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x890,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x890,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x8A0++0x0F line.long 0x00 "MRSA0x8A0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x8A0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x8A0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x8A0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x8B0++0x0F line.long 0x00 "MRSA0x8B0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x8B0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x8B0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x8B0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x8C0++0x0F line.long 0x00 "MRSA0x8C0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x8C0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x8C0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x8C0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x8D0++0x0F line.long 0x00 "MRSA0x8D0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x8D0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x8D0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x8D0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x8E0++0x0F line.long 0x00 "MRSA0x8E0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x8E0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x8E0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x8E0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x8F0++0x0F line.long 0x00 "MRSA0x8F0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x8F0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x8F0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x8F0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x900++0x0F line.long 0x00 "MRSA0x900,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x900,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x900,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x900,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x910++0x0F line.long 0x00 "MRSA0x910,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x910,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x910,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x910,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x920++0x0F line.long 0x00 "MRSA0x920,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x920,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x920,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x920,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x930++0x0F line.long 0x00 "MRSA0x930,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x930,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x930,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x930,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x940++0x0F line.long 0x00 "MRSA0x940,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x940,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x940,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x940,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x950++0x0F line.long 0x00 "MRSA0x950,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x950,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x950,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x950,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x960++0x0F line.long 0x00 "MRSA0x960,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x960,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x960,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x960,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x970++0x0F line.long 0x00 "MRSA0x970,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x970,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x970,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x970,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x980++0x0F line.long 0x00 "MRSA0x980,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x980,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x980,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x980,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x990++0x0F line.long 0x00 "MRSA0x990,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x990,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x990,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x990,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x9A0++0x0F line.long 0x00 "MRSA0x9A0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x9A0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x9A0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x9A0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x9B0++0x0F line.long 0x00 "MRSA0x9B0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x9B0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x9B0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x9B0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x9C0++0x0F line.long 0x00 "MRSA0x9C0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x9C0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x9C0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x9C0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x9D0++0x0F line.long 0x00 "MRSA0x9D0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x9D0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x9D0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x9D0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x9E0++0x0F line.long 0x00 "MRSA0x9E0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x9E0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x9E0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x9E0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0x9F0++0x0F line.long 0x00 "MRSA0x9F0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0x9F0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0x9F0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0x9F0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xA00++0x0F line.long 0x00 "MRSA0xA00,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xA00,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xA00,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xA00,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xA10++0x0F line.long 0x00 "MRSA0xA10,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xA10,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xA10,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xA10,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xA20++0x0F line.long 0x00 "MRSA0xA20,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xA20,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xA20,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xA20,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xA30++0x0F line.long 0x00 "MRSA0xA30,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xA30,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xA30,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xA30,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xA40++0x0F line.long 0x00 "MRSA0xA40,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xA40,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xA40,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xA40,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xA50++0x0F line.long 0x00 "MRSA0xA50,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xA50,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xA50,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xA50,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xA60++0x0F line.long 0x00 "MRSA0xA60,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xA60,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xA60,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xA60,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xA70++0x0F line.long 0x00 "MRSA0xA70,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xA70,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xA70,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xA70,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xA80++0x0F line.long 0x00 "MRSA0xA80,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xA80,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xA80,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xA80,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xA90++0x0F line.long 0x00 "MRSA0xA90,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xA90,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xA90,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xA90,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xAA0++0x0F line.long 0x00 "MRSA0xAA0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xAA0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xAA0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xAA0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xAB0++0x0F line.long 0x00 "MRSA0xAB0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xAB0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xAB0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xAB0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xAC0++0x0F line.long 0x00 "MRSA0xAC0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xAC0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xAC0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xAC0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xAD0++0x0F line.long 0x00 "MRSA0xAD0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xAD0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xAD0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xAD0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xAE0++0x0F line.long 0x00 "MRSA0xAE0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xAE0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xAE0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xAE0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xAF0++0x0F line.long 0x00 "MRSA0xAF0,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xAF0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xAF0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xAF0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xB00++0x0F line.long 0x00 "MRSA0xB00,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xB00,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xB00,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xB00,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xB10++0x0F line.long 0x00 "MRSA0xB10,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xB10,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xB10,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xB10,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xB20++0x0F line.long 0x00 "MRSA0xB20,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xB20,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xB20,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xB20,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" group.long 0xB30++0x0F line.long 0x00 "MRSA0xB30,Memory Region START Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0xB30,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory address" line.long 0x08 "MRC0xB30,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "Not allowed,Allowed" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "Not allowed,Allowed" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "Not allowed,Allowed" newline bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "Not allowed,Allowed" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "Not allowed,Allowed" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "Not allowed,Allowed" newline bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "Not allowed,Allowed" line.long 0x0C "MRVS0xB30,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 1. " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Disabled,Enabled" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "0,1,2,3" width 0x0B tree.end tree.open "RDC_SEMA42 (Resources Domain Controller Semaphore)" tree "RDC_SEMAPHORE_1" base ad:0x303B0000 width 9. group.byte 0x0++0x00 line.byte 0x00 "Gate0,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1++0x00 line.byte 0x00 "Gate1,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2++0x00 line.byte 0x00 "Gate2,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3++0x00 line.byte 0x00 "Gate3,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x4++0x00 line.byte 0x00 "Gate4,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x5++0x00 line.byte 0x00 "Gate5,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x6++0x00 line.byte 0x00 "Gate6,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x7++0x00 line.byte 0x00 "Gate7,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x8++0x00 line.byte 0x00 "Gate8,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x9++0x00 line.byte 0x00 "Gate9,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xA++0x00 line.byte 0x00 "Gate10,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xB++0x00 line.byte 0x00 "Gate11,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xC++0x00 line.byte 0x00 "Gate12,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xD++0x00 line.byte 0x00 "Gate13,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xE++0x00 line.byte 0x00 "Gate14,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xF++0x00 line.byte 0x00 "Gate15,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x10++0x00 line.byte 0x00 "Gate16,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x11++0x00 line.byte 0x00 "Gate17,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x12++0x00 line.byte 0x00 "Gate18,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x13++0x00 line.byte 0x00 "Gate19,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x14++0x00 line.byte 0x00 "Gate20,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x15++0x00 line.byte 0x00 "Gate21,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x16++0x00 line.byte 0x00 "Gate22,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x17++0x00 line.byte 0x00 "Gate23,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x18++0x00 line.byte 0x00 "Gate24,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x19++0x00 line.byte 0x00 "Gate25,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1A++0x00 line.byte 0x00 "Gate26,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1B++0x00 line.byte 0x00 "Gate27,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1C++0x00 line.byte 0x00 "Gate28,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1D++0x00 line.byte 0x00 "Gate29,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1E++0x00 line.byte 0x00 "Gate30,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1F++0x00 line.byte 0x00 "Gate31,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x20++0x00 line.byte 0x00 "Gate32,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x21++0x00 line.byte 0x00 "Gate33,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x22++0x00 line.byte 0x00 "Gate34,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x23++0x00 line.byte 0x00 "Gate35,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x24++0x00 line.byte 0x00 "Gate36,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x25++0x00 line.byte 0x00 "Gate37,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x26++0x00 line.byte 0x00 "Gate38,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x27++0x00 line.byte 0x00 "Gate39,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x28++0x00 line.byte 0x00 "Gate40,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x29++0x00 line.byte 0x00 "Gate41,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2A++0x00 line.byte 0x00 "Gate42,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2B++0x00 line.byte 0x00 "Gate43,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2C++0x00 line.byte 0x00 "Gate44,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2D++0x00 line.byte 0x00 "Gate45,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2E++0x00 line.byte 0x00 "Gate46,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2F++0x00 line.byte 0x00 "Gate47,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x30++0x00 line.byte 0x00 "Gate48,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x31++0x00 line.byte 0x00 "Gate49,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x32++0x00 line.byte 0x00 "Gate50,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x33++0x00 line.byte 0x00 "Gate51,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x34++0x00 line.byte 0x00 "Gate52,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x35++0x00 line.byte 0x00 "Gate53,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x36++0x00 line.byte 0x00 "Gate54,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x37++0x00 line.byte 0x00 "Gate55,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x38++0x00 line.byte 0x00 "Gate56,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x39++0x00 line.byte 0x00 "Gate57,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3A++0x00 line.byte 0x00 "Gate58,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3B++0x00 line.byte 0x00 "Gate59,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3C++0x00 line.byte 0x00 "Gate60,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3D++0x00 line.byte 0x00 "Gate61,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3E++0x00 line.byte 0x00 "Gate62,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3F++0x00 line.byte 0x00 "Gate63,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.word 0x40++0x01 line.byte 0x00 "RSTGT_W,Reset Gate Write" hexmask.word.byte 0x00 8.--15. " RSTGTN ,Reset gate number" hexmask.word.byte 0x00 0.--7. " RSTGDP ,Reset Gate Number" group.word 0x40++0x01 line.byte 0x00 "RSTGT_R,Reset Gate Read" hexmask.word.byte 0x00 8.--15. " RSTGTN ,Reset gate number" rbitfld.word 0x00 4.--5. " RSTGSM ,Reset gate finite state machine" "Idle,Waiting,Completed,?..." rbitfld.word 0x00 0.--3. " RSTGMS ,Reset gate bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "RDC_SEMAPHORE_2" base ad:0x303C0000 width 9. group.byte 0x0++0x00 line.byte 0x00 "Gate0,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1++0x00 line.byte 0x00 "Gate1,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2++0x00 line.byte 0x00 "Gate2,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3++0x00 line.byte 0x00 "Gate3,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x4++0x00 line.byte 0x00 "Gate4,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x5++0x00 line.byte 0x00 "Gate5,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x6++0x00 line.byte 0x00 "Gate6,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x7++0x00 line.byte 0x00 "Gate7,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x8++0x00 line.byte 0x00 "Gate8,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x9++0x00 line.byte 0x00 "Gate9,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xA++0x00 line.byte 0x00 "Gate10,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xB++0x00 line.byte 0x00 "Gate11,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xC++0x00 line.byte 0x00 "Gate12,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xD++0x00 line.byte 0x00 "Gate13,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xE++0x00 line.byte 0x00 "Gate14,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xF++0x00 line.byte 0x00 "Gate15,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x10++0x00 line.byte 0x00 "Gate16,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x11++0x00 line.byte 0x00 "Gate17,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x12++0x00 line.byte 0x00 "Gate18,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x13++0x00 line.byte 0x00 "Gate19,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x14++0x00 line.byte 0x00 "Gate20,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x15++0x00 line.byte 0x00 "Gate21,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x16++0x00 line.byte 0x00 "Gate22,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x17++0x00 line.byte 0x00 "Gate23,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x18++0x00 line.byte 0x00 "Gate24,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x19++0x00 line.byte 0x00 "Gate25,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1A++0x00 line.byte 0x00 "Gate26,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1B++0x00 line.byte 0x00 "Gate27,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1C++0x00 line.byte 0x00 "Gate28,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1D++0x00 line.byte 0x00 "Gate29,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1E++0x00 line.byte 0x00 "Gate30,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1F++0x00 line.byte 0x00 "Gate31,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x20++0x00 line.byte 0x00 "Gate32,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x21++0x00 line.byte 0x00 "Gate33,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x22++0x00 line.byte 0x00 "Gate34,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x23++0x00 line.byte 0x00 "Gate35,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x24++0x00 line.byte 0x00 "Gate36,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x25++0x00 line.byte 0x00 "Gate37,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x26++0x00 line.byte 0x00 "Gate38,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x27++0x00 line.byte 0x00 "Gate39,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x28++0x00 line.byte 0x00 "Gate40,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x29++0x00 line.byte 0x00 "Gate41,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2A++0x00 line.byte 0x00 "Gate42,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2B++0x00 line.byte 0x00 "Gate43,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2C++0x00 line.byte 0x00 "Gate44,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2D++0x00 line.byte 0x00 "Gate45,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2E++0x00 line.byte 0x00 "Gate46,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2F++0x00 line.byte 0x00 "Gate47,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x30++0x00 line.byte 0x00 "Gate48,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x31++0x00 line.byte 0x00 "Gate49,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x32++0x00 line.byte 0x00 "Gate50,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x33++0x00 line.byte 0x00 "Gate51,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x34++0x00 line.byte 0x00 "Gate52,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x35++0x00 line.byte 0x00 "Gate53,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x36++0x00 line.byte 0x00 "Gate54,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x37++0x00 line.byte 0x00 "Gate55,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x38++0x00 line.byte 0x00 "Gate56,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x39++0x00 line.byte 0x00 "Gate57,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3A++0x00 line.byte 0x00 "Gate58,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3B++0x00 line.byte 0x00 "Gate59,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3C++0x00 line.byte 0x00 "Gate60,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3D++0x00 line.byte 0x00 "Gate61,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3E++0x00 line.byte 0x00 "Gate62,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3F++0x00 line.byte 0x00 "Gate63,Gate Register" rbitfld.byte 0x00 4.--5. " LDOM ,Locked By Domain" "0,1,2,3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate Finite State Machine" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.word 0x40++0x01 line.byte 0x00 "RSTGT_W,Reset Gate Write" hexmask.word.byte 0x00 8.--15. " RSTGTN ,Reset gate number" hexmask.word.byte 0x00 0.--7. " RSTGDP ,Reset Gate Number" group.word 0x40++0x01 line.byte 0x00 "RSTGT_R,Reset Gate Read" hexmask.word.byte 0x00 8.--15. " RSTGTN ,Reset gate number" rbitfld.word 0x00 4.--5. " RSTGSM ,Reset gate finite state machine" "Idle,Waiting,Completed,?..." rbitfld.word 0x00 0.--3. " RSTGMS ,Reset gate bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree.end tree.end tree.open "ARM Platform and Debug" tree "LMEM (Local Memory Controller)" base ad:0xE0082000 width 9. group.long 0x00++0x03 line.long 0x00 "PCCCR,Cache Control Register" bitfld.long 0x00 31. " GO ,Initiate cache command [write/read]" "No effect/No activated,Initiated/Activated" bitfld.long 0x00 27. " PUSHW1 ,Push way 1" "No operation,Pushed" bitfld.long 0x00 26. " INVW1 ,Invalidate way 1" "No operation,Invalidated" bitfld.long 0x00 25. " PUSHW0 ,Push way 0" "No operation,Pushed" newline bitfld.long 0x00 24. " INVW0 ,Invalidate way 0" "No operation,Invalidated" bitfld.long 0x00 3. " PCCR3 ,Cache control allocation 3" "0,1" bitfld.long 0x00 2. " PCCR2 ,Cache control allocation 3" "0,1" bitfld.long 0x00 1. " ENWRBUF ,Enable write buffer" "Disabled,Enabled" newline bitfld.long 0x00 0. " ENCACHE ,Cache enable" "Disabled,Enabled" if (((per.l(ad:0xE0082000+0x04))&0x10000)==0x0) group.long 0x04++0x0B line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache,Physical" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and read and write,Invalidate,Push,Clear" rbitfld.long 0x00 22. " LCWAY ,Line command way" "0,1" newline rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "0,1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" newline hexmask.long.word 0x00 2.--11. 0x04 " CACHEADDR ,CACHEADDR bits are used to access the data arrays" bitfld.long 0x00 0. " LGO ,Initiate cache line command [write/read]" "No effect/No activated,Initiated/Activated" line.long 0x04 "PCCSAR,Cache search address register" hexmask.long.tbyte 0x04 12.--31. 0x10 " PHYADDR ,PHYADDR bits are used for tag compare" hexmask.long.word 0x04 2.--11. 0x04 " PHYADDR ,PHYADDR bits are used to access the data arrays" bitfld.long 0x04 0. " LGO ,Initiate cache line command [write/read]" "No effect/No activated,Initiated/Activated" line.long 0x08 "PCCCVR,Cache Read/Write Value Register" else group.long 0x04++0x0B line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address Select" "Cache,Physical" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and read and write,Invalidate,Push,Clear" rbitfld.long 0x00 22. " LCWAY ,Line command way" "0,1" newline rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "0,1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" newline hexmask.long.word 0x00 4.--11. 0x10 " CACHEADDR ,CACHEADDR bits are used to access the tag arrays" bitfld.long 0x00 0. " LGO ,Initiate cache line command [write/read]" "No effect/No activated,Initiated/Activated" line.long 0x04 "PCCSAR,Cache Search Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " PHYADDR ,PHYADDR bits are used for tag compare" hexmask.long.word 0x04 4.--11. 0x10 " PHYADDR ,PHYADDR bits are used to access the tag arrays" bitfld.long 0x04 0. " LGO ,Initiate cache line command [write/read]" "No effect/No activated,Initiated/Activated" line.long 0x08 "PCCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x08 12.--31. 1. " DATA ,DATA bits are used for tag array R/W value" hexmask.long.byte 0x08 4.--11. 1. " DATA ,DATA bits are used for tag set address on reads" endif group.long 0x800++0x03 line.long 0x00 "PSCCR,Cache Control Register" bitfld.long 0x00 31. " GO ,Initiate cache command [write/read]" "No effect/No activated,Initiated/Activated" bitfld.long 0x00 27. " PUSHW1 ,Push way 1" "No operation,Pushed" bitfld.long 0x00 26. " INVW1 ,Invalidate way 1" "No operation,Invalidated" bitfld.long 0x00 25. " PUSHW0 ,Push way 0" "No operation,Pushed" newline bitfld.long 0x00 24. " INVW0 ,Invalidate way 0" "No operation,Invalidated" bitfld.long 0x00 1. " ENWRBUF ,Enable write buffer" "Disabled,Enabled" bitfld.long 0x00 0. " ENCACHE ,Cache enable" "Disabled,Enabled" if (((per.l(ad:0xE0082000+0x804))&0x10000)==0x0) group.long 0x804++0x0B line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache,Physical" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and read and write,Invalidate,Push,Clear" rbitfld.long 0x00 22. " LCWAY ,Line command way" "0,1" newline rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "0,1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" newline hexmask.long.word 0x00 2.--11. 0x04 " CACHEADDR ,CACHEADDR bits are used to access the data arrays" bitfld.long 0x00 0. " LGO ,Initiate cache line command [write/read]" "No effect/No activated,Initiated/Activated" line.long 0x04 "PCCSAR,Cache Search Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " PHYADDR ,PHYADDR bits are used for tag compare" hexmask.long.word 0x04 2.--11. 0x04 " PHYADDR ,PHYADDR bits are used to access the data arrays" bitfld.long 0x04 0. " LGO ,Initiate cache line command [write/read]" "No effect/No activated,Initiated/Activated" line.long 0x08 "PCCCVR,Cache Read/Write Value Register" else group.long 0x804++0x0B line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache,Physical" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and read and write,Invalidate,Push,Clear" rbitfld.long 0x00 22. " LCWAY ,Line command way" "0,1" newline rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "0,1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" newline hexmask.long.word 0x00 4.--11. 0x10 " CACHEADDR ,CACHEADDR bits are used to access the tag arrays" bitfld.long 0x00 0. " LGO ,Initiate cache line command [write/read]" "No effect/No activated,Initiated/Activated" line.long 0x04 "PCCSAR,Cache Search Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " PHYADDR ,PHYADDR bits are used for tag compare" hexmask.long.word 0x04 4.--11. 0x10 " PHYADDR ,PHYADDR bits are used to access the tag arrays" bitfld.long 0x04 0. " LGO ,Initiate cache line command [write/read]" "No effect/No activated,Initiated/Activated" line.long 0x08 "PCCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x08 12.--31. 1. " DATA ,DATA bits are used for tag array R/W value" hexmask.long.byte 0x08 4.--11. 1. " DATA ,DATA bits are used for tag set address on reads" endif width 0x0B tree.end tree "MCM (Miscellaneous Control Module)" base ad:0xE0080000 width 7. rgroup.word 0x08++0x05 line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration" bitfld.word 0x00 7. " ASC[7] ,Bus slave connection to AXBS input port 7" "Absent,Present" bitfld.word 0x00 6. " [6] ,Bus slave connection to AXBS input port 6" "Absent,Present" bitfld.word 0x00 5. " [5] ,Bus slave connection to AXBS input port 5" "Absent,Present" bitfld.word 0x00 4. " [4] ,Bus slave connection to AXBS input port 4" "Absent,Present" textline " " bitfld.word 0x00 3. " [3] ,Bus slave connection to AXBS input port 3" "Absent,Present" bitfld.word 0x00 2. " [2] ,Bus slave connection to AXBS input port 2" "Absent,Present" bitfld.word 0x00 1. " [1] ,Bus slave connection to AXBS input port 1" "Absent,Present" bitfld.word 0x00 0. " [0] ,Bus slave connection to AXBS input port 0" "Absent,Present" line.word 0x02 "PLAMC,Crossbar Switch (AXBS) Master Configuration" bitfld.word 0x02 7. " AMC[7] ,Bus master connection to AXBS input port 7" "Absent,Present" bitfld.word 0x02 6. " [6] ,Bus master connection to AXBS input port 6" "Absent,Present" bitfld.word 0x02 5. " [5] ,Bus master connection to AXBS input port 5" "Absent,Present" bitfld.word 0x02 4. " [4] ,Bus master connection to AXBS input port 4" "Absent,Present" textline " " bitfld.word 0x02 3. " [3] ,Bus master connection to AXBS input port 3" "Absent,Present" bitfld.word 0x02 2. " [2] ,Bus master connection to AXBS input port 2" "Absent,Present" bitfld.word 0x02 1. " [1] ,Bus master connection to AXBS input port 1" "Absent,Present" bitfld.word 0x02 0. " [0] ,Bus master connection to AXBS input port 0" "Absent,Present" rgroup.long 0x20++0x0B line.long 0x00 "FADR,Fault address register" line.long 0x04 "FATR,Fault attributes register" bitfld.long 0x04 31. " BEOVR ,Bus error overrun" "No occurred,Occurred" bitfld.long 0x04 8.--11. " BEMN ,Bus error master number" ",1,?..." bitfld.long 0x04 7. " BEWT ,Bus error write" "Read,Write" textline " " bitfld.long 0x04 4.--5. " BESZ ,Bus size error" "8-bit,16-bit,32-bit,?..." bitfld.long 0x04 1. " BEMD ,Bus error privilege level" "User,Supervisor/privileged" bitfld.long 0x04 0. " BEDA ,Bus error access type" "Instruction,Data" line.long 0x08 "FDR,Fault data register" width 0x0B tree.end tree.open "MU (Messaging Unit)" tree "MUA (MU Processor A-side)" base ad:0x30AA0000 width 10. if (((per.l(ad:0x30AA0000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x30AA0000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x30AA0000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x30AA0000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif if (((per.l(ad:0x30AA0000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in endif if (((per.l(ad:0x30AA0000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in endif if (((per.l(ad:0x30AA0000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in endif if (((per.l(ad:0x30AA0000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" textline " " bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" textline " " bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" textline " " bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" textline " " bitfld.long 0x00 3. " F[3] ,Processor A-side flag 3" ",1" bitfld.long 0x00 2. " [2] ,Processor A-side flag 2" "0,1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" textline " " bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Self clearing bit,Self clearing bit" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "De-assert,Assert" textline " " bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Clear,Set" width 0x0B tree.end tree "MUB (MU Processor B-side)" base ad:0x30AB0000 width 10. if (((per.l(ad:0x30AB0000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x30AB0000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x30AB0000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x30AB0000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif if (((per.l(ad:0x30AB0000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in endif if (((per.l(ad:0x30AB0000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in endif if (((per.l(ad:0x30AB0000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in endif if (((per.l(ad:0x30AB0000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" textline " " bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" textline " " bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" textline " " bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 5.--6. " APM ,Processor A power mode" "Run,Wait,,Stop" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" textline " " bitfld.long 0x00 3. " F[3] ,Processor B-side flag 3" ",1" bitfld.long 0x00 2. " [2] ,Processor B-side flag 2" "0,1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" textline " " bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" textline " " bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree.end tree "SEMA4 (Semaphore)" base ad:0x30AC0000 width 9. group.byte 0x0++0x00 line.byte 0x00 "Gate0,Semaphores Gate 0 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0x1++0x00 line.byte 0x00 "Gate1,Semaphores Gate 1 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0x2++0x00 line.byte 0x00 "Gate2,Semaphores Gate 2 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0x3++0x00 line.byte 0x00 "Gate3,Semaphores Gate 3 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0x4++0x00 line.byte 0x00 "Gate4,Semaphores Gate 4 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0x5++0x00 line.byte 0x00 "Gate5,Semaphores Gate 5 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0x6++0x00 line.byte 0x00 "Gate6,Semaphores Gate 6 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0x7++0x00 line.byte 0x00 "Gate7,Semaphores Gate 7 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0x8++0x00 line.byte 0x00 "Gate8,Semaphores Gate 8 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0x9++0x00 line.byte 0x00 "Gate9,Semaphores Gate 9 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0xA++0x00 line.byte 0x00 "Gate10,Semaphores Gate 10 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0xB++0x00 line.byte 0x00 "Gate11,Semaphores Gate 11 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0xC++0x00 line.byte 0x00 "Gate12,Semaphores Gate 12 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0xD++0x00 line.byte 0x00 "Gate13,Semaphores Gate 13 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0xE++0x00 line.byte 0x00 "Gate14,Semaphores Gate 14 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.byte 0xF++0x00 line.byte 0x00 "Gate15,Semaphores Gate 15 Register" bitfld.byte 0x00 0.--1. " GTSFM ,Gate Finite Machine State" "Unlocked,Processor 0,Processor 1,?..." group.word 0x40++0x01 line.word 0x00 "CP0INE,Semaphores Processor 0x40 IRQ Notification Enable" bitfld.word 0x00 15. " INE8 ,Interrupt Request Notification Enable 8" "Disabled,Enabled" bitfld.word 0x00 14. " INE9 ,Interrupt Request Notification Enable 9" "Disabled,Enabled" bitfld.word 0x00 13. " INE10 ,Interrupt Request Notification Enable 10" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " INE11 ,Interrupt Request Notification Enable 11" "Disabled,Enabled" bitfld.word 0x00 11. " INE12 ,Interrupt Request Notification Enable 12" "Disabled,Enabled" bitfld.word 0x00 10. " INE13 ,Interrupt Request Notification Enable 13" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " INE14 ,Interrupt Request Notification Enable 14" "Disabled,Enabled" bitfld.word 0x00 8. " INE15 ,Interrupt Request Notification Enable 15" "Disabled,Enabled" bitfld.word 0x00 7. " INE0 ,Interrupt Request Notification Enable 0" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " INE1 ,Interrupt Request Notification Enable 1" "Disabled,Enabled" bitfld.word 0x00 5. " INE2 ,Interrupt Request Notification Enable 2" "Disabled,Enabled" bitfld.word 0x00 4. " INE3 ,Interrupt Request Notification Enable 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " INE4 ,Interrupt Request Notification Enable 4" "Disabled,Enabled" bitfld.word 0x00 2. " INE5 ,Interrupt Request Notification Enable 5" "Disabled,Enabled" bitfld.word 0x00 1. " INE6 ,Interrupt Request Notification Enable 6" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " INE7 ,Interrupt Request Notification Enable 7" "Disabled,Enabled" group.word 0x48++0x01 line.word 0x00 "CP1INE,Semaphores Processor 0x48 IRQ Notification Enable" bitfld.word 0x00 15. " INE8 ,Interrupt Request Notification Enable 8" "Disabled,Enabled" bitfld.word 0x00 14. " INE9 ,Interrupt Request Notification Enable 9" "Disabled,Enabled" bitfld.word 0x00 13. " INE10 ,Interrupt Request Notification Enable 10" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " INE11 ,Interrupt Request Notification Enable 11" "Disabled,Enabled" bitfld.word 0x00 11. " INE12 ,Interrupt Request Notification Enable 12" "Disabled,Enabled" bitfld.word 0x00 10. " INE13 ,Interrupt Request Notification Enable 13" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " INE14 ,Interrupt Request Notification Enable 14" "Disabled,Enabled" bitfld.word 0x00 8. " INE15 ,Interrupt Request Notification Enable 15" "Disabled,Enabled" bitfld.word 0x00 7. " INE0 ,Interrupt Request Notification Enable 0" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " INE1 ,Interrupt Request Notification Enable 1" "Disabled,Enabled" bitfld.word 0x00 5. " INE2 ,Interrupt Request Notification Enable 2" "Disabled,Enabled" bitfld.word 0x00 4. " INE3 ,Interrupt Request Notification Enable 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " INE4 ,Interrupt Request Notification Enable 4" "Disabled,Enabled" bitfld.word 0x00 2. " INE5 ,Interrupt Request Notification Enable 5" "Disabled,Enabled" bitfld.word 0x00 1. " INE6 ,Interrupt Request Notification Enable 6" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " INE7 ,Interrupt Request Notification Enable 7" "Disabled,Enabled" group.word 0x80++0x01 line.word 0x00 "CP0NTF,Semaphores Processor 0x80 IRQ Notification" bitfld.word 0x00 15. " GN8 ,Gate 8 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 14. " GN9 ,Gate 9 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 13. " GN10 ,Gate 10 Notification" "Not interrupt,Interrupt" textline " " bitfld.word 0x00 12. " GN11 ,Gate 11 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 11. " GN12 ,Gate 12 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 10. " GN13 ,Gate 13 Notification" "Not interrupt,Interrupt" textline " " bitfld.word 0x00 9. " GN14 ,Gate 14 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 8. " GN15 ,Gate 15 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 7. " GN0 ,Gate 0 Notification" "Not interrupt,Interrupt" textline " " bitfld.word 0x00 6. " GN1 ,Gate 1 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 5. " GN2 ,Gate 2 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 4. " GN3 ,Gate 3 Notification" "Not interrupt,Interrupt" textline " " bitfld.word 0x00 3. " GN4 ,Gate 4 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 2. " GN5 ,Gate 5 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 1. " GN6 ,Gate 6 Notification" "Not interrupt,Interrupt" textline " " bitfld.word 0x00 0. " GN7 ,Gate 7 Notification" "Not interrupt,Interrupt" group.word 0x88++0x01 line.word 0x00 "CP1NTF,Semaphores Processor 0x88 IRQ Notification" bitfld.word 0x00 15. " GN8 ,Gate 8 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 14. " GN9 ,Gate 9 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 13. " GN10 ,Gate 10 Notification" "Not interrupt,Interrupt" textline " " bitfld.word 0x00 12. " GN11 ,Gate 11 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 11. " GN12 ,Gate 12 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 10. " GN13 ,Gate 13 Notification" "Not interrupt,Interrupt" textline " " bitfld.word 0x00 9. " GN14 ,Gate 14 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 8. " GN15 ,Gate 15 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 7. " GN0 ,Gate 0 Notification" "Not interrupt,Interrupt" textline " " bitfld.word 0x00 6. " GN1 ,Gate 1 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 5. " GN2 ,Gate 2 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 4. " GN3 ,Gate 3 Notification" "Not interrupt,Interrupt" textline " " bitfld.word 0x00 3. " GN4 ,Gate 4 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 2. " GN5 ,Gate 5 Notification" "Not interrupt,Interrupt" bitfld.word 0x00 1. " GN6 ,Gate 6 Notification" "Not interrupt,Interrupt" textline " " bitfld.word 0x00 0. " GN7 ,Gate 7 Notification" "Not interrupt,Interrupt" rgroup.word 0x100++0x01 line.word 0x00 "RSTGT,Semaphores (Secure) Reset Gate N (Read-only)" hexmask.word.byte 0x00 8.--15. 1. " RSTGTN ,Reset gate number" bitfld.word 0x00 4.--5. " RSTGSM ,Reset gate finite state machine" "Idle,Waiting,Completed,?..." bitfld.word 0x00 0.--2. " RSTGMS ,Reset gate bus master" "0,1,2,3,4,5,6,7" wgroup.word 0x100++0x01 line.word 0x00 "RSTGT,Semaphores (Secure) Reset Gate N (Write-only)" hexmask.word.byte 0x00 8.--15. 1. " RSTGTN ,Reset gate number" hexmask.word.byte 0x00 0.--7. 1. " RSTGDP ,Reset gate data pattern" rgroup.word 0x104++0x01 line.word 0x00 "RSTNTF,Semaphores (Secure) Reset IRQ Notification (Read-only)" hexmask.word.byte 0x00 8.--15. 1. " RSTNTN ,Reset notification number" bitfld.word 0x00 4.--5. " RSTNSM ,Reset notification finite state machine" "Idle,Waiting,Completed,?..." bitfld.word 0x00 0.--2. " RSTNMS ,Reset notification bus master" "0,1,2,3,4,5,6,7" wgroup.word 0x104++0x01 line.word 0x00 "RSTNTF,Semaphores (Secure) Reset IRQ Notification (Write-only)" hexmask.word.byte 0x00 8.--15. 1. " RSTNTN ,Reset notification number" hexmask.word.byte 0x00 0.--7. 1. " RSTNDP ,Reset notification data pattern" width 0x0b tree.end tree "AIPSTZ (AHB to IP Bridge)" tree "Channel 1" base ad:0x301f0000 width 8. group.long 0x00++0x03 line.long 0x00 "MPR,Master Privilege Register" bitfld.long 0x00 31. " MPROT0[3] ,Master 0 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 30. " MPROT0[2] ,Master 0 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 29. " MPROT0[1] ,Master 0 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 28. " MPROT0[0] ,Master 0 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 27. " MPROT1[3] ,Master 1 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 26. " MPROT1[2] ,Master 1 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 25. " MPROT1[1] ,Master 1 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 24. " MPROT1[0] ,Master 1 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 23. " MPROT2[3] ,Master 2 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 22. " MPROT2[2] ,Master 2 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 21. " MPROT2[1] ,Master 2 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 20. " MPROT2[0] ,Master 2 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 19. " MPROT3[3] ,Master 3 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 18. " MPROT3[2] ,Master 3 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 17. " MPROT3[1] ,Master 3 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 16. " MPROT3[0] ,Master 3 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 11. " MPROT5[3] ,Master 5 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 10. " MPROT5[2] ,Master 5 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 9. " MPROT5[1] ,Master 5 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 8. " MPROT5[0] ,Master 5 Privilege Level(MPL)" "Forced,Not forced" group.long 0x40++0x13 line.long 0x00 "OPACR0,Off-Platform Peripheral Access Control Register" bitfld.long 0x00 31. " OPAC0[3] ,Buffer Writes (BW) Control 0" "Disabled,Enabled" bitfld.long 0x00 30. " OPAC0[2] ,Supervisor Protect (SP) Control 0" "Not Required,Required" bitfld.long 0x00 29. " OPAC0[1] ,Write Protect (WP) Control 0" "Disabled,Enabled" bitfld.long 0x00 28. " OPAC0[0] ,Trusted Protect (TP) Control 0" "Allowed,Not allowed" textline " " bitfld.long 0x00 27. " OPAC1[3] ,Buffer Writes (BW) Control 1" "Disabled,Enabled" bitfld.long 0x00 26. " OPAC1[2] ,Supervisor Protect (SP) Control 1" "Not Required,Required" bitfld.long 0x00 25. " OPAC1[1] ,Write Protect (WP) Control 1" "Disabled,Enabled" bitfld.long 0x00 24. " OPAC1[0] ,Trusted Protect (TP) Control 1" "Allowed,Not allowed" textline " " bitfld.long 0x00 23. " OPAC2[3] ,Buffer Writes (BW) Control 2" "Disabled,Enabled" bitfld.long 0x00 22. " OPAC2[2] ,Supervisor Protect (SP) Control 2" "Not Required,Required" bitfld.long 0x00 21. " OPAC2[1] ,Write Protect (WP) Control 2" "Disabled,Enabled" bitfld.long 0x00 20. " OPAC2[0] ,Trusted Protect (TP) Control 2" "Allowed,Not allowed" textline " " bitfld.long 0x00 19. " OPAC3[3] ,Buffer Writes (BW) Control 3" "Disabled,Enabled" bitfld.long 0x00 18. " OPAC3[2] ,Supervisor Protect (SP) Control 3" "Not Required,Required" bitfld.long 0x00 17. " OPAC3[1] ,Write Protect (WP) Control 3" "Disabled,Enabled" bitfld.long 0x00 16. " OPAC3[0] ,Trusted Protect (TP) Control 3" "Allowed,Not allowed" textline " " bitfld.long 0x00 15. " OPAC4[3] ,Buffer Writes (BW) Control 4" "Disabled,Enabled" bitfld.long 0x00 14. " OPAC4[2] ,Supervisor Protect (SP) Control 4" "Not Required,Required" bitfld.long 0x00 13. " OPAC4[1] ,Write Protect (WP) Control 4" "Disabled,Enabled" bitfld.long 0x00 12. " OPAC4[0] ,Trusted Protect (TP) Control 4" "Allowed,Not allowed" textline " " bitfld.long 0x00 11. " OPAC5[3] ,Buffer Writes (BW) Control 5" "Disabled,Enabled" bitfld.long 0x00 10. " OPAC5[2] ,Supervisor Protect (SP) Control 5" "Not Required,Required" bitfld.long 0x00 9. " OPAC5[1] ,Write Protect (WP) Control 5" "Disabled,Enabled" bitfld.long 0x00 8. " OPAC5[0] ,Trusted Protect (TP) Control 5" "Allowed,Not allowed" textline " " bitfld.long 0x00 7. " OPAC6[3] ,Buffer Writes (BW) Control 6" "Disabled,Enabled" bitfld.long 0x00 6. " OPAC6[2] ,Supervisor Protect (SP) Control 6" "Not Required,Required" bitfld.long 0x00 5. " OPAC6[1] ,Write Protect (WP) Control 6" "Disabled,Enabled" bitfld.long 0x00 4. " OPAC6[0] ,Trusted Protect (TP) Control 6" "Allowed,Not allowed" textline " " bitfld.long 0x00 3. " OPAC7[3] ,Buffer Writes (BW) Control 7" "Disabled,Enabled" bitfld.long 0x00 2. " OPAC7[2] ,Supervisor Protect (SP) Control 7" "Not Required,Required" bitfld.long 0x00 1. " OPAC7[1] ,Write Protect (WP) Control 7" "Disabled,Enabled" bitfld.long 0x00 0. " OPAC7[0] ,Trusted Protect (TP) Control 7" "Allowed,Not allowed" line.long 0x04 "OPACR1,Off-Platform Peripheral Access Control Register" bitfld.long 0x04 31. " OPAC8[3] ,Buffer Writes (BW) Control 8" "Disabled,Enabled" bitfld.long 0x04 30. " OPAC8[2] ,Supervisor Protect (SP) Control 8" "Not Required,Required" bitfld.long 0x04 29. " OPAC8[1] ,Write Protect (WP) Control 8" "Disabled,Enabled" bitfld.long 0x04 28. " OPAC8[0] ,Trusted Protect (TP) Control 8" "Allowed,Not allowed" textline " " bitfld.long 0x04 27. " OPAC9[3] ,Buffer Writes (BW) Control 9" "Disabled,Enabled" bitfld.long 0x04 26. " OPAC9[2] ,Supervisor Protect (SP) Control 9" "Not Required,Required" bitfld.long 0x04 25. " OPAC9[1] ,Write Protect (WP) Control 9" "Disabled,Enabled" bitfld.long 0x04 24. " OPAC9[0] ,Trusted Protect (TP) Control 9" "Allowed,Not allowed" textline " " bitfld.long 0x04 23. " OPAC10[3] ,Buffer Writes (BW) Control 10" "Disabled,Enabled" bitfld.long 0x04 22. " OPAC10[2] ,Supervisor Protect (SP) Control 10" "Not Required,Required" bitfld.long 0x04 21. " OPAC10[1] ,Write Protect (WP) Control 10" "Disabled,Enabled" bitfld.long 0x04 20. " OPAC10[0] ,Trusted Protect (TP) Control 10" "Allowed,Not allowed" textline " " bitfld.long 0x04 19. " OPAC11[3] ,Buffer Writes (BW) Control 11" "Disabled,Enabled" bitfld.long 0x04 18. " OPAC11[2] ,Supervisor Protect (SP) Control 11" "Not Required,Required" bitfld.long 0x04 17. " OPAC11[1] ,Write Protect (WP) Control 11" "Disabled,Enabled" bitfld.long 0x04 16. " OPAC11[0] ,Trusted Protect (TP) Control 11" "Allowed,Not allowed" textline " " bitfld.long 0x04 15. " OPAC12[3] ,Buffer Writes (BW) Control 12" "Disabled,Enabled" bitfld.long 0x04 14. " OPAC12[2] ,Supervisor Protect (SP) Control 12" "Not Required,Required" bitfld.long 0x04 13. " OPAC12[1] ,Write Protect (WP) Control 12" "Disabled,Enabled" bitfld.long 0x04 12. " OPAC12[0] ,Trusted Protect (TP) Control 12" "Allowed,Not allowed" textline " " bitfld.long 0x04 11. " OPAC13[3] ,Buffer Writes (BW) Control 13" "Disabled,Enabled" bitfld.long 0x04 10. " OPAC13[2] ,Supervisor Protect (SP) Control 13" "Not Required,Required" bitfld.long 0x04 9. " OPAC13[1] ,Write Protect (WP) Control 13" "Disabled,Enabled" bitfld.long 0x04 8. " OPAC13[0] ,Trusted Protect (TP) Control 13" "Allowed,Not allowed" textline " " bitfld.long 0x04 7. " OPAC14[3] ,Buffer Writes (BW) Control 14" "Disabled,Enabled" bitfld.long 0x04 6. " OPAC14[2] ,Supervisor Protect (SP) Control 14" "Not Required,Required" bitfld.long 0x04 5. " OPAC14[1] ,Write Protect (WP) Control 14" "Disabled,Enabled" bitfld.long 0x04 4. " OPAC14[0] ,Trusted Protect (TP) Control 14" "Allowed,Not allowed" textline " " bitfld.long 0x04 3. " OPAC15[3] ,Buffer Writes (BW) Control 15" "Disabled,Enabled" bitfld.long 0x04 2. " OPAC15[2] ,Supervisor Protect (SP) Control 15" "Not Required,Required" bitfld.long 0x04 1. " OPAC15[1] ,Write Protect (WP) Control 15" "Disabled,Enabled" bitfld.long 0x04 0. " OPAC15[0] ,Trusted Protect (TP) Control 15" "Allowed,Not allowed" line.long 0x08 "OPACR2,Off-Platform Peripheral Access Control Register" bitfld.long 0x08 31. " OPAC16[3] ,Buffer Writes (BW) Control 16" "Disabled,Enabled" bitfld.long 0x08 30. " OPAC16[2] ,Supervisor Protect (SP) Control 16" "Not Required,Required" bitfld.long 0x08 29. " OPAC16[1] ,Write Protect (WP) Control 16" "Disabled,Enabled" bitfld.long 0x08 28. " OPAC16[0] ,Trusted Protect (TP) Control 16" "Allowed,Not allowed" textline " " bitfld.long 0x08 27. " OPAC17[3] ,Buffer Writes (BW) Control 17" "Disabled,Enabled" bitfld.long 0x08 26. " OPAC17[2] ,Supervisor Protect (SP) Control 17" "Not Required,Required" bitfld.long 0x08 25. " OPAC17[1] ,Write Protect (WP) Control 17" "Disabled,Enabled" bitfld.long 0x08 24. " OPAC17[0] ,Trusted Protect (TP) Control 17" "Allowed,Not allowed" textline " " bitfld.long 0x08 23. " OPAC18[3] ,Buffer Writes (BW) Control 18" "Disabled,Enabled" bitfld.long 0x08 22. " OPAC18[2] ,Supervisor Protect (SP) Control 18" "Not Required,Required" bitfld.long 0x08 21. " OPAC18[1] ,Write Protect (WP) Control 18" "Disabled,Enabled" bitfld.long 0x08 20. " OPAC18[0] ,Trusted Protect (TP) Control 18" "Allowed,Not allowed" textline " " bitfld.long 0x08 19. " OPAC19[3] ,Buffer Writes (BW) Control 19" "Disabled,Enabled" bitfld.long 0x08 18. " OPAC19[2] ,Supervisor Protect (SP) Control 19" "Not Required,Required" bitfld.long 0x08 17. " OPAC19[1] ,Write Protect (WP) Control 19" "Disabled,Enabled" bitfld.long 0x08 16. " OPAC19[0] ,Trusted Protect (TP) Control 19" "Allowed,Not allowed" textline " " bitfld.long 0x08 15. " OPAC20[3] ,Buffer Writes (BW) Control 20" "Disabled,Enabled" bitfld.long 0x08 14. " OPAC20[2] ,Supervisor Protect (SP) Control 20" "Not Required,Required" bitfld.long 0x08 13. " OPAC20[1] ,Write Protect (WP) Control 20" "Disabled,Enabled" bitfld.long 0x08 12. " OPAC20[0] ,Trusted Protect (TP) Control 20" "Allowed,Not allowed" textline " " bitfld.long 0x08 11. " OPAC21[3] ,Buffer Writes (BW) Control 21" "Disabled,Enabled" bitfld.long 0x08 10. " OPAC21[2] ,Supervisor Protect (SP) Control 21" "Not Required,Required" bitfld.long 0x08 9. " OPAC21[1] ,Write Protect (WP) Control 21" "Disabled,Enabled" bitfld.long 0x08 8. " OPAC21[0] ,Trusted Protect (TP) Control 21" "Allowed,Not allowed" textline " " bitfld.long 0x08 7. " OPAC22[3] ,Buffer Writes (BW) Control 22" "Disabled,Enabled" bitfld.long 0x08 6. " OPAC22[2] ,Supervisor Protect (SP) Control 22" "Not Required,Required" bitfld.long 0x08 5. " OPAC22[1] ,Write Protect (WP) Control 22" "Disabled,Enabled" bitfld.long 0x08 4. " OPAC22[0] ,Trusted Protect (TP) Control 22" "Allowed,Not allowed" textline " " bitfld.long 0x08 3. " OPAC23[3] ,Buffer Writes (BW) Control 23" "Disabled,Enabled" bitfld.long 0x08 2. " OPAC23[2] ,Supervisor Protect (SP) Control 23" "Not Required,Required" bitfld.long 0x08 1. " OPAC23[1] ,Write Protect (WP) Control 23" "Disabled,Enabled" bitfld.long 0x08 0. " OPAC23[0] ,Trusted Protect (TP) Control 23" "Allowed,Not allowed" line.long 0x0C "OPACR3,Off-Platform Peripheral Access Control Register" bitfld.long 0x0C 31. " OPAC24[3] ,Buffer Writes (BW) Control 24" "Disabled,Enabled" bitfld.long 0x0C 30. " OPAC24[2] ,Supervisor Protect (SP) Control 24" "Not Required,Required" bitfld.long 0x0C 29. " OPAC24[1] ,Write Protect (WP) Control 24" "Disabled,Enabled" bitfld.long 0x0C 28. " OPAC24[0] ,Trusted Protect (TP) Control 24" "Allowed,Not allowed" textline " " bitfld.long 0x0C 27. " OPAC25[3] ,Buffer Writes (BW) Control 25" "Disabled,Enabled" bitfld.long 0x0C 26. " OPAC25[2] ,Supervisor Protect (SP) Control 25" "Not Required,Required" bitfld.long 0x0C 25. " OPAC25[1] ,Write Protect (WP) Control 25" "Disabled,Enabled" bitfld.long 0x0C 24. " OPAC25[0] ,Trusted Protect (TP) Control 25" "Allowed,Not allowed" textline " " bitfld.long 0x0C 23. " OPAC26[3] ,Buffer Writes (BW) Control 26" "Disabled,Enabled" bitfld.long 0x0C 22. " OPAC26[2] ,Supervisor Protect (SP) Control 26" "Not Required,Required" bitfld.long 0x0C 21. " OPAC26[1] ,Write Protect (WP) Control 26" "Disabled,Enabled" bitfld.long 0x0C 20. " OPAC26[0] ,Trusted Protect (TP) Control 26" "Allowed,Not allowed" textline " " bitfld.long 0x0C 19. " OPAC27[3] ,Buffer Writes (BW) Control 27" "Disabled,Enabled" bitfld.long 0x0C 18. " OPAC27[2] ,Supervisor Protect (SP) Control 27" "Not Required,Required" bitfld.long 0x0C 17. " OPAC27[1] ,Write Protect (WP) Control 27" "Disabled,Enabled" bitfld.long 0x0C 16. " OPAC27[0] ,Trusted Protect (TP) Control 27" "Allowed,Not allowed" textline " " bitfld.long 0x0C 15. " OPAC28[3] ,Buffer Writes (BW) Control 28" "Disabled,Enabled" bitfld.long 0x0C 14. " OPAC28[2] ,Supervisor Protect (SP) Control 28" "Not Required,Required" bitfld.long 0x0C 13. " OPAC28[1] ,Write Protect (WP) Control 28" "Disabled,Enabled" bitfld.long 0x0C 12. " OPAC28[0] ,Trusted Protect (TP) Control 28" "Allowed,Not allowed" textline " " bitfld.long 0x0C 11. " OPAC29[3] ,Buffer Writes (BW) Control 29" "Disabled,Enabled" bitfld.long 0x0C 10. " OPAC29[2] ,Supervisor Protect (SP) Control 29" "Not Required,Required" bitfld.long 0x0C 9. " OPAC29[1] ,Write Protect (WP) Control 29" "Disabled,Enabled" bitfld.long 0x0C 8. " OPAC29[0] ,Trusted Protect (TP) Control 29" "Allowed,Not allowed" textline " " bitfld.long 0x0C 7. " OPAC30[3] ,Buffer Writes (BW) Control 30" "Disabled,Enabled" bitfld.long 0x0C 6. " OPAC30[2] ,Supervisor Protect (SP) Control 30" "Not Required,Required" bitfld.long 0x0C 5. " OPAC30[1] ,Write Protect (WP) Control 30" "Disabled,Enabled" bitfld.long 0x0C 4. " OPAC30[0] ,Trusted Protect (TP) Control 30" "Allowed,Not allowed" textline " " bitfld.long 0x0C 3. " OPAC31[3] ,Buffer Writes (BW) Control 31" "Disabled,Enabled" bitfld.long 0x0C 2. " OPAC31[2] ,Supervisor Protect (SP) Control 31" "Not Required,Required" bitfld.long 0x0C 1. " OPAC31[1] ,Write Protect (WP) Control 31" "Disabled,Enabled" bitfld.long 0x0C 0. " OPAC31[0] ,Trusted Protect (TP) Control 31" "Allowed,Not allowed" line.long 0x10 "OPACR4,Off-Platform Peripheral Access Control Register" bitfld.long 0x10 31. " OPAC32[3] ,Buffer Writes (BW) Control 32" "Disabled,Enabled" bitfld.long 0x10 30. " OPAC32[2] ,Supervisor Protect (SP) Control 32" "Not Required,Required" bitfld.long 0x10 29. " OPAC32[1] ,Write Protect (WP) Control 32" "Disabled,Enabled" bitfld.long 0x10 28. " OPAC32[0] ,Trusted Protect (TP) Control 32" "Allowed,Not allowed" textline " " bitfld.long 0x10 27. " OPAC33[3] ,Buffer Writes (BW) Control 33" "Disabled,Enabled" bitfld.long 0x10 26. " OPAC33[2] ,Supervisor Protect (SP) Control 33" "Not Required,Required" bitfld.long 0x10 25. " OPAC33[1] ,Write Protect (WP) Control 33" "Disabled,Enabled" bitfld.long 0x10 24. " OPAC33[0] ,Trusted Protect (TP) Control 33" "Allowed,Not allowed" width 0x0B tree.end tree "Channel 2" base ad:0x305f0000 width 8. group.long 0x00++0x03 line.long 0x00 "MPR,Master Privilege Register" bitfld.long 0x00 31. " MPROT0[3] ,Master 0 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 30. " MPROT0[2] ,Master 0 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 29. " MPROT0[1] ,Master 0 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 28. " MPROT0[0] ,Master 0 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 27. " MPROT1[3] ,Master 1 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 26. " MPROT1[2] ,Master 1 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 25. " MPROT1[1] ,Master 1 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 24. " MPROT1[0] ,Master 1 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 23. " MPROT2[3] ,Master 2 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 22. " MPROT2[2] ,Master 2 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 21. " MPROT2[1] ,Master 2 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 20. " MPROT2[0] ,Master 2 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 19. " MPROT3[3] ,Master 3 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 18. " MPROT3[2] ,Master 3 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 17. " MPROT3[1] ,Master 3 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 16. " MPROT3[0] ,Master 3 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 11. " MPROT5[3] ,Master 5 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 10. " MPROT5[2] ,Master 5 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 9. " MPROT5[1] ,Master 5 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 8. " MPROT5[0] ,Master 5 Privilege Level(MPL)" "Forced,Not forced" group.long 0x40++0x13 line.long 0x00 "OPACR0,Off-Platform Peripheral Access Control Register" bitfld.long 0x00 31. " OPAC0[3] ,Buffer Writes (BW) Control 0" "Disabled,Enabled" bitfld.long 0x00 30. " OPAC0[2] ,Supervisor Protect (SP) Control 0" "Not Required,Required" bitfld.long 0x00 29. " OPAC0[1] ,Write Protect (WP) Control 0" "Disabled,Enabled" bitfld.long 0x00 28. " OPAC0[0] ,Trusted Protect (TP) Control 0" "Allowed,Not allowed" textline " " bitfld.long 0x00 27. " OPAC1[3] ,Buffer Writes (BW) Control 1" "Disabled,Enabled" bitfld.long 0x00 26. " OPAC1[2] ,Supervisor Protect (SP) Control 1" "Not Required,Required" bitfld.long 0x00 25. " OPAC1[1] ,Write Protect (WP) Control 1" "Disabled,Enabled" bitfld.long 0x00 24. " OPAC1[0] ,Trusted Protect (TP) Control 1" "Allowed,Not allowed" textline " " bitfld.long 0x00 23. " OPAC2[3] ,Buffer Writes (BW) Control 2" "Disabled,Enabled" bitfld.long 0x00 22. " OPAC2[2] ,Supervisor Protect (SP) Control 2" "Not Required,Required" bitfld.long 0x00 21. " OPAC2[1] ,Write Protect (WP) Control 2" "Disabled,Enabled" bitfld.long 0x00 20. " OPAC2[0] ,Trusted Protect (TP) Control 2" "Allowed,Not allowed" textline " " bitfld.long 0x00 19. " OPAC3[3] ,Buffer Writes (BW) Control 3" "Disabled,Enabled" bitfld.long 0x00 18. " OPAC3[2] ,Supervisor Protect (SP) Control 3" "Not Required,Required" bitfld.long 0x00 17. " OPAC3[1] ,Write Protect (WP) Control 3" "Disabled,Enabled" bitfld.long 0x00 16. " OPAC3[0] ,Trusted Protect (TP) Control 3" "Allowed,Not allowed" textline " " bitfld.long 0x00 15. " OPAC4[3] ,Buffer Writes (BW) Control 4" "Disabled,Enabled" bitfld.long 0x00 14. " OPAC4[2] ,Supervisor Protect (SP) Control 4" "Not Required,Required" bitfld.long 0x00 13. " OPAC4[1] ,Write Protect (WP) Control 4" "Disabled,Enabled" bitfld.long 0x00 12. " OPAC4[0] ,Trusted Protect (TP) Control 4" "Allowed,Not allowed" textline " " bitfld.long 0x00 11. " OPAC5[3] ,Buffer Writes (BW) Control 5" "Disabled,Enabled" bitfld.long 0x00 10. " OPAC5[2] ,Supervisor Protect (SP) Control 5" "Not Required,Required" bitfld.long 0x00 9. " OPAC5[1] ,Write Protect (WP) Control 5" "Disabled,Enabled" bitfld.long 0x00 8. " OPAC5[0] ,Trusted Protect (TP) Control 5" "Allowed,Not allowed" textline " " bitfld.long 0x00 7. " OPAC6[3] ,Buffer Writes (BW) Control 6" "Disabled,Enabled" bitfld.long 0x00 6. " OPAC6[2] ,Supervisor Protect (SP) Control 6" "Not Required,Required" bitfld.long 0x00 5. " OPAC6[1] ,Write Protect (WP) Control 6" "Disabled,Enabled" bitfld.long 0x00 4. " OPAC6[0] ,Trusted Protect (TP) Control 6" "Allowed,Not allowed" textline " " bitfld.long 0x00 3. " OPAC7[3] ,Buffer Writes (BW) Control 7" "Disabled,Enabled" bitfld.long 0x00 2. " OPAC7[2] ,Supervisor Protect (SP) Control 7" "Not Required,Required" bitfld.long 0x00 1. " OPAC7[1] ,Write Protect (WP) Control 7" "Disabled,Enabled" bitfld.long 0x00 0. " OPAC7[0] ,Trusted Protect (TP) Control 7" "Allowed,Not allowed" line.long 0x04 "OPACR1,Off-Platform Peripheral Access Control Register" bitfld.long 0x04 31. " OPAC8[3] ,Buffer Writes (BW) Control 8" "Disabled,Enabled" bitfld.long 0x04 30. " OPAC8[2] ,Supervisor Protect (SP) Control 8" "Not Required,Required" bitfld.long 0x04 29. " OPAC8[1] ,Write Protect (WP) Control 8" "Disabled,Enabled" bitfld.long 0x04 28. " OPAC8[0] ,Trusted Protect (TP) Control 8" "Allowed,Not allowed" textline " " bitfld.long 0x04 27. " OPAC9[3] ,Buffer Writes (BW) Control 9" "Disabled,Enabled" bitfld.long 0x04 26. " OPAC9[2] ,Supervisor Protect (SP) Control 9" "Not Required,Required" bitfld.long 0x04 25. " OPAC9[1] ,Write Protect (WP) Control 9" "Disabled,Enabled" bitfld.long 0x04 24. " OPAC9[0] ,Trusted Protect (TP) Control 9" "Allowed,Not allowed" textline " " bitfld.long 0x04 23. " OPAC10[3] ,Buffer Writes (BW) Control 10" "Disabled,Enabled" bitfld.long 0x04 22. " OPAC10[2] ,Supervisor Protect (SP) Control 10" "Not Required,Required" bitfld.long 0x04 21. " OPAC10[1] ,Write Protect (WP) Control 10" "Disabled,Enabled" bitfld.long 0x04 20. " OPAC10[0] ,Trusted Protect (TP) Control 10" "Allowed,Not allowed" textline " " bitfld.long 0x04 19. " OPAC11[3] ,Buffer Writes (BW) Control 11" "Disabled,Enabled" bitfld.long 0x04 18. " OPAC11[2] ,Supervisor Protect (SP) Control 11" "Not Required,Required" bitfld.long 0x04 17. " OPAC11[1] ,Write Protect (WP) Control 11" "Disabled,Enabled" bitfld.long 0x04 16. " OPAC11[0] ,Trusted Protect (TP) Control 11" "Allowed,Not allowed" textline " " bitfld.long 0x04 15. " OPAC12[3] ,Buffer Writes (BW) Control 12" "Disabled,Enabled" bitfld.long 0x04 14. " OPAC12[2] ,Supervisor Protect (SP) Control 12" "Not Required,Required" bitfld.long 0x04 13. " OPAC12[1] ,Write Protect (WP) Control 12" "Disabled,Enabled" bitfld.long 0x04 12. " OPAC12[0] ,Trusted Protect (TP) Control 12" "Allowed,Not allowed" textline " " bitfld.long 0x04 11. " OPAC13[3] ,Buffer Writes (BW) Control 13" "Disabled,Enabled" bitfld.long 0x04 10. " OPAC13[2] ,Supervisor Protect (SP) Control 13" "Not Required,Required" bitfld.long 0x04 9. " OPAC13[1] ,Write Protect (WP) Control 13" "Disabled,Enabled" bitfld.long 0x04 8. " OPAC13[0] ,Trusted Protect (TP) Control 13" "Allowed,Not allowed" textline " " bitfld.long 0x04 7. " OPAC14[3] ,Buffer Writes (BW) Control 14" "Disabled,Enabled" bitfld.long 0x04 6. " OPAC14[2] ,Supervisor Protect (SP) Control 14" "Not Required,Required" bitfld.long 0x04 5. " OPAC14[1] ,Write Protect (WP) Control 14" "Disabled,Enabled" bitfld.long 0x04 4. " OPAC14[0] ,Trusted Protect (TP) Control 14" "Allowed,Not allowed" textline " " bitfld.long 0x04 3. " OPAC15[3] ,Buffer Writes (BW) Control 15" "Disabled,Enabled" bitfld.long 0x04 2. " OPAC15[2] ,Supervisor Protect (SP) Control 15" "Not Required,Required" bitfld.long 0x04 1. " OPAC15[1] ,Write Protect (WP) Control 15" "Disabled,Enabled" bitfld.long 0x04 0. " OPAC15[0] ,Trusted Protect (TP) Control 15" "Allowed,Not allowed" line.long 0x08 "OPACR2,Off-Platform Peripheral Access Control Register" bitfld.long 0x08 31. " OPAC16[3] ,Buffer Writes (BW) Control 16" "Disabled,Enabled" bitfld.long 0x08 30. " OPAC16[2] ,Supervisor Protect (SP) Control 16" "Not Required,Required" bitfld.long 0x08 29. " OPAC16[1] ,Write Protect (WP) Control 16" "Disabled,Enabled" bitfld.long 0x08 28. " OPAC16[0] ,Trusted Protect (TP) Control 16" "Allowed,Not allowed" textline " " bitfld.long 0x08 27. " OPAC17[3] ,Buffer Writes (BW) Control 17" "Disabled,Enabled" bitfld.long 0x08 26. " OPAC17[2] ,Supervisor Protect (SP) Control 17" "Not Required,Required" bitfld.long 0x08 25. " OPAC17[1] ,Write Protect (WP) Control 17" "Disabled,Enabled" bitfld.long 0x08 24. " OPAC17[0] ,Trusted Protect (TP) Control 17" "Allowed,Not allowed" textline " " bitfld.long 0x08 23. " OPAC18[3] ,Buffer Writes (BW) Control 18" "Disabled,Enabled" bitfld.long 0x08 22. " OPAC18[2] ,Supervisor Protect (SP) Control 18" "Not Required,Required" bitfld.long 0x08 21. " OPAC18[1] ,Write Protect (WP) Control 18" "Disabled,Enabled" bitfld.long 0x08 20. " OPAC18[0] ,Trusted Protect (TP) Control 18" "Allowed,Not allowed" textline " " bitfld.long 0x08 19. " OPAC19[3] ,Buffer Writes (BW) Control 19" "Disabled,Enabled" bitfld.long 0x08 18. " OPAC19[2] ,Supervisor Protect (SP) Control 19" "Not Required,Required" bitfld.long 0x08 17. " OPAC19[1] ,Write Protect (WP) Control 19" "Disabled,Enabled" bitfld.long 0x08 16. " OPAC19[0] ,Trusted Protect (TP) Control 19" "Allowed,Not allowed" textline " " bitfld.long 0x08 15. " OPAC20[3] ,Buffer Writes (BW) Control 20" "Disabled,Enabled" bitfld.long 0x08 14. " OPAC20[2] ,Supervisor Protect (SP) Control 20" "Not Required,Required" bitfld.long 0x08 13. " OPAC20[1] ,Write Protect (WP) Control 20" "Disabled,Enabled" bitfld.long 0x08 12. " OPAC20[0] ,Trusted Protect (TP) Control 20" "Allowed,Not allowed" textline " " bitfld.long 0x08 11. " OPAC21[3] ,Buffer Writes (BW) Control 21" "Disabled,Enabled" bitfld.long 0x08 10. " OPAC21[2] ,Supervisor Protect (SP) Control 21" "Not Required,Required" bitfld.long 0x08 9. " OPAC21[1] ,Write Protect (WP) Control 21" "Disabled,Enabled" bitfld.long 0x08 8. " OPAC21[0] ,Trusted Protect (TP) Control 21" "Allowed,Not allowed" textline " " bitfld.long 0x08 7. " OPAC22[3] ,Buffer Writes (BW) Control 22" "Disabled,Enabled" bitfld.long 0x08 6. " OPAC22[2] ,Supervisor Protect (SP) Control 22" "Not Required,Required" bitfld.long 0x08 5. " OPAC22[1] ,Write Protect (WP) Control 22" "Disabled,Enabled" bitfld.long 0x08 4. " OPAC22[0] ,Trusted Protect (TP) Control 22" "Allowed,Not allowed" textline " " bitfld.long 0x08 3. " OPAC23[3] ,Buffer Writes (BW) Control 23" "Disabled,Enabled" bitfld.long 0x08 2. " OPAC23[2] ,Supervisor Protect (SP) Control 23" "Not Required,Required" bitfld.long 0x08 1. " OPAC23[1] ,Write Protect (WP) Control 23" "Disabled,Enabled" bitfld.long 0x08 0. " OPAC23[0] ,Trusted Protect (TP) Control 23" "Allowed,Not allowed" line.long 0x0C "OPACR3,Off-Platform Peripheral Access Control Register" bitfld.long 0x0C 31. " OPAC24[3] ,Buffer Writes (BW) Control 24" "Disabled,Enabled" bitfld.long 0x0C 30. " OPAC24[2] ,Supervisor Protect (SP) Control 24" "Not Required,Required" bitfld.long 0x0C 29. " OPAC24[1] ,Write Protect (WP) Control 24" "Disabled,Enabled" bitfld.long 0x0C 28. " OPAC24[0] ,Trusted Protect (TP) Control 24" "Allowed,Not allowed" textline " " bitfld.long 0x0C 27. " OPAC25[3] ,Buffer Writes (BW) Control 25" "Disabled,Enabled" bitfld.long 0x0C 26. " OPAC25[2] ,Supervisor Protect (SP) Control 25" "Not Required,Required" bitfld.long 0x0C 25. " OPAC25[1] ,Write Protect (WP) Control 25" "Disabled,Enabled" bitfld.long 0x0C 24. " OPAC25[0] ,Trusted Protect (TP) Control 25" "Allowed,Not allowed" textline " " bitfld.long 0x0C 23. " OPAC26[3] ,Buffer Writes (BW) Control 26" "Disabled,Enabled" bitfld.long 0x0C 22. " OPAC26[2] ,Supervisor Protect (SP) Control 26" "Not Required,Required" bitfld.long 0x0C 21. " OPAC26[1] ,Write Protect (WP) Control 26" "Disabled,Enabled" bitfld.long 0x0C 20. " OPAC26[0] ,Trusted Protect (TP) Control 26" "Allowed,Not allowed" textline " " bitfld.long 0x0C 19. " OPAC27[3] ,Buffer Writes (BW) Control 27" "Disabled,Enabled" bitfld.long 0x0C 18. " OPAC27[2] ,Supervisor Protect (SP) Control 27" "Not Required,Required" bitfld.long 0x0C 17. " OPAC27[1] ,Write Protect (WP) Control 27" "Disabled,Enabled" bitfld.long 0x0C 16. " OPAC27[0] ,Trusted Protect (TP) Control 27" "Allowed,Not allowed" textline " " bitfld.long 0x0C 15. " OPAC28[3] ,Buffer Writes (BW) Control 28" "Disabled,Enabled" bitfld.long 0x0C 14. " OPAC28[2] ,Supervisor Protect (SP) Control 28" "Not Required,Required" bitfld.long 0x0C 13. " OPAC28[1] ,Write Protect (WP) Control 28" "Disabled,Enabled" bitfld.long 0x0C 12. " OPAC28[0] ,Trusted Protect (TP) Control 28" "Allowed,Not allowed" textline " " bitfld.long 0x0C 11. " OPAC29[3] ,Buffer Writes (BW) Control 29" "Disabled,Enabled" bitfld.long 0x0C 10. " OPAC29[2] ,Supervisor Protect (SP) Control 29" "Not Required,Required" bitfld.long 0x0C 9. " OPAC29[1] ,Write Protect (WP) Control 29" "Disabled,Enabled" bitfld.long 0x0C 8. " OPAC29[0] ,Trusted Protect (TP) Control 29" "Allowed,Not allowed" textline " " bitfld.long 0x0C 7. " OPAC30[3] ,Buffer Writes (BW) Control 30" "Disabled,Enabled" bitfld.long 0x0C 6. " OPAC30[2] ,Supervisor Protect (SP) Control 30" "Not Required,Required" bitfld.long 0x0C 5. " OPAC30[1] ,Write Protect (WP) Control 30" "Disabled,Enabled" bitfld.long 0x0C 4. " OPAC30[0] ,Trusted Protect (TP) Control 30" "Allowed,Not allowed" textline " " bitfld.long 0x0C 3. " OPAC31[3] ,Buffer Writes (BW) Control 31" "Disabled,Enabled" bitfld.long 0x0C 2. " OPAC31[2] ,Supervisor Protect (SP) Control 31" "Not Required,Required" bitfld.long 0x0C 1. " OPAC31[1] ,Write Protect (WP) Control 31" "Disabled,Enabled" bitfld.long 0x0C 0. " OPAC31[0] ,Trusted Protect (TP) Control 31" "Allowed,Not allowed" line.long 0x10 "OPACR4,Off-Platform Peripheral Access Control Register" bitfld.long 0x10 31. " OPAC32[3] ,Buffer Writes (BW) Control 32" "Disabled,Enabled" bitfld.long 0x10 30. " OPAC32[2] ,Supervisor Protect (SP) Control 32" "Not Required,Required" bitfld.long 0x10 29. " OPAC32[1] ,Write Protect (WP) Control 32" "Disabled,Enabled" bitfld.long 0x10 28. " OPAC32[0] ,Trusted Protect (TP) Control 32" "Allowed,Not allowed" textline " " bitfld.long 0x10 27. " OPAC33[3] ,Buffer Writes (BW) Control 33" "Disabled,Enabled" bitfld.long 0x10 26. " OPAC33[2] ,Supervisor Protect (SP) Control 33" "Not Required,Required" bitfld.long 0x10 25. " OPAC33[1] ,Write Protect (WP) Control 33" "Disabled,Enabled" bitfld.long 0x10 24. " OPAC33[0] ,Trusted Protect (TP) Control 33" "Allowed,Not allowed" width 0x0B tree.end tree "Channel 3" base ad:0x309f0000 width 8. group.long 0x00++0x03 line.long 0x00 "MPR,Master Privilege Register" bitfld.long 0x00 31. " MPROT0[3] ,Master 0 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 30. " MPROT0[2] ,Master 0 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 29. " MPROT0[1] ,Master 0 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 28. " MPROT0[0] ,Master 0 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 27. " MPROT1[3] ,Master 1 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 26. " MPROT1[2] ,Master 1 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 25. " MPROT1[1] ,Master 1 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 24. " MPROT1[0] ,Master 1 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 23. " MPROT2[3] ,Master 2 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 22. " MPROT2[2] ,Master 2 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 21. " MPROT2[1] ,Master 2 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 20. " MPROT2[0] ,Master 2 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 19. " MPROT3[3] ,Master 3 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 18. " MPROT3[2] ,Master 3 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 17. " MPROT3[1] ,Master 3 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 16. " MPROT3[0] ,Master 3 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 11. " MPROT5[3] ,Master 5 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 10. " MPROT5[2] ,Master 5 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 9. " MPROT5[1] ,Master 5 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 8. " MPROT5[0] ,Master 5 Privilege Level(MPL)" "Forced,Not forced" group.long 0x40++0x13 line.long 0x00 "OPACR0,Off-Platform Peripheral Access Control Register" bitfld.long 0x00 31. " OPAC0[3] ,Buffer Writes (BW) Control 0" "Disabled,Enabled" bitfld.long 0x00 30. " OPAC0[2] ,Supervisor Protect (SP) Control 0" "Not Required,Required" bitfld.long 0x00 29. " OPAC0[1] ,Write Protect (WP) Control 0" "Disabled,Enabled" bitfld.long 0x00 28. " OPAC0[0] ,Trusted Protect (TP) Control 0" "Allowed,Not allowed" textline " " bitfld.long 0x00 27. " OPAC1[3] ,Buffer Writes (BW) Control 1" "Disabled,Enabled" bitfld.long 0x00 26. " OPAC1[2] ,Supervisor Protect (SP) Control 1" "Not Required,Required" bitfld.long 0x00 25. " OPAC1[1] ,Write Protect (WP) Control 1" "Disabled,Enabled" bitfld.long 0x00 24. " OPAC1[0] ,Trusted Protect (TP) Control 1" "Allowed,Not allowed" textline " " bitfld.long 0x00 23. " OPAC2[3] ,Buffer Writes (BW) Control 2" "Disabled,Enabled" bitfld.long 0x00 22. " OPAC2[2] ,Supervisor Protect (SP) Control 2" "Not Required,Required" bitfld.long 0x00 21. " OPAC2[1] ,Write Protect (WP) Control 2" "Disabled,Enabled" bitfld.long 0x00 20. " OPAC2[0] ,Trusted Protect (TP) Control 2" "Allowed,Not allowed" textline " " bitfld.long 0x00 19. " OPAC3[3] ,Buffer Writes (BW) Control 3" "Disabled,Enabled" bitfld.long 0x00 18. " OPAC3[2] ,Supervisor Protect (SP) Control 3" "Not Required,Required" bitfld.long 0x00 17. " OPAC3[1] ,Write Protect (WP) Control 3" "Disabled,Enabled" bitfld.long 0x00 16. " OPAC3[0] ,Trusted Protect (TP) Control 3" "Allowed,Not allowed" textline " " bitfld.long 0x00 15. " OPAC4[3] ,Buffer Writes (BW) Control 4" "Disabled,Enabled" bitfld.long 0x00 14. " OPAC4[2] ,Supervisor Protect (SP) Control 4" "Not Required,Required" bitfld.long 0x00 13. " OPAC4[1] ,Write Protect (WP) Control 4" "Disabled,Enabled" bitfld.long 0x00 12. " OPAC4[0] ,Trusted Protect (TP) Control 4" "Allowed,Not allowed" textline " " bitfld.long 0x00 11. " OPAC5[3] ,Buffer Writes (BW) Control 5" "Disabled,Enabled" bitfld.long 0x00 10. " OPAC5[2] ,Supervisor Protect (SP) Control 5" "Not Required,Required" bitfld.long 0x00 9. " OPAC5[1] ,Write Protect (WP) Control 5" "Disabled,Enabled" bitfld.long 0x00 8. " OPAC5[0] ,Trusted Protect (TP) Control 5" "Allowed,Not allowed" textline " " bitfld.long 0x00 7. " OPAC6[3] ,Buffer Writes (BW) Control 6" "Disabled,Enabled" bitfld.long 0x00 6. " OPAC6[2] ,Supervisor Protect (SP) Control 6" "Not Required,Required" bitfld.long 0x00 5. " OPAC6[1] ,Write Protect (WP) Control 6" "Disabled,Enabled" bitfld.long 0x00 4. " OPAC6[0] ,Trusted Protect (TP) Control 6" "Allowed,Not allowed" textline " " bitfld.long 0x00 3. " OPAC7[3] ,Buffer Writes (BW) Control 7" "Disabled,Enabled" bitfld.long 0x00 2. " OPAC7[2] ,Supervisor Protect (SP) Control 7" "Not Required,Required" bitfld.long 0x00 1. " OPAC7[1] ,Write Protect (WP) Control 7" "Disabled,Enabled" bitfld.long 0x00 0. " OPAC7[0] ,Trusted Protect (TP) Control 7" "Allowed,Not allowed" line.long 0x04 "OPACR1,Off-Platform Peripheral Access Control Register" bitfld.long 0x04 31. " OPAC8[3] ,Buffer Writes (BW) Control 8" "Disabled,Enabled" bitfld.long 0x04 30. " OPAC8[2] ,Supervisor Protect (SP) Control 8" "Not Required,Required" bitfld.long 0x04 29. " OPAC8[1] ,Write Protect (WP) Control 8" "Disabled,Enabled" bitfld.long 0x04 28. " OPAC8[0] ,Trusted Protect (TP) Control 8" "Allowed,Not allowed" textline " " bitfld.long 0x04 27. " OPAC9[3] ,Buffer Writes (BW) Control 9" "Disabled,Enabled" bitfld.long 0x04 26. " OPAC9[2] ,Supervisor Protect (SP) Control 9" "Not Required,Required" bitfld.long 0x04 25. " OPAC9[1] ,Write Protect (WP) Control 9" "Disabled,Enabled" bitfld.long 0x04 24. " OPAC9[0] ,Trusted Protect (TP) Control 9" "Allowed,Not allowed" textline " " bitfld.long 0x04 23. " OPAC10[3] ,Buffer Writes (BW) Control 10" "Disabled,Enabled" bitfld.long 0x04 22. " OPAC10[2] ,Supervisor Protect (SP) Control 10" "Not Required,Required" bitfld.long 0x04 21. " OPAC10[1] ,Write Protect (WP) Control 10" "Disabled,Enabled" bitfld.long 0x04 20. " OPAC10[0] ,Trusted Protect (TP) Control 10" "Allowed,Not allowed" textline " " bitfld.long 0x04 19. " OPAC11[3] ,Buffer Writes (BW) Control 11" "Disabled,Enabled" bitfld.long 0x04 18. " OPAC11[2] ,Supervisor Protect (SP) Control 11" "Not Required,Required" bitfld.long 0x04 17. " OPAC11[1] ,Write Protect (WP) Control 11" "Disabled,Enabled" bitfld.long 0x04 16. " OPAC11[0] ,Trusted Protect (TP) Control 11" "Allowed,Not allowed" textline " " bitfld.long 0x04 15. " OPAC12[3] ,Buffer Writes (BW) Control 12" "Disabled,Enabled" bitfld.long 0x04 14. " OPAC12[2] ,Supervisor Protect (SP) Control 12" "Not Required,Required" bitfld.long 0x04 13. " OPAC12[1] ,Write Protect (WP) Control 12" "Disabled,Enabled" bitfld.long 0x04 12. " OPAC12[0] ,Trusted Protect (TP) Control 12" "Allowed,Not allowed" textline " " bitfld.long 0x04 11. " OPAC13[3] ,Buffer Writes (BW) Control 13" "Disabled,Enabled" bitfld.long 0x04 10. " OPAC13[2] ,Supervisor Protect (SP) Control 13" "Not Required,Required" bitfld.long 0x04 9. " OPAC13[1] ,Write Protect (WP) Control 13" "Disabled,Enabled" bitfld.long 0x04 8. " OPAC13[0] ,Trusted Protect (TP) Control 13" "Allowed,Not allowed" textline " " bitfld.long 0x04 7. " OPAC14[3] ,Buffer Writes (BW) Control 14" "Disabled,Enabled" bitfld.long 0x04 6. " OPAC14[2] ,Supervisor Protect (SP) Control 14" "Not Required,Required" bitfld.long 0x04 5. " OPAC14[1] ,Write Protect (WP) Control 14" "Disabled,Enabled" bitfld.long 0x04 4. " OPAC14[0] ,Trusted Protect (TP) Control 14" "Allowed,Not allowed" textline " " bitfld.long 0x04 3. " OPAC15[3] ,Buffer Writes (BW) Control 15" "Disabled,Enabled" bitfld.long 0x04 2. " OPAC15[2] ,Supervisor Protect (SP) Control 15" "Not Required,Required" bitfld.long 0x04 1. " OPAC15[1] ,Write Protect (WP) Control 15" "Disabled,Enabled" bitfld.long 0x04 0. " OPAC15[0] ,Trusted Protect (TP) Control 15" "Allowed,Not allowed" line.long 0x08 "OPACR2,Off-Platform Peripheral Access Control Register" bitfld.long 0x08 31. " OPAC16[3] ,Buffer Writes (BW) Control 16" "Disabled,Enabled" bitfld.long 0x08 30. " OPAC16[2] ,Supervisor Protect (SP) Control 16" "Not Required,Required" bitfld.long 0x08 29. " OPAC16[1] ,Write Protect (WP) Control 16" "Disabled,Enabled" bitfld.long 0x08 28. " OPAC16[0] ,Trusted Protect (TP) Control 16" "Allowed,Not allowed" textline " " bitfld.long 0x08 27. " OPAC17[3] ,Buffer Writes (BW) Control 17" "Disabled,Enabled" bitfld.long 0x08 26. " OPAC17[2] ,Supervisor Protect (SP) Control 17" "Not Required,Required" bitfld.long 0x08 25. " OPAC17[1] ,Write Protect (WP) Control 17" "Disabled,Enabled" bitfld.long 0x08 24. " OPAC17[0] ,Trusted Protect (TP) Control 17" "Allowed,Not allowed" textline " " bitfld.long 0x08 23. " OPAC18[3] ,Buffer Writes (BW) Control 18" "Disabled,Enabled" bitfld.long 0x08 22. " OPAC18[2] ,Supervisor Protect (SP) Control 18" "Not Required,Required" bitfld.long 0x08 21. " OPAC18[1] ,Write Protect (WP) Control 18" "Disabled,Enabled" bitfld.long 0x08 20. " OPAC18[0] ,Trusted Protect (TP) Control 18" "Allowed,Not allowed" textline " " bitfld.long 0x08 19. " OPAC19[3] ,Buffer Writes (BW) Control 19" "Disabled,Enabled" bitfld.long 0x08 18. " OPAC19[2] ,Supervisor Protect (SP) Control 19" "Not Required,Required" bitfld.long 0x08 17. " OPAC19[1] ,Write Protect (WP) Control 19" "Disabled,Enabled" bitfld.long 0x08 16. " OPAC19[0] ,Trusted Protect (TP) Control 19" "Allowed,Not allowed" textline " " bitfld.long 0x08 15. " OPAC20[3] ,Buffer Writes (BW) Control 20" "Disabled,Enabled" bitfld.long 0x08 14. " OPAC20[2] ,Supervisor Protect (SP) Control 20" "Not Required,Required" bitfld.long 0x08 13. " OPAC20[1] ,Write Protect (WP) Control 20" "Disabled,Enabled" bitfld.long 0x08 12. " OPAC20[0] ,Trusted Protect (TP) Control 20" "Allowed,Not allowed" textline " " bitfld.long 0x08 11. " OPAC21[3] ,Buffer Writes (BW) Control 21" "Disabled,Enabled" bitfld.long 0x08 10. " OPAC21[2] ,Supervisor Protect (SP) Control 21" "Not Required,Required" bitfld.long 0x08 9. " OPAC21[1] ,Write Protect (WP) Control 21" "Disabled,Enabled" bitfld.long 0x08 8. " OPAC21[0] ,Trusted Protect (TP) Control 21" "Allowed,Not allowed" textline " " bitfld.long 0x08 7. " OPAC22[3] ,Buffer Writes (BW) Control 22" "Disabled,Enabled" bitfld.long 0x08 6. " OPAC22[2] ,Supervisor Protect (SP) Control 22" "Not Required,Required" bitfld.long 0x08 5. " OPAC22[1] ,Write Protect (WP) Control 22" "Disabled,Enabled" bitfld.long 0x08 4. " OPAC22[0] ,Trusted Protect (TP) Control 22" "Allowed,Not allowed" textline " " bitfld.long 0x08 3. " OPAC23[3] ,Buffer Writes (BW) Control 23" "Disabled,Enabled" bitfld.long 0x08 2. " OPAC23[2] ,Supervisor Protect (SP) Control 23" "Not Required,Required" bitfld.long 0x08 1. " OPAC23[1] ,Write Protect (WP) Control 23" "Disabled,Enabled" bitfld.long 0x08 0. " OPAC23[0] ,Trusted Protect (TP) Control 23" "Allowed,Not allowed" line.long 0x0C "OPACR3,Off-Platform Peripheral Access Control Register" bitfld.long 0x0C 31. " OPAC24[3] ,Buffer Writes (BW) Control 24" "Disabled,Enabled" bitfld.long 0x0C 30. " OPAC24[2] ,Supervisor Protect (SP) Control 24" "Not Required,Required" bitfld.long 0x0C 29. " OPAC24[1] ,Write Protect (WP) Control 24" "Disabled,Enabled" bitfld.long 0x0C 28. " OPAC24[0] ,Trusted Protect (TP) Control 24" "Allowed,Not allowed" textline " " bitfld.long 0x0C 27. " OPAC25[3] ,Buffer Writes (BW) Control 25" "Disabled,Enabled" bitfld.long 0x0C 26. " OPAC25[2] ,Supervisor Protect (SP) Control 25" "Not Required,Required" bitfld.long 0x0C 25. " OPAC25[1] ,Write Protect (WP) Control 25" "Disabled,Enabled" bitfld.long 0x0C 24. " OPAC25[0] ,Trusted Protect (TP) Control 25" "Allowed,Not allowed" textline " " bitfld.long 0x0C 23. " OPAC26[3] ,Buffer Writes (BW) Control 26" "Disabled,Enabled" bitfld.long 0x0C 22. " OPAC26[2] ,Supervisor Protect (SP) Control 26" "Not Required,Required" bitfld.long 0x0C 21. " OPAC26[1] ,Write Protect (WP) Control 26" "Disabled,Enabled" bitfld.long 0x0C 20. " OPAC26[0] ,Trusted Protect (TP) Control 26" "Allowed,Not allowed" textline " " bitfld.long 0x0C 19. " OPAC27[3] ,Buffer Writes (BW) Control 27" "Disabled,Enabled" bitfld.long 0x0C 18. " OPAC27[2] ,Supervisor Protect (SP) Control 27" "Not Required,Required" bitfld.long 0x0C 17. " OPAC27[1] ,Write Protect (WP) Control 27" "Disabled,Enabled" bitfld.long 0x0C 16. " OPAC27[0] ,Trusted Protect (TP) Control 27" "Allowed,Not allowed" textline " " bitfld.long 0x0C 15. " OPAC28[3] ,Buffer Writes (BW) Control 28" "Disabled,Enabled" bitfld.long 0x0C 14. " OPAC28[2] ,Supervisor Protect (SP) Control 28" "Not Required,Required" bitfld.long 0x0C 13. " OPAC28[1] ,Write Protect (WP) Control 28" "Disabled,Enabled" bitfld.long 0x0C 12. " OPAC28[0] ,Trusted Protect (TP) Control 28" "Allowed,Not allowed" textline " " bitfld.long 0x0C 11. " OPAC29[3] ,Buffer Writes (BW) Control 29" "Disabled,Enabled" bitfld.long 0x0C 10. " OPAC29[2] ,Supervisor Protect (SP) Control 29" "Not Required,Required" bitfld.long 0x0C 9. " OPAC29[1] ,Write Protect (WP) Control 29" "Disabled,Enabled" bitfld.long 0x0C 8. " OPAC29[0] ,Trusted Protect (TP) Control 29" "Allowed,Not allowed" textline " " bitfld.long 0x0C 7. " OPAC30[3] ,Buffer Writes (BW) Control 30" "Disabled,Enabled" bitfld.long 0x0C 6. " OPAC30[2] ,Supervisor Protect (SP) Control 30" "Not Required,Required" bitfld.long 0x0C 5. " OPAC30[1] ,Write Protect (WP) Control 30" "Disabled,Enabled" bitfld.long 0x0C 4. " OPAC30[0] ,Trusted Protect (TP) Control 30" "Allowed,Not allowed" textline " " bitfld.long 0x0C 3. " OPAC31[3] ,Buffer Writes (BW) Control 31" "Disabled,Enabled" bitfld.long 0x0C 2. " OPAC31[2] ,Supervisor Protect (SP) Control 31" "Not Required,Required" bitfld.long 0x0C 1. " OPAC31[1] ,Write Protect (WP) Control 31" "Disabled,Enabled" bitfld.long 0x0C 0. " OPAC31[0] ,Trusted Protect (TP) Control 31" "Allowed,Not allowed" line.long 0x10 "OPACR4,Off-Platform Peripheral Access Control Register" bitfld.long 0x10 31. " OPAC32[3] ,Buffer Writes (BW) Control 32" "Disabled,Enabled" bitfld.long 0x10 30. " OPAC32[2] ,Supervisor Protect (SP) Control 32" "Not Required,Required" bitfld.long 0x10 29. " OPAC32[1] ,Write Protect (WP) Control 32" "Disabled,Enabled" bitfld.long 0x10 28. " OPAC32[0] ,Trusted Protect (TP) Control 32" "Allowed,Not allowed" textline " " bitfld.long 0x10 27. " OPAC33[3] ,Buffer Writes (BW) Control 33" "Disabled,Enabled" bitfld.long 0x10 26. " OPAC33[2] ,Supervisor Protect (SP) Control 33" "Not Required,Required" bitfld.long 0x10 25. " OPAC33[1] ,Write Protect (WP) Control 33" "Disabled,Enabled" bitfld.long 0x10 24. " OPAC33[0] ,Trusted Protect (TP) Control 33" "Allowed,Not allowed" width 0x0B tree.end tree "Channel 4" base ad:0x32df0000 width 8. group.long 0x00++0x03 line.long 0x00 "MPR,Master Privilege Register" bitfld.long 0x00 31. " MPROT0[3] ,Master 0 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 30. " MPROT0[2] ,Master 0 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 29. " MPROT0[1] ,Master 0 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 28. " MPROT0[0] ,Master 0 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 27. " MPROT1[3] ,Master 1 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 26. " MPROT1[2] ,Master 1 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 25. " MPROT1[1] ,Master 1 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 24. " MPROT1[0] ,Master 1 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 23. " MPROT2[3] ,Master 2 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 22. " MPROT2[2] ,Master 2 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 21. " MPROT2[1] ,Master 2 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 20. " MPROT2[0] ,Master 2 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 19. " MPROT3[3] ,Master 3 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 18. " MPROT3[2] ,Master 3 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 17. " MPROT3[1] ,Master 3 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 16. " MPROT3[0] ,Master 3 Privilege Level(MPL)" "Forced,Not forced" textline " " bitfld.long 0x00 11. " MPROT5[3] ,Master 5 Buffer Writes(MBW)" "Disabled,Enabled" bitfld.long 0x00 10. " MPROT5[2] ,Master 5 Trusted for Reads(MTR)" "Not trusted,Trusted" bitfld.long 0x00 9. " MPROT5[1] ,Master 5 Trusted for Writes(MTW)" "Not trusted,Trusted" bitfld.long 0x00 8. " MPROT5[0] ,Master 5 Privilege Level(MPL)" "Forced,Not forced" group.long 0x40++0x13 line.long 0x00 "OPACR0,Off-Platform Peripheral Access Control Register" bitfld.long 0x00 31. " OPAC0[3] ,Buffer Writes (BW) Control 0" "Disabled,Enabled" bitfld.long 0x00 30. " OPAC0[2] ,Supervisor Protect (SP) Control 0" "Not Required,Required" bitfld.long 0x00 29. " OPAC0[1] ,Write Protect (WP) Control 0" "Disabled,Enabled" bitfld.long 0x00 28. " OPAC0[0] ,Trusted Protect (TP) Control 0" "Allowed,Not allowed" textline " " bitfld.long 0x00 27. " OPAC1[3] ,Buffer Writes (BW) Control 1" "Disabled,Enabled" bitfld.long 0x00 26. " OPAC1[2] ,Supervisor Protect (SP) Control 1" "Not Required,Required" bitfld.long 0x00 25. " OPAC1[1] ,Write Protect (WP) Control 1" "Disabled,Enabled" bitfld.long 0x00 24. " OPAC1[0] ,Trusted Protect (TP) Control 1" "Allowed,Not allowed" textline " " bitfld.long 0x00 23. " OPAC2[3] ,Buffer Writes (BW) Control 2" "Disabled,Enabled" bitfld.long 0x00 22. " OPAC2[2] ,Supervisor Protect (SP) Control 2" "Not Required,Required" bitfld.long 0x00 21. " OPAC2[1] ,Write Protect (WP) Control 2" "Disabled,Enabled" bitfld.long 0x00 20. " OPAC2[0] ,Trusted Protect (TP) Control 2" "Allowed,Not allowed" textline " " bitfld.long 0x00 19. " OPAC3[3] ,Buffer Writes (BW) Control 3" "Disabled,Enabled" bitfld.long 0x00 18. " OPAC3[2] ,Supervisor Protect (SP) Control 3" "Not Required,Required" bitfld.long 0x00 17. " OPAC3[1] ,Write Protect (WP) Control 3" "Disabled,Enabled" bitfld.long 0x00 16. " OPAC3[0] ,Trusted Protect (TP) Control 3" "Allowed,Not allowed" textline " " bitfld.long 0x00 15. " OPAC4[3] ,Buffer Writes (BW) Control 4" "Disabled,Enabled" bitfld.long 0x00 14. " OPAC4[2] ,Supervisor Protect (SP) Control 4" "Not Required,Required" bitfld.long 0x00 13. " OPAC4[1] ,Write Protect (WP) Control 4" "Disabled,Enabled" bitfld.long 0x00 12. " OPAC4[0] ,Trusted Protect (TP) Control 4" "Allowed,Not allowed" textline " " bitfld.long 0x00 11. " OPAC5[3] ,Buffer Writes (BW) Control 5" "Disabled,Enabled" bitfld.long 0x00 10. " OPAC5[2] ,Supervisor Protect (SP) Control 5" "Not Required,Required" bitfld.long 0x00 9. " OPAC5[1] ,Write Protect (WP) Control 5" "Disabled,Enabled" bitfld.long 0x00 8. " OPAC5[0] ,Trusted Protect (TP) Control 5" "Allowed,Not allowed" textline " " bitfld.long 0x00 7. " OPAC6[3] ,Buffer Writes (BW) Control 6" "Disabled,Enabled" bitfld.long 0x00 6. " OPAC6[2] ,Supervisor Protect (SP) Control 6" "Not Required,Required" bitfld.long 0x00 5. " OPAC6[1] ,Write Protect (WP) Control 6" "Disabled,Enabled" bitfld.long 0x00 4. " OPAC6[0] ,Trusted Protect (TP) Control 6" "Allowed,Not allowed" textline " " bitfld.long 0x00 3. " OPAC7[3] ,Buffer Writes (BW) Control 7" "Disabled,Enabled" bitfld.long 0x00 2. " OPAC7[2] ,Supervisor Protect (SP) Control 7" "Not Required,Required" bitfld.long 0x00 1. " OPAC7[1] ,Write Protect (WP) Control 7" "Disabled,Enabled" bitfld.long 0x00 0. " OPAC7[0] ,Trusted Protect (TP) Control 7" "Allowed,Not allowed" line.long 0x04 "OPACR1,Off-Platform Peripheral Access Control Register" bitfld.long 0x04 31. " OPAC8[3] ,Buffer Writes (BW) Control 8" "Disabled,Enabled" bitfld.long 0x04 30. " OPAC8[2] ,Supervisor Protect (SP) Control 8" "Not Required,Required" bitfld.long 0x04 29. " OPAC8[1] ,Write Protect (WP) Control 8" "Disabled,Enabled" bitfld.long 0x04 28. " OPAC8[0] ,Trusted Protect (TP) Control 8" "Allowed,Not allowed" textline " " bitfld.long 0x04 27. " OPAC9[3] ,Buffer Writes (BW) Control 9" "Disabled,Enabled" bitfld.long 0x04 26. " OPAC9[2] ,Supervisor Protect (SP) Control 9" "Not Required,Required" bitfld.long 0x04 25. " OPAC9[1] ,Write Protect (WP) Control 9" "Disabled,Enabled" bitfld.long 0x04 24. " OPAC9[0] ,Trusted Protect (TP) Control 9" "Allowed,Not allowed" textline " " bitfld.long 0x04 23. " OPAC10[3] ,Buffer Writes (BW) Control 10" "Disabled,Enabled" bitfld.long 0x04 22. " OPAC10[2] ,Supervisor Protect (SP) Control 10" "Not Required,Required" bitfld.long 0x04 21. " OPAC10[1] ,Write Protect (WP) Control 10" "Disabled,Enabled" bitfld.long 0x04 20. " OPAC10[0] ,Trusted Protect (TP) Control 10" "Allowed,Not allowed" textline " " bitfld.long 0x04 19. " OPAC11[3] ,Buffer Writes (BW) Control 11" "Disabled,Enabled" bitfld.long 0x04 18. " OPAC11[2] ,Supervisor Protect (SP) Control 11" "Not Required,Required" bitfld.long 0x04 17. " OPAC11[1] ,Write Protect (WP) Control 11" "Disabled,Enabled" bitfld.long 0x04 16. " OPAC11[0] ,Trusted Protect (TP) Control 11" "Allowed,Not allowed" textline " " bitfld.long 0x04 15. " OPAC12[3] ,Buffer Writes (BW) Control 12" "Disabled,Enabled" bitfld.long 0x04 14. " OPAC12[2] ,Supervisor Protect (SP) Control 12" "Not Required,Required" bitfld.long 0x04 13. " OPAC12[1] ,Write Protect (WP) Control 12" "Disabled,Enabled" bitfld.long 0x04 12. " OPAC12[0] ,Trusted Protect (TP) Control 12" "Allowed,Not allowed" textline " " bitfld.long 0x04 11. " OPAC13[3] ,Buffer Writes (BW) Control 13" "Disabled,Enabled" bitfld.long 0x04 10. " OPAC13[2] ,Supervisor Protect (SP) Control 13" "Not Required,Required" bitfld.long 0x04 9. " OPAC13[1] ,Write Protect (WP) Control 13" "Disabled,Enabled" bitfld.long 0x04 8. " OPAC13[0] ,Trusted Protect (TP) Control 13" "Allowed,Not allowed" textline " " bitfld.long 0x04 7. " OPAC14[3] ,Buffer Writes (BW) Control 14" "Disabled,Enabled" bitfld.long 0x04 6. " OPAC14[2] ,Supervisor Protect (SP) Control 14" "Not Required,Required" bitfld.long 0x04 5. " OPAC14[1] ,Write Protect (WP) Control 14" "Disabled,Enabled" bitfld.long 0x04 4. " OPAC14[0] ,Trusted Protect (TP) Control 14" "Allowed,Not allowed" textline " " bitfld.long 0x04 3. " OPAC15[3] ,Buffer Writes (BW) Control 15" "Disabled,Enabled" bitfld.long 0x04 2. " OPAC15[2] ,Supervisor Protect (SP) Control 15" "Not Required,Required" bitfld.long 0x04 1. " OPAC15[1] ,Write Protect (WP) Control 15" "Disabled,Enabled" bitfld.long 0x04 0. " OPAC15[0] ,Trusted Protect (TP) Control 15" "Allowed,Not allowed" line.long 0x08 "OPACR2,Off-Platform Peripheral Access Control Register" bitfld.long 0x08 31. " OPAC16[3] ,Buffer Writes (BW) Control 16" "Disabled,Enabled" bitfld.long 0x08 30. " OPAC16[2] ,Supervisor Protect (SP) Control 16" "Not Required,Required" bitfld.long 0x08 29. " OPAC16[1] ,Write Protect (WP) Control 16" "Disabled,Enabled" bitfld.long 0x08 28. " OPAC16[0] ,Trusted Protect (TP) Control 16" "Allowed,Not allowed" textline " " bitfld.long 0x08 27. " OPAC17[3] ,Buffer Writes (BW) Control 17" "Disabled,Enabled" bitfld.long 0x08 26. " OPAC17[2] ,Supervisor Protect (SP) Control 17" "Not Required,Required" bitfld.long 0x08 25. " OPAC17[1] ,Write Protect (WP) Control 17" "Disabled,Enabled" bitfld.long 0x08 24. " OPAC17[0] ,Trusted Protect (TP) Control 17" "Allowed,Not allowed" textline " " bitfld.long 0x08 23. " OPAC18[3] ,Buffer Writes (BW) Control 18" "Disabled,Enabled" bitfld.long 0x08 22. " OPAC18[2] ,Supervisor Protect (SP) Control 18" "Not Required,Required" bitfld.long 0x08 21. " OPAC18[1] ,Write Protect (WP) Control 18" "Disabled,Enabled" bitfld.long 0x08 20. " OPAC18[0] ,Trusted Protect (TP) Control 18" "Allowed,Not allowed" textline " " bitfld.long 0x08 19. " OPAC19[3] ,Buffer Writes (BW) Control 19" "Disabled,Enabled" bitfld.long 0x08 18. " OPAC19[2] ,Supervisor Protect (SP) Control 19" "Not Required,Required" bitfld.long 0x08 17. " OPAC19[1] ,Write Protect (WP) Control 19" "Disabled,Enabled" bitfld.long 0x08 16. " OPAC19[0] ,Trusted Protect (TP) Control 19" "Allowed,Not allowed" textline " " bitfld.long 0x08 15. " OPAC20[3] ,Buffer Writes (BW) Control 20" "Disabled,Enabled" bitfld.long 0x08 14. " OPAC20[2] ,Supervisor Protect (SP) Control 20" "Not Required,Required" bitfld.long 0x08 13. " OPAC20[1] ,Write Protect (WP) Control 20" "Disabled,Enabled" bitfld.long 0x08 12. " OPAC20[0] ,Trusted Protect (TP) Control 20" "Allowed,Not allowed" textline " " bitfld.long 0x08 11. " OPAC21[3] ,Buffer Writes (BW) Control 21" "Disabled,Enabled" bitfld.long 0x08 10. " OPAC21[2] ,Supervisor Protect (SP) Control 21" "Not Required,Required" bitfld.long 0x08 9. " OPAC21[1] ,Write Protect (WP) Control 21" "Disabled,Enabled" bitfld.long 0x08 8. " OPAC21[0] ,Trusted Protect (TP) Control 21" "Allowed,Not allowed" textline " " bitfld.long 0x08 7. " OPAC22[3] ,Buffer Writes (BW) Control 22" "Disabled,Enabled" bitfld.long 0x08 6. " OPAC22[2] ,Supervisor Protect (SP) Control 22" "Not Required,Required" bitfld.long 0x08 5. " OPAC22[1] ,Write Protect (WP) Control 22" "Disabled,Enabled" bitfld.long 0x08 4. " OPAC22[0] ,Trusted Protect (TP) Control 22" "Allowed,Not allowed" textline " " bitfld.long 0x08 3. " OPAC23[3] ,Buffer Writes (BW) Control 23" "Disabled,Enabled" bitfld.long 0x08 2. " OPAC23[2] ,Supervisor Protect (SP) Control 23" "Not Required,Required" bitfld.long 0x08 1. " OPAC23[1] ,Write Protect (WP) Control 23" "Disabled,Enabled" bitfld.long 0x08 0. " OPAC23[0] ,Trusted Protect (TP) Control 23" "Allowed,Not allowed" line.long 0x0C "OPACR3,Off-Platform Peripheral Access Control Register" bitfld.long 0x0C 31. " OPAC24[3] ,Buffer Writes (BW) Control 24" "Disabled,Enabled" bitfld.long 0x0C 30. " OPAC24[2] ,Supervisor Protect (SP) Control 24" "Not Required,Required" bitfld.long 0x0C 29. " OPAC24[1] ,Write Protect (WP) Control 24" "Disabled,Enabled" bitfld.long 0x0C 28. " OPAC24[0] ,Trusted Protect (TP) Control 24" "Allowed,Not allowed" textline " " bitfld.long 0x0C 27. " OPAC25[3] ,Buffer Writes (BW) Control 25" "Disabled,Enabled" bitfld.long 0x0C 26. " OPAC25[2] ,Supervisor Protect (SP) Control 25" "Not Required,Required" bitfld.long 0x0C 25. " OPAC25[1] ,Write Protect (WP) Control 25" "Disabled,Enabled" bitfld.long 0x0C 24. " OPAC25[0] ,Trusted Protect (TP) Control 25" "Allowed,Not allowed" textline " " bitfld.long 0x0C 23. " OPAC26[3] ,Buffer Writes (BW) Control 26" "Disabled,Enabled" bitfld.long 0x0C 22. " OPAC26[2] ,Supervisor Protect (SP) Control 26" "Not Required,Required" bitfld.long 0x0C 21. " OPAC26[1] ,Write Protect (WP) Control 26" "Disabled,Enabled" bitfld.long 0x0C 20. " OPAC26[0] ,Trusted Protect (TP) Control 26" "Allowed,Not allowed" textline " " bitfld.long 0x0C 19. " OPAC27[3] ,Buffer Writes (BW) Control 27" "Disabled,Enabled" bitfld.long 0x0C 18. " OPAC27[2] ,Supervisor Protect (SP) Control 27" "Not Required,Required" bitfld.long 0x0C 17. " OPAC27[1] ,Write Protect (WP) Control 27" "Disabled,Enabled" bitfld.long 0x0C 16. " OPAC27[0] ,Trusted Protect (TP) Control 27" "Allowed,Not allowed" textline " " bitfld.long 0x0C 15. " OPAC28[3] ,Buffer Writes (BW) Control 28" "Disabled,Enabled" bitfld.long 0x0C 14. " OPAC28[2] ,Supervisor Protect (SP) Control 28" "Not Required,Required" bitfld.long 0x0C 13. " OPAC28[1] ,Write Protect (WP) Control 28" "Disabled,Enabled" bitfld.long 0x0C 12. " OPAC28[0] ,Trusted Protect (TP) Control 28" "Allowed,Not allowed" textline " " bitfld.long 0x0C 11. " OPAC29[3] ,Buffer Writes (BW) Control 29" "Disabled,Enabled" bitfld.long 0x0C 10. " OPAC29[2] ,Supervisor Protect (SP) Control 29" "Not Required,Required" bitfld.long 0x0C 9. " OPAC29[1] ,Write Protect (WP) Control 29" "Disabled,Enabled" bitfld.long 0x0C 8. " OPAC29[0] ,Trusted Protect (TP) Control 29" "Allowed,Not allowed" textline " " bitfld.long 0x0C 7. " OPAC30[3] ,Buffer Writes (BW) Control 30" "Disabled,Enabled" bitfld.long 0x0C 6. " OPAC30[2] ,Supervisor Protect (SP) Control 30" "Not Required,Required" bitfld.long 0x0C 5. " OPAC30[1] ,Write Protect (WP) Control 30" "Disabled,Enabled" bitfld.long 0x0C 4. " OPAC30[0] ,Trusted Protect (TP) Control 30" "Allowed,Not allowed" textline " " bitfld.long 0x0C 3. " OPAC31[3] ,Buffer Writes (BW) Control 31" "Disabled,Enabled" bitfld.long 0x0C 2. " OPAC31[2] ,Supervisor Protect (SP) Control 31" "Not Required,Required" bitfld.long 0x0C 1. " OPAC31[1] ,Write Protect (WP) Control 31" "Disabled,Enabled" bitfld.long 0x0C 0. " OPAC31[0] ,Trusted Protect (TP) Control 31" "Allowed,Not allowed" line.long 0x10 "OPACR4,Off-Platform Peripheral Access Control Register" bitfld.long 0x10 31. " OPAC32[3] ,Buffer Writes (BW) Control 32" "Disabled,Enabled" bitfld.long 0x10 30. " OPAC32[2] ,Supervisor Protect (SP) Control 32" "Not Required,Required" bitfld.long 0x10 29. " OPAC32[1] ,Write Protect (WP) Control 32" "Disabled,Enabled" bitfld.long 0x10 28. " OPAC32[0] ,Trusted Protect (TP) Control 32" "Allowed,Not allowed" textline " " bitfld.long 0x10 27. " OPAC33[3] ,Buffer Writes (BW) Control 33" "Disabled,Enabled" bitfld.long 0x10 26. " OPAC33[2] ,Supervisor Protect (SP) Control 33" "Not Required,Required" bitfld.long 0x10 25. " OPAC33[1] ,Write Protect (WP) Control 33" "Disabled,Enabled" bitfld.long 0x10 24. " OPAC33[0] ,Trusted Protect (TP) Control 33" "Allowed,Not allowed" width 0x0B tree.end tree.end tree.open "SPBA (Shared Peripheral Bus Arbiter)" tree "Channel 2" base ad:0x300F0000 width 6. group.long 0x0++0x03 line.long 0x00 "PRR0,Peripheral Rights Register 0" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x4++0x03 line.long 0x00 "PRR1,Peripheral Rights Register 1" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x8++0x03 line.long 0x00 "PRR2,Peripheral Rights Register 2" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0xC++0x03 line.long 0x00 "PRR3,Peripheral Rights Register 3" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x10++0x03 line.long 0x00 "PRR4,Peripheral Rights Register 4" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x14++0x03 line.long 0x00 "PRR5,Peripheral Rights Register 5" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x18++0x03 line.long 0x00 "PRR6,Peripheral Rights Register 6" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x1C++0x03 line.long 0x00 "PRR7,Peripheral Rights Register 7" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x20++0x03 line.long 0x00 "PRR8,Peripheral Rights Register 8" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x24++0x03 line.long 0x00 "PRR9,Peripheral Rights Register 9" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x28++0x03 line.long 0x00 "PRR10,Peripheral Rights Register 10" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x2C++0x03 line.long 0x00 "PRR11,Peripheral Rights Register 11" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x30++0x03 line.long 0x00 "PRR12,Peripheral Rights Register 12" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x34++0x03 line.long 0x00 "PRR13,Peripheral Rights Register 13" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x38++0x03 line.long 0x00 "PRR14,Peripheral Rights Register 14" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x3C++0x03 line.long 0x00 "PRR15,Peripheral Rights Register 15" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x40++0x03 line.long 0x00 "PRR16,Peripheral Rights Register 16" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x44++0x03 line.long 0x00 "PRR17,Peripheral Rights Register 17" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x48++0x03 line.long 0x00 "PRR18,Peripheral Rights Register 18" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x4C++0x03 line.long 0x00 "PRR19,Peripheral Rights Register 19" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x50++0x03 line.long 0x00 "PRR20,Peripheral Rights Register 20" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x54++0x03 line.long 0x00 "PRR21,Peripheral Rights Register 21" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x58++0x03 line.long 0x00 "PRR22,Peripheral Rights Register 22" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x5C++0x03 line.long 0x00 "PRR23,Peripheral Rights Register 23" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x60++0x03 line.long 0x00 "PRR24,Peripheral Rights Register 24" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x64++0x03 line.long 0x00 "PRR25,Peripheral Rights Register 25" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x68++0x03 line.long 0x00 "PRR26,Peripheral Rights Register 26" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x6C++0x03 line.long 0x00 "PRR27,Peripheral Rights Register 27" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x70++0x03 line.long 0x00 "PRR28,Peripheral Rights Register 28" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x74++0x03 line.long 0x00 "PRR29,Peripheral Rights Register 29" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x78++0x03 line.long 0x00 "PRR30,Peripheral Rights Register 30" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x7C++0x03 line.long 0x00 "PRR31,Peripheral Rights Register 31" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" width 0x0B tree.end tree "Channel 1" base ad:0x308F0000 width 6. group.long 0x0++0x03 line.long 0x00 "PRR0,Peripheral Rights Register 0" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x4++0x03 line.long 0x00 "PRR1,Peripheral Rights Register 1" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x8++0x03 line.long 0x00 "PRR2,Peripheral Rights Register 2" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0xC++0x03 line.long 0x00 "PRR3,Peripheral Rights Register 3" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x10++0x03 line.long 0x00 "PRR4,Peripheral Rights Register 4" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x14++0x03 line.long 0x00 "PRR5,Peripheral Rights Register 5" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x18++0x03 line.long 0x00 "PRR6,Peripheral Rights Register 6" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x1C++0x03 line.long 0x00 "PRR7,Peripheral Rights Register 7" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x20++0x03 line.long 0x00 "PRR8,Peripheral Rights Register 8" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x24++0x03 line.long 0x00 "PRR9,Peripheral Rights Register 9" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x28++0x03 line.long 0x00 "PRR10,Peripheral Rights Register 10" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x2C++0x03 line.long 0x00 "PRR11,Peripheral Rights Register 11" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x30++0x03 line.long 0x00 "PRR12,Peripheral Rights Register 12" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x34++0x03 line.long 0x00 "PRR13,Peripheral Rights Register 13" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x38++0x03 line.long 0x00 "PRR14,Peripheral Rights Register 14" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x3C++0x03 line.long 0x00 "PRR15,Peripheral Rights Register 15" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x40++0x03 line.long 0x00 "PRR16,Peripheral Rights Register 16" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x44++0x03 line.long 0x00 "PRR17,Peripheral Rights Register 17" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x48++0x03 line.long 0x00 "PRR18,Peripheral Rights Register 18" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x4C++0x03 line.long 0x00 "PRR19,Peripheral Rights Register 19" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x50++0x03 line.long 0x00 "PRR20,Peripheral Rights Register 20" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x54++0x03 line.long 0x00 "PRR21,Peripheral Rights Register 21" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x58++0x03 line.long 0x00 "PRR22,Peripheral Rights Register 22" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x5C++0x03 line.long 0x00 "PRR23,Peripheral Rights Register 23" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x60++0x03 line.long 0x00 "PRR24,Peripheral Rights Register 24" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x64++0x03 line.long 0x00 "PRR25,Peripheral Rights Register 25" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x68++0x03 line.long 0x00 "PRR26,Peripheral Rights Register 26" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x6C++0x03 line.long 0x00 "PRR27,Peripheral Rights Register 27" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x70++0x03 line.long 0x00 "PRR28,Peripheral Rights Register 28" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x74++0x03 line.long 0x00 "PRR29,Peripheral Rights Register 29" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x78++0x03 line.long 0x00 "PRR30,Peripheral Rights Register 30" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" group.long 0x7C++0x03 line.long 0x00 "PRR31,Peripheral Rights Register 31" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resources owner ID" "Unowned,Master A,Master B,Master C" textline " " bitfld.long 0x00 2. " RARC ,Resources access right C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resources access right B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resources access right A" "Prohibited,Allowed" width 0x0B tree.end tree.end tree "ROMPC (ROM Controller with Patch)" base ad:0x303100D4 width 14. sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) group.long 0xD4++0x03 line.long 0x00 "ROMPATCH7D,Data Registers" group.long 0xD8++0x03 line.long 0x00 "ROMPATCH6D,Data Registers" group.long 0xDC++0x03 line.long 0x00 "ROMPATCH5D,Data Registers" group.long 0xE0++0x03 line.long 0x00 "ROMPATCH4D,Data Registers" group.long 0xE4++0x03 line.long 0x00 "ROMPATCH3D,Data Registers" group.long 0xE8++0x03 line.long 0x00 "ROMPATCH2D,Data Registers" group.long 0xEC++0x03 line.long 0x00 "ROMPATCH1D,Data Registers" group.long 0xF0++0x03 line.long 0x00 "ROMPATCH0D,Data Registers" else group.long 0xD4++0x03 line.long 0x00 "ROMPATCH0D,Data Registers" group.long 0xD8++0x03 line.long 0x00 "ROMPATCH1D,Data Registers" group.long 0xDC++0x03 line.long 0x00 "ROMPATCH2D,Data Registers" group.long 0xE0++0x03 line.long 0x00 "ROMPATCH3D,Data Registers" group.long 0xE4++0x03 line.long 0x00 "ROMPATCH4D,Data Registers" group.long 0xE8++0x03 line.long 0x00 "ROMPATCH5D,Data Registers" group.long 0xEC++0x03 line.long 0x00 "ROMPATCH6D,Data Registers" group.long 0xF0++0x03 line.long 0x00 "ROMPATCH7D,Data Registers" endif newline group.long 0xF4++0x03 line.long 0x00 "ROMPATCHCNTL,Control Register" bitfld.long 0x00 29. " DIS ,ROMC disable" "No,Yes" newline bitfld.long 0x00 7. " DATAFIX[7] ,Data fix enable 7" "Opcode patch,Data fix" bitfld.long 0x00 6. " [6] ,Data fix enable 6" "Opcode patch,Data fix" bitfld.long 0x00 5. " [5] ,Data fix enable 5" "Opcode patch,Data fix" bitfld.long 0x00 4. " [4] ,Data fix enable 4" "Opcode patch,Data fix" newline bitfld.long 0x00 3. " [3] ,Data fix enable 3" "Opcode patch,Data fix" bitfld.long 0x00 2. " [2] ,Data fix enable 2" "Opcode patch,Data fix" bitfld.long 0x00 1. " [1] ,Data fix enable 1" "Opcode patch,Data fix" bitfld.long 0x00 0. " [0] ,Data fix enable 0" "Opcode patch,Data fix" group.long 0xFC++0x03 line.long 0x00 "ROMPATCHENL,Enable Register Low" bitfld.long 0x00 15. " ENABLE[15] ,Enable address comparator 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable address comparator 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable address comparator 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable address comparator 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable address comparator 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable address comparator 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable address comparator 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable address comparator 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable address comparator 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable address comparator 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable address comparator 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable address comparator 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable address comparator 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable address comparator 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable address comparator 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable address comparator 0" "Disabled,Enabled" newline group.long 0x100++0x03 line.long 0x00 "ROMPATCH0A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x104++0x03 line.long 0x00 "ROMPATCH1A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x108++0x03 line.long 0x00 "ROMPATCH2A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x10C++0x03 line.long 0x00 "ROMPATCH3A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x110++0x03 line.long 0x00 "ROMPATCH4A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x114++0x03 line.long 0x00 "ROMPATCH5A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x118++0x03 line.long 0x00 "ROMPATCH6A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x11C++0x03 line.long 0x00 "ROMPATCH7A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x120++0x03 line.long 0x00 "ROMPATCH8A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x124++0x03 line.long 0x00 "ROMPATCH9A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x128++0x03 line.long 0x00 "ROMPATCH10A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x12C++0x03 line.long 0x00 "ROMPATCH11A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x130++0x03 line.long 0x00 "ROMPATCH12A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x134++0x03 line.long 0x00 "ROMPATCH13A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x138++0x03 line.long 0x00 "ROMPATCH14A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x13C++0x03 line.long 0x00 "ROMPATCH15A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" newline group.long 0x208++0x03 line.long 0x00 "ROMPATCHSR,Status Register" eventfld.long 0x00 17. " SW ,ROMC AHB multiple address comparator matches indicator" "No collision,Collision" newline rbitfld.long 0x00 0.--5. " SOURCE ,ROMC source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." width 0x0B tree.end tree.open "WDOG (Watchdog Timer)" tree "Channel 1" base ad:0x30280000 width 6. group.word 0x00++0x03 line.word 0x00 "WCR,Watchdog Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog timeout field" bitfld.word 0x00 7. " WDW ,Watchdog disable for wait" "Continue,Suspended" bitfld.word 0x00 6. " SRE ,Software Reset Extension" ",1" textline " " bitfld.word 0x00 5. " WDA ,WDOG_B Assertion" "Asserted,No effect" bitfld.word 0x00 4. " SRS ,Software Reset Signal" "Asserted,No effect" bitfld.word 0x00 3. " WDT ,WDOG_B Timeout assertion" "No effect,Asserted" textline " " bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" bitfld.word 0x00 1. " WDBG ,Watchdog DEBUG enable" "Continue,Suspended" bitfld.word 0x00 0. " WDZST ,Watchdog low power" "Continue,Suspended" line.word 0x02 "WSR,Watchdog Service Register" rgroup.word 0x04++0x01 line.word 0x00 "WRSR,Watchdog Reset Status Register" bitfld.word 0x00 4. " POR ,Power On reset" "No reset,Reset" bitfld.word 0x00 1. " TOUT ,Time-out reset" "No reset,Reset" bitfld.word 0x00 0. " SFTW ,Software reset" "No reset,Reset" group.word 0x06++0x03 line.word 0x00 "WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog timer interrupt enable" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog timer interrupt status" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog interrupt count timeout" line.word 0x02 "WMCR,Watchdog Miscellaneous Control Register" bitfld.word 0x02 0. " PDE ,Power down enable bit" "Disabled,Enabled" width 0x0B tree.end tree "Channel 2" base ad:0x30290000 width 6. group.word 0x00++0x03 line.word 0x00 "WCR,Watchdog Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog timeout field" bitfld.word 0x00 7. " WDW ,Watchdog disable for wait" "Continue,Suspended" bitfld.word 0x00 6. " SRE ,Software Reset Extension" ",1" textline " " bitfld.word 0x00 5. " WDA ,WDOG_B Assertion" "Asserted,No effect" bitfld.word 0x00 4. " SRS ,Software Reset Signal" "Asserted,No effect" bitfld.word 0x00 3. " WDT ,WDOG_B Timeout assertion" "No effect,Asserted" textline " " bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" bitfld.word 0x00 1. " WDBG ,Watchdog DEBUG enable" "Continue,Suspended" bitfld.word 0x00 0. " WDZST ,Watchdog low power" "Continue,Suspended" line.word 0x02 "WSR,Watchdog Service Register" rgroup.word 0x04++0x01 line.word 0x00 "WRSR,Watchdog Reset Status Register" bitfld.word 0x00 4. " POR ,Power On reset" "No reset,Reset" bitfld.word 0x00 1. " TOUT ,Time-out reset" "No reset,Reset" bitfld.word 0x00 0. " SFTW ,Software reset" "No reset,Reset" group.word 0x06++0x03 line.word 0x00 "WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog timer interrupt enable" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog timer interrupt status" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog interrupt count timeout" line.word 0x02 "WMCR,Watchdog Miscellaneous Control Register" bitfld.word 0x02 0. " PDE ,Power down enable bit" "Disabled,Enabled" width 0x0B tree.end tree "Channel 3" base ad:0x302A0000 width 6. group.word 0x00++0x03 line.word 0x00 "WCR,Watchdog Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog timeout field" bitfld.word 0x00 7. " WDW ,Watchdog disable for wait" "Continue,Suspended" bitfld.word 0x00 6. " SRE ,Software Reset Extension" ",1" textline " " bitfld.word 0x00 5. " WDA ,WDOG_B Assertion" "Asserted,No effect" bitfld.word 0x00 4. " SRS ,Software Reset Signal" "Asserted,No effect" bitfld.word 0x00 3. " WDT ,WDOG_B Timeout assertion" "No effect,Asserted" textline " " bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" bitfld.word 0x00 1. " WDBG ,Watchdog DEBUG enable" "Continue,Suspended" bitfld.word 0x00 0. " WDZST ,Watchdog low power" "Continue,Suspended" line.word 0x02 "WSR,Watchdog Service Register" rgroup.word 0x04++0x01 line.word 0x00 "WRSR,Watchdog Reset Status Register" bitfld.word 0x00 4. " POR ,Power On reset" "No reset,Reset" bitfld.word 0x00 1. " TOUT ,Time-out reset" "No reset,Reset" bitfld.word 0x00 0. " SFTW ,Software reset" "No reset,Reset" group.word 0x06++0x03 line.word 0x00 "WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog timer interrupt enable" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog timer interrupt status" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog interrupt count timeout" line.word 0x02 "WMCR,Watchdog Miscellaneous Control Register" bitfld.word 0x02 0. " PDE ,Power down enable bit" "Disabled,Enabled" width 0x0B tree.end tree.end tree "TZASC" base ad:0x32f80000 width 18. tree "Configuration, Lockdown and Interrupt Registers" rgroup.long 0x00++0x03 line.long 0x00 "CONFIGURATION,TZC-380 Configuration Register" bitfld.long 0x00 8.--13. " ADDRESS_WIDTH ,Address Width of the AXI address bus" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 0.--3. " NO_OF_REGIONS ,Number of Regions" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x04++0x0B line.long 0x00 "ACTION,TZC-380 Action Register" bitfld.long 0x00 0.--1. " REACTION_VALUE ,bresps[1:0]/rresps[1:0]/tzasc_int signals usage on region permission failure" "tzasc_int LOW/OKAY,tzasc_int LOW/DECERR,tzasc_int HIGH/OKAY,tzasc_int HIGH/DECERR" line.long 0x04 "LOCKDOWN_RANGE,TZC-380 Lockdown Range Register" bitfld.long 0x04 31. " ENABLE ,Lockdown_regions field regions lock enable" "Disabled,Enabled" bitfld.long 0x04 0.--3. " LOCKDOWN_REGIONS ,Controls the number of regions to lockdown" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" line.long 0x08 "LOCKDOWN_SELECT,TZC-380 Lockdown Select Register" bitfld.long 0x08 2. " ACC_SPECULATION_CNTL ,SPECULATION_CONTROL register access type" "Read/Write,Read-only" bitfld.long 0x08 1. " SECURITY_INV ,SECURITY_INVERSION_EN register access type" "Read/Write,Read-only" newline bitfld.long 0x08 0. " REGION_REGISTER ,LOCKDOWN_RANGE register access type" "Read/Write,Read-only" rgroup.long 0x10++0x03 line.long 0x00 "INTERRUPT_STATUS,TZC-380 Interrupt Status Register" bitfld.long 0x00 1. " OVERRUN ,Two or more region permission failures occurrence interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " STATUS ,Status of the interrupt" "Inactive,Active" wgroup.long 0x14++0x03 line.long 0x00 "INTERRUPT_CLEAR,TZC-380 Interrupt Clear Register" bitfld.long 0x00 1. " CLR_OVERRUN ,Overrun interrupt clear" "No effect,Clear" bitfld.long 0x00 0. " CLR_STATUS ,Interrupt status clear" "No effect,Clear" tree.end width 19. tree "Fail Status Registers" rgroup.long 0x20++0x0F line.long 0x00 "FAIL_ADDRESS_LOW,TZC-380 fail_address_low Register" line.long 0x04 "FAIL_ADDRESS_HIGH,TZC-380 fail_address_high Register" hexmask.long.byte 0x04 0.--7. 0x01 " ADDR_STAT_HIGH ,Address bits [axi_address_msb:32] of the first access to fail a region permission check after the interrupt was cleared" line.long 0x08 "FAIL_CONTROL,TZC-380 fail_control Register" bitfld.long 0x08 24. " WRITE ,Failed access type" "Read,Write" bitfld.long 0x08 21. " NONSECURE ,Permission check failed region first access secure state" "Secure,Non-secure" bitfld.long 0x08 20. " PRIVILEGED ,Permission check failed region first access privileged state" "Unprivileged,Privileged" line.long 0x0C "FAIL_ID,TZC-380 fail_id Register" hexmask.long.word 0x0C 0.--15. 0x01 " ID ,Permission check failed region first access master AXI ID" tree.end width 27. tree "Control Registers" group.long 0x30++0x07 line.long 0x00 "SPECULATION_CONTROL,TZC-380 speculation_control Register" bitfld.long 0x00 1. " WRITE_SPECULATION ,Write access speculation enable" "Enabled,Disabled" bitfld.long 0x00 0. " READ_SPECULATION ,Read access speculation enable" "Enabled,Disabled" line.long 0x04 "SECURITY_INVERSION_ENABLE,TZC-380 security_inversion_enable Register" bitfld.long 0x04 1. " SECURITY_INV_EN ,Security inversion enable" "Disabled,Enabled" tree.end width 22. tree "Region Control Registers" tree "Region 0 " group.long 0x100++0x07 line.long 0x00 "REGION_SETUP_LOW_0 ,TZC-380 The region_setup_low_0 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_0 ,Region 0 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_0 ,TZC-380 The region_setup_high_0 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x100+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_0 ,TZS-380 Region Attributes 0 Register" bitfld.long 0x00 28.--31. " SP0 ,Region 0 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" else group.long (0x100+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_0 ,TZS-380 Region Attributes 0 Register" bitfld.long 0x00 28.--31. " SP0 ,Region 0 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" endif tree.end tree "Region 1 " group.long 0x110++0x07 line.long 0x00 "REGION_SETUP_LOW_1 ,TZC-380 The region_setup_low_1 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_1 ,Region 1 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_1 ,TZC-380 The region_setup_high_1 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x110+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_1 ,TZS-380 Region Attributes 1 Register" bitfld.long 0x00 28.--31. " SP1 ,Region 1 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 1 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 1 Enable" "Disabled,Enabled" else group.long (0x110+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_1 ,TZS-380 Region Attributes 1 Register" bitfld.long 0x00 28.--31. " SP1 ,Region 1 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 1 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 1 Enable" "Disabled,Enabled" endif tree.end tree "Region 2 " group.long 0x120++0x07 line.long 0x00 "REGION_SETUP_LOW_2 ,TZC-380 The region_setup_low_2 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_2 ,Region 2 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_2 ,TZC-380 The region_setup_high_2 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x120+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_2 ,TZS-380 Region Attributes 2 Register" bitfld.long 0x00 28.--31. " SP2 ,Region 2 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 2 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 2 Enable" "Disabled,Enabled" else group.long (0x120+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_2 ,TZS-380 Region Attributes 2 Register" bitfld.long 0x00 28.--31. " SP2 ,Region 2 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 2 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 2 Enable" "Disabled,Enabled" endif tree.end tree "Region 3 " group.long 0x130++0x07 line.long 0x00 "REGION_SETUP_LOW_3 ,TZC-380 The region_setup_low_3 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_3 ,Region 3 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_3 ,TZC-380 The region_setup_high_3 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x130+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_3 ,TZS-380 Region Attributes 3 Register" bitfld.long 0x00 28.--31. " SP3 ,Region 3 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 3 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 3 Enable" "Disabled,Enabled" else group.long (0x130+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_3 ,TZS-380 Region Attributes 3 Register" bitfld.long 0x00 28.--31. " SP3 ,Region 3 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 3 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 3 Enable" "Disabled,Enabled" endif tree.end tree "Region 4 " group.long 0x140++0x07 line.long 0x00 "REGION_SETUP_LOW_4 ,TZC-380 The region_setup_low_4 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_4 ,Region 4 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_4 ,TZC-380 The region_setup_high_4 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x140+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_4 ,TZS-380 Region Attributes 4 Register" bitfld.long 0x00 28.--31. " SP4 ,Region 4 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 4 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 4 Enable" "Disabled,Enabled" else group.long (0x140+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_4 ,TZS-380 Region Attributes 4 Register" bitfld.long 0x00 28.--31. " SP4 ,Region 4 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 4 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 4 Enable" "Disabled,Enabled" endif tree.end tree "Region 5 " group.long 0x150++0x07 line.long 0x00 "REGION_SETUP_LOW_5 ,TZC-380 The region_setup_low_5 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_5 ,Region 5 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_5 ,TZC-380 The region_setup_high_5 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x150+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_5 ,TZS-380 Region Attributes 5 Register" bitfld.long 0x00 28.--31. " SP5 ,Region 5 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 5 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 5 Enable" "Disabled,Enabled" else group.long (0x150+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_5 ,TZS-380 Region Attributes 5 Register" bitfld.long 0x00 28.--31. " SP5 ,Region 5 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 5 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 5 Enable" "Disabled,Enabled" endif tree.end tree "Region 6 " group.long 0x160++0x07 line.long 0x00 "REGION_SETUP_LOW_6 ,TZC-380 The region_setup_low_6 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_6 ,Region 6 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_6 ,TZC-380 The region_setup_high_6 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x160+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_6 ,TZS-380 Region Attributes 6 Register" bitfld.long 0x00 28.--31. " SP6 ,Region 6 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 6 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 6 Enable" "Disabled,Enabled" else group.long (0x160+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_6 ,TZS-380 Region Attributes 6 Register" bitfld.long 0x00 28.--31. " SP6 ,Region 6 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 6 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 6 Enable" "Disabled,Enabled" endif tree.end tree "Region 7 " group.long 0x170++0x07 line.long 0x00 "REGION_SETUP_LOW_7 ,TZC-380 The region_setup_low_7 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_7 ,Region 7 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_7 ,TZC-380 The region_setup_high_7 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x170+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_7 ,TZS-380 Region Attributes 7 Register" bitfld.long 0x00 28.--31. " SP7 ,Region 7 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 7 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 7 Enable" "Disabled,Enabled" else group.long (0x170+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_7 ,TZS-380 Region Attributes 7 Register" bitfld.long 0x00 28.--31. " SP7 ,Region 7 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 7 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 7 Enable" "Disabled,Enabled" endif tree.end tree "Region 8 " group.long 0x180++0x07 line.long 0x00 "REGION_SETUP_LOW_8 ,TZC-380 The region_setup_low_8 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_8 ,Region 8 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_8 ,TZC-380 The region_setup_high_8 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x180+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_8 ,TZS-380 Region Attributes 8 Register" bitfld.long 0x00 28.--31. " SP8 ,Region 8 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 8 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 8 Enable" "Disabled,Enabled" else group.long (0x180+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_8 ,TZS-380 Region Attributes 8 Register" bitfld.long 0x00 28.--31. " SP8 ,Region 8 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 8 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 8 Enable" "Disabled,Enabled" endif tree.end tree "Region 9 " group.long 0x190++0x07 line.long 0x00 "REGION_SETUP_LOW_9 ,TZC-380 The region_setup_low_9 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_9 ,Region 9 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_9 ,TZC-380 The region_setup_high_9 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x190+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_9 ,TZS-380 Region Attributes 9 Register" bitfld.long 0x00 28.--31. " SP9 ,Region 9 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 9 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 9 Enable" "Disabled,Enabled" else group.long (0x190+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_9 ,TZS-380 Region Attributes 9 Register" bitfld.long 0x00 28.--31. " SP9 ,Region 9 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 9 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 9 Enable" "Disabled,Enabled" endif tree.end tree "Region 10" group.long 0x1A0++0x07 line.long 0x00 "REGION_SETUP_LOW_10,TZC-380 The region_setup_low_10 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_10 ,Region 10 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_10,TZC-380 The region_setup_high_10 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x1A0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_10,TZS-380 Region Attributes 10 Register" bitfld.long 0x00 28.--31. " SP10 ,Region 10 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 10 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 10 Enable" "Disabled,Enabled" else group.long (0x1A0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_10,TZS-380 Region Attributes 10 Register" bitfld.long 0x00 28.--31. " SP10 ,Region 10 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 10 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 10 Enable" "Disabled,Enabled" endif tree.end tree "Region 11" group.long 0x1B0++0x07 line.long 0x00 "REGION_SETUP_LOW_11,TZC-380 The region_setup_low_11 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_11 ,Region 11 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_11,TZC-380 The region_setup_high_11 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x1B0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_11,TZS-380 Region Attributes 11 Register" bitfld.long 0x00 28.--31. " SP11 ,Region 11 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 11 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 11 Enable" "Disabled,Enabled" else group.long (0x1B0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_11,TZS-380 Region Attributes 11 Register" bitfld.long 0x00 28.--31. " SP11 ,Region 11 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 11 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 11 Enable" "Disabled,Enabled" endif tree.end tree "Region 12" group.long 0x1C0++0x07 line.long 0x00 "REGION_SETUP_LOW_12,TZC-380 The region_setup_low_12 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_12 ,Region 12 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_12,TZC-380 The region_setup_high_12 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x1C0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_12,TZS-380 Region Attributes 12 Register" bitfld.long 0x00 28.--31. " SP12 ,Region 12 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 12 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 12 Enable" "Disabled,Enabled" else group.long (0x1C0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_12,TZS-380 Region Attributes 12 Register" bitfld.long 0x00 28.--31. " SP12 ,Region 12 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 12 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 12 Enable" "Disabled,Enabled" endif tree.end tree "Region 13" group.long 0x1D0++0x07 line.long 0x00 "REGION_SETUP_LOW_13,TZC-380 The region_setup_low_13 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_13 ,Region 13 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_13,TZC-380 The region_setup_high_13 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x1D0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_13,TZS-380 Region Attributes 13 Register" bitfld.long 0x00 28.--31. " SP13 ,Region 13 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 13 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 13 Enable" "Disabled,Enabled" else group.long (0x1D0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_13,TZS-380 Region Attributes 13 Register" bitfld.long 0x00 28.--31. " SP13 ,Region 13 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 13 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 13 Enable" "Disabled,Enabled" endif tree.end tree "Region 14" group.long 0x1E0++0x07 line.long 0x00 "REGION_SETUP_LOW_14,TZC-380 The region_setup_low_14 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_14 ,Region 14 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_14,TZC-380 The region_setup_high_14 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x1E0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_14,TZS-380 Region Attributes 14 Register" bitfld.long 0x00 28.--31. " SP14 ,Region 14 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 14 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 14 Enable" "Disabled,Enabled" else group.long (0x1E0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_14,TZS-380 Region Attributes 14 Register" bitfld.long 0x00 28.--31. " SP14 ,Region 14 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 14 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 14 Enable" "Disabled,Enabled" endif tree.end tree "Region 15" group.long 0x1F0++0x07 line.long 0x00 "REGION_SETUP_LOW_15,TZC-380 The region_setup_low_15 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_15 ,Region 15 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_15,TZC-380 The region_setup_high_15 Register" if (((per.l(ad:0x32f80000+0x34))&0x01)==0x01) group.long (0x1F0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_15,TZS-380 Region Attributes 15 Register" bitfld.long 0x00 28.--31. " SP15 ,Region 15 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 15 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 15 Enable" "Disabled,Enabled" else group.long (0x1F0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_15,TZS-380 Region Attributes 15 Register" bitfld.long 0x00 28.--31. " SP15 ,Region 15 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 15 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 15 Enable" "Disabled,Enabled" endif tree.end tree.end width 28. tree "Integration Test Registers" group.long 0xE00++0x03 line.long 0x00 "INTEGRATION_TEST_CONTROL,TZS-380 Integration Test Control Register" bitfld.long 0x00 0. " INT_TEST_EN ,Integration test logic enable" "Disabled,Enabled" rgroup.long 0xE04++0x03 line.long 0x00 "INTEGRATION_INPUT_CONTROL,TZS-380 Integration Test Input Register" bitfld.long 0x00 0. " ITIP_SECURE_BOOT_LOCK ,secure_boot_lock status" "Low,High" group.long 0xE08++0x03 line.long 0x00 "INTEGRATION_OUTPUT_CONTROL,TZS-380 Integration Test Output Register" bitfld.long 0x00 0. " ITOP_INT ,tzasc_int port value" "Low,High" tree.end width 16. tree "Component Configuration Registers" rgroup.long 0xFD0++0x03 line.long 0x00 "PERIPH_ID_4,TZS-380 Peripheral Identification 4 Register" bitfld.long 0x00 4.--7. " COUNT_4KB ,The number of 4KB address blocks you require to access the registers" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x00 0.--3. " JEP106_C_CODE ,The JEP106 continuation code value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFE0++0x1F line.long 0x00 "PERIPH_ID_0,TZS-380 Peripheral Identification 0 Register" hexmask.long.byte 0x00 0.--7. 0x1 " PART_NUM_0 ,part_number_0" line.long 0x04 "PERIPH_ID_1,TZS-380 Peripheral Identification 1 Register" bitfld.long 0x04 4.--7. " JEP106_ID_3_0 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " PART_NUM_1 ,part_number_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PERIPH_ID_2,TZS-380 Peripheral Identification 2 Register" bitfld.long 0x08 4.--7. " REVISION ,Revision of the TZASC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 3. " JEDEC_USED ,A JEDEC manufacturer identity code by JEP106 is used" "Not used,Used" bitfld.long 0x08 0.--2. " JEP106_ID_6_4 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" line.long 0x0C "PERIPH_ID_3,TZS-380 Peripheral Identification 3 Register" bitfld.long 0x0C 4.--7. " REVAND ,Silicon revision occurrence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " MOD_NUMBER ,mod_number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFF0++0x03 line.long 0x00 "COMPONENT_ID_0,TZS-380 The Component ID 0 Register" hexmask.long.byte 0x00 0.--7. 0x1 " COMPONENT_ID_0 ,component_id_0" rgroup.long 0xFF4++0x03 line.long 0x00 "COMPONENT_ID_1,TZS-380 The Component ID 1 Register" hexmask.long.byte 0x00 0.--7. 0x1 " COMPONENT_ID_1 ,component_id_1" rgroup.long 0xFF8++0x03 line.long 0x00 "COMPONENT_ID_2,TZS-380 The Component ID 2 Register" hexmask.long.byte 0x00 0.--7. 0x1 " COMPONENT_ID_2 ,component_id_2" rgroup.long 0xFFC++0x03 line.long 0x00 "COMPONENT_ID_3,TZS-380 The Component ID 3 Register" hexmask.long.byte 0x00 0.--7. 0x1 " COMPONENT_ID_3 ,component_id_3" tree.end width 0x0B tree.end tree.end tree.open "Clocks and Power Management" tree "CCM (Clock Control Module)" base ad:0x30380000 width 21. group.long 0x0++0x03 line.long 0x00 "GPR00x0,General purpose register" group.long 0x4++0x03 line.long 0x00 "GPR00x4,General purpose register" group.long 0x8++0x03 line.long 0x00 "GPR00x8,General purpose register" group.long 0xC++0x03 line.long 0x00 "GPR00xC,General purpose register" group.long 0x800++0x0F line.long 0x00 "PLL_CTRL0,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL0_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL0_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL0_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x810++0x0F line.long 0x00 "PLL_CTRL1,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL1_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL1_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL1_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x820++0x0F line.long 0x00 "PLL_CTRL2,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL2_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL2_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL2_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x830++0x0F line.long 0x00 "PLL_CTRL3,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL3_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL3_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL3_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x840++0x0F line.long 0x00 "PLL_CTRL4,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL4_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL4_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL4_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x850++0x0F line.long 0x00 "PLL_CTRL5,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL5_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL5_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL5_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x860++0x0F line.long 0x00 "PLL_CTRL6,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL6_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL6_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL6_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x870++0x0F line.long 0x00 "PLL_CTRL7,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL7_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL7_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL7_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x880++0x0F line.long 0x00 "PLL_CTRL8,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL8_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL8_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL8_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x890++0x0F line.long 0x00 "PLL_CTRL9,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL9_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL9_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL9_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x8A0++0x0F line.long 0x00 "PLL_CTRL10,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL10_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL10_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL10_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x8B0++0x0F line.long 0x00 "PLL_CTRL11,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL11_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL11_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL11_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x8C0++0x0F line.long 0x00 "PLL_CTRL12,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL12_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL12_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL12_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x8D0++0x0F line.long 0x00 "PLL_CTRL13,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL13_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL13_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL13_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x8E0++0x0F line.long 0x00 "PLL_CTRL14,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL14_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL14_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL14_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x8F0++0x0F line.long 0x00 "PLL_CTRL15,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL15_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL15_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL15_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x900++0x0F line.long 0x00 "PLL_CTRL16,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL16_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL16_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL16_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x910++0x0F line.long 0x00 "PLL_CTRL17,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL17_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL17_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL17_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x920++0x0F line.long 0x00 "PLL_CTRL18,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL18_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL18_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL18_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x930++0x0F line.long 0x00 "PLL_CTRL19,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL19_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL19_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL19_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x940++0x0F line.long 0x00 "PLL_CTRL20,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL20_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL20_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL20_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x950++0x0F line.long 0x00 "PLL_CTRL21,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL21_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL21_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL21_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x960++0x0F line.long 0x00 "PLL_CTRL22,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL22_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL22_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL22_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x970++0x0F line.long 0x00 "PLL_CTRL23,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL23_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL23_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL23_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x980++0x0F line.long 0x00 "PLL_CTRL24,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL24_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL24_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL24_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x990++0x0F line.long 0x00 "PLL_CTRL25,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL25_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL25_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL25_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x9A0++0x0F line.long 0x00 "PLL_CTRL26,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL26_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL26_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL26_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x9B0++0x0F line.long 0x00 "PLL_CTRL27,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL27_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL27_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL27_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x9C0++0x0F line.long 0x00 "PLL_CTRL28,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL28_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL28_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL28_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x9D0++0x0F line.long 0x00 "PLL_CTRL29,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL29_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL29_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL29_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x9E0++0x0F line.long 0x00 "PLL_CTRL30,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL30_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL30_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL30_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x9F0++0x0F line.long 0x00 "PLL_CTRL31,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL31_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL31_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL31_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0xA00++0x0F line.long 0x00 "PLL_CTRL32,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL32_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL32_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL32_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0xA10++0x0F line.long 0x00 "PLL_CTRL33,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL33_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL33_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL33_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0xA20++0x0F line.long 0x00 "PLL_CTRL34,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL34_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL34_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL34_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0xA30++0x0F line.long 0x00 "PLL_CTRL35,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL35_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL35_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL35_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0xA40++0x0F line.long 0x00 "PLL_CTRL36,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL36_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL36_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL36_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0xA50++0x0F line.long 0x00 "PLL_CTRL37,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL37_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL37_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL37_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0xA60++0x0F line.long 0x00 "PLL_CTRL38,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "PLL_CTRL38_SET,CCM PLL Control Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "PLL_CTRL38_CLR,CCM PLL Control Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "PLL_CTRL38_TOG,PLL control register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4000++0x0F line.long 0x00 "CCGR0,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR0_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR0_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR0_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4010++0x0F line.long 0x00 "CCGR1,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR1_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR1_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR1_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4020++0x0F line.long 0x00 "CCGR2,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR2_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR2_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR2_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4030++0x0F line.long 0x00 "CCGR3,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR3_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR3_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR3_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4040++0x0F line.long 0x00 "CCGR4,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR4_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR4_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR4_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4050++0x0F line.long 0x00 "CCGR5,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR5_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR5_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR5_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4060++0x0F line.long 0x00 "CCGR6,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR6_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR6_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR6_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4070++0x0F line.long 0x00 "CCGR7,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR7_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR7_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR7_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4080++0x0F line.long 0x00 "CCGR8,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR8_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR8_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR8_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4090++0x0F line.long 0x00 "CCGR9,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR9_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR9_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR9_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x40A0++0x0F line.long 0x00 "CCGR10,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR10_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR10_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR10_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x40B0++0x0F line.long 0x00 "CCGR11,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR11_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR11_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR11_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x40C0++0x0F line.long 0x00 "CCGR12,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR12_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR12_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR12_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x40D0++0x0F line.long 0x00 "CCGR13,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR13_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR13_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR13_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x40E0++0x0F line.long 0x00 "CCGR14,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR14_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR14_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR14_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x40F0++0x0F line.long 0x00 "CCGR15,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR15_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR15_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR15_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4100++0x0F line.long 0x00 "CCGR16,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR16_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR16_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR16_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4110++0x0F line.long 0x00 "CCGR17,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR17_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR17_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR17_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4120++0x0F line.long 0x00 "CCGR18,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR18_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR18_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR18_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4130++0x0F line.long 0x00 "CCGR19,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR19_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR19_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR19_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4140++0x0F line.long 0x00 "CCGR20,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR20_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR20_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR20_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4150++0x0F line.long 0x00 "CCGR21,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR21_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR21_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR21_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4160++0x0F line.long 0x00 "CCGR22,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR22_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR22_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR22_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4170++0x0F line.long 0x00 "CCGR23,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR23_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR23_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR23_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4180++0x0F line.long 0x00 "CCGR24,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR24_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR24_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR24_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4190++0x0F line.long 0x00 "CCGR25,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR25_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR25_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR25_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x41A0++0x0F line.long 0x00 "CCGR26,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR26_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR26_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR26_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x41B0++0x0F line.long 0x00 "CCGR27,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR27_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR27_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR27_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x41C0++0x0F line.long 0x00 "CCGR28,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR28_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR28_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR28_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x41D0++0x0F line.long 0x00 "CCGR29,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR29_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR29_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR29_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x41E0++0x0F line.long 0x00 "CCGR30,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR30_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR30_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR30_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x41F0++0x0F line.long 0x00 "CCGR31,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR31_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR31_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR31_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4200++0x0F line.long 0x00 "CCGR32,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR32_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR32_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR32_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4210++0x0F line.long 0x00 "CCGR33,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR33_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR33_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR33_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4220++0x0F line.long 0x00 "CCGR34,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR34_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR34_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR34_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4230++0x0F line.long 0x00 "CCGR35,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR35_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR35_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR35_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4240++0x0F line.long 0x00 "CCGR36,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR36_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR36_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR36_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4250++0x0F line.long 0x00 "CCGR37,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR37_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR37_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR37_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4260++0x0F line.long 0x00 "CCGR38,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR38_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR38_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR38_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4270++0x0F line.long 0x00 "CCGR39,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR39_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR39_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR39_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4280++0x0F line.long 0x00 "CCGR40,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR40_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR40_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR40_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4290++0x0F line.long 0x00 "CCGR41,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR41_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR41_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR41_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x42A0++0x0F line.long 0x00 "CCGR42,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR42_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR42_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR42_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x42B0++0x0F line.long 0x00 "CCGR43,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR43_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR43_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR43_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x42C0++0x0F line.long 0x00 "CCGR44,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR44_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR44_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR44_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x42D0++0x0F line.long 0x00 "CCGR45,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR45_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR45_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR45_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x42E0++0x0F line.long 0x00 "CCGR46,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR46_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR46_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR46_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x42F0++0x0F line.long 0x00 "CCGR47,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR47_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR47_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR47_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4300++0x0F line.long 0x00 "CCGR48,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR48_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR48_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR48_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4310++0x0F line.long 0x00 "CCGR49,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR49_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR49_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR49_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4320++0x0F line.long 0x00 "CCGR50,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR50_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR50_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR50_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4330++0x0F line.long 0x00 "CCGR51,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR51_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR51_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR51_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4340++0x0F line.long 0x00 "CCGR52,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR52_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR52_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR52_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4350++0x0F line.long 0x00 "CCGR53,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR53_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR53_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR53_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4360++0x0F line.long 0x00 "CCGR54,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR54_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR54_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR54_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4370++0x0F line.long 0x00 "CCGR55,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR55_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR55_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR55_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4380++0x0F line.long 0x00 "CCGR56,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR56_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR56_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR56_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4390++0x0F line.long 0x00 "CCGR57,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR57_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR57_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR57_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x43A0++0x0F line.long 0x00 "CCGR58,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR58_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR58_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR58_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x43B0++0x0F line.long 0x00 "CCGR59,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR59_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR59_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR59_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x43C0++0x0F line.long 0x00 "CCGR60,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR60_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR60_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR60_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x43D0++0x0F line.long 0x00 "CCGR61,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR61_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR61_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR61_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x43E0++0x0F line.long 0x00 "CCGR62,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR62_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR62_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR62_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x43F0++0x0F line.long 0x00 "CCGR63,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR63_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR63_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR63_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4400++0x0F line.long 0x00 "CCGR64,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR64_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR64_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR64_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4410++0x0F line.long 0x00 "CCGR65,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR65_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR65_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR65_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4420++0x0F line.long 0x00 "CCGR66,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR66_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR66_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR66_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4430++0x0F line.long 0x00 "CCGR67,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR67_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR67_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR67_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4440++0x0F line.long 0x00 "CCGR68,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR68_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR68_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR68_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4450++0x0F line.long 0x00 "CCGR69,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR69_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR69_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR69_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4460++0x0F line.long 0x00 "CCGR70,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR70_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR70_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR70_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4470++0x0F line.long 0x00 "CCGR71,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR71_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR71_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR71_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4480++0x0F line.long 0x00 "CCGR72,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR72_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR72_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR72_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4490++0x0F line.long 0x00 "CCGR73,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR73_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR73_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR73_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x44A0++0x0F line.long 0x00 "CCGR74,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR74_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR74_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR74_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x44B0++0x0F line.long 0x00 "CCGR75,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR75_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR75_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR75_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x44C0++0x0F line.long 0x00 "CCGR76,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR76_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR76_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR76_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x44D0++0x0F line.long 0x00 "CCGR77,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR77_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR77_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR77_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x44E0++0x0F line.long 0x00 "CCGR78,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR78_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR78_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR78_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x44F0++0x0F line.long 0x00 "CCGR79,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR79_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR79_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR79_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4500++0x0F line.long 0x00 "CCGR80,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR80_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR80_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR80_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4510++0x0F line.long 0x00 "CCGR81,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR81_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR81_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR81_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4520++0x0F line.long 0x00 "CCGR82,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR82_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR82_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR82_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4530++0x0F line.long 0x00 "CCGR83,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR83_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR83_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR83_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4540++0x0F line.long 0x00 "CCGR84,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR84_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR84_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR84_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4550++0x0F line.long 0x00 "CCGR85,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR85_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR85_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR85_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4560++0x0F line.long 0x00 "CCGR86,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR86_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR86_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR86_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4570++0x0F line.long 0x00 "CCGR87,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR87_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR87_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR87_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4580++0x0F line.long 0x00 "CCGR88,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR88_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR88_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR88_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4590++0x0F line.long 0x00 "CCGR89,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR89_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR89_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR89_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x45A0++0x0F line.long 0x00 "CCGR90,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR90_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR90_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR90_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x45B0++0x0F line.long 0x00 "CCGR91,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR91_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR91_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR91_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x45C0++0x0F line.long 0x00 "CCGR92,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR92_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR92_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR92_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x45D0++0x0F line.long 0x00 "CCGR93,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR93_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR93_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR93_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x45E0++0x0F line.long 0x00 "CCGR94,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR94_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR94_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR94_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x45F0++0x0F line.long 0x00 "CCGR95,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR95_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR95_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR95_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4600++0x0F line.long 0x00 "CCGR96,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR96_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR96_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR96_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4610++0x0F line.long 0x00 "CCGR97,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR97_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR97_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR97_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4620++0x0F line.long 0x00 "CCGR98,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR98_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR98_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR98_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4630++0x0F line.long 0x00 "CCGR99,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR99_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR99_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR99_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4640++0x0F line.long 0x00 "CCGR100,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR100_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR100_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR100_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4650++0x0F line.long 0x00 "CCGR101,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR101_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR101_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR101_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4660++0x0F line.long 0x00 "CCGR102,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR102_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR102_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR102_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4670++0x0F line.long 0x00 "CCGR103,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR103_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR103_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR103_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4680++0x0F line.long 0x00 "CCGR104,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR104_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR104_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR104_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4690++0x0F line.long 0x00 "CCGR105,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR105_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR105_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR105_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x46A0++0x0F line.long 0x00 "CCGR106,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR106_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR106_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR106_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x46B0++0x0F line.long 0x00 "CCGR107,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR107_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR107_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR107_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x46C0++0x0F line.long 0x00 "CCGR108,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR108_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR108_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR108_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x46D0++0x0F line.long 0x00 "CCGR109,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR109_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR109_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR109_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x46E0++0x0F line.long 0x00 "CCGR110,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR110_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR110_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR110_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x46F0++0x0F line.long 0x00 "CCGR111,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR111_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR111_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR111_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4700++0x0F line.long 0x00 "CCGR112,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR112_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR112_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR112_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4710++0x0F line.long 0x00 "CCGR113,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR113_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR113_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR113_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4720++0x0F line.long 0x00 "CCGR114,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR114_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR114_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR114_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4730++0x0F line.long 0x00 "CCGR115,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR115_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR115_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR115_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4740++0x0F line.long 0x00 "CCGR116,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR116_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR116_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR116_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4750++0x0F line.long 0x00 "CCGR117,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR117_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR117_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR117_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4760++0x0F line.long 0x00 "CCGR118,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR118_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR118_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR118_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4770++0x0F line.long 0x00 "CCGR119,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR119_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR119_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR119_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4780++0x0F line.long 0x00 "CCGR120,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR120_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR120_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR120_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4790++0x0F line.long 0x00 "CCGR121,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR121_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR121_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR121_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x47A0++0x0F line.long 0x00 "CCGR122,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR122_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR122_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR122_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x47B0++0x0F line.long 0x00 "CCGR123,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR123_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR123_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR123_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x47C0++0x0F line.long 0x00 "CCGR124,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR124_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR124_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR124_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x47D0++0x0F line.long 0x00 "CCGR125,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR125_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR125_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR125_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x47E0++0x0F line.long 0x00 "CCGR126,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR126_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR126_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR126_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x47F0++0x0F line.long 0x00 "CCGR127,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR127_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR127_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR127_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4800++0x0F line.long 0x00 "CCGR128,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR128_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR128_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR128_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4810++0x0F line.long 0x00 "CCGR129,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR129_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR129_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR129_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4820++0x0F line.long 0x00 "CCGR130,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR130_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR130_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR130_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4830++0x0F line.long 0x00 "CCGR131,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR131_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR131_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR131_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4840++0x0F line.long 0x00 "CCGR132,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR132_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR132_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR132_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4850++0x0F line.long 0x00 "CCGR133,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR133_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR133_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR133_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4860++0x0F line.long 0x00 "CCGR134,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR134_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR134_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR134_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4870++0x0F line.long 0x00 "CCGR135,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR135_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR135_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR135_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4880++0x0F line.long 0x00 "CCGR136,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR136_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR136_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR136_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4890++0x0F line.long 0x00 "CCGR137,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR137_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR137_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR137_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x48A0++0x0F line.long 0x00 "CCGR138,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR138_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR138_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR138_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x48B0++0x0F line.long 0x00 "CCGR139,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR139_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR139_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR139_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x48C0++0x0F line.long 0x00 "CCGR140,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR140_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR140_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR140_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x48D0++0x0F line.long 0x00 "CCGR141,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR141_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR141_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR141_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x48E0++0x0F line.long 0x00 "CCGR142,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR142_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR142_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR142_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x48F0++0x0F line.long 0x00 "CCGR143,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR143_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR143_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR143_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4900++0x0F line.long 0x00 "CCGR144,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR144_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR144_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR144_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4910++0x0F line.long 0x00 "CCGR145,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR145_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR145_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR145_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4920++0x0F line.long 0x00 "CCGR146,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR146_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR146_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR146_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4930++0x0F line.long 0x00 "CCGR147,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR147_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR147_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR147_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4940++0x0F line.long 0x00 "CCGR148,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR148_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR148_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR148_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4950++0x0F line.long 0x00 "CCGR149,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR149_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR149_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR149_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4960++0x0F line.long 0x00 "CCGR150,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR150_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR150_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR150_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4970++0x0F line.long 0x00 "CCGR151,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR151_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR151_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR151_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4980++0x0F line.long 0x00 "CCGR152,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR152_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR152_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR152_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4990++0x0F line.long 0x00 "CCGR153,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR153_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR153_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR153_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x49A0++0x0F line.long 0x00 "CCGR154,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR154_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR154_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR154_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x49B0++0x0F line.long 0x00 "CCGR155,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR155_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR155_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR155_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x49C0++0x0F line.long 0x00 "CCGR156,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR156_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR156_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR156_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x49D0++0x0F line.long 0x00 "CCGR157,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR157_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR157_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR157_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x49E0++0x0F line.long 0x00 "CCGR158,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR158_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR158_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR158_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x49F0++0x0F line.long 0x00 "CCGR159,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR159_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR159_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR159_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4A00++0x0F line.long 0x00 "CCGR160,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR160_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR160_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR160_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4A10++0x0F line.long 0x00 "CCGR161,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR161_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR161_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR161_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4A20++0x0F line.long 0x00 "CCGR162,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR162_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR162_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR162_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4A30++0x0F line.long 0x00 "CCGR163,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR163_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR163_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR163_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4A40++0x0F line.long 0x00 "CCGR164,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR164_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR164_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR164_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4A50++0x0F line.long 0x00 "CCGR165,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR165_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR165_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR165_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4A60++0x0F line.long 0x00 "CCGR166,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR166_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR166_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR166_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4A70++0x0F line.long 0x00 "CCGR167,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR167_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR167_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR167_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4A80++0x0F line.long 0x00 "CCGR168,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR168_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR168_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR168_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4A90++0x0F line.long 0x00 "CCGR169,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR169_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR169_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR169_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4AA0++0x0F line.long 0x00 "CCGR170,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR170_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR170_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR170_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4AB0++0x0F line.long 0x00 "CCGR171,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR171_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR171_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR171_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4AC0++0x0F line.long 0x00 "CCGR172,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR172_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR172_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR172_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4AD0++0x0F line.long 0x00 "CCGR173,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR173_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR173_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR173_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4AE0++0x0F line.long 0x00 "CCGR174,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR174_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR174_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR174_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4AF0++0x0F line.long 0x00 "CCGR175,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR175_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR175_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR175_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4B00++0x0F line.long 0x00 "CCGR176,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR176_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR176_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR176_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4B10++0x0F line.long 0x00 "CCGR177,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR177_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR177_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR177_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4B20++0x0F line.long 0x00 "CCGR178,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR178_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR178_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR178_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4B30++0x0F line.long 0x00 "CCGR179,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR179_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR179_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR179_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4B40++0x0F line.long 0x00 "CCGR180,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR180_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR180_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR180_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4B50++0x0F line.long 0x00 "CCGR181,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR181_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR181_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR181_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4B60++0x0F line.long 0x00 "CCGR182,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR182_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR182_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR182_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4B70++0x0F line.long 0x00 "CCGR183,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR183_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR183_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR183_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4B80++0x0F line.long 0x00 "CCGR184,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR184_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR184_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR184_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4B90++0x0F line.long 0x00 "CCGR185,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR185_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR185_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR185_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4BA0++0x0F line.long 0x00 "CCGR186,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR186_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR186_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR186_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4BB0++0x0F line.long 0x00 "CCGR187,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR187_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR187_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR187_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4BC0++0x0F line.long 0x00 "CCGR188,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR188_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR188_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR188_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4BD0++0x0F line.long 0x00 "CCGR189,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR189_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR189_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR189_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x4BE0++0x0F line.long 0x00 "CCGR190,CCM Clock Gaiting Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x04 "CCGR190_SET,CCM Clock Gaiting Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x08 "CCGR190_CLR,CCM Clock Gaiting Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" line.long 0x0C "CCGR190_TOG,CCM Clock Gaiting Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Run,Run and wait,All time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Run,Run and wait,All time" group.long 0x8000++0x3F line.long 0x00 "TARGET_ROOT0,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT0_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT0_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT0_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC0,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC0_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC0_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC0_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT0,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT0_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT0_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT0_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE0,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT0_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT0_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT0_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8080++0x3F line.long 0x00 "TARGET_ROOT1,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT1_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT1_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT1_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC1,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC1_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC1_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC1_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT1,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT1_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT1_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT1_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE1,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT1_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT1_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT1_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8100++0x3F line.long 0x00 "TARGET_ROOT2,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT2_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT2_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT2_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC2,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC2_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC2_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC2_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT2,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT2_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT2_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT2_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE2,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT2_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT2_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT2_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8180++0x3F line.long 0x00 "TARGET_ROOT3,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT3_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT3_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT3_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC3,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC3_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC3_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC3_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT3,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT3_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT3_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT3_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE3,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT3_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT3_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT3_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8200++0x3F line.long 0x00 "TARGET_ROOT4,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT4_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT4_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT4_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC4,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC4_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC4_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC4_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT4,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT4_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT4_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT4_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE4,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT4_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT4_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT4_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8280++0x3F line.long 0x00 "TARGET_ROOT5,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT5_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT5_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT5_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC5,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC5_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC5_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC5_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT5,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT5_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT5_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT5_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE5,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT5_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT5_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT5_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8300++0x3F line.long 0x00 "TARGET_ROOT6,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT6_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT6_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT6_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC6,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC6_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC6_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC6_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT6,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT6_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT6_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT6_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE6,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT6_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT6_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT6_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8380++0x3F line.long 0x00 "TARGET_ROOT7,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT7_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT7_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT7_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC7,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC7_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC7_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC7_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT7,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT7_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT7_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT7_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE7,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT7_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT7_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT7_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8400++0x3F line.long 0x00 "TARGET_ROOT8,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT8_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT8_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT8_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC8,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC8_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC8_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC8_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT8,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT8_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT8_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT8_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE8,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT8_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT8_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT8_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8480++0x3F line.long 0x00 "TARGET_ROOT9,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT9_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT9_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT9_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC9,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC9_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC9_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC9_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT9,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT9_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT9_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT9_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE9,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT9_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT9_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT9_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8500++0x3F line.long 0x00 "TARGET_ROOT10,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT10_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT10_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT10_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC10,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC10_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC10_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC10_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT10,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT10_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT10_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT10_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE10,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT10_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT10_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT10_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8580++0x3F line.long 0x00 "TARGET_ROOT11,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT11_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT11_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT11_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC11,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC11_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC11_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC11_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT11,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT11_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT11_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT11_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE11,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT11_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT11_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT11_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8600++0x3F line.long 0x00 "TARGET_ROOT12,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT12_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT12_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT12_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC12,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC12_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC12_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC12_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT12,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT12_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT12_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT12_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE12,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT12_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT12_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT12_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8680++0x3F line.long 0x00 "TARGET_ROOT13,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT13_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT13_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT13_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC13,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC13_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC13_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC13_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT13,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT13_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT13_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT13_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE13,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT13_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT13_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT13_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8700++0x3F line.long 0x00 "TARGET_ROOT14,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT14_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT14_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT14_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC14,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC14_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC14_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC14_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT14,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT14_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT14_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT14_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE14,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT14_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT14_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT14_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8780++0x3F line.long 0x00 "TARGET_ROOT15,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT15_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT15_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT15_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC15,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC15_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC15_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC15_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT15,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT15_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT15_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT15_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE15,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT15_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT15_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT15_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8800++0x3F line.long 0x00 "TARGET_ROOT16,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT16_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT16_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT16_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC16,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC16_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC16_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC16_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT16,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT16_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT16_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT16_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE16,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT16_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT16_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT16_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8880++0x3F line.long 0x00 "TARGET_ROOT17,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT17_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT17_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT17_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC17,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC17_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC17_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC17_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT17,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT17_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT17_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT17_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE17,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT17_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT17_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT17_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8900++0x3F line.long 0x00 "TARGET_ROOT18,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT18_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT18_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT18_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC18,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC18_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC18_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC18_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT18,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT18_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT18_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT18_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE18,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT18_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT18_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT18_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8980++0x3F line.long 0x00 "TARGET_ROOT19,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT19_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT19_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT19_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC19,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC19_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC19_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC19_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT19,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT19_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT19_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT19_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE19,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT19_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT19_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT19_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8A00++0x3F line.long 0x00 "TARGET_ROOT20,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT20_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT20_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT20_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC20,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC20_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC20_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC20_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT20,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT20_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT20_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT20_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE20,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT20_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT20_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT20_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8A80++0x3F line.long 0x00 "TARGET_ROOT21,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT21_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT21_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT21_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC21,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC21_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC21_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC21_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT21,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT21_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT21_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT21_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE21,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT21_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT21_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT21_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8B00++0x3F line.long 0x00 "TARGET_ROOT22,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT22_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT22_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT22_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC22,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC22_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC22_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC22_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT22,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT22_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT22_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT22_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE22,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT22_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT22_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT22_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8B80++0x3F line.long 0x00 "TARGET_ROOT23,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT23_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT23_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT23_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC23,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC23_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC23_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC23_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT23,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT23_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT23_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT23_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE23,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT23_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT23_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT23_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8C00++0x3F line.long 0x00 "TARGET_ROOT24,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT24_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT24_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT24_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC24,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC24_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC24_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC24_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT24,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT24_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT24_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT24_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE24,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT24_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT24_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT24_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8C80++0x3F line.long 0x00 "TARGET_ROOT25,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT25_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT25_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT25_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC25,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC25_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC25_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC25_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT25,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT25_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT25_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT25_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE25,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT25_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT25_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT25_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8D00++0x3F line.long 0x00 "TARGET_ROOT26,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT26_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT26_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT26_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC26,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC26_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC26_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC26_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT26,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT26_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT26_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT26_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE26,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT26_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT26_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT26_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8D80++0x3F line.long 0x00 "TARGET_ROOT27,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT27_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT27_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT27_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC27,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC27_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC27_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC27_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT27,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT27_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT27_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT27_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE27,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT27_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT27_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT27_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8E00++0x3F line.long 0x00 "TARGET_ROOT28,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT28_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT28_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT28_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC28,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC28_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC28_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC28_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT28,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT28_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT28_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT28_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE28,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT28_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT28_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT28_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8E80++0x3F line.long 0x00 "TARGET_ROOT29,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT29_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT29_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT29_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC29,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC29_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC29_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC29_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT29,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT29_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT29_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT29_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE29,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT29_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT29_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT29_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8F00++0x3F line.long 0x00 "TARGET_ROOT30,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT30_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT30_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT30_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC30,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC30_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC30_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC30_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT30,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT30_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT30_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT30_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE30,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT30_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT30_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT30_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x8F80++0x3F line.long 0x00 "TARGET_ROOT31,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT31_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT31_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT31_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC31,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC31_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC31_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC31_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT31,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT31_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT31_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT31_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE31,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT31_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT31_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT31_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9000++0x3F line.long 0x00 "TARGET_ROOT32,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT32_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT32_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT32_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC32,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC32_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC32_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC32_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT32,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT32_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT32_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT32_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE32,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT32_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT32_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT32_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9080++0x3F line.long 0x00 "TARGET_ROOT33,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT33_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT33_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT33_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC33,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC33_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC33_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC33_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT33,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT33_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT33_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT33_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE33,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT33_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT33_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT33_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9100++0x3F line.long 0x00 "TARGET_ROOT34,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT34_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT34_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT34_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC34,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC34_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC34_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC34_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT34,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT34_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT34_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT34_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE34,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT34_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT34_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT34_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9180++0x3F line.long 0x00 "TARGET_ROOT35,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT35_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT35_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT35_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC35,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC35_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC35_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC35_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT35,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT35_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT35_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT35_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE35,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT35_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT35_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT35_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9200++0x3F line.long 0x00 "TARGET_ROOT36,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT36_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT36_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT36_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC36,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC36_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC36_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC36_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT36,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT36_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT36_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT36_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE36,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT36_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT36_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT36_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9280++0x3F line.long 0x00 "TARGET_ROOT37,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT37_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT37_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT37_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC37,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC37_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC37_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC37_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT37,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT37_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT37_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT37_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE37,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT37_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT37_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT37_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9300++0x3F line.long 0x00 "TARGET_ROOT38,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT38_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT38_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT38_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC38,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC38_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC38_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC38_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT38,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT38_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT38_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT38_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE38,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT38_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT38_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT38_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9380++0x3F line.long 0x00 "TARGET_ROOT39,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT39_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT39_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT39_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC39,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC39_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC39_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC39_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT39,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT39_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT39_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT39_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE39,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT39_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT39_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT39_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9400++0x3F line.long 0x00 "TARGET_ROOT40,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT40_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT40_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT40_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC40,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC40_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC40_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC40_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT40,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT40_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT40_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT40_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE40,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT40_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT40_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT40_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9480++0x3F line.long 0x00 "TARGET_ROOT41,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT41_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT41_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT41_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC41,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC41_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC41_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC41_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT41,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT41_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT41_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT41_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE41,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT41_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT41_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT41_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9500++0x3F line.long 0x00 "TARGET_ROOT42,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT42_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT42_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT42_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC42,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC42_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC42_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC42_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT42,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT42_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT42_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT42_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE42,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT42_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT42_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT42_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9580++0x3F line.long 0x00 "TARGET_ROOT43,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT43_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT43_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT43_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC43,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC43_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC43_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC43_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT43,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT43_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT43_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT43_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE43,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT43_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT43_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT43_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9600++0x3F line.long 0x00 "TARGET_ROOT44,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT44_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT44_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT44_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC44,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC44_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC44_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC44_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT44,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT44_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT44_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT44_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE44,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT44_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT44_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT44_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9680++0x3F line.long 0x00 "TARGET_ROOT45,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT45_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT45_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT45_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC45,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC45_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC45_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC45_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT45,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT45_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT45_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT45_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE45,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT45_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT45_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT45_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9700++0x3F line.long 0x00 "TARGET_ROOT46,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT46_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT46_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT46_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC46,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC46_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC46_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC46_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT46,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT46_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT46_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT46_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE46,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT46_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT46_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT46_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9780++0x3F line.long 0x00 "TARGET_ROOT47,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT47_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT47_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT47_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC47,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC47_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC47_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC47_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT47,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT47_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT47_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT47_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE47,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT47_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT47_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT47_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9800++0x3F line.long 0x00 "TARGET_ROOT48,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT48_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT48_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT48_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC48,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC48_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC48_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC48_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT48,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT48_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT48_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT48_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE48,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT48_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT48_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT48_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9880++0x3F line.long 0x00 "TARGET_ROOT49,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT49_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT49_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT49_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC49,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC49_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC49_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC49_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT49,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT49_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT49_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT49_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE49,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT49_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT49_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT49_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9900++0x3F line.long 0x00 "TARGET_ROOT50,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT50_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT50_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT50_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC50,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC50_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC50_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC50_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT50,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT50_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT50_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT50_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE50,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT50_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT50_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT50_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9980++0x3F line.long 0x00 "TARGET_ROOT51,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT51_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT51_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT51_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC51,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC51_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC51_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC51_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT51,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT51_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT51_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT51_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE51,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT51_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT51_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT51_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9A00++0x3F line.long 0x00 "TARGET_ROOT52,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT52_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT52_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT52_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC52,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC52_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC52_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC52_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT52,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT52_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT52_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT52_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE52,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT52_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT52_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT52_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9A80++0x3F line.long 0x00 "TARGET_ROOT53,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT53_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT53_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT53_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC53,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC53_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC53_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC53_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT53,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT53_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT53_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT53_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE53,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT53_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT53_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT53_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9B00++0x3F line.long 0x00 "TARGET_ROOT54,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT54_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT54_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT54_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC54,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC54_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC54_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC54_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT54,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT54_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT54_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT54_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE54,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT54_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT54_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT54_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9B80++0x3F line.long 0x00 "TARGET_ROOT55,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT55_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT55_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT55_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC55,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC55_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC55_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC55_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT55,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT55_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT55_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT55_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE55,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT55_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT55_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT55_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9C00++0x3F line.long 0x00 "TARGET_ROOT56,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT56_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT56_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT56_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC56,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC56_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC56_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC56_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT56,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT56_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT56_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT56_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE56,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT56_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT56_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT56_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9C80++0x3F line.long 0x00 "TARGET_ROOT57,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT57_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT57_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT57_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC57,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC57_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC57_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC57_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT57,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT57_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT57_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT57_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE57,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT57_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT57_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT57_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9D00++0x3F line.long 0x00 "TARGET_ROOT58,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT58_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT58_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT58_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC58,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC58_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC58_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC58_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT58,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT58_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT58_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT58_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE58,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT58_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT58_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT58_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9D80++0x3F line.long 0x00 "TARGET_ROOT59,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT59_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT59_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT59_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC59,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC59_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC59_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC59_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT59,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT59_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT59_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT59_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE59,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT59_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT59_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT59_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9E00++0x3F line.long 0x00 "TARGET_ROOT60,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT60_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT60_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT60_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC60,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC60_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC60_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC60_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT60,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT60_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT60_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT60_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE60,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT60_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT60_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT60_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9E80++0x3F line.long 0x00 "TARGET_ROOT61,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT61_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT61_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT61_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC61,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC61_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC61_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC61_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT61,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT61_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT61_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT61_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE61,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT61_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT61_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT61_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9F00++0x3F line.long 0x00 "TARGET_ROOT62,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT62_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT62_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT62_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC62,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC62_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC62_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC62_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT62,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT62_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT62_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT62_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE62,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT62_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT62_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT62_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0x9F80++0x3F line.long 0x00 "TARGET_ROOT63,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT63_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT63_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT63_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC63,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC63_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC63_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC63_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT63,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT63_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT63_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT63_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE63,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT63_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT63_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT63_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA000++0x3F line.long 0x00 "TARGET_ROOT64,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT64_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT64_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT64_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC64,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC64_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC64_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC64_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT64,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT64_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT64_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT64_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE64,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT64_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT64_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT64_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA080++0x3F line.long 0x00 "TARGET_ROOT65,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT65_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT65_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT65_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC65,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC65_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC65_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC65_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT65,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT65_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT65_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT65_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE65,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT65_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT65_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT65_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA100++0x3F line.long 0x00 "TARGET_ROOT66,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT66_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT66_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT66_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC66,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC66_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC66_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC66_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT66,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT66_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT66_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT66_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE66,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT66_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT66_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT66_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA180++0x3F line.long 0x00 "TARGET_ROOT67,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT67_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT67_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT67_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC67,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC67_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC67_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC67_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT67,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT67_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT67_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT67_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE67,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT67_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT67_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT67_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA200++0x3F line.long 0x00 "TARGET_ROOT68,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT68_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT68_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT68_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC68,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC68_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC68_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC68_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT68,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT68_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT68_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT68_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE68,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT68_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT68_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT68_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA280++0x3F line.long 0x00 "TARGET_ROOT69,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT69_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT69_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT69_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC69,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC69_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC69_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC69_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT69,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT69_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT69_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT69_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE69,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT69_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT69_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT69_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA300++0x3F line.long 0x00 "TARGET_ROOT70,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT70_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT70_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT70_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC70,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC70_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC70_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC70_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT70,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT70_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT70_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT70_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE70,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT70_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT70_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT70_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA380++0x3F line.long 0x00 "TARGET_ROOT71,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT71_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT71_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT71_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC71,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC71_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC71_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC71_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT71,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT71_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT71_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT71_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE71,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT71_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT71_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT71_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA400++0x3F line.long 0x00 "TARGET_ROOT72,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT72_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT72_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT72_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC72,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC72_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC72_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC72_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT72,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT72_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT72_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT72_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE72,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT72_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT72_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT72_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA480++0x3F line.long 0x00 "TARGET_ROOT73,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT73_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT73_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT73_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC73,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC73_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC73_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC73_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT73,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT73_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT73_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT73_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE73,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT73_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT73_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT73_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA500++0x3F line.long 0x00 "TARGET_ROOT74,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT74_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT74_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT74_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC74,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC74_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC74_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC74_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT74,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT74_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT74_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT74_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE74,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT74_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT74_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT74_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA580++0x3F line.long 0x00 "TARGET_ROOT75,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT75_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT75_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT75_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC75,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC75_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC75_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC75_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT75,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT75_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT75_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT75_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE75,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT75_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT75_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT75_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA600++0x3F line.long 0x00 "TARGET_ROOT76,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT76_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT76_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT76_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC76,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC76_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC76_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC76_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT76,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT76_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT76_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT76_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE76,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT76_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT76_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT76_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA680++0x3F line.long 0x00 "TARGET_ROOT77,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT77_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT77_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT77_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC77,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC77_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC77_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC77_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT77,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT77_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT77_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT77_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE77,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT77_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT77_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT77_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA700++0x3F line.long 0x00 "TARGET_ROOT78,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT78_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT78_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT78_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC78,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC78_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC78_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC78_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT78,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT78_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT78_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT78_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE78,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT78_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT78_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT78_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA780++0x3F line.long 0x00 "TARGET_ROOT79,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT79_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT79_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT79_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC79,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC79_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC79_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC79_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT79,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT79_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT79_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT79_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE79,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT79_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT79_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT79_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA800++0x3F line.long 0x00 "TARGET_ROOT80,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT80_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT80_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT80_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC80,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC80_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC80_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC80_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT80,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT80_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT80_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT80_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE80,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT80_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT80_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT80_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA880++0x3F line.long 0x00 "TARGET_ROOT81,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT81_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT81_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT81_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC81,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC81_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC81_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC81_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT81,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT81_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT81_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT81_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE81,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT81_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT81_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT81_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA900++0x3F line.long 0x00 "TARGET_ROOT82,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT82_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT82_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT82_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC82,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC82_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC82_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC82_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT82,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT82_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT82_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT82_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE82,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT82_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT82_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT82_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xA980++0x3F line.long 0x00 "TARGET_ROOT83,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT83_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT83_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT83_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC83,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC83_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC83_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC83_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT83,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT83_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT83_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT83_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE83,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT83_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT83_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT83_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xAA00++0x3F line.long 0x00 "TARGET_ROOT84,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT84_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT84_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT84_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC84,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC84_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC84_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC84_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT84,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT84_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT84_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT84_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE84,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT84_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT84_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT84_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xAA80++0x3F line.long 0x00 "TARGET_ROOT85,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT85_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT85_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT85_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC85,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC85_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC85_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC85_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT85,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT85_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT85_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT85_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE85,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT85_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT85_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT85_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xAB00++0x3F line.long 0x00 "TARGET_ROOT86,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT86_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT86_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT86_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC86,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC86_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC86_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC86_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT86,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT86_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT86_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT86_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE86,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT86_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT86_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT86_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xAB80++0x3F line.long 0x00 "TARGET_ROOT87,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT87_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT87_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT87_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC87,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC87_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC87_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC87_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT87,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT87_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT87_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT87_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE87,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT87_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT87_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT87_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xAC00++0x3F line.long 0x00 "TARGET_ROOT88,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT88_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT88_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT88_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC88,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC88_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC88_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC88_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT88,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT88_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT88_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT88_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE88,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT88_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT88_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT88_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xAC80++0x3F line.long 0x00 "TARGET_ROOT89,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT89_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT89_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT89_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC89,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC89_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC89_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC89_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT89,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT89_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT89_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT89_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE89,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT89_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT89_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT89_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xAD00++0x3F line.long 0x00 "TARGET_ROOT90,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT90_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT90_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT90_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC90,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC90_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC90_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC90_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT90,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT90_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT90_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT90_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE90,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT90_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT90_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT90_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xAD80++0x3F line.long 0x00 "TARGET_ROOT91,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT91_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT91_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT91_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC91,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC91_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC91_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC91_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT91,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT91_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT91_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT91_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE91,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT91_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT91_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT91_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xAE00++0x3F line.long 0x00 "TARGET_ROOT92,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT92_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT92_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT92_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC92,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC92_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC92_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC92_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT92,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT92_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT92_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT92_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE92,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT92_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT92_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT92_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xAE80++0x3F line.long 0x00 "TARGET_ROOT93,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT93_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT93_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT93_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC93,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC93_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC93_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC93_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT93,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT93_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT93_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT93_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE93,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT93_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT93_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT93_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xAF00++0x3F line.long 0x00 "TARGET_ROOT94,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT94_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT94_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT94_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC94,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC94_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC94_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC94_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT94,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT94_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT94_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT94_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE94,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT94_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT94_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT94_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xAF80++0x3F line.long 0x00 "TARGET_ROOT95,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT95_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT95_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT95_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC95,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC95_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC95_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC95_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT95,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT95_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT95_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT95_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE95,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT95_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT95_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT95_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB000++0x3F line.long 0x00 "TARGET_ROOT96,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT96_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT96_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT96_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC96,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC96_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC96_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC96_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT96,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT96_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT96_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT96_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE96,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT96_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT96_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT96_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB080++0x3F line.long 0x00 "TARGET_ROOT97,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT97_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT97_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT97_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC97,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC97_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC97_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC97_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT97,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT97_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT97_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT97_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE97,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT97_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT97_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT97_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB100++0x3F line.long 0x00 "TARGET_ROOT98,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT98_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT98_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT98_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC98,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC98_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC98_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC98_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT98,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT98_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT98_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT98_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE98,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT98_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT98_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT98_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB180++0x3F line.long 0x00 "TARGET_ROOT99,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT99_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT99_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT99_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC99,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC99_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC99_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC99_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT99,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT99_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT99_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT99_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE99,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT99_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT99_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT99_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB200++0x3F line.long 0x00 "TARGET_ROOT100,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT100_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT100_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT100_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC100,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC100_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC100_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC100_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT100,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT100_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT100_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT100_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE100,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT100_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT100_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT100_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB280++0x3F line.long 0x00 "TARGET_ROOT101,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT101_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT101_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT101_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC101,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC101_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC101_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC101_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT101,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT101_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT101_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT101_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE101,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT101_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT101_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT101_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB300++0x3F line.long 0x00 "TARGET_ROOT102,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT102_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT102_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT102_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC102,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC102_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC102_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC102_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT102,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT102_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT102_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT102_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE102,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT102_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT102_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT102_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB380++0x3F line.long 0x00 "TARGET_ROOT103,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT103_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT103_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT103_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC103,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC103_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC103_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC103_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT103,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT103_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT103_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT103_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE103,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT103_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT103_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT103_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB400++0x3F line.long 0x00 "TARGET_ROOT104,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT104_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT104_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT104_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC104,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC104_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC104_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC104_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT104,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT104_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT104_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT104_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE104,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT104_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT104_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT104_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB480++0x3F line.long 0x00 "TARGET_ROOT105,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT105_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT105_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT105_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC105,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC105_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC105_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC105_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT105,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT105_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT105_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT105_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE105,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT105_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT105_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT105_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB500++0x3F line.long 0x00 "TARGET_ROOT106,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT106_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT106_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT106_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC106,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC106_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC106_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC106_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT106,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT106_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT106_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT106_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE106,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT106_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT106_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT106_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB580++0x3F line.long 0x00 "TARGET_ROOT107,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT107_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT107_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT107_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC107,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC107_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC107_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC107_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT107,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT107_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT107_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT107_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE107,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT107_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT107_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT107_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB600++0x3F line.long 0x00 "TARGET_ROOT108,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT108_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT108_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT108_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC108,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC108_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC108_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC108_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT108,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT108_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT108_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT108_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE108,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT108_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT108_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT108_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB680++0x3F line.long 0x00 "TARGET_ROOT109,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT109_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT109_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT109_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC109,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC109_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC109_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC109_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT109,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT109_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT109_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT109_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE109,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT109_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT109_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT109_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB700++0x3F line.long 0x00 "TARGET_ROOT110,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT110_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT110_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT110_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC110,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC110_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC110_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC110_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT110,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT110_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT110_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT110_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE110,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT110_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT110_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT110_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB780++0x3F line.long 0x00 "TARGET_ROOT111,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT111_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT111_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT111_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC111,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC111_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC111_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC111_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT111,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT111_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT111_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT111_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE111,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT111_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT111_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT111_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB800++0x3F line.long 0x00 "TARGET_ROOT112,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT112_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT112_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT112_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC112,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC112_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC112_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC112_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT112,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT112_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT112_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT112_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE112,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT112_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT112_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT112_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB880++0x3F line.long 0x00 "TARGET_ROOT113,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT113_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT113_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT113_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC113,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC113_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC113_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC113_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT113,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT113_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT113_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT113_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE113,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT113_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT113_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT113_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB900++0x3F line.long 0x00 "TARGET_ROOT114,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT114_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT114_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT114_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC114,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC114_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC114_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC114_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT114,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT114_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT114_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT114_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE114,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT114_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT114_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT114_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xB980++0x3F line.long 0x00 "TARGET_ROOT115,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT115_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT115_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT115_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC115,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC115_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC115_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC115_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT115,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT115_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT115_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT115_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE115,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT115_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT115_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT115_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xBA00++0x3F line.long 0x00 "TARGET_ROOT116,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT116_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT116_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT116_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC116,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC116_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC116_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC116_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT116,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT116_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT116_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT116_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE116,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT116_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT116_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT116_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xBA80++0x3F line.long 0x00 "TARGET_ROOT117,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT117_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT117_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT117_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC117,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC117_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC117_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC117_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT117,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT117_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT117_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT117_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE117,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT117_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT117_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT117_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xBB00++0x3F line.long 0x00 "TARGET_ROOT118,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT118_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT118_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT118_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC118,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC118_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC118_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC118_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT118,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT118_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT118_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT118_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE118,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT118_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT118_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT118_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xBB80++0x3F line.long 0x00 "TARGET_ROOT119,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT119_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT119_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT119_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC119,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC119_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC119_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC119_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT119,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT119_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT119_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT119_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE119,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT119_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT119_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT119_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xBC00++0x3F line.long 0x00 "TARGET_ROOT120,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT120_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT120_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT120_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC120,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC120_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC120_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC120_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT120,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT120_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT120_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT120_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE120,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT120_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT120_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT120_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xBC80++0x3F line.long 0x00 "TARGET_ROOT121,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT121_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT121_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT121_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC121,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC121_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC121_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC121_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT121,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT121_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT121_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT121_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE121,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT121_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT121_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT121_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xBD00++0x3F line.long 0x00 "TARGET_ROOT122,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT122_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT122_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT122_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC122,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC122_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC122_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC122_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT122,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT122_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT122_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT122_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE122,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT122_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT122_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT122_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xBD80++0x3F line.long 0x00 "TARGET_ROOT123,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT123_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT123_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT123_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC123,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC123_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC123_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC123_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT123,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT123_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT123_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT123_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE123,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT123_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT123_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT123_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" group.long 0xBE00++0x3F line.long 0x00 "TARGET_ROOT124,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT124_SET,Target Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT124_CLR,Target Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT124_TOG,Target Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PDF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x10 "MISC124,Miscellaneous Register" bitfld.long 0x10 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x10 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x10 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x14 "MISC124_SET,Miscellaneous Register" bitfld.long 0x14 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x14 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x14 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x18 "MISC124_CLR,Miscellaneous Register" bitfld.long 0x18 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x18 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x18 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x1C "MISC124_TOG,Miscellaneous Register" bitfld.long 0x1C 8. " VIOLATE ,Violation in normal interface of this clock" "Not occurred,Occurred" bitfld.long 0x1C 4. " TIMEOUT ,Time out during accessing this clock" "Not occurred,Occurred" bitfld.long 0x1C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "Not occurred,Occurred" line.long 0x20 "POST_ROOT124,Post Divider Register" rbitfld.long 0x20 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x20 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x20 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x20 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "POST_ROOT124_SET,Post Divider Register" rbitfld.long 0x24 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x24 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x24 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x24 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x28 "POST_ROOT124_CLR,Post Divider Register" rbitfld.long 0x28 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x28 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x28 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x28 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x2C "POST_ROOT124_TOG,Post Divider Register" rbitfld.long 0x2C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 28. " SELECT ,Selection of pre clock branches" "Off,ON" rbitfld.long 0x2C 7. " BUSY1 ,Post divider is applying new setting" "Disabled,Enabled" bitfld.long 0x2C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x30 "PRE124,Pre Divider Register" rbitfld.long 0x30 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x30 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x30 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x30 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x30 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x30 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x30 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x30 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x30 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x30 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x34 "PRE_ROOT124_SET,Pre Divider Register" rbitfld.long 0x34 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x34 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x34 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x34 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x34 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x34 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x34 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x34 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x34 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x34 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x38 "PRE_ROOT124_CLR,Pre Divider Register" rbitfld.long 0x38 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x38 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x38 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x38 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x38 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x38 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x38 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x38 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x38 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x38 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x3C "PRE_ROOT124_TOG,Pre Divider Register" rbitfld.long 0x3C 31. " BUSY4 , EN_A field is applied to field" "Disabled,Enabled" bitfld.long 0x3C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x3C 24.--26. " MUX_A ,Selection control multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x3C 19. " BUSY3 ,Pre divider value for branch A is applied" "Disabled,Enabled" textline " " bitfld.long 0x3C 16.--18. " POST_PODF_A ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x3C 15. " BUSY1 ,EN_B is applied to field" "Disabled,Enabled" bitfld.long 0x3C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x3C 8.--10. " MUX_B ,Selection control multiplexer of branch B" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x3C 3. " BUSY0 ,Pre divider value for branch B is applied" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " PRE_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8" if (((per.l(ad:0x30380000+0x8070))&0x80000000)==0x00) group.long 0x8070++0x03 line.long 0x00 "ACCESS_CTRL0,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8070++0x03 line.long 0x00 "ACCESS_CTRL0,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8070+0x04))&0x80000000)==0x00) group.long (0x8070+0x04)++0x03 line.long 0x00 "ACCESS_CTRL0_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8070+0x04)++0x03 line.long 0x00 "ACCESS_CTRL0_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8070+0x08))&0x80000000)==0x00) group.long (0x8070+0x08)++0x03 line.long 0x00 "ACCESS_CTRL0_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8070+0x08)++0x03 line.long 0x00 "ACCESS_CTRL0_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8070+0x0C))&0x80000000)==0x00) group.long (0x8070+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL0_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8070+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL0_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x80F0))&0x80000000)==0x00) group.long 0x80F0++0x03 line.long 0x00 "ACCESS_CTRL1,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x80F0++0x03 line.long 0x00 "ACCESS_CTRL1,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x80F0+0x04))&0x80000000)==0x00) group.long (0x80F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL1_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x80F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL1_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x80F0+0x08))&0x80000000)==0x00) group.long (0x80F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL1_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x80F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL1_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x80F0+0x0C))&0x80000000)==0x00) group.long (0x80F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL1_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x80F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL1_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8170))&0x80000000)==0x00) group.long 0x8170++0x03 line.long 0x00 "ACCESS_CTRL2,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8170++0x03 line.long 0x00 "ACCESS_CTRL2,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8170+0x04))&0x80000000)==0x00) group.long (0x8170+0x04)++0x03 line.long 0x00 "ACCESS_CTRL2_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8170+0x04)++0x03 line.long 0x00 "ACCESS_CTRL2_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8170+0x08))&0x80000000)==0x00) group.long (0x8170+0x08)++0x03 line.long 0x00 "ACCESS_CTRL2_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8170+0x08)++0x03 line.long 0x00 "ACCESS_CTRL2_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8170+0x0C))&0x80000000)==0x00) group.long (0x8170+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL2_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8170+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL2_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x81F0))&0x80000000)==0x00) group.long 0x81F0++0x03 line.long 0x00 "ACCESS_CTRL3,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x81F0++0x03 line.long 0x00 "ACCESS_CTRL3,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x81F0+0x04))&0x80000000)==0x00) group.long (0x81F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL3_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x81F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL3_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x81F0+0x08))&0x80000000)==0x00) group.long (0x81F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL3_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x81F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL3_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x81F0+0x0C))&0x80000000)==0x00) group.long (0x81F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL3_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x81F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL3_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8270))&0x80000000)==0x00) group.long 0x8270++0x03 line.long 0x00 "ACCESS_CTRL4,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8270++0x03 line.long 0x00 "ACCESS_CTRL4,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8270+0x04))&0x80000000)==0x00) group.long (0x8270+0x04)++0x03 line.long 0x00 "ACCESS_CTRL4_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8270+0x04)++0x03 line.long 0x00 "ACCESS_CTRL4_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8270+0x08))&0x80000000)==0x00) group.long (0x8270+0x08)++0x03 line.long 0x00 "ACCESS_CTRL4_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8270+0x08)++0x03 line.long 0x00 "ACCESS_CTRL4_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8270+0x0C))&0x80000000)==0x00) group.long (0x8270+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL4_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8270+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL4_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x82F0))&0x80000000)==0x00) group.long 0x82F0++0x03 line.long 0x00 "ACCESS_CTRL5,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x82F0++0x03 line.long 0x00 "ACCESS_CTRL5,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x82F0+0x04))&0x80000000)==0x00) group.long (0x82F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL5_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x82F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL5_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x82F0+0x08))&0x80000000)==0x00) group.long (0x82F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL5_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x82F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL5_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x82F0+0x0C))&0x80000000)==0x00) group.long (0x82F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL5_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x82F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL5_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8370))&0x80000000)==0x00) group.long 0x8370++0x03 line.long 0x00 "ACCESS_CTRL6,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8370++0x03 line.long 0x00 "ACCESS_CTRL6,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8370+0x04))&0x80000000)==0x00) group.long (0x8370+0x04)++0x03 line.long 0x00 "ACCESS_CTRL6_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8370+0x04)++0x03 line.long 0x00 "ACCESS_CTRL6_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8370+0x08))&0x80000000)==0x00) group.long (0x8370+0x08)++0x03 line.long 0x00 "ACCESS_CTRL6_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8370+0x08)++0x03 line.long 0x00 "ACCESS_CTRL6_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8370+0x0C))&0x80000000)==0x00) group.long (0x8370+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL6_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8370+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL6_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x83F0))&0x80000000)==0x00) group.long 0x83F0++0x03 line.long 0x00 "ACCESS_CTRL7,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x83F0++0x03 line.long 0x00 "ACCESS_CTRL7,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x83F0+0x04))&0x80000000)==0x00) group.long (0x83F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL7_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x83F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL7_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x83F0+0x08))&0x80000000)==0x00) group.long (0x83F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL7_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x83F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL7_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x83F0+0x0C))&0x80000000)==0x00) group.long (0x83F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL7_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x83F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL7_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8470))&0x80000000)==0x00) group.long 0x8470++0x03 line.long 0x00 "ACCESS_CTRL8,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8470++0x03 line.long 0x00 "ACCESS_CTRL8,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8470+0x04))&0x80000000)==0x00) group.long (0x8470+0x04)++0x03 line.long 0x00 "ACCESS_CTRL8_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8470+0x04)++0x03 line.long 0x00 "ACCESS_CTRL8_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8470+0x08))&0x80000000)==0x00) group.long (0x8470+0x08)++0x03 line.long 0x00 "ACCESS_CTRL8_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8470+0x08)++0x03 line.long 0x00 "ACCESS_CTRL8_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8470+0x0C))&0x80000000)==0x00) group.long (0x8470+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL8_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8470+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL8_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x84F0))&0x80000000)==0x00) group.long 0x84F0++0x03 line.long 0x00 "ACCESS_CTRL9,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x84F0++0x03 line.long 0x00 "ACCESS_CTRL9,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x84F0+0x04))&0x80000000)==0x00) group.long (0x84F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL9_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x84F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL9_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x84F0+0x08))&0x80000000)==0x00) group.long (0x84F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL9_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x84F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL9_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x84F0+0x0C))&0x80000000)==0x00) group.long (0x84F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL9_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x84F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL9_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8570))&0x80000000)==0x00) group.long 0x8570++0x03 line.long 0x00 "ACCESS_CTRL10,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8570++0x03 line.long 0x00 "ACCESS_CTRL10,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8570+0x04))&0x80000000)==0x00) group.long (0x8570+0x04)++0x03 line.long 0x00 "ACCESS_CTRL10_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8570+0x04)++0x03 line.long 0x00 "ACCESS_CTRL10_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8570+0x08))&0x80000000)==0x00) group.long (0x8570+0x08)++0x03 line.long 0x00 "ACCESS_CTRL10_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8570+0x08)++0x03 line.long 0x00 "ACCESS_CTRL10_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8570+0x0C))&0x80000000)==0x00) group.long (0x8570+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL10_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8570+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL10_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x85F0))&0x80000000)==0x00) group.long 0x85F0++0x03 line.long 0x00 "ACCESS_CTRL11,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x85F0++0x03 line.long 0x00 "ACCESS_CTRL11,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x85F0+0x04))&0x80000000)==0x00) group.long (0x85F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL11_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x85F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL11_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x85F0+0x08))&0x80000000)==0x00) group.long (0x85F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL11_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x85F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL11_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x85F0+0x0C))&0x80000000)==0x00) group.long (0x85F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL11_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x85F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL11_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8670))&0x80000000)==0x00) group.long 0x8670++0x03 line.long 0x00 "ACCESS_CTRL12,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8670++0x03 line.long 0x00 "ACCESS_CTRL12,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8670+0x04))&0x80000000)==0x00) group.long (0x8670+0x04)++0x03 line.long 0x00 "ACCESS_CTRL12_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8670+0x04)++0x03 line.long 0x00 "ACCESS_CTRL12_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8670+0x08))&0x80000000)==0x00) group.long (0x8670+0x08)++0x03 line.long 0x00 "ACCESS_CTRL12_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8670+0x08)++0x03 line.long 0x00 "ACCESS_CTRL12_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8670+0x0C))&0x80000000)==0x00) group.long (0x8670+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL12_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8670+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL12_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x86F0))&0x80000000)==0x00) group.long 0x86F0++0x03 line.long 0x00 "ACCESS_CTRL13,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x86F0++0x03 line.long 0x00 "ACCESS_CTRL13,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x86F0+0x04))&0x80000000)==0x00) group.long (0x86F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL13_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x86F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL13_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x86F0+0x08))&0x80000000)==0x00) group.long (0x86F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL13_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x86F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL13_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x86F0+0x0C))&0x80000000)==0x00) group.long (0x86F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL13_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x86F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL13_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8770))&0x80000000)==0x00) group.long 0x8770++0x03 line.long 0x00 "ACCESS_CTRL14,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8770++0x03 line.long 0x00 "ACCESS_CTRL14,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8770+0x04))&0x80000000)==0x00) group.long (0x8770+0x04)++0x03 line.long 0x00 "ACCESS_CTRL14_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8770+0x04)++0x03 line.long 0x00 "ACCESS_CTRL14_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8770+0x08))&0x80000000)==0x00) group.long (0x8770+0x08)++0x03 line.long 0x00 "ACCESS_CTRL14_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8770+0x08)++0x03 line.long 0x00 "ACCESS_CTRL14_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8770+0x0C))&0x80000000)==0x00) group.long (0x8770+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL14_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8770+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL14_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x87F0))&0x80000000)==0x00) group.long 0x87F0++0x03 line.long 0x00 "ACCESS_CTRL15,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x87F0++0x03 line.long 0x00 "ACCESS_CTRL15,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x87F0+0x04))&0x80000000)==0x00) group.long (0x87F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL15_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x87F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL15_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x87F0+0x08))&0x80000000)==0x00) group.long (0x87F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL15_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x87F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL15_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x87F0+0x0C))&0x80000000)==0x00) group.long (0x87F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL15_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x87F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL15_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8870))&0x80000000)==0x00) group.long 0x8870++0x03 line.long 0x00 "ACCESS_CTRL16,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8870++0x03 line.long 0x00 "ACCESS_CTRL16,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8870+0x04))&0x80000000)==0x00) group.long (0x8870+0x04)++0x03 line.long 0x00 "ACCESS_CTRL16_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8870+0x04)++0x03 line.long 0x00 "ACCESS_CTRL16_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8870+0x08))&0x80000000)==0x00) group.long (0x8870+0x08)++0x03 line.long 0x00 "ACCESS_CTRL16_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8870+0x08)++0x03 line.long 0x00 "ACCESS_CTRL16_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8870+0x0C))&0x80000000)==0x00) group.long (0x8870+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL16_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8870+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL16_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x88F0))&0x80000000)==0x00) group.long 0x88F0++0x03 line.long 0x00 "ACCESS_CTRL17,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x88F0++0x03 line.long 0x00 "ACCESS_CTRL17,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x88F0+0x04))&0x80000000)==0x00) group.long (0x88F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL17_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x88F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL17_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x88F0+0x08))&0x80000000)==0x00) group.long (0x88F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL17_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x88F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL17_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x88F0+0x0C))&0x80000000)==0x00) group.long (0x88F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL17_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x88F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL17_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8970))&0x80000000)==0x00) group.long 0x8970++0x03 line.long 0x00 "ACCESS_CTRL18,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8970++0x03 line.long 0x00 "ACCESS_CTRL18,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8970+0x04))&0x80000000)==0x00) group.long (0x8970+0x04)++0x03 line.long 0x00 "ACCESS_CTRL18_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8970+0x04)++0x03 line.long 0x00 "ACCESS_CTRL18_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8970+0x08))&0x80000000)==0x00) group.long (0x8970+0x08)++0x03 line.long 0x00 "ACCESS_CTRL18_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8970+0x08)++0x03 line.long 0x00 "ACCESS_CTRL18_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8970+0x0C))&0x80000000)==0x00) group.long (0x8970+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL18_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8970+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL18_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x89F0))&0x80000000)==0x00) group.long 0x89F0++0x03 line.long 0x00 "ACCESS_CTRL19,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x89F0++0x03 line.long 0x00 "ACCESS_CTRL19,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x89F0+0x04))&0x80000000)==0x00) group.long (0x89F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL19_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x89F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL19_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x89F0+0x08))&0x80000000)==0x00) group.long (0x89F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL19_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x89F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL19_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x89F0+0x0C))&0x80000000)==0x00) group.long (0x89F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL19_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x89F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL19_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8A70))&0x80000000)==0x00) group.long 0x8A70++0x03 line.long 0x00 "ACCESS_CTRL20,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8A70++0x03 line.long 0x00 "ACCESS_CTRL20,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8A70+0x04))&0x80000000)==0x00) group.long (0x8A70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL20_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8A70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL20_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8A70+0x08))&0x80000000)==0x00) group.long (0x8A70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL20_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8A70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL20_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8A70+0x0C))&0x80000000)==0x00) group.long (0x8A70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL20_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8A70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL20_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8AF0))&0x80000000)==0x00) group.long 0x8AF0++0x03 line.long 0x00 "ACCESS_CTRL21,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8AF0++0x03 line.long 0x00 "ACCESS_CTRL21,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8AF0+0x04))&0x80000000)==0x00) group.long (0x8AF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL21_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8AF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL21_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8AF0+0x08))&0x80000000)==0x00) group.long (0x8AF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL21_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8AF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL21_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8AF0+0x0C))&0x80000000)==0x00) group.long (0x8AF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL21_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8AF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL21_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8B70))&0x80000000)==0x00) group.long 0x8B70++0x03 line.long 0x00 "ACCESS_CTRL22,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8B70++0x03 line.long 0x00 "ACCESS_CTRL22,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8B70+0x04))&0x80000000)==0x00) group.long (0x8B70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL22_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8B70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL22_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8B70+0x08))&0x80000000)==0x00) group.long (0x8B70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL22_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8B70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL22_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8B70+0x0C))&0x80000000)==0x00) group.long (0x8B70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL22_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8B70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL22_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8BF0))&0x80000000)==0x00) group.long 0x8BF0++0x03 line.long 0x00 "ACCESS_CTRL23,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8BF0++0x03 line.long 0x00 "ACCESS_CTRL23,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8BF0+0x04))&0x80000000)==0x00) group.long (0x8BF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL23_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8BF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL23_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8BF0+0x08))&0x80000000)==0x00) group.long (0x8BF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL23_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8BF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL23_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8BF0+0x0C))&0x80000000)==0x00) group.long (0x8BF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL23_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8BF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL23_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8C70))&0x80000000)==0x00) group.long 0x8C70++0x03 line.long 0x00 "ACCESS_CTRL24,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8C70++0x03 line.long 0x00 "ACCESS_CTRL24,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8C70+0x04))&0x80000000)==0x00) group.long (0x8C70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL24_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8C70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL24_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8C70+0x08))&0x80000000)==0x00) group.long (0x8C70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL24_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8C70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL24_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8C70+0x0C))&0x80000000)==0x00) group.long (0x8C70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL24_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8C70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL24_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8CF0))&0x80000000)==0x00) group.long 0x8CF0++0x03 line.long 0x00 "ACCESS_CTRL25,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8CF0++0x03 line.long 0x00 "ACCESS_CTRL25,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8CF0+0x04))&0x80000000)==0x00) group.long (0x8CF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL25_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8CF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL25_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8CF0+0x08))&0x80000000)==0x00) group.long (0x8CF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL25_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8CF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL25_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8CF0+0x0C))&0x80000000)==0x00) group.long (0x8CF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL25_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8CF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL25_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8D70))&0x80000000)==0x00) group.long 0x8D70++0x03 line.long 0x00 "ACCESS_CTRL26,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8D70++0x03 line.long 0x00 "ACCESS_CTRL26,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8D70+0x04))&0x80000000)==0x00) group.long (0x8D70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL26_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8D70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL26_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8D70+0x08))&0x80000000)==0x00) group.long (0x8D70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL26_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8D70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL26_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8D70+0x0C))&0x80000000)==0x00) group.long (0x8D70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL26_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8D70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL26_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8DF0))&0x80000000)==0x00) group.long 0x8DF0++0x03 line.long 0x00 "ACCESS_CTRL27,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8DF0++0x03 line.long 0x00 "ACCESS_CTRL27,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8DF0+0x04))&0x80000000)==0x00) group.long (0x8DF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL27_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8DF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL27_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8DF0+0x08))&0x80000000)==0x00) group.long (0x8DF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL27_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8DF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL27_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8DF0+0x0C))&0x80000000)==0x00) group.long (0x8DF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL27_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8DF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL27_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8E70))&0x80000000)==0x00) group.long 0x8E70++0x03 line.long 0x00 "ACCESS_CTRL28,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8E70++0x03 line.long 0x00 "ACCESS_CTRL28,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8E70+0x04))&0x80000000)==0x00) group.long (0x8E70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL28_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8E70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL28_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8E70+0x08))&0x80000000)==0x00) group.long (0x8E70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL28_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8E70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL28_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8E70+0x0C))&0x80000000)==0x00) group.long (0x8E70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL28_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8E70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL28_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8EF0))&0x80000000)==0x00) group.long 0x8EF0++0x03 line.long 0x00 "ACCESS_CTRL29,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8EF0++0x03 line.long 0x00 "ACCESS_CTRL29,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8EF0+0x04))&0x80000000)==0x00) group.long (0x8EF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL29_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8EF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL29_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8EF0+0x08))&0x80000000)==0x00) group.long (0x8EF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL29_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8EF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL29_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8EF0+0x0C))&0x80000000)==0x00) group.long (0x8EF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL29_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8EF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL29_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8F70))&0x80000000)==0x00) group.long 0x8F70++0x03 line.long 0x00 "ACCESS_CTRL30,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8F70++0x03 line.long 0x00 "ACCESS_CTRL30,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8F70+0x04))&0x80000000)==0x00) group.long (0x8F70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL30_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8F70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL30_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8F70+0x08))&0x80000000)==0x00) group.long (0x8F70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL30_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8F70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL30_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8F70+0x0C))&0x80000000)==0x00) group.long (0x8F70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL30_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8F70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL30_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8FF0))&0x80000000)==0x00) group.long 0x8FF0++0x03 line.long 0x00 "ACCESS_CTRL31,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x8FF0++0x03 line.long 0x00 "ACCESS_CTRL31,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8FF0+0x04))&0x80000000)==0x00) group.long (0x8FF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL31_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8FF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL31_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8FF0+0x08))&0x80000000)==0x00) group.long (0x8FF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL31_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8FF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL31_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x8FF0+0x0C))&0x80000000)==0x00) group.long (0x8FF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL31_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8FF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL31_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9070))&0x80000000)==0x00) group.long 0x9070++0x03 line.long 0x00 "ACCESS_CTRL32,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9070++0x03 line.long 0x00 "ACCESS_CTRL32,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9070+0x04))&0x80000000)==0x00) group.long (0x9070+0x04)++0x03 line.long 0x00 "ACCESS_CTRL32_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9070+0x04)++0x03 line.long 0x00 "ACCESS_CTRL32_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9070+0x08))&0x80000000)==0x00) group.long (0x9070+0x08)++0x03 line.long 0x00 "ACCESS_CTRL32_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9070+0x08)++0x03 line.long 0x00 "ACCESS_CTRL32_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9070+0x0C))&0x80000000)==0x00) group.long (0x9070+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL32_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9070+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL32_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x90F0))&0x80000000)==0x00) group.long 0x90F0++0x03 line.long 0x00 "ACCESS_CTRL33,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x90F0++0x03 line.long 0x00 "ACCESS_CTRL33,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x90F0+0x04))&0x80000000)==0x00) group.long (0x90F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL33_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x90F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL33_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x90F0+0x08))&0x80000000)==0x00) group.long (0x90F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL33_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x90F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL33_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x90F0+0x0C))&0x80000000)==0x00) group.long (0x90F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL33_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x90F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL33_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9170))&0x80000000)==0x00) group.long 0x9170++0x03 line.long 0x00 "ACCESS_CTRL34,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9170++0x03 line.long 0x00 "ACCESS_CTRL34,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9170+0x04))&0x80000000)==0x00) group.long (0x9170+0x04)++0x03 line.long 0x00 "ACCESS_CTRL34_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9170+0x04)++0x03 line.long 0x00 "ACCESS_CTRL34_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9170+0x08))&0x80000000)==0x00) group.long (0x9170+0x08)++0x03 line.long 0x00 "ACCESS_CTRL34_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9170+0x08)++0x03 line.long 0x00 "ACCESS_CTRL34_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9170+0x0C))&0x80000000)==0x00) group.long (0x9170+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL34_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9170+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL34_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x91F0))&0x80000000)==0x00) group.long 0x91F0++0x03 line.long 0x00 "ACCESS_CTRL35,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x91F0++0x03 line.long 0x00 "ACCESS_CTRL35,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x91F0+0x04))&0x80000000)==0x00) group.long (0x91F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL35_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x91F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL35_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x91F0+0x08))&0x80000000)==0x00) group.long (0x91F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL35_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x91F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL35_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x91F0+0x0C))&0x80000000)==0x00) group.long (0x91F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL35_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x91F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL35_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9270))&0x80000000)==0x00) group.long 0x9270++0x03 line.long 0x00 "ACCESS_CTRL36,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9270++0x03 line.long 0x00 "ACCESS_CTRL36,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9270+0x04))&0x80000000)==0x00) group.long (0x9270+0x04)++0x03 line.long 0x00 "ACCESS_CTRL36_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9270+0x04)++0x03 line.long 0x00 "ACCESS_CTRL36_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9270+0x08))&0x80000000)==0x00) group.long (0x9270+0x08)++0x03 line.long 0x00 "ACCESS_CTRL36_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9270+0x08)++0x03 line.long 0x00 "ACCESS_CTRL36_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9270+0x0C))&0x80000000)==0x00) group.long (0x9270+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL36_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9270+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL36_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x92F0))&0x80000000)==0x00) group.long 0x92F0++0x03 line.long 0x00 "ACCESS_CTRL37,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x92F0++0x03 line.long 0x00 "ACCESS_CTRL37,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x92F0+0x04))&0x80000000)==0x00) group.long (0x92F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL37_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x92F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL37_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x92F0+0x08))&0x80000000)==0x00) group.long (0x92F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL37_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x92F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL37_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x92F0+0x0C))&0x80000000)==0x00) group.long (0x92F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL37_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x92F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL37_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9370))&0x80000000)==0x00) group.long 0x9370++0x03 line.long 0x00 "ACCESS_CTRL38,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9370++0x03 line.long 0x00 "ACCESS_CTRL38,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9370+0x04))&0x80000000)==0x00) group.long (0x9370+0x04)++0x03 line.long 0x00 "ACCESS_CTRL38_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9370+0x04)++0x03 line.long 0x00 "ACCESS_CTRL38_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9370+0x08))&0x80000000)==0x00) group.long (0x9370+0x08)++0x03 line.long 0x00 "ACCESS_CTRL38_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9370+0x08)++0x03 line.long 0x00 "ACCESS_CTRL38_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9370+0x0C))&0x80000000)==0x00) group.long (0x9370+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL38_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9370+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL38_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x93F0))&0x80000000)==0x00) group.long 0x93F0++0x03 line.long 0x00 "ACCESS_CTRL39,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x93F0++0x03 line.long 0x00 "ACCESS_CTRL39,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x93F0+0x04))&0x80000000)==0x00) group.long (0x93F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL39_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x93F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL39_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x93F0+0x08))&0x80000000)==0x00) group.long (0x93F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL39_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x93F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL39_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x93F0+0x0C))&0x80000000)==0x00) group.long (0x93F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL39_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x93F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL39_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9470))&0x80000000)==0x00) group.long 0x9470++0x03 line.long 0x00 "ACCESS_CTRL40,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9470++0x03 line.long 0x00 "ACCESS_CTRL40,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9470+0x04))&0x80000000)==0x00) group.long (0x9470+0x04)++0x03 line.long 0x00 "ACCESS_CTRL40_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9470+0x04)++0x03 line.long 0x00 "ACCESS_CTRL40_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9470+0x08))&0x80000000)==0x00) group.long (0x9470+0x08)++0x03 line.long 0x00 "ACCESS_CTRL40_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9470+0x08)++0x03 line.long 0x00 "ACCESS_CTRL40_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9470+0x0C))&0x80000000)==0x00) group.long (0x9470+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL40_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9470+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL40_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x94F0))&0x80000000)==0x00) group.long 0x94F0++0x03 line.long 0x00 "ACCESS_CTRL41,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x94F0++0x03 line.long 0x00 "ACCESS_CTRL41,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x94F0+0x04))&0x80000000)==0x00) group.long (0x94F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL41_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x94F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL41_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x94F0+0x08))&0x80000000)==0x00) group.long (0x94F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL41_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x94F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL41_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x94F0+0x0C))&0x80000000)==0x00) group.long (0x94F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL41_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x94F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL41_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9570))&0x80000000)==0x00) group.long 0x9570++0x03 line.long 0x00 "ACCESS_CTRL42,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9570++0x03 line.long 0x00 "ACCESS_CTRL42,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9570+0x04))&0x80000000)==0x00) group.long (0x9570+0x04)++0x03 line.long 0x00 "ACCESS_CTRL42_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9570+0x04)++0x03 line.long 0x00 "ACCESS_CTRL42_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9570+0x08))&0x80000000)==0x00) group.long (0x9570+0x08)++0x03 line.long 0x00 "ACCESS_CTRL42_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9570+0x08)++0x03 line.long 0x00 "ACCESS_CTRL42_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9570+0x0C))&0x80000000)==0x00) group.long (0x9570+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL42_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9570+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL42_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x95F0))&0x80000000)==0x00) group.long 0x95F0++0x03 line.long 0x00 "ACCESS_CTRL43,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x95F0++0x03 line.long 0x00 "ACCESS_CTRL43,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x95F0+0x04))&0x80000000)==0x00) group.long (0x95F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL43_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x95F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL43_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x95F0+0x08))&0x80000000)==0x00) group.long (0x95F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL43_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x95F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL43_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x95F0+0x0C))&0x80000000)==0x00) group.long (0x95F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL43_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x95F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL43_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9670))&0x80000000)==0x00) group.long 0x9670++0x03 line.long 0x00 "ACCESS_CTRL44,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9670++0x03 line.long 0x00 "ACCESS_CTRL44,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9670+0x04))&0x80000000)==0x00) group.long (0x9670+0x04)++0x03 line.long 0x00 "ACCESS_CTRL44_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9670+0x04)++0x03 line.long 0x00 "ACCESS_CTRL44_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9670+0x08))&0x80000000)==0x00) group.long (0x9670+0x08)++0x03 line.long 0x00 "ACCESS_CTRL44_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9670+0x08)++0x03 line.long 0x00 "ACCESS_CTRL44_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9670+0x0C))&0x80000000)==0x00) group.long (0x9670+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL44_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9670+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL44_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x96F0))&0x80000000)==0x00) group.long 0x96F0++0x03 line.long 0x00 "ACCESS_CTRL45,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x96F0++0x03 line.long 0x00 "ACCESS_CTRL45,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x96F0+0x04))&0x80000000)==0x00) group.long (0x96F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL45_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x96F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL45_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x96F0+0x08))&0x80000000)==0x00) group.long (0x96F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL45_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x96F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL45_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x96F0+0x0C))&0x80000000)==0x00) group.long (0x96F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL45_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x96F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL45_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9770))&0x80000000)==0x00) group.long 0x9770++0x03 line.long 0x00 "ACCESS_CTRL46,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9770++0x03 line.long 0x00 "ACCESS_CTRL46,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9770+0x04))&0x80000000)==0x00) group.long (0x9770+0x04)++0x03 line.long 0x00 "ACCESS_CTRL46_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9770+0x04)++0x03 line.long 0x00 "ACCESS_CTRL46_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9770+0x08))&0x80000000)==0x00) group.long (0x9770+0x08)++0x03 line.long 0x00 "ACCESS_CTRL46_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9770+0x08)++0x03 line.long 0x00 "ACCESS_CTRL46_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9770+0x0C))&0x80000000)==0x00) group.long (0x9770+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL46_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9770+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL46_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x97F0))&0x80000000)==0x00) group.long 0x97F0++0x03 line.long 0x00 "ACCESS_CTRL47,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x97F0++0x03 line.long 0x00 "ACCESS_CTRL47,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x97F0+0x04))&0x80000000)==0x00) group.long (0x97F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL47_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x97F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL47_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x97F0+0x08))&0x80000000)==0x00) group.long (0x97F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL47_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x97F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL47_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x97F0+0x0C))&0x80000000)==0x00) group.long (0x97F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL47_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x97F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL47_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9870))&0x80000000)==0x00) group.long 0x9870++0x03 line.long 0x00 "ACCESS_CTRL48,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9870++0x03 line.long 0x00 "ACCESS_CTRL48,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9870+0x04))&0x80000000)==0x00) group.long (0x9870+0x04)++0x03 line.long 0x00 "ACCESS_CTRL48_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9870+0x04)++0x03 line.long 0x00 "ACCESS_CTRL48_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9870+0x08))&0x80000000)==0x00) group.long (0x9870+0x08)++0x03 line.long 0x00 "ACCESS_CTRL48_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9870+0x08)++0x03 line.long 0x00 "ACCESS_CTRL48_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9870+0x0C))&0x80000000)==0x00) group.long (0x9870+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL48_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9870+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL48_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x98F0))&0x80000000)==0x00) group.long 0x98F0++0x03 line.long 0x00 "ACCESS_CTRL49,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x98F0++0x03 line.long 0x00 "ACCESS_CTRL49,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x98F0+0x04))&0x80000000)==0x00) group.long (0x98F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL49_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x98F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL49_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x98F0+0x08))&0x80000000)==0x00) group.long (0x98F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL49_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x98F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL49_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x98F0+0x0C))&0x80000000)==0x00) group.long (0x98F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL49_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x98F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL49_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9970))&0x80000000)==0x00) group.long 0x9970++0x03 line.long 0x00 "ACCESS_CTRL50,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9970++0x03 line.long 0x00 "ACCESS_CTRL50,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9970+0x04))&0x80000000)==0x00) group.long (0x9970+0x04)++0x03 line.long 0x00 "ACCESS_CTRL50_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9970+0x04)++0x03 line.long 0x00 "ACCESS_CTRL50_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9970+0x08))&0x80000000)==0x00) group.long (0x9970+0x08)++0x03 line.long 0x00 "ACCESS_CTRL50_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9970+0x08)++0x03 line.long 0x00 "ACCESS_CTRL50_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9970+0x0C))&0x80000000)==0x00) group.long (0x9970+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL50_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9970+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL50_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x99F0))&0x80000000)==0x00) group.long 0x99F0++0x03 line.long 0x00 "ACCESS_CTRL51,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x99F0++0x03 line.long 0x00 "ACCESS_CTRL51,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x99F0+0x04))&0x80000000)==0x00) group.long (0x99F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL51_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x99F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL51_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x99F0+0x08))&0x80000000)==0x00) group.long (0x99F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL51_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x99F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL51_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x99F0+0x0C))&0x80000000)==0x00) group.long (0x99F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL51_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x99F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL51_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9A70))&0x80000000)==0x00) group.long 0x9A70++0x03 line.long 0x00 "ACCESS_CTRL52,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9A70++0x03 line.long 0x00 "ACCESS_CTRL52,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9A70+0x04))&0x80000000)==0x00) group.long (0x9A70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL52_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9A70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL52_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9A70+0x08))&0x80000000)==0x00) group.long (0x9A70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL52_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9A70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL52_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9A70+0x0C))&0x80000000)==0x00) group.long (0x9A70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL52_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9A70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL52_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9AF0))&0x80000000)==0x00) group.long 0x9AF0++0x03 line.long 0x00 "ACCESS_CTRL53,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9AF0++0x03 line.long 0x00 "ACCESS_CTRL53,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9AF0+0x04))&0x80000000)==0x00) group.long (0x9AF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL53_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9AF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL53_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9AF0+0x08))&0x80000000)==0x00) group.long (0x9AF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL53_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9AF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL53_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9AF0+0x0C))&0x80000000)==0x00) group.long (0x9AF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL53_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9AF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL53_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9B70))&0x80000000)==0x00) group.long 0x9B70++0x03 line.long 0x00 "ACCESS_CTRL54,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9B70++0x03 line.long 0x00 "ACCESS_CTRL54,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9B70+0x04))&0x80000000)==0x00) group.long (0x9B70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL54_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9B70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL54_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9B70+0x08))&0x80000000)==0x00) group.long (0x9B70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL54_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9B70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL54_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9B70+0x0C))&0x80000000)==0x00) group.long (0x9B70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL54_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9B70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL54_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9BF0))&0x80000000)==0x00) group.long 0x9BF0++0x03 line.long 0x00 "ACCESS_CTRL55,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9BF0++0x03 line.long 0x00 "ACCESS_CTRL55,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9BF0+0x04))&0x80000000)==0x00) group.long (0x9BF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL55_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9BF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL55_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9BF0+0x08))&0x80000000)==0x00) group.long (0x9BF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL55_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9BF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL55_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9BF0+0x0C))&0x80000000)==0x00) group.long (0x9BF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL55_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9BF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL55_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9C70))&0x80000000)==0x00) group.long 0x9C70++0x03 line.long 0x00 "ACCESS_CTRL56,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9C70++0x03 line.long 0x00 "ACCESS_CTRL56,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9C70+0x04))&0x80000000)==0x00) group.long (0x9C70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL56_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9C70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL56_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9C70+0x08))&0x80000000)==0x00) group.long (0x9C70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL56_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9C70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL56_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9C70+0x0C))&0x80000000)==0x00) group.long (0x9C70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL56_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9C70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL56_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9CF0))&0x80000000)==0x00) group.long 0x9CF0++0x03 line.long 0x00 "ACCESS_CTRL57,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9CF0++0x03 line.long 0x00 "ACCESS_CTRL57,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9CF0+0x04))&0x80000000)==0x00) group.long (0x9CF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL57_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9CF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL57_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9CF0+0x08))&0x80000000)==0x00) group.long (0x9CF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL57_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9CF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL57_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9CF0+0x0C))&0x80000000)==0x00) group.long (0x9CF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL57_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9CF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL57_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9D70))&0x80000000)==0x00) group.long 0x9D70++0x03 line.long 0x00 "ACCESS_CTRL58,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9D70++0x03 line.long 0x00 "ACCESS_CTRL58,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9D70+0x04))&0x80000000)==0x00) group.long (0x9D70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL58_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9D70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL58_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9D70+0x08))&0x80000000)==0x00) group.long (0x9D70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL58_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9D70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL58_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9D70+0x0C))&0x80000000)==0x00) group.long (0x9D70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL58_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9D70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL58_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9DF0))&0x80000000)==0x00) group.long 0x9DF0++0x03 line.long 0x00 "ACCESS_CTRL59,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9DF0++0x03 line.long 0x00 "ACCESS_CTRL59,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9DF0+0x04))&0x80000000)==0x00) group.long (0x9DF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL59_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9DF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL59_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9DF0+0x08))&0x80000000)==0x00) group.long (0x9DF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL59_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9DF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL59_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9DF0+0x0C))&0x80000000)==0x00) group.long (0x9DF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL59_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9DF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL59_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9E70))&0x80000000)==0x00) group.long 0x9E70++0x03 line.long 0x00 "ACCESS_CTRL60,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9E70++0x03 line.long 0x00 "ACCESS_CTRL60,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9E70+0x04))&0x80000000)==0x00) group.long (0x9E70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL60_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9E70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL60_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9E70+0x08))&0x80000000)==0x00) group.long (0x9E70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL60_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9E70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL60_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9E70+0x0C))&0x80000000)==0x00) group.long (0x9E70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL60_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9E70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL60_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9EF0))&0x80000000)==0x00) group.long 0x9EF0++0x03 line.long 0x00 "ACCESS_CTRL61,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9EF0++0x03 line.long 0x00 "ACCESS_CTRL61,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9EF0+0x04))&0x80000000)==0x00) group.long (0x9EF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL61_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9EF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL61_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9EF0+0x08))&0x80000000)==0x00) group.long (0x9EF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL61_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9EF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL61_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9EF0+0x0C))&0x80000000)==0x00) group.long (0x9EF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL61_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9EF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL61_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9F70))&0x80000000)==0x00) group.long 0x9F70++0x03 line.long 0x00 "ACCESS_CTRL62,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9F70++0x03 line.long 0x00 "ACCESS_CTRL62,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9F70+0x04))&0x80000000)==0x00) group.long (0x9F70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL62_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9F70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL62_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9F70+0x08))&0x80000000)==0x00) group.long (0x9F70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL62_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9F70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL62_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9F70+0x0C))&0x80000000)==0x00) group.long (0x9F70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL62_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9F70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL62_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9FF0))&0x80000000)==0x00) group.long 0x9FF0++0x03 line.long 0x00 "ACCESS_CTRL63,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x9FF0++0x03 line.long 0x00 "ACCESS_CTRL63,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9FF0+0x04))&0x80000000)==0x00) group.long (0x9FF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL63_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9FF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL63_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9FF0+0x08))&0x80000000)==0x00) group.long (0x9FF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL63_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9FF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL63_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0x9FF0+0x0C))&0x80000000)==0x00) group.long (0x9FF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL63_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x9FF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL63_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA070))&0x80000000)==0x00) group.long 0xA070++0x03 line.long 0x00 "ACCESS_CTRL64,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA070++0x03 line.long 0x00 "ACCESS_CTRL64,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA070+0x04))&0x80000000)==0x00) group.long (0xA070+0x04)++0x03 line.long 0x00 "ACCESS_CTRL64_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA070+0x04)++0x03 line.long 0x00 "ACCESS_CTRL64_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA070+0x08))&0x80000000)==0x00) group.long (0xA070+0x08)++0x03 line.long 0x00 "ACCESS_CTRL64_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA070+0x08)++0x03 line.long 0x00 "ACCESS_CTRL64_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA070+0x0C))&0x80000000)==0x00) group.long (0xA070+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL64_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA070+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL64_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA0F0))&0x80000000)==0x00) group.long 0xA0F0++0x03 line.long 0x00 "ACCESS_CTRL65,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA0F0++0x03 line.long 0x00 "ACCESS_CTRL65,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA0F0+0x04))&0x80000000)==0x00) group.long (0xA0F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL65_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA0F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL65_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA0F0+0x08))&0x80000000)==0x00) group.long (0xA0F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL65_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA0F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL65_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA0F0+0x0C))&0x80000000)==0x00) group.long (0xA0F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL65_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA0F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL65_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA170))&0x80000000)==0x00) group.long 0xA170++0x03 line.long 0x00 "ACCESS_CTRL66,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA170++0x03 line.long 0x00 "ACCESS_CTRL66,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA170+0x04))&0x80000000)==0x00) group.long (0xA170+0x04)++0x03 line.long 0x00 "ACCESS_CTRL66_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA170+0x04)++0x03 line.long 0x00 "ACCESS_CTRL66_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA170+0x08))&0x80000000)==0x00) group.long (0xA170+0x08)++0x03 line.long 0x00 "ACCESS_CTRL66_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA170+0x08)++0x03 line.long 0x00 "ACCESS_CTRL66_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA170+0x0C))&0x80000000)==0x00) group.long (0xA170+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL66_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA170+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL66_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA1F0))&0x80000000)==0x00) group.long 0xA1F0++0x03 line.long 0x00 "ACCESS_CTRL67,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA1F0++0x03 line.long 0x00 "ACCESS_CTRL67,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA1F0+0x04))&0x80000000)==0x00) group.long (0xA1F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL67_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA1F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL67_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA1F0+0x08))&0x80000000)==0x00) group.long (0xA1F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL67_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA1F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL67_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA1F0+0x0C))&0x80000000)==0x00) group.long (0xA1F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL67_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA1F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL67_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA270))&0x80000000)==0x00) group.long 0xA270++0x03 line.long 0x00 "ACCESS_CTRL68,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA270++0x03 line.long 0x00 "ACCESS_CTRL68,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA270+0x04))&0x80000000)==0x00) group.long (0xA270+0x04)++0x03 line.long 0x00 "ACCESS_CTRL68_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA270+0x04)++0x03 line.long 0x00 "ACCESS_CTRL68_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA270+0x08))&0x80000000)==0x00) group.long (0xA270+0x08)++0x03 line.long 0x00 "ACCESS_CTRL68_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA270+0x08)++0x03 line.long 0x00 "ACCESS_CTRL68_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA270+0x0C))&0x80000000)==0x00) group.long (0xA270+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL68_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA270+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL68_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA2F0))&0x80000000)==0x00) group.long 0xA2F0++0x03 line.long 0x00 "ACCESS_CTRL69,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA2F0++0x03 line.long 0x00 "ACCESS_CTRL69,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA2F0+0x04))&0x80000000)==0x00) group.long (0xA2F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL69_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA2F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL69_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA2F0+0x08))&0x80000000)==0x00) group.long (0xA2F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL69_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA2F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL69_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA2F0+0x0C))&0x80000000)==0x00) group.long (0xA2F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL69_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA2F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL69_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA370))&0x80000000)==0x00) group.long 0xA370++0x03 line.long 0x00 "ACCESS_CTRL70,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA370++0x03 line.long 0x00 "ACCESS_CTRL70,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA370+0x04))&0x80000000)==0x00) group.long (0xA370+0x04)++0x03 line.long 0x00 "ACCESS_CTRL70_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA370+0x04)++0x03 line.long 0x00 "ACCESS_CTRL70_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA370+0x08))&0x80000000)==0x00) group.long (0xA370+0x08)++0x03 line.long 0x00 "ACCESS_CTRL70_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA370+0x08)++0x03 line.long 0x00 "ACCESS_CTRL70_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA370+0x0C))&0x80000000)==0x00) group.long (0xA370+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL70_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA370+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL70_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA3F0))&0x80000000)==0x00) group.long 0xA3F0++0x03 line.long 0x00 "ACCESS_CTRL71,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA3F0++0x03 line.long 0x00 "ACCESS_CTRL71,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA3F0+0x04))&0x80000000)==0x00) group.long (0xA3F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL71_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA3F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL71_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA3F0+0x08))&0x80000000)==0x00) group.long (0xA3F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL71_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA3F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL71_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA3F0+0x0C))&0x80000000)==0x00) group.long (0xA3F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL71_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA3F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL71_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA470))&0x80000000)==0x00) group.long 0xA470++0x03 line.long 0x00 "ACCESS_CTRL72,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA470++0x03 line.long 0x00 "ACCESS_CTRL72,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA470+0x04))&0x80000000)==0x00) group.long (0xA470+0x04)++0x03 line.long 0x00 "ACCESS_CTRL72_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA470+0x04)++0x03 line.long 0x00 "ACCESS_CTRL72_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA470+0x08))&0x80000000)==0x00) group.long (0xA470+0x08)++0x03 line.long 0x00 "ACCESS_CTRL72_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA470+0x08)++0x03 line.long 0x00 "ACCESS_CTRL72_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA470+0x0C))&0x80000000)==0x00) group.long (0xA470+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL72_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA470+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL72_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA4F0))&0x80000000)==0x00) group.long 0xA4F0++0x03 line.long 0x00 "ACCESS_CTRL73,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA4F0++0x03 line.long 0x00 "ACCESS_CTRL73,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA4F0+0x04))&0x80000000)==0x00) group.long (0xA4F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL73_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA4F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL73_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA4F0+0x08))&0x80000000)==0x00) group.long (0xA4F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL73_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA4F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL73_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA4F0+0x0C))&0x80000000)==0x00) group.long (0xA4F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL73_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA4F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL73_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA570))&0x80000000)==0x00) group.long 0xA570++0x03 line.long 0x00 "ACCESS_CTRL74,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA570++0x03 line.long 0x00 "ACCESS_CTRL74,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA570+0x04))&0x80000000)==0x00) group.long (0xA570+0x04)++0x03 line.long 0x00 "ACCESS_CTRL74_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA570+0x04)++0x03 line.long 0x00 "ACCESS_CTRL74_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA570+0x08))&0x80000000)==0x00) group.long (0xA570+0x08)++0x03 line.long 0x00 "ACCESS_CTRL74_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA570+0x08)++0x03 line.long 0x00 "ACCESS_CTRL74_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA570+0x0C))&0x80000000)==0x00) group.long (0xA570+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL74_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA570+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL74_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA5F0))&0x80000000)==0x00) group.long 0xA5F0++0x03 line.long 0x00 "ACCESS_CTRL75,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA5F0++0x03 line.long 0x00 "ACCESS_CTRL75,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA5F0+0x04))&0x80000000)==0x00) group.long (0xA5F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL75_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA5F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL75_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA5F0+0x08))&0x80000000)==0x00) group.long (0xA5F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL75_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA5F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL75_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA5F0+0x0C))&0x80000000)==0x00) group.long (0xA5F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL75_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA5F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL75_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA670))&0x80000000)==0x00) group.long 0xA670++0x03 line.long 0x00 "ACCESS_CTRL76,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA670++0x03 line.long 0x00 "ACCESS_CTRL76,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA670+0x04))&0x80000000)==0x00) group.long (0xA670+0x04)++0x03 line.long 0x00 "ACCESS_CTRL76_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA670+0x04)++0x03 line.long 0x00 "ACCESS_CTRL76_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA670+0x08))&0x80000000)==0x00) group.long (0xA670+0x08)++0x03 line.long 0x00 "ACCESS_CTRL76_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA670+0x08)++0x03 line.long 0x00 "ACCESS_CTRL76_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA670+0x0C))&0x80000000)==0x00) group.long (0xA670+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL76_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA670+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL76_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA6F0))&0x80000000)==0x00) group.long 0xA6F0++0x03 line.long 0x00 "ACCESS_CTRL77,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA6F0++0x03 line.long 0x00 "ACCESS_CTRL77,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA6F0+0x04))&0x80000000)==0x00) group.long (0xA6F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL77_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA6F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL77_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA6F0+0x08))&0x80000000)==0x00) group.long (0xA6F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL77_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA6F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL77_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA6F0+0x0C))&0x80000000)==0x00) group.long (0xA6F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL77_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA6F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL77_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA770))&0x80000000)==0x00) group.long 0xA770++0x03 line.long 0x00 "ACCESS_CTRL78,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA770++0x03 line.long 0x00 "ACCESS_CTRL78,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA770+0x04))&0x80000000)==0x00) group.long (0xA770+0x04)++0x03 line.long 0x00 "ACCESS_CTRL78_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA770+0x04)++0x03 line.long 0x00 "ACCESS_CTRL78_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA770+0x08))&0x80000000)==0x00) group.long (0xA770+0x08)++0x03 line.long 0x00 "ACCESS_CTRL78_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA770+0x08)++0x03 line.long 0x00 "ACCESS_CTRL78_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA770+0x0C))&0x80000000)==0x00) group.long (0xA770+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL78_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA770+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL78_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA7F0))&0x80000000)==0x00) group.long 0xA7F0++0x03 line.long 0x00 "ACCESS_CTRL79,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA7F0++0x03 line.long 0x00 "ACCESS_CTRL79,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA7F0+0x04))&0x80000000)==0x00) group.long (0xA7F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL79_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA7F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL79_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA7F0+0x08))&0x80000000)==0x00) group.long (0xA7F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL79_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA7F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL79_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA7F0+0x0C))&0x80000000)==0x00) group.long (0xA7F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL79_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA7F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL79_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA870))&0x80000000)==0x00) group.long 0xA870++0x03 line.long 0x00 "ACCESS_CTRL80,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA870++0x03 line.long 0x00 "ACCESS_CTRL80,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA870+0x04))&0x80000000)==0x00) group.long (0xA870+0x04)++0x03 line.long 0x00 "ACCESS_CTRL80_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA870+0x04)++0x03 line.long 0x00 "ACCESS_CTRL80_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA870+0x08))&0x80000000)==0x00) group.long (0xA870+0x08)++0x03 line.long 0x00 "ACCESS_CTRL80_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA870+0x08)++0x03 line.long 0x00 "ACCESS_CTRL80_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA870+0x0C))&0x80000000)==0x00) group.long (0xA870+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL80_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA870+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL80_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA8F0))&0x80000000)==0x00) group.long 0xA8F0++0x03 line.long 0x00 "ACCESS_CTRL81,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA8F0++0x03 line.long 0x00 "ACCESS_CTRL81,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA8F0+0x04))&0x80000000)==0x00) group.long (0xA8F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL81_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA8F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL81_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA8F0+0x08))&0x80000000)==0x00) group.long (0xA8F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL81_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA8F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL81_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA8F0+0x0C))&0x80000000)==0x00) group.long (0xA8F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL81_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA8F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL81_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA970))&0x80000000)==0x00) group.long 0xA970++0x03 line.long 0x00 "ACCESS_CTRL82,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA970++0x03 line.long 0x00 "ACCESS_CTRL82,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA970+0x04))&0x80000000)==0x00) group.long (0xA970+0x04)++0x03 line.long 0x00 "ACCESS_CTRL82_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA970+0x04)++0x03 line.long 0x00 "ACCESS_CTRL82_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA970+0x08))&0x80000000)==0x00) group.long (0xA970+0x08)++0x03 line.long 0x00 "ACCESS_CTRL82_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA970+0x08)++0x03 line.long 0x00 "ACCESS_CTRL82_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA970+0x0C))&0x80000000)==0x00) group.long (0xA970+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL82_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA970+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL82_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA9F0))&0x80000000)==0x00) group.long 0xA9F0++0x03 line.long 0x00 "ACCESS_CTRL83,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xA9F0++0x03 line.long 0x00 "ACCESS_CTRL83,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA9F0+0x04))&0x80000000)==0x00) group.long (0xA9F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL83_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA9F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL83_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA9F0+0x08))&0x80000000)==0x00) group.long (0xA9F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL83_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA9F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL83_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xA9F0+0x0C))&0x80000000)==0x00) group.long (0xA9F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL83_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xA9F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL83_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAA70))&0x80000000)==0x00) group.long 0xAA70++0x03 line.long 0x00 "ACCESS_CTRL84,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xAA70++0x03 line.long 0x00 "ACCESS_CTRL84,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAA70+0x04))&0x80000000)==0x00) group.long (0xAA70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL84_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAA70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL84_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAA70+0x08))&0x80000000)==0x00) group.long (0xAA70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL84_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAA70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL84_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAA70+0x0C))&0x80000000)==0x00) group.long (0xAA70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL84_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAA70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL84_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAAF0))&0x80000000)==0x00) group.long 0xAAF0++0x03 line.long 0x00 "ACCESS_CTRL85,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xAAF0++0x03 line.long 0x00 "ACCESS_CTRL85,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAAF0+0x04))&0x80000000)==0x00) group.long (0xAAF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL85_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAAF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL85_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAAF0+0x08))&0x80000000)==0x00) group.long (0xAAF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL85_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAAF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL85_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAAF0+0x0C))&0x80000000)==0x00) group.long (0xAAF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL85_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAAF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL85_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAB70))&0x80000000)==0x00) group.long 0xAB70++0x03 line.long 0x00 "ACCESS_CTRL86,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xAB70++0x03 line.long 0x00 "ACCESS_CTRL86,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAB70+0x04))&0x80000000)==0x00) group.long (0xAB70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL86_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAB70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL86_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAB70+0x08))&0x80000000)==0x00) group.long (0xAB70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL86_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAB70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL86_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAB70+0x0C))&0x80000000)==0x00) group.long (0xAB70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL86_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAB70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL86_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xABF0))&0x80000000)==0x00) group.long 0xABF0++0x03 line.long 0x00 "ACCESS_CTRL87,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xABF0++0x03 line.long 0x00 "ACCESS_CTRL87,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xABF0+0x04))&0x80000000)==0x00) group.long (0xABF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL87_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xABF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL87_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xABF0+0x08))&0x80000000)==0x00) group.long (0xABF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL87_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xABF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL87_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xABF0+0x0C))&0x80000000)==0x00) group.long (0xABF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL87_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xABF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL87_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAC70))&0x80000000)==0x00) group.long 0xAC70++0x03 line.long 0x00 "ACCESS_CTRL88,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xAC70++0x03 line.long 0x00 "ACCESS_CTRL88,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAC70+0x04))&0x80000000)==0x00) group.long (0xAC70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL88_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAC70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL88_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAC70+0x08))&0x80000000)==0x00) group.long (0xAC70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL88_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAC70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL88_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAC70+0x0C))&0x80000000)==0x00) group.long (0xAC70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL88_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAC70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL88_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xACF0))&0x80000000)==0x00) group.long 0xACF0++0x03 line.long 0x00 "ACCESS_CTRL89,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xACF0++0x03 line.long 0x00 "ACCESS_CTRL89,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xACF0+0x04))&0x80000000)==0x00) group.long (0xACF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL89_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xACF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL89_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xACF0+0x08))&0x80000000)==0x00) group.long (0xACF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL89_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xACF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL89_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xACF0+0x0C))&0x80000000)==0x00) group.long (0xACF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL89_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xACF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL89_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAD70))&0x80000000)==0x00) group.long 0xAD70++0x03 line.long 0x00 "ACCESS_CTRL90,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xAD70++0x03 line.long 0x00 "ACCESS_CTRL90,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAD70+0x04))&0x80000000)==0x00) group.long (0xAD70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL90_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAD70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL90_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAD70+0x08))&0x80000000)==0x00) group.long (0xAD70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL90_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAD70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL90_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAD70+0x0C))&0x80000000)==0x00) group.long (0xAD70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL90_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAD70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL90_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xADF0))&0x80000000)==0x00) group.long 0xADF0++0x03 line.long 0x00 "ACCESS_CTRL91,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xADF0++0x03 line.long 0x00 "ACCESS_CTRL91,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xADF0+0x04))&0x80000000)==0x00) group.long (0xADF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL91_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xADF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL91_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xADF0+0x08))&0x80000000)==0x00) group.long (0xADF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL91_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xADF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL91_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xADF0+0x0C))&0x80000000)==0x00) group.long (0xADF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL91_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xADF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL91_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAE70))&0x80000000)==0x00) group.long 0xAE70++0x03 line.long 0x00 "ACCESS_CTRL92,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xAE70++0x03 line.long 0x00 "ACCESS_CTRL92,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAE70+0x04))&0x80000000)==0x00) group.long (0xAE70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL92_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAE70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL92_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAE70+0x08))&0x80000000)==0x00) group.long (0xAE70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL92_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAE70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL92_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAE70+0x0C))&0x80000000)==0x00) group.long (0xAE70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL92_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAE70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL92_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAEF0))&0x80000000)==0x00) group.long 0xAEF0++0x03 line.long 0x00 "ACCESS_CTRL93,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xAEF0++0x03 line.long 0x00 "ACCESS_CTRL93,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAEF0+0x04))&0x80000000)==0x00) group.long (0xAEF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL93_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAEF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL93_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAEF0+0x08))&0x80000000)==0x00) group.long (0xAEF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL93_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAEF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL93_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAEF0+0x0C))&0x80000000)==0x00) group.long (0xAEF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL93_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAEF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL93_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAF70))&0x80000000)==0x00) group.long 0xAF70++0x03 line.long 0x00 "ACCESS_CTRL94,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xAF70++0x03 line.long 0x00 "ACCESS_CTRL94,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAF70+0x04))&0x80000000)==0x00) group.long (0xAF70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL94_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAF70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL94_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAF70+0x08))&0x80000000)==0x00) group.long (0xAF70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL94_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAF70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL94_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAF70+0x0C))&0x80000000)==0x00) group.long (0xAF70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL94_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAF70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL94_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAFF0))&0x80000000)==0x00) group.long 0xAFF0++0x03 line.long 0x00 "ACCESS_CTRL95,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xAFF0++0x03 line.long 0x00 "ACCESS_CTRL95,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAFF0+0x04))&0x80000000)==0x00) group.long (0xAFF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL95_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAFF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL95_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAFF0+0x08))&0x80000000)==0x00) group.long (0xAFF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL95_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAFF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL95_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xAFF0+0x0C))&0x80000000)==0x00) group.long (0xAFF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL95_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xAFF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL95_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB070))&0x80000000)==0x00) group.long 0xB070++0x03 line.long 0x00 "ACCESS_CTRL96,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB070++0x03 line.long 0x00 "ACCESS_CTRL96,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB070+0x04))&0x80000000)==0x00) group.long (0xB070+0x04)++0x03 line.long 0x00 "ACCESS_CTRL96_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB070+0x04)++0x03 line.long 0x00 "ACCESS_CTRL96_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB070+0x08))&0x80000000)==0x00) group.long (0xB070+0x08)++0x03 line.long 0x00 "ACCESS_CTRL96_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB070+0x08)++0x03 line.long 0x00 "ACCESS_CTRL96_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB070+0x0C))&0x80000000)==0x00) group.long (0xB070+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL96_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB070+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL96_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB0F0))&0x80000000)==0x00) group.long 0xB0F0++0x03 line.long 0x00 "ACCESS_CTRL97,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB0F0++0x03 line.long 0x00 "ACCESS_CTRL97,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB0F0+0x04))&0x80000000)==0x00) group.long (0xB0F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL97_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB0F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL97_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB0F0+0x08))&0x80000000)==0x00) group.long (0xB0F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL97_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB0F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL97_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB0F0+0x0C))&0x80000000)==0x00) group.long (0xB0F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL97_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB0F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL97_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB170))&0x80000000)==0x00) group.long 0xB170++0x03 line.long 0x00 "ACCESS_CTRL98,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB170++0x03 line.long 0x00 "ACCESS_CTRL98,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB170+0x04))&0x80000000)==0x00) group.long (0xB170+0x04)++0x03 line.long 0x00 "ACCESS_CTRL98_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB170+0x04)++0x03 line.long 0x00 "ACCESS_CTRL98_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB170+0x08))&0x80000000)==0x00) group.long (0xB170+0x08)++0x03 line.long 0x00 "ACCESS_CTRL98_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB170+0x08)++0x03 line.long 0x00 "ACCESS_CTRL98_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB170+0x0C))&0x80000000)==0x00) group.long (0xB170+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL98_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB170+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL98_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB1F0))&0x80000000)==0x00) group.long 0xB1F0++0x03 line.long 0x00 "ACCESS_CTRL99,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB1F0++0x03 line.long 0x00 "ACCESS_CTRL99,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB1F0+0x04))&0x80000000)==0x00) group.long (0xB1F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL99_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB1F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL99_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB1F0+0x08))&0x80000000)==0x00) group.long (0xB1F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL99_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB1F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL99_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB1F0+0x0C))&0x80000000)==0x00) group.long (0xB1F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL99_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB1F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL99_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB270))&0x80000000)==0x00) group.long 0xB270++0x03 line.long 0x00 "ACCESS_CTRL100,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB270++0x03 line.long 0x00 "ACCESS_CTRL100,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB270+0x04))&0x80000000)==0x00) group.long (0xB270+0x04)++0x03 line.long 0x00 "ACCESS_CTRL100_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB270+0x04)++0x03 line.long 0x00 "ACCESS_CTRL100_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB270+0x08))&0x80000000)==0x00) group.long (0xB270+0x08)++0x03 line.long 0x00 "ACCESS_CTRL100_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB270+0x08)++0x03 line.long 0x00 "ACCESS_CTRL100_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB270+0x0C))&0x80000000)==0x00) group.long (0xB270+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL100_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB270+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL100_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB2F0))&0x80000000)==0x00) group.long 0xB2F0++0x03 line.long 0x00 "ACCESS_CTRL101,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB2F0++0x03 line.long 0x00 "ACCESS_CTRL101,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB2F0+0x04))&0x80000000)==0x00) group.long (0xB2F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL101_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB2F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL101_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB2F0+0x08))&0x80000000)==0x00) group.long (0xB2F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL101_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB2F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL101_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB2F0+0x0C))&0x80000000)==0x00) group.long (0xB2F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL101_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB2F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL101_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB370))&0x80000000)==0x00) group.long 0xB370++0x03 line.long 0x00 "ACCESS_CTRL102,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB370++0x03 line.long 0x00 "ACCESS_CTRL102,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB370+0x04))&0x80000000)==0x00) group.long (0xB370+0x04)++0x03 line.long 0x00 "ACCESS_CTRL102_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB370+0x04)++0x03 line.long 0x00 "ACCESS_CTRL102_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB370+0x08))&0x80000000)==0x00) group.long (0xB370+0x08)++0x03 line.long 0x00 "ACCESS_CTRL102_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB370+0x08)++0x03 line.long 0x00 "ACCESS_CTRL102_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB370+0x0C))&0x80000000)==0x00) group.long (0xB370+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL102_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB370+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL102_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB3F0))&0x80000000)==0x00) group.long 0xB3F0++0x03 line.long 0x00 "ACCESS_CTRL103,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB3F0++0x03 line.long 0x00 "ACCESS_CTRL103,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB3F0+0x04))&0x80000000)==0x00) group.long (0xB3F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL103_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB3F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL103_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB3F0+0x08))&0x80000000)==0x00) group.long (0xB3F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL103_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB3F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL103_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB3F0+0x0C))&0x80000000)==0x00) group.long (0xB3F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL103_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB3F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL103_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB470))&0x80000000)==0x00) group.long 0xB470++0x03 line.long 0x00 "ACCESS_CTRL104,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB470++0x03 line.long 0x00 "ACCESS_CTRL104,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB470+0x04))&0x80000000)==0x00) group.long (0xB470+0x04)++0x03 line.long 0x00 "ACCESS_CTRL104_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB470+0x04)++0x03 line.long 0x00 "ACCESS_CTRL104_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB470+0x08))&0x80000000)==0x00) group.long (0xB470+0x08)++0x03 line.long 0x00 "ACCESS_CTRL104_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB470+0x08)++0x03 line.long 0x00 "ACCESS_CTRL104_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB470+0x0C))&0x80000000)==0x00) group.long (0xB470+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL104_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB470+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL104_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB4F0))&0x80000000)==0x00) group.long 0xB4F0++0x03 line.long 0x00 "ACCESS_CTRL105,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB4F0++0x03 line.long 0x00 "ACCESS_CTRL105,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB4F0+0x04))&0x80000000)==0x00) group.long (0xB4F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL105_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB4F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL105_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB4F0+0x08))&0x80000000)==0x00) group.long (0xB4F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL105_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB4F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL105_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB4F0+0x0C))&0x80000000)==0x00) group.long (0xB4F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL105_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB4F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL105_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB570))&0x80000000)==0x00) group.long 0xB570++0x03 line.long 0x00 "ACCESS_CTRL106,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB570++0x03 line.long 0x00 "ACCESS_CTRL106,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB570+0x04))&0x80000000)==0x00) group.long (0xB570+0x04)++0x03 line.long 0x00 "ACCESS_CTRL106_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB570+0x04)++0x03 line.long 0x00 "ACCESS_CTRL106_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB570+0x08))&0x80000000)==0x00) group.long (0xB570+0x08)++0x03 line.long 0x00 "ACCESS_CTRL106_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB570+0x08)++0x03 line.long 0x00 "ACCESS_CTRL106_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB570+0x0C))&0x80000000)==0x00) group.long (0xB570+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL106_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB570+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL106_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB5F0))&0x80000000)==0x00) group.long 0xB5F0++0x03 line.long 0x00 "ACCESS_CTRL107,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB5F0++0x03 line.long 0x00 "ACCESS_CTRL107,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB5F0+0x04))&0x80000000)==0x00) group.long (0xB5F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL107_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB5F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL107_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB5F0+0x08))&0x80000000)==0x00) group.long (0xB5F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL107_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB5F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL107_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB5F0+0x0C))&0x80000000)==0x00) group.long (0xB5F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL107_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB5F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL107_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB670))&0x80000000)==0x00) group.long 0xB670++0x03 line.long 0x00 "ACCESS_CTRL108,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB670++0x03 line.long 0x00 "ACCESS_CTRL108,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB670+0x04))&0x80000000)==0x00) group.long (0xB670+0x04)++0x03 line.long 0x00 "ACCESS_CTRL108_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB670+0x04)++0x03 line.long 0x00 "ACCESS_CTRL108_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB670+0x08))&0x80000000)==0x00) group.long (0xB670+0x08)++0x03 line.long 0x00 "ACCESS_CTRL108_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB670+0x08)++0x03 line.long 0x00 "ACCESS_CTRL108_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB670+0x0C))&0x80000000)==0x00) group.long (0xB670+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL108_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB670+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL108_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB6F0))&0x80000000)==0x00) group.long 0xB6F0++0x03 line.long 0x00 "ACCESS_CTRL109,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB6F0++0x03 line.long 0x00 "ACCESS_CTRL109,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB6F0+0x04))&0x80000000)==0x00) group.long (0xB6F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL109_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB6F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL109_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB6F0+0x08))&0x80000000)==0x00) group.long (0xB6F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL109_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB6F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL109_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB6F0+0x0C))&0x80000000)==0x00) group.long (0xB6F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL109_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB6F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL109_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB770))&0x80000000)==0x00) group.long 0xB770++0x03 line.long 0x00 "ACCESS_CTRL110,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB770++0x03 line.long 0x00 "ACCESS_CTRL110,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB770+0x04))&0x80000000)==0x00) group.long (0xB770+0x04)++0x03 line.long 0x00 "ACCESS_CTRL110_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB770+0x04)++0x03 line.long 0x00 "ACCESS_CTRL110_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB770+0x08))&0x80000000)==0x00) group.long (0xB770+0x08)++0x03 line.long 0x00 "ACCESS_CTRL110_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB770+0x08)++0x03 line.long 0x00 "ACCESS_CTRL110_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB770+0x0C))&0x80000000)==0x00) group.long (0xB770+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL110_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB770+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL110_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB7F0))&0x80000000)==0x00) group.long 0xB7F0++0x03 line.long 0x00 "ACCESS_CTRL111,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB7F0++0x03 line.long 0x00 "ACCESS_CTRL111,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB7F0+0x04))&0x80000000)==0x00) group.long (0xB7F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL111_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB7F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL111_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB7F0+0x08))&0x80000000)==0x00) group.long (0xB7F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL111_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB7F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL111_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB7F0+0x0C))&0x80000000)==0x00) group.long (0xB7F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL111_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB7F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL111_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB870))&0x80000000)==0x00) group.long 0xB870++0x03 line.long 0x00 "ACCESS_CTRL112,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB870++0x03 line.long 0x00 "ACCESS_CTRL112,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB870+0x04))&0x80000000)==0x00) group.long (0xB870+0x04)++0x03 line.long 0x00 "ACCESS_CTRL112_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB870+0x04)++0x03 line.long 0x00 "ACCESS_CTRL112_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB870+0x08))&0x80000000)==0x00) group.long (0xB870+0x08)++0x03 line.long 0x00 "ACCESS_CTRL112_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB870+0x08)++0x03 line.long 0x00 "ACCESS_CTRL112_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB870+0x0C))&0x80000000)==0x00) group.long (0xB870+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL112_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB870+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL112_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB8F0))&0x80000000)==0x00) group.long 0xB8F0++0x03 line.long 0x00 "ACCESS_CTRL113,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB8F0++0x03 line.long 0x00 "ACCESS_CTRL113,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB8F0+0x04))&0x80000000)==0x00) group.long (0xB8F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL113_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB8F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL113_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB8F0+0x08))&0x80000000)==0x00) group.long (0xB8F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL113_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB8F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL113_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB8F0+0x0C))&0x80000000)==0x00) group.long (0xB8F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL113_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB8F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL113_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB970))&0x80000000)==0x00) group.long 0xB970++0x03 line.long 0x00 "ACCESS_CTRL114,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB970++0x03 line.long 0x00 "ACCESS_CTRL114,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB970+0x04))&0x80000000)==0x00) group.long (0xB970+0x04)++0x03 line.long 0x00 "ACCESS_CTRL114_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB970+0x04)++0x03 line.long 0x00 "ACCESS_CTRL114_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB970+0x08))&0x80000000)==0x00) group.long (0xB970+0x08)++0x03 line.long 0x00 "ACCESS_CTRL114_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB970+0x08)++0x03 line.long 0x00 "ACCESS_CTRL114_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB970+0x0C))&0x80000000)==0x00) group.long (0xB970+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL114_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB970+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL114_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB9F0))&0x80000000)==0x00) group.long 0xB9F0++0x03 line.long 0x00 "ACCESS_CTRL115,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xB9F0++0x03 line.long 0x00 "ACCESS_CTRL115,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB9F0+0x04))&0x80000000)==0x00) group.long (0xB9F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL115_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB9F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL115_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB9F0+0x08))&0x80000000)==0x00) group.long (0xB9F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL115_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB9F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL115_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xB9F0+0x0C))&0x80000000)==0x00) group.long (0xB9F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL115_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xB9F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL115_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBA70))&0x80000000)==0x00) group.long 0xBA70++0x03 line.long 0x00 "ACCESS_CTRL116,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xBA70++0x03 line.long 0x00 "ACCESS_CTRL116,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBA70+0x04))&0x80000000)==0x00) group.long (0xBA70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL116_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBA70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL116_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBA70+0x08))&0x80000000)==0x00) group.long (0xBA70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL116_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBA70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL116_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBA70+0x0C))&0x80000000)==0x00) group.long (0xBA70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL116_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBA70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL116_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBAF0))&0x80000000)==0x00) group.long 0xBAF0++0x03 line.long 0x00 "ACCESS_CTRL117,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xBAF0++0x03 line.long 0x00 "ACCESS_CTRL117,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBAF0+0x04))&0x80000000)==0x00) group.long (0xBAF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL117_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBAF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL117_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBAF0+0x08))&0x80000000)==0x00) group.long (0xBAF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL117_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBAF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL117_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBAF0+0x0C))&0x80000000)==0x00) group.long (0xBAF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL117_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBAF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL117_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBB70))&0x80000000)==0x00) group.long 0xBB70++0x03 line.long 0x00 "ACCESS_CTRL118,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xBB70++0x03 line.long 0x00 "ACCESS_CTRL118,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBB70+0x04))&0x80000000)==0x00) group.long (0xBB70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL118_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBB70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL118_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBB70+0x08))&0x80000000)==0x00) group.long (0xBB70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL118_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBB70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL118_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBB70+0x0C))&0x80000000)==0x00) group.long (0xBB70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL118_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBB70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL118_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBBF0))&0x80000000)==0x00) group.long 0xBBF0++0x03 line.long 0x00 "ACCESS_CTRL119,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xBBF0++0x03 line.long 0x00 "ACCESS_CTRL119,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBBF0+0x04))&0x80000000)==0x00) group.long (0xBBF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL119_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBBF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL119_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBBF0+0x08))&0x80000000)==0x00) group.long (0xBBF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL119_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBBF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL119_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBBF0+0x0C))&0x80000000)==0x00) group.long (0xBBF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL119_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBBF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL119_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBC70))&0x80000000)==0x00) group.long 0xBC70++0x03 line.long 0x00 "ACCESS_CTRL120,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xBC70++0x03 line.long 0x00 "ACCESS_CTRL120,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBC70+0x04))&0x80000000)==0x00) group.long (0xBC70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL120_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBC70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL120_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBC70+0x08))&0x80000000)==0x00) group.long (0xBC70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL120_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBC70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL120_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBC70+0x0C))&0x80000000)==0x00) group.long (0xBC70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL120_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBC70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL120_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBCF0))&0x80000000)==0x00) group.long 0xBCF0++0x03 line.long 0x00 "ACCESS_CTRL121,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xBCF0++0x03 line.long 0x00 "ACCESS_CTRL121,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBCF0+0x04))&0x80000000)==0x00) group.long (0xBCF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL121_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBCF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL121_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBCF0+0x08))&0x80000000)==0x00) group.long (0xBCF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL121_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBCF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL121_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBCF0+0x0C))&0x80000000)==0x00) group.long (0xBCF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL121_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBCF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL121_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBD70))&0x80000000)==0x00) group.long 0xBD70++0x03 line.long 0x00 "ACCESS_CTRL122,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xBD70++0x03 line.long 0x00 "ACCESS_CTRL122,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBD70+0x04))&0x80000000)==0x00) group.long (0xBD70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL122_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBD70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL122_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBD70+0x08))&0x80000000)==0x00) group.long (0xBD70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL122_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBD70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL122_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBD70+0x0C))&0x80000000)==0x00) group.long (0xBD70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL122_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBD70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL122_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBDF0))&0x80000000)==0x00) group.long 0xBDF0++0x03 line.long 0x00 "ACCESS_CTRL123,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xBDF0++0x03 line.long 0x00 "ACCESS_CTRL123,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBDF0+0x04))&0x80000000)==0x00) group.long (0xBDF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL123_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBDF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL123_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBDF0+0x08))&0x80000000)==0x00) group.long (0xBDF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL123_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBDF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL123_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBDF0+0x0C))&0x80000000)==0x00) group.long (0xBDF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL123_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBDF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL123_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBE70))&0x80000000)==0x00) group.long 0xBE70++0x03 line.long 0x00 "ACCESS_CTRL124,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xBE70++0x03 line.long 0x00 "ACCESS_CTRL124,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBE70+0x04))&0x80000000)==0x00) group.long (0xBE70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL124_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBE70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL124_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBE70+0x08))&0x80000000)==0x00) group.long (0xBE70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL124_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBE70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL124_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBE70+0x0C))&0x80000000)==0x00) group.long (0xBE70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL124_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBE70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL124_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBEF0))&0x80000000)==0x00) group.long 0xBEF0++0x03 line.long 0x00 "ACCESS_CTRL125,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xBEF0++0x03 line.long 0x00 "ACCESS_CTRL125,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBEF0+0x04))&0x80000000)==0x00) group.long (0xBEF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL125_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBEF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL125_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBEF0+0x08))&0x80000000)==0x00) group.long (0xBEF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL125_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBEF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL125_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBEF0+0x0C))&0x80000000)==0x00) group.long (0xBEF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL125_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBEF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL125_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBF70))&0x80000000)==0x00) group.long 0xBF70++0x03 line.long 0x00 "ACCESS_CTRL126,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xBF70++0x03 line.long 0x00 "ACCESS_CTRL126,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBF70+0x04))&0x80000000)==0x00) group.long (0xBF70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL126_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBF70+0x04)++0x03 line.long 0x00 "ACCESS_CTRL126_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBF70+0x08))&0x80000000)==0x00) group.long (0xBF70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL126_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBF70+0x08)++0x03 line.long 0x00 "ACCESS_CTRL126_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBF70+0x0C))&0x80000000)==0x00) group.long (0xBF70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL126_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBF70+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL126_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBFF0))&0x80000000)==0x00) group.long 0xBFF0++0x03 line.long 0x00 "ACCESS_CTRL127,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xBFF0++0x03 line.long 0x00 "ACCESS_CTRL127,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBFF0+0x04))&0x80000000)==0x00) group.long (0xBFF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL127_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBFF0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL127_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBFF0+0x08))&0x80000000)==0x00) group.long (0xBFF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL127_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBFF0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL127_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xBFF0+0x0C))&0x80000000)==0x00) group.long (0xBFF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL127_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xBFF0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL127_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC070))&0x80000000)==0x00) group.long 0xC070++0x03 line.long 0x00 "ACCESS_CTRL128,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC070++0x03 line.long 0x00 "ACCESS_CTRL128,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC070+0x04))&0x80000000)==0x00) group.long (0xC070+0x04)++0x03 line.long 0x00 "ACCESS_CTRL128_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC070+0x04)++0x03 line.long 0x00 "ACCESS_CTRL128_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC070+0x08))&0x80000000)==0x00) group.long (0xC070+0x08)++0x03 line.long 0x00 "ACCESS_CTRL128_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC070+0x08)++0x03 line.long 0x00 "ACCESS_CTRL128_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC070+0x0C))&0x80000000)==0x00) group.long (0xC070+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL128_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC070+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL128_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC0F0))&0x80000000)==0x00) group.long 0xC0F0++0x03 line.long 0x00 "ACCESS_CTRL129,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC0F0++0x03 line.long 0x00 "ACCESS_CTRL129,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC0F0+0x04))&0x80000000)==0x00) group.long (0xC0F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL129_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC0F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL129_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC0F0+0x08))&0x80000000)==0x00) group.long (0xC0F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL129_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC0F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL129_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC0F0+0x0C))&0x80000000)==0x00) group.long (0xC0F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL129_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC0F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL129_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC170))&0x80000000)==0x00) group.long 0xC170++0x03 line.long 0x00 "ACCESS_CTRL130,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC170++0x03 line.long 0x00 "ACCESS_CTRL130,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC170+0x04))&0x80000000)==0x00) group.long (0xC170+0x04)++0x03 line.long 0x00 "ACCESS_CTRL130_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC170+0x04)++0x03 line.long 0x00 "ACCESS_CTRL130_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC170+0x08))&0x80000000)==0x00) group.long (0xC170+0x08)++0x03 line.long 0x00 "ACCESS_CTRL130_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC170+0x08)++0x03 line.long 0x00 "ACCESS_CTRL130_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC170+0x0C))&0x80000000)==0x00) group.long (0xC170+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL130_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC170+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL130_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC1F0))&0x80000000)==0x00) group.long 0xC1F0++0x03 line.long 0x00 "ACCESS_CTRL131,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC1F0++0x03 line.long 0x00 "ACCESS_CTRL131,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC1F0+0x04))&0x80000000)==0x00) group.long (0xC1F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL131_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC1F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL131_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC1F0+0x08))&0x80000000)==0x00) group.long (0xC1F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL131_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC1F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL131_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC1F0+0x0C))&0x80000000)==0x00) group.long (0xC1F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL131_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC1F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL131_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC270))&0x80000000)==0x00) group.long 0xC270++0x03 line.long 0x00 "ACCESS_CTRL132,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC270++0x03 line.long 0x00 "ACCESS_CTRL132,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC270+0x04))&0x80000000)==0x00) group.long (0xC270+0x04)++0x03 line.long 0x00 "ACCESS_CTRL132_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC270+0x04)++0x03 line.long 0x00 "ACCESS_CTRL132_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC270+0x08))&0x80000000)==0x00) group.long (0xC270+0x08)++0x03 line.long 0x00 "ACCESS_CTRL132_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC270+0x08)++0x03 line.long 0x00 "ACCESS_CTRL132_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC270+0x0C))&0x80000000)==0x00) group.long (0xC270+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL132_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC270+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL132_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC2F0))&0x80000000)==0x00) group.long 0xC2F0++0x03 line.long 0x00 "ACCESS_CTRL133,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC2F0++0x03 line.long 0x00 "ACCESS_CTRL133,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC2F0+0x04))&0x80000000)==0x00) group.long (0xC2F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL133_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC2F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL133_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC2F0+0x08))&0x80000000)==0x00) group.long (0xC2F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL133_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC2F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL133_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC2F0+0x0C))&0x80000000)==0x00) group.long (0xC2F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL133_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC2F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL133_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC370))&0x80000000)==0x00) group.long 0xC370++0x03 line.long 0x00 "ACCESS_CTRL134,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC370++0x03 line.long 0x00 "ACCESS_CTRL134,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC370+0x04))&0x80000000)==0x00) group.long (0xC370+0x04)++0x03 line.long 0x00 "ACCESS_CTRL134_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC370+0x04)++0x03 line.long 0x00 "ACCESS_CTRL134_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC370+0x08))&0x80000000)==0x00) group.long (0xC370+0x08)++0x03 line.long 0x00 "ACCESS_CTRL134_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC370+0x08)++0x03 line.long 0x00 "ACCESS_CTRL134_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC370+0x0C))&0x80000000)==0x00) group.long (0xC370+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL134_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC370+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL134_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC3F0))&0x80000000)==0x00) group.long 0xC3F0++0x03 line.long 0x00 "ACCESS_CTRL135,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC3F0++0x03 line.long 0x00 "ACCESS_CTRL135,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC3F0+0x04))&0x80000000)==0x00) group.long (0xC3F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL135_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC3F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL135_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC3F0+0x08))&0x80000000)==0x00) group.long (0xC3F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL135_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC3F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL135_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC3F0+0x0C))&0x80000000)==0x00) group.long (0xC3F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL135_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC3F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL135_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC470))&0x80000000)==0x00) group.long 0xC470++0x03 line.long 0x00 "ACCESS_CTRL136,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC470++0x03 line.long 0x00 "ACCESS_CTRL136,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC470+0x04))&0x80000000)==0x00) group.long (0xC470+0x04)++0x03 line.long 0x00 "ACCESS_CTRL136_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC470+0x04)++0x03 line.long 0x00 "ACCESS_CTRL136_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC470+0x08))&0x80000000)==0x00) group.long (0xC470+0x08)++0x03 line.long 0x00 "ACCESS_CTRL136_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC470+0x08)++0x03 line.long 0x00 "ACCESS_CTRL136_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC470+0x0C))&0x80000000)==0x00) group.long (0xC470+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL136_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC470+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL136_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC4F0))&0x80000000)==0x00) group.long 0xC4F0++0x03 line.long 0x00 "ACCESS_CTRL137,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC4F0++0x03 line.long 0x00 "ACCESS_CTRL137,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC4F0+0x04))&0x80000000)==0x00) group.long (0xC4F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL137_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC4F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL137_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC4F0+0x08))&0x80000000)==0x00) group.long (0xC4F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL137_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC4F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL137_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC4F0+0x0C))&0x80000000)==0x00) group.long (0xC4F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL137_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC4F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL137_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC570))&0x80000000)==0x00) group.long 0xC570++0x03 line.long 0x00 "ACCESS_CTRL138,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC570++0x03 line.long 0x00 "ACCESS_CTRL138,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC570+0x04))&0x80000000)==0x00) group.long (0xC570+0x04)++0x03 line.long 0x00 "ACCESS_CTRL138_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC570+0x04)++0x03 line.long 0x00 "ACCESS_CTRL138_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC570+0x08))&0x80000000)==0x00) group.long (0xC570+0x08)++0x03 line.long 0x00 "ACCESS_CTRL138_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC570+0x08)++0x03 line.long 0x00 "ACCESS_CTRL138_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC570+0x0C))&0x80000000)==0x00) group.long (0xC570+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL138_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC570+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL138_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC5F0))&0x80000000)==0x00) group.long 0xC5F0++0x03 line.long 0x00 "ACCESS_CTRL139,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC5F0++0x03 line.long 0x00 "ACCESS_CTRL139,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC5F0+0x04))&0x80000000)==0x00) group.long (0xC5F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL139_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC5F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL139_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC5F0+0x08))&0x80000000)==0x00) group.long (0xC5F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL139_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC5F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL139_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC5F0+0x0C))&0x80000000)==0x00) group.long (0xC5F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL139_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC5F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL139_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC670))&0x80000000)==0x00) group.long 0xC670++0x03 line.long 0x00 "ACCESS_CTRL140,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC670++0x03 line.long 0x00 "ACCESS_CTRL140,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC670+0x04))&0x80000000)==0x00) group.long (0xC670+0x04)++0x03 line.long 0x00 "ACCESS_CTRL140_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC670+0x04)++0x03 line.long 0x00 "ACCESS_CTRL140_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC670+0x08))&0x80000000)==0x00) group.long (0xC670+0x08)++0x03 line.long 0x00 "ACCESS_CTRL140_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC670+0x08)++0x03 line.long 0x00 "ACCESS_CTRL140_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC670+0x0C))&0x80000000)==0x00) group.long (0xC670+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL140_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC670+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL140_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC6F0))&0x80000000)==0x00) group.long 0xC6F0++0x03 line.long 0x00 "ACCESS_CTRL141,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xC6F0++0x03 line.long 0x00 "ACCESS_CTRL141,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC6F0+0x04))&0x80000000)==0x00) group.long (0xC6F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL141_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC6F0+0x04)++0x03 line.long 0x00 "ACCESS_CTRL141_SET,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC6F0+0x08))&0x80000000)==0x00) group.long (0xC6F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL141_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC6F0+0x08)++0x03 line.long 0x00 "ACCESS_CTRL141_CLR,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x30380000+0xC6F0+0x0C))&0x80000000)==0x00) group.long (0xC6F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL141_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0xC6F0+0x0C)++0x03 line.long 0x00 "ACCESS_CTRL141_TOG,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactivated,Activated" rbitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" textline " " bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,List of domains that can change setting of this clock root" "No,Yes" bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Released,Acquired" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns ID" "Domain 0,Domain 1,Domain 2,Domain 3" textline " " bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0xb tree.end tree "CCMA (Clock Control Module Analog)" base ad:0x30360000 width 21. group.long 0x0++0x07 line.long 0x00 "AUDIO_PLL1_CFG0,AUDIO_PLL1 Configuration 0 Register" rbitfld.long 0x00 31. " PLL_LOCK ,PLL lock status" "Unlocked,Locked" bitfld.long 0x00 21. " PLL_CLKE ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 20. " PLL_CLKE_OVERRIDE ,Override the PLL_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 19. " PLL_PD ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 18. " PLL_PD_OVERRIDE ,Override the PLL_PD" "Not overridden,Overridden" bitfld.long 0x00 16.--17. " PLL_REFCLK_SEL ,PLL reference clock select" "25M_REF_CLK,27M_REF_CLK,HDMI_PHY_27M_CLK,CLK_P_N" textline " " bitfld.long 0x00 15. " PLL_LOCK_SEL ,PLL Lock signal select" "PLL,Maximum" bitfld.long 0x00 14. " PLL_BYPASS ,PLL bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 13. " PLL_COUNTCLK_SET ,PLL maximum lock timer counter clock select" "25M_REF_CLK,27M_REF_CLK" textline " " bitfld.long 0x00 12. " PLL_NEWDIV_VAL ,PLL new fraction divide input control" "Not divided,Divided" rbitfld.long 0x00 11. " PLL_NEWDIV_ACK ,PLL new fraction divide handshake signal" "No,Yes" bitfld.long 0x00 5.--10. " PLL_REFCLK_DIV_VAL ,PLL reference clock divide value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x00 0.--4. " PLL_OUTPUT_DIV_VAL ,Output clock divide value" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64" line.long 0x04 "AUDIO_PLL1_CFG1,AUDIO_PLL1 Configuration 1 Register" hexmask.long.tbyte 0x04 7.--30. 1. " PLL_FRAC_DIV_CTL ,PLL fraction divide control" hexmask.long.byte 0x04 0.--6. 1. " PLL_INT_DIV_CTL ,PLL Integer divide control" group.long 0x8++0x07 line.long 0x00 "AUDIO_PLL2_CFG0,AUDIO_PLL2 Configuration 0 Register" rbitfld.long 0x00 31. " PLL_LOCK ,PLL lock status" "Unlocked,Locked" bitfld.long 0x00 21. " PLL_CLKE ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 20. " PLL_CLKE_OVERRIDE ,Override the PLL_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 19. " PLL_PD ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 18. " PLL_PD_OVERRIDE ,Override the PLL_PD" "Not overridden,Overridden" bitfld.long 0x00 16.--17. " PLL_REFCLK_SEL ,PLL reference clock select" "25M_REF_CLK,27M_REF_CLK,HDMI_PHY_27M_CLK,CLK_P_N" textline " " bitfld.long 0x00 15. " PLL_LOCK_SEL ,PLL Lock signal select" "PLL,Maximum" bitfld.long 0x00 14. " PLL_BYPASS ,PLL bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 13. " PLL_COUNTCLK_SET ,PLL maximum lock timer counter clock select" "25M_REF_CLK,27M_REF_CLK" textline " " bitfld.long 0x00 12. " PLL_NEWDIV_VAL ,PLL new fraction divide input control" "Not divided,Divided" rbitfld.long 0x00 11. " PLL_NEWDIV_ACK ,PLL new fraction divide handshake signal" "No,Yes" bitfld.long 0x00 5.--10. " PLL_REFCLK_DIV_VAL ,PLL reference clock divide value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x00 0.--4. " PLL_OUTPUT_DIV_VAL ,Output clock divide value" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64" line.long 0x04 "AUDIO_PLL2_CFG1,AUDIO_PLL2 Configuration 1 Register" hexmask.long.tbyte 0x04 7.--30. 1. " PLL_FRAC_DIV_CTL ,PLL fraction divide control" hexmask.long.byte 0x04 0.--6. 1. " PLL_INT_DIV_CTL ,PLL Integer divide control" group.long 0x10++0x07 line.long 0x00 "VIDEO_PLL1_CFG0,VIDEO_PLL1 Configuration 0 Register" rbitfld.long 0x00 31. " PLL_LOCK ,PLL lock status" "Unlocked,Locked" bitfld.long 0x00 21. " PLL_CLKE ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 20. " PLL_CLKE_OVERRIDE ,Override the PLL_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 19. " PLL_PD ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 18. " PLL_PD_OVERRIDE ,Override the PLL_PD" "Not overridden,Overridden" bitfld.long 0x00 16.--17. " PLL_REFCLK_SEL ,PLL reference clock select" "25M_REF_CLK,27M_REF_CLK,HDMI_PHY_27M_CLK,CLK_P_N" textline " " bitfld.long 0x00 15. " PLL_LOCK_SEL ,PLL Lock signal select" "PLL,Maximum" bitfld.long 0x00 14. " PLL_BYPASS ,PLL bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 13. " PLL_COUNTCLK_SET ,PLL maximum lock timer counter clock select" "25M_REF_CLK,27M_REF_CLK" textline " " bitfld.long 0x00 12. " PLL_NEWDIV_VAL ,PLL new fraction divide input control" "Not divided,Divided" rbitfld.long 0x00 11. " PLL_NEWDIV_ACK ,PLL new fraction divide handshake signal" "No,Yes" bitfld.long 0x00 5.--10. " PLL_REFCLK_DIV_VAL ,PLL reference clock divide value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x00 0.--4. " PLL_OUTPUT_DIV_VAL ,Output clock divide value" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64" line.long 0x04 "VIDEO_PLL1_CFG1,VIDEO_PLL1 Configuration 1 Register" hexmask.long.tbyte 0x04 7.--30. 1. " PLL_FRAC_DIV_CTL ,PLL fraction divide control" hexmask.long.byte 0x04 0.--6. 1. " PLL_INT_DIV_CTL ,PLL Integer divide control" group.long 0x18++0x07 line.long 0x00 "GPU_PLL_CFG0,GPU_PLL Configuration 0 Register" rbitfld.long 0x00 31. " PLL_LOCK ,PLL lock status" "Unlocked,Locked" bitfld.long 0x00 21. " PLL_CLKE ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 20. " PLL_CLKE_OVERRIDE ,Override the PLL_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 19. " PLL_PD ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 18. " PLL_PD_OVERRIDE ,Override the PLL_PD" "Not overridden,Overridden" bitfld.long 0x00 16.--17. " PLL_REFCLK_SEL ,PLL reference clock select" "25M_REF_CLK,27M_REF_CLK,HDMI_PHY_27M_CLK,CLK_P_N" textline " " bitfld.long 0x00 15. " PLL_LOCK_SEL ,PLL Lock signal select" "PLL,Maximum" bitfld.long 0x00 14. " PLL_BYPASS ,PLL bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 13. " PLL_COUNTCLK_SET ,PLL maximum lock timer counter clock select" "25M_REF_CLK,27M_REF_CLK" textline " " bitfld.long 0x00 12. " PLL_NEWDIV_VAL ,PLL new fraction divide input control" "Not divided,Divided" rbitfld.long 0x00 11. " PLL_NEWDIV_ACK ,PLL new fraction divide handshake signal" "No,Yes" bitfld.long 0x00 5.--10. " PLL_REFCLK_DIV_VAL ,PLL reference clock divide value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x00 0.--4. " PLL_OUTPUT_DIV_VAL ,Output clock divide value" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64" line.long 0x04 "GPU_PLL_CFG1,GPU_PLL Configuration 1 Register" hexmask.long.tbyte 0x04 7.--30. 1. " PLL_FRAC_DIV_CTL ,PLL fraction divide control" hexmask.long.byte 0x04 0.--6. 1. " PLL_INT_DIV_CTL ,PLL Integer divide control" group.long 0x20++0x07 line.long 0x00 "VPU_PLL_CFG0,VPU_PLL Configuration 0 Register" rbitfld.long 0x00 31. " PLL_LOCK ,PLL lock status" "Unlocked,Locked" bitfld.long 0x00 21. " PLL_CLKE ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 20. " PLL_CLKE_OVERRIDE ,Override the PLL_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 19. " PLL_PD ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 18. " PLL_PD_OVERRIDE ,Override the PLL_PD" "Not overridden,Overridden" bitfld.long 0x00 16.--17. " PLL_REFCLK_SEL ,PLL reference clock select" "25M_REF_CLK,27M_REF_CLK,HDMI_PHY_27M_CLK,CLK_P_N" textline " " bitfld.long 0x00 15. " PLL_LOCK_SEL ,PLL Lock signal select" "PLL,Maximum" bitfld.long 0x00 14. " PLL_BYPASS ,PLL bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 13. " PLL_COUNTCLK_SET ,PLL maximum lock timer counter clock select" "25M_REF_CLK,27M_REF_CLK" textline " " bitfld.long 0x00 12. " PLL_NEWDIV_VAL ,PLL new fraction divide input control" "Not divided,Divided" rbitfld.long 0x00 11. " PLL_NEWDIV_ACK ,PLL new fraction divide handshake signal" "No,Yes" bitfld.long 0x00 5.--10. " PLL_REFCLK_DIV_VAL ,PLL reference clock divide value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x00 0.--4. " PLL_OUTPUT_DIV_VAL ,Output clock divide value" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64" line.long 0x04 "VPU_PLL_CFG1,VPU_PLL Configuration 1 Register" hexmask.long.tbyte 0x04 7.--30. 1. " PLL_FRAC_DIV_CTL ,PLL fraction divide control" hexmask.long.byte 0x04 0.--6. 1. " PLL_INT_DIV_CTL ,PLL Integer divide control" group.long 0x28++0x07 line.long 0x00 "ARM_PLL_CFG0,ARM_PLL Configuration 0 Register" rbitfld.long 0x00 31. " PLL_LOCK ,PLL lock status" "Unlocked,Locked" bitfld.long 0x00 21. " PLL_CLKE ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 20. " PLL_CLKE_OVERRIDE ,Override the PLL_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 19. " PLL_PD ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 18. " PLL_PD_OVERRIDE ,Override the PLL_PD" "Not overridden,Overridden" bitfld.long 0x00 16.--17. " PLL_REFCLK_SEL ,PLL reference clock select" "25M_REF_CLK,27M_REF_CLK,HDMI_PHY_27M_CLK,CLK_P_N" textline " " bitfld.long 0x00 15. " PLL_LOCK_SEL ,PLL Lock signal select" "PLL,Maximum" bitfld.long 0x00 14. " PLL_BYPASS ,PLL bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 13. " PLL_COUNTCLK_SET ,PLL maximum lock timer counter clock select" "25M_REF_CLK,27M_REF_CLK" textline " " bitfld.long 0x00 12. " PLL_NEWDIV_VAL ,PLL new fraction divide input control" "Not divided,Divided" rbitfld.long 0x00 11. " PLL_NEWDIV_ACK ,PLL new fraction divide handshake signal" "No,Yes" bitfld.long 0x00 5.--10. " PLL_REFCLK_DIV_VAL ,PLL reference clock divide value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x00 0.--4. " PLL_OUTPUT_DIV_VAL ,Output clock divide value" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64" line.long 0x04 "ARM_PLL_CFG1,ARM_PLL Configuration 1 Register" hexmask.long.tbyte 0x04 7.--30. 1. " PLL_FRAC_DIV_CTL ,PLL fraction divide control" hexmask.long.byte 0x04 0.--6. 1. " PLL_INT_DIV_CTL ,PLL Integer divide control" group.long 0x30++0x0B line.long 0x00 "SYS_PLL1_CFG0,System PLL Configuration 0 Register" rbitfld.long 0x00 31. " PLL_LOCK ,PLL lock status" "Not locked,Locked" bitfld.long 0x00 25. " PLL_CLKE ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 24. " PLL_CLKE_OVERRIDE ,Override the PLL_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 23. " PLL_DIV2_CLKE ,PLL output clock divide by 2 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 22. " PLL_DIV2_OVERRIDE ,Override the PLL_DIV2_CLKE" "Not overridden,Overridden" bitfld.long 0x00 21. " PLL_DIV3_CCLKE ,PLL output clock divide by 3 clock gating enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " PLL_DIV3_OVERRIDE ,Override the PLL_DIV3_CLKE" "Not overridden,Overridden" bitfld.long 0x00 19. " PLL_DIV4_CCLKE ,PLL output clock divide by 4 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 18. " PLL_DIV4_OVERRIDE ,Override the PLL_DIV4_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 17. " PLL_DIV5_CCLKE ,PLL output clock divide by 5 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 16. " PLL_DIV5_OVERRIDE ,Override the PLL_DIV5_CLKE" "Not overridden,Overridden" bitfld.long 0x00 15. " PLL_DIV6_CCLKE ,PLL output clock divide by 6 clock gating enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " PLL_DIV6_OVERRIDE ,Override the PLL_DIV6_CLKE" "Not overridden,Overridden" bitfld.long 0x00 13. " PLL_DIV8_CCLKE ,PLL output clock divide by 8 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 12. " PLL_DIV8_OVERRIDE ,Override the PLL_DIV8_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 11. " PLL_DIV10_CCLKE ,PLL output clock divide by 10 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 10. " PLL_DIV10_OVERRIDE ,Override the PLL_DIV10_CLKE" "Not overridden,Overridden" bitfld.long 0x00 9. " PLL_DIV20_CCLKE ,PLL output clock divide by 20 clock gating enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PLL_DIV20_OVERRIDE ,Override the PLL_DIV20_CLKE" "Not overridden,Overridden" bitfld.long 0x00 7. " PLL_PD ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 6. " PLL_PD_OVERRIDE ,Override the PLL_PD" "Not overridden,Overridden" textline " " bitfld.long 0x00 5. " PLL_BYPASS1 ,Internal PLL1 bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 4. " PLL_BYPASS2 ,Internal PLL2 bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 3. " PLL_LOCK_SEL ,PLL Lock signal select" "PLL lock output,Maximum lock output" textline " " bitfld.long 0x00 2. " PLL_COUNTCLK_SET ,PLL maximum lock timer counter clock select" "25M_REF_CLK,27M_REF_CLK" bitfld.long 0x00 0.--1. " PLL_REFCLK_SEL ,PLL reference clocks select" "25M_REF_CLK,27M_REF_CLK,HDMI_PHY_27M_CLK,CLK_P_N" line.long 0x04 "SYS_PLL1_CFG1,System PLL Configuration 1 Register" bitfld.long 0x04 8. " PLL_SSDS ,Selects between Spread Spectrum Center Spread and Down Spread Modes" "Center Spread,Down Spread" bitfld.long 0x04 5.--7. " PLL_SSMD ,Controls Spread Spectrum modulation depth" "0.25,0.5,0.75,1,1.5,2,3,4" bitfld.long 0x04 1.--4. " PLL_SSMF ,Controls Spread Spectrum Modulation Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 0. " PLL_SSE ,Enables Spread Spectrum Mode" "Disabled,Enabled" line.long 0x08 "SYS_PLL1_CFG2,System PLL Configuration 2 Register" bitfld.long 0x08 25.--27. " PLL_REF_DIVR1 ,Internal PLL1 reference clock divider value" "1,2,3,4,5,6,7,8" bitfld.long 0x08 19.--24. " PLL_REF_DIVR2 ,Internal PLL2 reference clock divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 13.--18. " PLL_FEEDBACK_DIVF1 ,Internal PLL1 reference clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x08 7.--12. " PLL_FEEDBACK_DIVF2 ,Internal PLL2 reference clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 1.--6. " PLL_OUTPUT_DIV_VAL ,Internal PLL2 output clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 0. " PLL_FILTER_RANGE ,Internal PLL1 loop filter" "25 to 35MHZ,35 to 54MHZ" group.long 0x3C++0x0B line.long 0x00 "SYS_PLL2_CFG0,System PLL Configuration 0 Register" rbitfld.long 0x00 31. " PLL_LOCK ,PLL lock status" "Not locked,Locked" bitfld.long 0x00 25. " PLL_CLKE ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 24. " PLL_CLKE_OVERRIDE ,Override the PLL_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 23. " PLL_DIV2_CLKE ,PLL output clock divide by 2 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 22. " PLL_DIV2_OVERRIDE ,Override the PLL_DIV2_CLKE" "Not overridden,Overridden" bitfld.long 0x00 21. " PLL_DIV3_CCLKE ,PLL output clock divide by 3 clock gating enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " PLL_DIV3_OVERRIDE ,Override the PLL_DIV3_CLKE" "Not overridden,Overridden" bitfld.long 0x00 19. " PLL_DIV4_CCLKE ,PLL output clock divide by 4 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 18. " PLL_DIV4_OVERRIDE ,Override the PLL_DIV4_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 17. " PLL_DIV5_CCLKE ,PLL output clock divide by 5 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 16. " PLL_DIV5_OVERRIDE ,Override the PLL_DIV5_CLKE" "Not overridden,Overridden" bitfld.long 0x00 15. " PLL_DIV6_CCLKE ,PLL output clock divide by 6 clock gating enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " PLL_DIV6_OVERRIDE ,Override the PLL_DIV6_CLKE" "Not overridden,Overridden" bitfld.long 0x00 13. " PLL_DIV8_CCLKE ,PLL output clock divide by 8 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 12. " PLL_DIV8_OVERRIDE ,Override the PLL_DIV8_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 11. " PLL_DIV10_CCLKE ,PLL output clock divide by 10 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 10. " PLL_DIV10_OVERRIDE ,Override the PLL_DIV10_CLKE" "Not overridden,Overridden" bitfld.long 0x00 9. " PLL_DIV20_CCLKE ,PLL output clock divide by 20 clock gating enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PLL_DIV20_OVERRIDE ,Override the PLL_DIV20_CLKE" "Not overridden,Overridden" bitfld.long 0x00 7. " PLL_PD ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 6. " PLL_PD_OVERRIDE ,Override the PLL_PD" "Not overridden,Overridden" textline " " bitfld.long 0x00 5. " PLL_BYPASS1 ,Internal PLL1 bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 4. " PLL_BYPASS2 ,Internal PLL2 bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 3. " PLL_LOCK_SEL ,PLL Lock signal select" "PLL lock output,Maximum lock output" textline " " bitfld.long 0x00 2. " PLL_COUNTCLK_SET ,PLL maximum lock timer counter clock select" "25M_REF_CLK,27M_REF_CLK" bitfld.long 0x00 0.--1. " PLL_REFCLK_SEL ,PLL reference clocks select" "25M_REF_CLK,27M_REF_CLK,HDMI_PHY_27M_CLK,CLK_P_N" line.long 0x04 "SYS_PLL2_CFG1,System PLL Configuration 1 Register" bitfld.long 0x04 8. " PLL_SSDS ,Selects between Spread Spectrum Center Spread and Down Spread Modes" "Center Spread,Down Spread" bitfld.long 0x04 5.--7. " PLL_SSMD ,Controls Spread Spectrum modulation depth" "0.25,0.5,0.75,1,1.5,2,3,4" bitfld.long 0x04 1.--4. " PLL_SSMF ,Controls Spread Spectrum Modulation Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 0. " PLL_SSE ,Enables Spread Spectrum Mode" "Disabled,Enabled" line.long 0x08 "SYS_PLL2_CFG2,System PLL Configuration 2 Register" bitfld.long 0x08 25.--27. " PLL_REF_DIVR1 ,Internal PLL1 reference clock divider value" "1,2,3,4,5,6,7,8" bitfld.long 0x08 19.--24. " PLL_REF_DIVR2 ,Internal PLL2 reference clock divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 13.--18. " PLL_FEEDBACK_DIVF1 ,Internal PLL1 reference clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x08 7.--12. " PLL_FEEDBACK_DIVF2 ,Internal PLL2 reference clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 1.--6. " PLL_OUTPUT_DIV_VAL ,Internal PLL2 output clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 0. " PLL_FILTER_RANGE ,Internal PLL1 loop filter" "25 to 35MHZ,35 to 54MHZ" group.long 0x48++0x0B line.long 0x00 "SYS_PLL3_CFG0,System PLL Configuration 0 Register" rbitfld.long 0x00 31. " PLL_LOCK ,PLL lock status" "Not locked,Locked" bitfld.long 0x00 25. " PLL_CLKE ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 24. " PLL_CLKE_OVERRIDE ,Override the PLL_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 23. " PLL_DIV2_CLKE ,PLL output clock divide by 2 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 22. " PLL_DIV2_OVERRIDE ,Override the PLL_DIV2_CLKE" "Not overridden,Overridden" bitfld.long 0x00 21. " PLL_DIV3_CCLKE ,PLL output clock divide by 3 clock gating enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " PLL_DIV3_OVERRIDE ,Override the PLL_DIV3_CLKE" "Not overridden,Overridden" bitfld.long 0x00 19. " PLL_DIV4_CCLKE ,PLL output clock divide by 4 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 18. " PLL_DIV4_OVERRIDE ,Override the PLL_DIV4_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 17. " PLL_DIV5_CCLKE ,PLL output clock divide by 5 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 16. " PLL_DIV5_OVERRIDE ,Override the PLL_DIV5_CLKE" "Not overridden,Overridden" bitfld.long 0x00 15. " PLL_DIV6_CCLKE ,PLL output clock divide by 6 clock gating enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " PLL_DIV6_OVERRIDE ,Override the PLL_DIV6_CLKE" "Not overridden,Overridden" bitfld.long 0x00 13. " PLL_DIV8_CCLKE ,PLL output clock divide by 8 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 12. " PLL_DIV8_OVERRIDE ,Override the PLL_DIV8_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 11. " PLL_DIV10_CCLKE ,PLL output clock divide by 10 clock gating enable" "Disabled,Enabled" bitfld.long 0x00 10. " PLL_DIV10_OVERRIDE ,Override the PLL_DIV10_CLKE" "Not overridden,Overridden" bitfld.long 0x00 9. " PLL_DIV20_CCLKE ,PLL output clock divide by 20 clock gating enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PLL_DIV20_OVERRIDE ,Override the PLL_DIV20_CLKE" "Not overridden,Overridden" bitfld.long 0x00 7. " PLL_PD ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 6. " PLL_PD_OVERRIDE ,Override the PLL_PD" "Not overridden,Overridden" textline " " bitfld.long 0x00 5. " PLL_BYPASS1 ,Internal PLL1 bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 4. " PLL_BYPASS2 ,Internal PLL2 bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 3. " PLL_LOCK_SEL ,PLL Lock signal select" "PLL lock output,Maximum lock output" textline " " bitfld.long 0x00 2. " PLL_COUNTCLK_SET ,PLL maximum lock timer counter clock select" "25M_REF_CLK,27M_REF_CLK" bitfld.long 0x00 0.--1. " PLL_REFCLK_SEL ,PLL reference clocks select" "25M_REF_CLK,27M_REF_CLK,HDMI_PHY_27M_CLK,CLK_P_N" line.long 0x04 "SYS_PLL3_CFG1,System PLL Configuration 1 Register" bitfld.long 0x04 8. " PLL_SSDS ,Selects between Spread Spectrum Center Spread and Down Spread Modes" "Center Spread,Down Spread" bitfld.long 0x04 5.--7. " PLL_SSMD ,Controls Spread Spectrum modulation depth" "0.25,0.5,0.75,1,1.5,2,3,4" bitfld.long 0x04 1.--4. " PLL_SSMF ,Controls Spread Spectrum Modulation Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 0. " PLL_SSE ,Enables Spread Spectrum Mode" "Disabled,Enabled" line.long 0x08 "SYS_PLL3_CFG2,System PLL Configuration 2 Register" bitfld.long 0x08 25.--27. " PLL_REF_DIVR1 ,Internal PLL1 reference clock divider value" "1,2,3,4,5,6,7,8" bitfld.long 0x08 19.--24. " PLL_REF_DIVR2 ,Internal PLL2 reference clock divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 13.--18. " PLL_FEEDBACK_DIVF1 ,Internal PLL1 reference clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x08 7.--12. " PLL_FEEDBACK_DIVF2 ,Internal PLL2 reference clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 1.--6. " PLL_OUTPUT_DIV_VAL ,Internal PLL2 output clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 0. " PLL_FILTER_RANGE ,Internal PLL1 loop filter" "25 to 35MHZ,35 to 54MHZ" group.long 0x54++0x0B line.long 0x00 "VIDEO_PLL2_CFG0,VIDEO_PLL2 Configuration 0 Register" rbitfld.long 0x00 31. " PLL_LOCK ,PLL lock status" "Unlocked,Locked" bitfld.long 0x00 9. " PLL_CCLKE ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 8. " PLL_OVERRIDE ,Override the PLL_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 7. " PLL_PD ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 6. " PLL_PD_OVERRIDE ,Override the PLL_PD" "Not overridden,Overridden" bitfld.long 0x00 5. " PLL_BYPASS1 ,Internal PLL1 bypass control" "Not bypassed,Bypassed" textline " " bitfld.long 0x00 4. " PLL_BYPASS2 ,Internal PLL2 bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 3. " PLL_LOCK_SEL ,PLL Lock signal select" "PLL lock output,Maximum lock output" bitfld.long 0x00 2. " PLL_COUNTCLK_SET ,PLL maximum lock timer counter clock select" "25M_REF_CLK,27M_REF_CLK" textline " " bitfld.long 0x00 0.--1. " PLL_REFCLK_SEL ,PLL reference clocks select" "25M_REF_CLK,27M_REF_CLK,HDMI_PHY_27M_CLK,CLK_P_N" line.long 0x04 "VIDEO_PLL2_CFG0,VIDEO_PLL2 Configuration 1 Register" bitfld.long 0x04 8. " PLL_SSDS ,Selects between Spread Spectrum Center Spread and Down Spread Modes" "Center Spread,Down Spread" bitfld.long 0x04 5.--7. " PLL_SSMD ,Controls Spread Spectrum modulation depth" "0.25,0.5,0.75,1,1.5,2,3,4" bitfld.long 0x04 1.--4. " PLL_SSMF ,Controls Spread Spectrum Modulation Frequency" "2*Fvco,4*Fvco,6*Fvco,8*Fvco,10*Fvco,12*Fvco,14*Fvco,16*Fvco,18*Fvco,20*Fvco,22*Fvco,24*Fvco,26*Fvco,28*Fvco,30*Fvco,32*Fvco" textline " " bitfld.long 0x04 0. " PLL_SSE ,Enables Spread Spectrum Mode" "Disabled,Enabled" line.long 0x08 "VIDEO_PLL2_CFG0,VIDEO_PLL2 Configuration 2 Register" bitfld.long 0x08 25.--27. " PLL_REF_DIVR1 ,Internal PLL1 reference clock divider value" "1,2,3,4,5,6,7,8" bitfld.long 0x08 19.--24. " PLL_REF_DIVR2 ,Internal PLL2 reference clock divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 13.--18. " PLL_FEEDBACK_DIVF1 ,Internal PLL1 reference clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x08 7.--12. " PLL_FEEDBACK_DIVF2 ,Internal PLL2 reference clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 1.--6. " PLL_OUTPUT_DIV_VAL ,Internal PLL2 output clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 0. " PLL_FILTER_RANGE ,Internal PLL1 loop filter" "25 to 35MHZ,35 to 54MHZ" group.long 0x60++0x0B line.long 0x00 "DRAM_PLL_CFG0,DRAM_PLL Configuration 0 Register" rbitfld.long 0x00 31. " PLL_LOCK ,PLL lock status" "Unlocked,Locked" bitfld.long 0x00 9. " PLL_CCLKE ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 8. " PLL_OVERRIDE ,Override the PLL_CLKE" "Not overridden,Overridden" textline " " bitfld.long 0x00 7. " PLL_PD ,PLL output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 6. " PLL_PD_OVERRIDE ,Override the PLL_PD" "Not overridden,Overridden" bitfld.long 0x00 5. " PLL_BYPASS1 ,Internal PLL1 bypass control" "Not bypassed,Bypassed" textline " " bitfld.long 0x00 4. " PLL_BYPASS2 ,Internal PLL2 bypass control" "Not bypassed,Bypassed" bitfld.long 0x00 3. " PLL_LOCK_SEL ,PLL Lock signal select" "PLL lock output,Maximum lock output" bitfld.long 0x00 2. " PLL_COUNTCLK_SET ,PLL maximum lock timer counter clock select" "25M_REF_CLK,27M_REF_CLK" textline " " bitfld.long 0x00 0.--1. " PLL_REFCLK_SEL ,PLL reference clocks select" "25M_REF_CLK,27M_REF_CLK,HDMI_PHY_27M_CLK,CLK_P_N" line.long 0x04 "DRAM_PLL_CFG0,DRAM_PLL Configuration 1 Register" bitfld.long 0x04 8. " PLL_SSDS ,Selects between Spread Spectrum Center Spread and Down Spread Modes" "Center Spread,Down Spread" bitfld.long 0x04 5.--7. " PLL_SSMD ,Controls Spread Spectrum modulation depth" "0.25,0.5,0.75,1,1.5,2,3,4" bitfld.long 0x04 1.--4. " PLL_SSMF ,Controls Spread Spectrum Modulation Frequency" "2*Fvco,4*Fvco,6*Fvco,8*Fvco,10*Fvco,12*Fvco,14*Fvco,16*Fvco,18*Fvco,20*Fvco,22*Fvco,24*Fvco,26*Fvco,28*Fvco,30*Fvco,32*Fvco" textline " " bitfld.long 0x04 0. " PLL_SSE ,Enables Spread Spectrum Mode" "Disabled,Enabled" line.long 0x08 "DRAM_PLL_CFG0,DRAM_PLL Configuration 2 Register" bitfld.long 0x08 25.--27. " PLL_REF_DIVR1 ,Internal PLL1 reference clock divider value" "1,2,3,4,5,6,7,8" bitfld.long 0x08 19.--24. " PLL_REF_DIVR2 ,Internal PLL2 reference clock divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 13.--18. " PLL_FEEDBACK_DIVF1 ,Internal PLL1 reference clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x08 7.--12. " PLL_FEEDBACK_DIVF2 ,Internal PLL2 reference clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 1.--6. " PLL_OUTPUT_DIV_VAL ,Internal PLL2 output clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 0. " PLL_FILTER_RANGE ,Internal PLL1 loop filter" "25 to 35MHZ,35 to 54MHZ" rgroup.long 0x6C++0x03 line.long 0x00 "DIGPROG,DIGPROG Register" hexmask.long.byte 0x00 16.--23. 1. " DIGPROG_MAJOR_UPPER ,DIGPROG Major Upper" hexmask.long.byte 0x00 8.--15. 1. " DIGPROG_MAJOR_LOWER ,DIGPROG Major Lower" hexmask.long.byte 0x00 0.--7. 1. " DIGPROG_MINOR ,DIGPROG Minor" group.long 0x70++0x0F line.long 0x00 "OSC_MISC_CFG,Osc Misc Register" bitfld.long 0x00 4. " OSC_27M_CLKE ,27MHz OSC output clock gating enable" "Disabled,Enabled" bitfld.long 0x00 3. " OSC_27M_CLKE_OVERRIDE ,Override the OSC_27M_CLKE" "Not overridden,Overridden" bitfld.long 0x00 2. " OSC_25M_CLKE ,25MHz OSC output clock gating enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OSC_25M_CLKE_OVERRIDE ,Override the OSC_25M_CLKE" "Not overridden,Overridden" bitfld.long 0x00 0. " OSC_32K_SEL ,32kHz OSC input select" "25M_REF_CLK_DIV8000,RTC" line.long 0x04 "PLLOUT_MONITOR_CFG,PLLOUT Monitor Configuration" bitfld.long 0x04 4. " PLLOUT_MONITOR_CKE ,Clock monitor output clock gating enable" "Disabled,Enabled" bitfld.long 0x04 0.--3. " PLLOUT_MONITOR_CLK_SEL ,Clock monitor output select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "FRAC_PLLOUT_DIV_CFG,Fractional PLLOUT Divider Configuration Register" bitfld.long 0x08 20.--22. " ARM_PLL_DIV_VAL ,ARM PLL clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 16.--18. " VPU_PLL_DIV_VAL ,VPU PLL clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 12.--14. " GPU_PLL_DIV_VAL ,GPU PLL clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " bitfld.long 0x08 8.--10. " VIDEO_PLL_DIV_VAL ,VIDEO PLL clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 4.--6. " AUDIO_PLL2_DIV_VAL ,AUDIO PLL2 clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--2. " AUDIO_PLL1_DIV_VAL ,AUDIO PLL1 clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "SCCG_PLLOUT_DIV_CFG,SCCG PLLOUT Divider Configuration Register" bitfld.long 0x0C 16.--18. " VIDEO_PLL2_DIV_VAL ,VIDEO PLL2 clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 12.--14. " DRAM_PLL_DIV_VAL ,DRAM PLL clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 8.--10. " SYSTEM_PLL3_DIV_VAL ,SYSTEM PLL3 clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " bitfld.long 0x0C 4.--6. " SYSTEM_PLL2_DIV_VAL ,SYSTEM PLL2 clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--2. " SYSTEM_PLL1_DIV_VAL ,SYSTEM PLL1 clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8" width 0x0B tree.end tree "GPC (General Power Controller)" base ad:0x303A0000 width 26. group.long 0x00++0x0B line.long 0x00 "LPCR_A53_BSC,Basic Low power control register of A53 platform" bitfld.long 0x00 31. " MASK_DSM_TRIGGER ,DSM Trigger Mask" "Not masked,Masked" bitfld.long 0x00 30. " IRQ_SRC_A53_WUP ,Interrupt Request Source A53 Wake up" "Not interrupt,Interrupt" bitfld.long 0x00 29. " IRQ_SRC_C1 ,Interrupt Request Source Core1" "Not interrupt,Interrupt" textline " " bitfld.long 0x00 28. " IRQ_SRC_C0 ,Interrupt Request Source Core0" "Not interrupt,Interrupt" bitfld.long 0x00 26. " MASK_L2CC_WIFI ,L2 cache controller Wait For Interrupt Mask Register" "Not masked,Masked" bitfld.long 0x00 24. " MASK_SCU_WIFI ,SCU Wait For Interrupt Mask Register" "Not masked,Masked" textline " " bitfld.long 0x00 23. " IRQ_SRC_C3 ,Interrupt Request Source Core3" "Not interrupt,Interrupt" bitfld.long 0x00 22. " IRQ_SRC_C2 ,Interrupt Request Source Core2" "Not interrupt,Interrupt" bitfld.long 0x00 19. " MASK_CORE3_WIFI ,CORE3 Wait For Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 18. " MASK_CORE2_WIFI ,CORE2 Wait For Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 17. " MASK_CORE1_WIFI ,CORE1 Wait For Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK_CORE0_WIFI ,CORE0 Wait For Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 14. " CPU_CLK_ON_LPM ,Define if clock will be disabled on wait/stop mode" "Disabled,Enabled" bitfld.long 0x00 6. " MST_LPM_HSK_MASK ,MASTER0 LPM handshake mask" "Enabled,Disabled" bitfld.long 0x00 2.--3. " LPM1 ,CORE1 Setting the low power mode" "Remain in Run,Transfer to WAIT,Transfer to STOP,?..." textline " " bitfld.long 0x00 0.--1. " LPM0 ,CORE0 Setting the low power mode" "Remain in Run,Transfer to WAIT,Transfer to STOP,?..." line.long 0x04 "LPCR_A53_AD,Advanced Low power control register of A53 platform" bitfld.long 0x04 31. " L2PGE ,L2 cache RAM power down with SCU power domain in A53 platform" "Enabled,Disabled" bitfld.long 0x04 27. " EN_C3_PUP ,CORE3 power up with lower power mode request" "Enabled,Disabled" bitfld.long 0x04 26. " EN_C3_IRQ_PUP ,IRQ request for CORE3 power up" "Enabled,Disabled" textline " " bitfld.long 0x04 25. " EN_C2_PUP ,CORE2 power up with lower power mode request" "Enabled,Disabled" bitfld.long 0x04 24. " EN_C2_IRQ_PUP ,IRQ request for CORE2 power up" "Enabled,Disabled" bitfld.long 0x04 23. " EN_C3_WIFI_PDN_DIS ,WIFI Power down CORE3 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " EN_C2_WIFI_PDN_DIS ,WIFI Power down CORE2 enable" "Disabled,Enabled" bitfld.long 0x04 21. " EN_C1_WIFI_PDN_DIS ,WIFI Power down CORE1 enable" "Disabled,Enabled" bitfld.long 0x04 20. " EN_C0_WIFI_PDN_DIS ,WIFI Power down CORE0 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " EN_C3_PDN ,Power down CORE3 with low power mode request" "Disabled,Enabled" bitfld.long 0x04 18. " EN_C3_WIFI_PDN ,Power down CORE3 WIFI request" "Disabled,Enabled" bitfld.long 0x04 17. " EN_C2_PDN ,Power down CORE2 with low power mode request" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " EN_C2_WIFI_PDN ,Power down CORE2 WIFI request" "Disabled,Enabled" bitfld.long 0x04 11. " EN_C1_PUP ,CORE1 power up with lower power mode request" "Enabled,Disabled" bitfld.long 0x04 10. " EN_C1_IRQ_PUP ,IRQ request for CORE1 power up" "Enabled,Disabled" textline " " bitfld.long 0x04 9. " EN_C0_PUP ,CORE0 power up with lower power mode request" "Enabled,Disabled" bitfld.long 0x04 8. " EN_C0_IRQ_PUP ,IRQ request for CORE0 power up" "Enabled,Disabled" bitfld.long 0x04 5. " EN_L2_WIFI_PDN ,SCU and L2 power down with WIFI Request" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " EN_PLAT_PDN ,SCU and L2 cache RAM power down with low power mode Request" "Disabled,Enabled" bitfld.long 0x04 3. " EN_C1_PDN ,Core1 power down with low power mode Request" "Disabled,Enabled" bitfld.long 0x04 2. " EN_C1__WIFI_PDN ,Core1 power down with WIFI Request" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " EN_C0_PDN ,Core0 power down with low power mode Request" "Disabled,Enabled" bitfld.long 0x04 0. " EN_C0__WIFI_PDN ,Core0 power down with WIFI Request" "Disabled,Enabled" line.long 0x08 "LPCR_M4,Low power control register of CPU1" bitfld.long 0x08 31. " MASK_DSM_TRTGGER ,DSM trigger mask" "Not masked,Masked" bitfld.long 0x08 16. " MASK_M4_WIFI ,M4 WIFI Mask" "Not masked,Masked" bitfld.long 0x08 14. " CPU_CLK_ON_LPM ,M4 clocks enable in wait/stop mode" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " EN_M4_PUP ,Enable m4 virtual PGC power up with LPM enter" "Disabled,Enabled" bitfld.long 0x08 2. " EN_M4_PDN ,Enable m4 virtual PGC power down with LPM enter" "Disabled,Enabled" bitfld.long 0x08 0.--1. " LPM0 ,Setting the low power mode" "Remain in RUN,Transfer to WAIT,Transfer to STOP,?..." if (((per.l(ad:0x303A0000+0x14))&0x40000004)==0x40000004) group.long 0x14++0x03 line.long 0x00 "SLPCR,System low power control register" bitfld.long 0x00 31. " EN_DSM ,DSM enable" "Disabled,Enabled" bitfld.long 0x00 30. " RBC_EN ,Enable for REG_BYPASS_COUNTER" "Disabled,Enabled" bitfld.long 0x00 24.--29. " REG_BYPASS_COUNT ,Counter for REG_BYPASS signal assertion" "No delay,1 CKIL,2 CKIL,3 CKIL,4 CKIL,5 CKIL,6 CKIL,7 CKIL,8 CKIL,9 CKIL,10 CKIL,11 CKIL,12 CKIL,13 CKIL,14 CKIL,15 CKIL,16 CKIL,17 CKIL,18 CKIL,19 CKIL,20 CKIL,21 CKIL,22 CKIL,23 CKIL,24 CKIL,25 CKIL,26 CKIL,27 CKIL,28 CKIL,29 CKIL,30 CKIL,31 CKIL,32 CKIL,33 CKIL,34 CKIL,35 CKIL,36 CKIL,37 CKIL,38 CKIL,39 CKIL,40 CKIL,41 CKIL,42 CKIL,43 CKIL,44 CKIL,45 CKIL,46 CKIL,47 CKIL,48 CKIL,49 CKIL,50 CKIL,51 CKIL,52 CKIL,53 CKIL,54 CKIL,55 CKIL,56 CKIL,57 CKIL,58 CKIL,59 CKIL,60 CKIL,61 CKIL,62 CKIL,63 CKIL" textline " " bitfld.long 0x00 23. " DISABLE_A53_IS_DSM ,A53 isolation signal in DSM" "Enabled,Disabled" bitfld.long 0x00 19. " EN_M4_FASTWUP_STOP_MODE ,Enable M4 fast wake up stop mode" "Disabled,Enabled" bitfld.long 0x00 18. " EN_M4_FASTWUP_WAIT_MODE ,Enable M4 fast wake up wait mode" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " EN_A53_FASTWUP_STOP_MODE ,Enable A53 fast wake up stop mode" "Disabled,Enabled" bitfld.long 0x00 16. " EN_A53_FASTWUP_WAIT_MODE ,Enable A53 fast wake up wait mode" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " OSCCNT ,Oscillator ready counter value" textline " " bitfld.long 0x00 7. " COSC_EN ,ON-chip oscillator enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " COSC_PWRDOWN ,ON-chip oscillator power down" "Not powered down,Powered down" bitfld.long 0x00 3.--5. " STBY_COUNT ,Standby counter definition" "4 CKIL,8 CKIL,16 CKIL,32 CKIL,64 CKIL,128 CKIL,256 CKIL,512 CKIL" textline " " bitfld.long 0x00 2. " VSTBY ,Voltage standby request after entrance to stop mode" "Not requested,Requested" bitfld.long 0x00 1. " SBYOS ,Standby clock oscillator" "Not powered down,Powered down" bitfld.long 0x00 0. " BYPASS_PMIC_READY ,Bypass PMIC_READY signal" "Not bypass,Bypass" else group.long 0x14++0x03 line.long 0x00 "SLPCR,System low power control register" bitfld.long 0x00 31. " EN_DSM ,DSM enable" "Disabled,Enabled" bitfld.long 0x00 30. " RBC_EN ,Enable for REG_BYPASS_COUNTER" "Disabled,Enabled" bitfld.long 0x00 23. " DISABLE_A53_IS_DSM ,A53 isolation signal in DSM" "Enabled,Disabled" textline " " bitfld.long 0x00 19. " EN_M4_FASTWUP_STOP_MODE ,Enable M4 fast wake up stop mode" "Disabled,Enabled" bitfld.long 0x00 18. " EN_M4_FASTWUP_WAIT_MODE ,Enable M4 fast wake up wait mode" "Disabled,Enabled" bitfld.long 0x00 17. " EN_A53_FASTWUP_STOP_MODE ,Enable A53 fast wake up stop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " EN_A53_FASTWUP_WAIT_MODE ,Enable A53 fast wake up wait mode" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " OSCCNT ,Oscillator ready counter value" bitfld.long 0x00 7. " COSC_EN ,ON-chip oscillator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " COSC_PWRDOWN ,ON-chip oscillator power down" "Not powered down,Powered down" bitfld.long 0x00 3.--5. " STBY_COUNT ,Standby counter definition" "4 CKIL,8 CKIL,16 CKIL,32 CKIL,64 CKIL,128 CKIL,256 CKIL,512 CKIL" bitfld.long 0x00 2. " VSTBY ,Voltage standby request after entrance to stop mode" "Not requested,Requested" textline " " bitfld.long 0x00 1. " SBYOS ,Standby clock oscillator" ",Powered down" bitfld.long 0x00 0. " BYPASS_PMIC_READY ,Bypass PMIC_READY signal" "Not bypass,Bypass" endif group.long 0x18++0x03 line.long 0x00 "MST_CPU_MAPPING,MASTER LPM Handshake" hexmask.long 0x00 1.--31. 1. " MEMLP_RET_PGEN ,Delay counter for retnx and pgen" bitfld.long 0x00 0. " MST0_CPU_MAPPING ,MASTER0 CPU Mapping" "Not sent,Sent" group.long 0x20++0x3F line.long 0x00 "MLPCR, Memory low power control register" hexmask.long.byte 0x00 24.--31. 1. " MEMLP_RET_PGEN ,Delay counter for retnx and pgen" hexmask.long.byte 0x00 16.--23. 1. " MEM_EXT_CNT ,Delay counter to start existing from memory low power" hexmask.long.byte 0x00 8.--15. 1. " MEMLP_ENT_CNT ,Delay counter to make all clock off" textline " " bitfld.long 0x00 2. " ROMLP_PDN_DIS ,ROM shut down control disable" "No,Yes" bitfld.long 0x00 1. " MEMLP_RET_SEL ,Retention select" "Mode 2,Mode 1" bitfld.long 0x00 0. " MEMLP_CTL_DIS ,ROM low-power control disable" "No,Yes" line.long 0x04 "PGC_ACK_SEL_A53,PGC acknowledge signal selection of A53 platform" bitfld.long 0x04 31. " A53_PGC_PUP_ACK ,Power up acknowledge signal of A53 PGC" "Disabled,Enabled" bitfld.long 0x04 30. " A53_C3_PGC_PUP_ACK ,Power up acknowledge signal of A53 CORE3 PGC" "Disabled,Enabled" bitfld.long 0x04 29. " A53_C2_PGC_PUP_ACK ,Power up acknowledge signal of A53 CORE2 PGC" "Disabled,Enabled" textline " " bitfld.long 0x04 18. " A53_PLAT_PGC_PUP_ACK ,Power up acknowledge signal of A53 Platform PGC" "Disabled,Enabled" bitfld.long 0x04 17. " A53_C1_PGC_PUP_ACK ,Power up acknowledge signal of A53 CORE1 PGC" "Disabled,Enabled" bitfld.long 0x04 16. " A53_C0_PGC_PUP_ACK ,Power up acknowledge signal of A53 CORE0 PGC" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " A53_PGC_PDN_ACK ,Power down acknowledge signal of A53 PGC" "Disabled,Enabled" bitfld.long 0x04 14. " A53_C3_PGC_PDN_ACK ,Power down acknowledge signal of A53 CORE3 PGC" "Disabled,Enabled" bitfld.long 0x04 13. " A53_C2_PGC_PDN_ACK ,Power down acknowledge signal of A53 CORE2 PGC" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " A53_PLAT_PGC_PDN_ACK ,Power down acknowledge signal of A53 Platform PGC" "Disabled,Enabled" bitfld.long 0x04 1. " A53_C1_PGC_PDN_ACK ,Power down acknowledge signal of A53 CORE1 PGC" "Disabled,Enabled" bitfld.long 0x04 0. " A53_C0_PGC_PDN_ACK ,Power down acknowledge signal of A53 CORE0 PGC" "Disabled,Enabled" line.long 0x08 "PGC_ACK_SEL_M4,PGC acknowledge signal selection of M4 platform" bitfld.long 0x08 31. " M4_DUMMY_PGC_PUP_ACK ,Power up acknowledge signal of M4 PGC" "Disabled,Enabled" bitfld.long 0x08 16. " M4_VIRTUAL_PGC_PUP_ACK ,Power up acknowledge signal of M4 virtual PGC" "Disabled,Enabled" bitfld.long 0x08 15. " M4_DUMMY_PGC_PDN_ACK ,Power down acknowledge signal of M4 PGC" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " M4_VIRTUAL_PGC_PDN_ACK ,Power down acknowledge signal of M4 virtual PGC" "Disabled,Enabled" line.long 0x0C "MISC,Miscellaneous register" bitfld.long 0x0C 25. " M4_BYPASS_PUP_MASK ,M4 power up bypass mask" "Not masked,Masked" bitfld.long 0x0C 24. " A53_BYPASS_PUP_MASK ,A53 power up bypass mask" "Not masked,Masked" bitfld.long 0x0C 8. " M4_PDN_REQ_MASK ,M4 power-down mask" "Masked,Not masked" textline " " bitfld.long 0x0C 5. " GPC_IRQ_MASK ,GPC interrupt/event masking" "Not masked,Masked" bitfld.long 0x0C 1. " A53_SLEEP_HOLD_REQ_B ,A53 sleep hold" "Held,Not held" bitfld.long 0x0C 0. " M4_SLEEP_HOLD_REQ_B ,M4 sleep hold" "Held,Not held" line.long 0x10 "IMR1_CORE0_A53,IRQ masking register 1 of A53 core0" bitfld.long 0x10 31. " IMR1_CORE0_A53[31] ,A53 core0 IRQ[31] mask bit 31" "Not masked,Masked" bitfld.long 0x10 30. " [30] ,A53 core0 IRQ[30] mask bit 30" "Not masked,Masked" bitfld.long 0x10 29. " [29] ,A53 core0 IRQ[29] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x10 28. " [28] ,A53 core0 IRQ[28] mask bit 28" "Not masked,Masked" bitfld.long 0x10 27. " [27] ,A53 core0 IRQ[27] mask bit 27" "Not masked,Masked" bitfld.long 0x10 26. " [26] ,A53 core0 IRQ[26] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x10 25. " [25] ,A53 core0 IRQ[25] mask bit 25" "Not masked,Masked" bitfld.long 0x10 24. " [24] ,A53 core0 IRQ[24] mask bit 24" "Not masked,Masked" bitfld.long 0x10 23. " [23] ,A53 core0 IRQ[23] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x10 22. " [22] ,A53 core0 IRQ[22] mask bit 22" "Not masked,Masked" bitfld.long 0x10 21. " [21] ,A53 core0 IRQ[21] mask bit 21" "Not masked,Masked" bitfld.long 0x10 20. " [20] ,A53 core0 IRQ[20] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x10 19. " [19] ,A53 core0 IRQ[19] mask bit 19" "Not masked,Masked" bitfld.long 0x10 18. " [18] ,A53 core0 IRQ[18] mask bit 18" "Not masked,Masked" bitfld.long 0x10 17. " [17] ,A53 core0 IRQ[17] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x10 16. " [16] ,A53 core0 IRQ[16] mask bit 16" "Not masked,Masked" bitfld.long 0x10 15. " [15] ,A53 core0 IRQ[15] mask bit 15" "Not masked,Masked" bitfld.long 0x10 14. " [14] ,A53 core0 IRQ[14] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x10 13. " [13] ,A53 core0 IRQ[13] mask bit 13" "Not masked,Masked" bitfld.long 0x10 12. " [12] ,A53 core0 IRQ[12] mask bit 12" "Not masked,Masked" bitfld.long 0x10 11. " [11] ,A53 core0 IRQ[11] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x10 10. " [10] ,A53 core0 IRQ[10] mask bit 10" "Not masked,Masked" bitfld.long 0x10 9. " [9] ,A53 core0 IRQ[9] mask bit 9" "Not masked,Masked" bitfld.long 0x10 8. " [8] ,A53 core0 IRQ[8] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x10 7. " [7] ,A53 core0 IRQ[7] mask bit 7" "Not masked,Masked" bitfld.long 0x10 6. " [6] ,A53 core0 IRQ[6] mask bit 6" "Not masked,Masked" bitfld.long 0x10 5. " [5] ,A53 core0 IRQ[5] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x10 4. " [4] ,A53 core0 IRQ[4] mask bit 4" "Not masked,Masked" bitfld.long 0x10 3. " [3] ,A53 core0 IRQ[3] mask bit 3" "Not masked,Masked" bitfld.long 0x10 2. " [2] ,A53 core0 IRQ[2] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x10 1. " [1] ,A53 core0 IRQ[1] mask bit 1" "Not masked,Masked" bitfld.long 0x10 0. " [0] ,A53 core0 IRQ[0] mask bit 0" "Not masked,Masked" line.long 0x14 "IMR2_CORE0_A53,IRQ masking register 2 of A53 core0" bitfld.long 0x14 31. " IMR2_CORE0_A53[63] ,A53 core0 IRQ[63] mask bit 31" "Not masked,Masked" bitfld.long 0x14 30. " [62] ,A53 core0 IRQ[62] mask bit 30" "Not masked,Masked" bitfld.long 0x14 29. " [61] ,A53 core0 IRQ[61] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x14 28. " [60] ,A53 core0 IRQ[60] mask bit 28" "Not masked,Masked" bitfld.long 0x14 27. " [59] ,A53 core0 IRQ[59] mask bit 27" "Not masked,Masked" bitfld.long 0x14 26. " [58] ,A53 core0 IRQ[58] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x14 25. " [57] ,A53 core0 IRQ[57] mask bit 25" "Not masked,Masked" bitfld.long 0x14 24. " [56] ,A53 core0 IRQ[56] mask bit 24" "Not masked,Masked" bitfld.long 0x14 23. " [55] ,A53 core0 IRQ[55] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x14 22. " [54] ,A53 core0 IRQ[54] mask bit 22" "Not masked,Masked" bitfld.long 0x14 21. " [53] ,A53 core0 IRQ[53] mask bit 21" "Not masked,Masked" bitfld.long 0x14 20. " [52] ,A53 core0 IRQ[52] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x14 19. " [51] ,A53 core0 IRQ[51] mask bit 19" "Not masked,Masked" bitfld.long 0x14 18. " [50] ,A53 core0 IRQ[50] mask bit 18" "Not masked,Masked" bitfld.long 0x14 17. " [49] ,A53 core0 IRQ[49] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x14 16. " [48] ,A53 core0 IRQ[48] mask bit 16" "Not masked,Masked" bitfld.long 0x14 15. " [47] ,A53 core0 IRQ[47] mask bit 15" "Not masked,Masked" bitfld.long 0x14 14. " [46] ,A53 core0 IRQ[46] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x14 13. " [45] ,A53 core0 IRQ[45] mask bit 13" "Not masked,Masked" bitfld.long 0x14 12. " [44] ,A53 core0 IRQ[44] mask bit 12" "Not masked,Masked" bitfld.long 0x14 11. " [43] ,A53 core0 IRQ[43] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x14 10. " [42] ,A53 core0 IRQ[42] mask bit 10" "Not masked,Masked" bitfld.long 0x14 9. " [41] ,A53 core0 IRQ[41] mask bit 9" "Not masked,Masked" bitfld.long 0x14 8. " [40] ,A53 core0 IRQ[40] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x14 7. " [39] ,A53 core0 IRQ[39] mask bit 7" "Not masked,Masked" bitfld.long 0x14 6. " [38] ,A53 core0 IRQ[38] mask bit 6" "Not masked,Masked" bitfld.long 0x14 5. " [37] ,A53 core0 IRQ[37] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x14 4. " [36] ,A53 core0 IRQ[36] mask bit 4" "Not masked,Masked" bitfld.long 0x14 3. " [35] ,A53 core0 IRQ[35] mask bit 3" "Not masked,Masked" bitfld.long 0x14 2. " [34] ,A53 core0 IRQ[34] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x14 1. " [33] ,A53 core0 IRQ[33] mask bit 1" "Not masked,Masked" bitfld.long 0x14 0. " [32] ,A53 core0 IRQ[32] mask bit 0" "Not masked,Masked" line.long 0x18 "IMR3_CORE0_A53,IRQ masking register 3 of A53 core0" bitfld.long 0x18 31. " IMR3_CORE0_A53[95] ,A53 core0 IRQ[95] mask bit 31" "Not masked,Masked" bitfld.long 0x18 30. " [94] ,A53 core0 IRQ[94] mask bit 30" "Not masked,Masked" bitfld.long 0x18 29. " [93] ,A53 core0 IRQ[93] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x18 28. " [92] ,A53 core0 IRQ[92] mask bit 28" "Not masked,Masked" bitfld.long 0x18 27. " [91] ,A53 core0 IRQ[91] mask bit 27" "Not masked,Masked" bitfld.long 0x18 26. " [90] ,A53 core0 IRQ[90] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x18 25. " [89] ,A53 core0 IRQ[89] mask bit 25" "Not masked,Masked" bitfld.long 0x18 24. " [88] ,A53 core0 IRQ[88] mask bit 24" "Not masked,Masked" bitfld.long 0x18 23. " [87] ,A53 core0 IRQ[87] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x18 22. " [86] ,A53 core0 IRQ[86] mask bit 22" "Not masked,Masked" bitfld.long 0x18 21. " [85] ,A53 core0 IRQ[85] mask bit 21" "Not masked,Masked" bitfld.long 0x18 20. " [84] ,A53 core0 IRQ[84] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x18 19. " [83] ,A53 core0 IRQ[83] mask bit 19" "Not masked,Masked" bitfld.long 0x18 18. " [82] ,A53 core0 IRQ[82] mask bit 18" "Not masked,Masked" bitfld.long 0x18 17. " [81] ,A53 core0 IRQ[81] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x18 16. " [80] ,A53 core0 IRQ[80] mask bit 16" "Not masked,Masked" bitfld.long 0x18 15. " [79] ,A53 core0 IRQ[79] mask bit 15" "Not masked,Masked" bitfld.long 0x18 14. " [78] ,A53 core0 IRQ[78] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x18 13. " [77] ,A53 core0 IRQ[77] mask bit 13" "Not masked,Masked" bitfld.long 0x18 12. " [76] ,A53 core0 IRQ[76] mask bit 12" "Not masked,Masked" bitfld.long 0x18 11. " [75] ,A53 core0 IRQ[75] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x18 10. " [74] ,A53 core0 IRQ[74] mask bit 10" "Not masked,Masked" bitfld.long 0x18 9. " [73] ,A53 core0 IRQ[73] mask bit 9" "Not masked,Masked" bitfld.long 0x18 8. " [72] ,A53 core0 IRQ[72] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x18 7. " [71] ,A53 core0 IRQ[71] mask bit 7" "Not masked,Masked" bitfld.long 0x18 6. " [70] ,A53 core0 IRQ[70] mask bit 6" "Not masked,Masked" bitfld.long 0x18 5. " [69] ,A53 core0 IRQ[69] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x18 4. " [68] ,A53 core0 IRQ[68] mask bit 4" "Not masked,Masked" bitfld.long 0x18 3. " [67] ,A53 core0 IRQ[67] mask bit 3" "Not masked,Masked" bitfld.long 0x18 2. " [66] ,A53 core0 IRQ[66] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x18 1. " [65] ,A53 core0 IRQ[65] mask bit 1" "Not masked,Masked" bitfld.long 0x18 0. " [64] ,A53 core0 IRQ[64] mask bit 0" "Not masked,Masked" line.long 0x1C "IMR4_CORE0_A53,IRQ masking register 4 of A53 core0" bitfld.long 0x1C 31. " IMR4_CORE0_A53[127] ,A53 core0 IRQ[127] mask bit 31" "Not masked,Masked" bitfld.long 0x1C 30. " [126] ,A53 core0 IRQ[126] mask bit 30" "Not masked,Masked" bitfld.long 0x1C 29. " [125] ,A53 core0 IRQ[125] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x1C 28. " [124] ,A53 core0 IRQ[124] mask bit 28" "Not masked,Masked" bitfld.long 0x1C 27. " [123] ,A53 core0 IRQ[123] mask bit 27" "Not masked,Masked" bitfld.long 0x1C 26. " [122] ,A53 core0 IRQ[122] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x1C 25. " [121] ,A53 core0 IRQ[121] mask bit 25" "Not masked,Masked" bitfld.long 0x1C 24. " [120] ,A53 core0 IRQ[120] mask bit 24" "Not masked,Masked" bitfld.long 0x1C 23. " [119] ,A53 core0 IRQ[119] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x1C 22. " [118] ,A53 core0 IRQ[118] mask bit 22" "Not masked,Masked" bitfld.long 0x1C 21. " [117] ,A53 core0 IRQ[117] mask bit 21" "Not masked,Masked" bitfld.long 0x1C 20. " [116] ,A53 core0 IRQ[116] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x1C 19. " [115] ,A53 core0 IRQ[115] mask bit 19" "Not masked,Masked" bitfld.long 0x1C 18. " [114] ,A53 core0 IRQ[114] mask bit 18" "Not masked,Masked" bitfld.long 0x1C 17. " [113] ,A53 core0 IRQ[113] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x1C 16. " [112] ,A53 core0 IRQ[112] mask bit 16" "Not masked,Masked" bitfld.long 0x1C 15. " [111] ,A53 core0 IRQ[111] mask bit 15" "Not masked,Masked" bitfld.long 0x1C 14. " [110] ,A53 core0 IRQ[110] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x1C 13. " [109] ,A53 core0 IRQ[109] mask bit 13" "Not masked,Masked" bitfld.long 0x1C 12. " [108] ,A53 core0 IRQ[108] mask bit 12" "Not masked,Masked" bitfld.long 0x1C 11. " [107] ,A53 core0 IRQ[107] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x1C 10. " [106] ,A53 core0 IRQ[106] mask bit 10" "Not masked,Masked" bitfld.long 0x1C 9. " [105] ,A53 core0 IRQ[105] mask bit 9" "Not masked,Masked" bitfld.long 0x1C 8. " [104] ,A53 core0 IRQ[104] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x1C 7. " [103] ,A53 core0 IRQ[103] mask bit 7" "Not masked,Masked" bitfld.long 0x1C 6. " [102] ,A53 core0 IRQ[102] mask bit 6" "Not masked,Masked" bitfld.long 0x1C 5. " [101] ,A53 core0 IRQ[101] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x1C 4. " [100] ,A53 core0 IRQ[100] mask bit 4" "Not masked,Masked" bitfld.long 0x1C 3. " [99] ,A53 core0 IRQ[99] mask bit 3" "Not masked,Masked" bitfld.long 0x1C 2. " [98] ,A53 core0 IRQ[98] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x1C 1. " [97] ,A53 core0 IRQ[97] mask bit 1" "Not masked,Masked" bitfld.long 0x1C 0. " [96] ,A53 core0 IRQ[96] mask bit 0" "Not masked,Masked" line.long 0x20 "IMR1_CORE1_A53,IRQ masking register 1 of A53 core1" bitfld.long 0x20 31. " IMR1_CORE1_A53[31] ,A53 core1 IRQ[31] mask bit 31" "Not masked,Masked" bitfld.long 0x20 30. " [30] ,A53 core1 IRQ[30] mask bit 30" "Not masked,Masked" bitfld.long 0x20 29. " [29] ,A53 core1 IRQ[29] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x20 28. " [28] ,A53 core1 IRQ[28] mask bit 28" "Not masked,Masked" bitfld.long 0x20 27. " [27] ,A53 core1 IRQ[27] mask bit 27" "Not masked,Masked" bitfld.long 0x20 26. " [26] ,A53 core1 IRQ[26] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x20 25. " [25] ,A53 core1 IRQ[25] mask bit 25" "Not masked,Masked" bitfld.long 0x20 24. " [24] ,A53 core1 IRQ[24] mask bit 24" "Not masked,Masked" bitfld.long 0x20 23. " [23] ,A53 core1 IRQ[23] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x20 22. " [22] ,A53 core1 IRQ[22] mask bit 22" "Not masked,Masked" bitfld.long 0x20 21. " [21] ,A53 core1 IRQ[21] mask bit 21" "Not masked,Masked" bitfld.long 0x20 20. " [20] ,A53 core1 IRQ[20] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x20 19. " [19] ,A53 core1 IRQ[19] mask bit 19" "Not masked,Masked" bitfld.long 0x20 18. " [18] ,A53 core1 IRQ[18] mask bit 18" "Not masked,Masked" bitfld.long 0x20 17. " [17] ,A53 core1 IRQ[17] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x20 16. " [16] ,A53 core1 IRQ[16] mask bit 16" "Not masked,Masked" bitfld.long 0x20 15. " [15] ,A53 core1 IRQ[15] mask bit 15" "Not masked,Masked" bitfld.long 0x20 14. " [14] ,A53 core1 IRQ[14] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x20 13. " [13] ,A53 core1 IRQ[13] mask bit 13" "Not masked,Masked" bitfld.long 0x20 12. " [12] ,A53 core1 IRQ[12] mask bit 12" "Not masked,Masked" bitfld.long 0x20 11. " [11] ,A53 core1 IRQ[11] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x20 10. " [10] ,A53 core1 IRQ[10] mask bit 10" "Not masked,Masked" bitfld.long 0x20 9. " [9] ,A53 core1 IRQ[9] mask bit 9" "Not masked,Masked" bitfld.long 0x20 8. " [8] ,A53 core1 IRQ[8] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x20 7. " [7] ,A53 core1 IRQ[7] mask bit 7" "Not masked,Masked" bitfld.long 0x20 6. " [6] ,A53 core1 IRQ[6] mask bit 6" "Not masked,Masked" bitfld.long 0x20 5. " [5] ,A53 core1 IRQ[5] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x20 4. " [4] ,A53 core1 IRQ[4] mask bit 4" "Not masked,Masked" bitfld.long 0x20 3. " [3] ,A53 core1 IRQ[3] mask bit 3" "Not masked,Masked" bitfld.long 0x20 2. " [2] ,A53 core1 IRQ[2] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x20 1. " [1] ,A53 core1 IRQ[1] mask bit 1" "Not masked,Masked" bitfld.long 0x20 0. " [0] ,A53 core1 IRQ[0] mask bit 0" "Not masked,Masked" line.long 0x24 "IMR2_CORE1_A53,IRQ masking register 2 of A53 core1" bitfld.long 0x24 31. " IMR2_CORE1_A53[63] ,A53 core1 IRQ[63] mask bit 31" "Not masked,Masked" bitfld.long 0x24 30. " [62] ,A53 core1 IRQ[62] mask bit 30" "Not masked,Masked" bitfld.long 0x24 29. " [61] ,A53 core1 IRQ[61] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x24 28. " [60] ,A53 core1 IRQ[60] mask bit 28" "Not masked,Masked" bitfld.long 0x24 27. " [59] ,A53 core1 IRQ[59] mask bit 27" "Not masked,Masked" bitfld.long 0x24 26. " [58] ,A53 core1 IRQ[58] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x24 25. " [57] ,A53 core1 IRQ[57] mask bit 25" "Not masked,Masked" bitfld.long 0x24 24. " [56] ,A53 core1 IRQ[56] mask bit 24" "Not masked,Masked" bitfld.long 0x24 23. " [55] ,A53 core1 IRQ[55] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x24 22. " [54] ,A53 core1 IRQ[54] mask bit 22" "Not masked,Masked" bitfld.long 0x24 21. " [53] ,A53 core1 IRQ[53] mask bit 21" "Not masked,Masked" bitfld.long 0x24 20. " [52] ,A53 core1 IRQ[52] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x24 19. " [51] ,A53 core1 IRQ[51] mask bit 19" "Not masked,Masked" bitfld.long 0x24 18. " [50] ,A53 core1 IRQ[50] mask bit 18" "Not masked,Masked" bitfld.long 0x24 17. " [49] ,A53 core1 IRQ[49] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x24 16. " [48] ,A53 core1 IRQ[48] mask bit 16" "Not masked,Masked" bitfld.long 0x24 15. " [47] ,A53 core1 IRQ[47] mask bit 15" "Not masked,Masked" bitfld.long 0x24 14. " [46] ,A53 core1 IRQ[46] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x24 13. " [45] ,A53 core1 IRQ[45] mask bit 13" "Not masked,Masked" bitfld.long 0x24 12. " [44] ,A53 core1 IRQ[44] mask bit 12" "Not masked,Masked" bitfld.long 0x24 11. " [43] ,A53 core1 IRQ[43] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x24 10. " [42] ,A53 core1 IRQ[42] mask bit 10" "Not masked,Masked" bitfld.long 0x24 8. " [40] ,A53 core1 IRQ[40] mask bit 9" "Not masked,Masked" bitfld.long 0x24 9. " [41] ,A53 core1 IRQ[41] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x24 7. " [39] ,A53 core1 IRQ[39] mask bit 7" "Not masked,Masked" bitfld.long 0x24 6. " [38] ,A53 core1 IRQ[38] mask bit 6" "Not masked,Masked" bitfld.long 0x24 5. " [37] ,A53 core1 IRQ[37] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x24 4. " [36] ,A53 core1 IRQ[36] mask bit 4" "Not masked,Masked" bitfld.long 0x24 3. " [35] ,A53 core1 IRQ[35] mask bit 3" "Not masked,Masked" bitfld.long 0x24 2. " [34] ,A53 core1 IRQ[34] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x24 1. " [33] ,A53 core1 IRQ[33] mask bit 1" "Not masked,Masked" bitfld.long 0x24 0. " [32] ,A53 core1 IRQ[32] mask bit 0" "Not masked,Masked" line.long 0x28 "IMR3_CORE1_A53,IRQ masking register 3 of A53 core1" bitfld.long 0x28 31. " IMR3_CORE3_A53[95] ,A53 core1 IRQ[95] mask bit 31" "Not masked,Masked" bitfld.long 0x28 30. " [94] ,A53 core1 IRQ[94] mask bit 30" "Not masked,Masked" bitfld.long 0x28 29. " [93] ,A53 core1 IRQ[93] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x28 28. " [92] ,A53 core1 IRQ[92] mask bit 28" "Not masked,Masked" bitfld.long 0x28 27. " [91] ,A53 core1 IRQ[91] mask bit 27" "Not masked,Masked" bitfld.long 0x28 26. " [90] ,A53 core1 IRQ[90] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x28 25. " [89] ,A53 core1 IRQ[89] mask bit 25" "Not masked,Masked" bitfld.long 0x28 24. " [88] ,A53 core1 IRQ[88] mask bit 24" "Not masked,Masked" bitfld.long 0x28 23. " [87] ,A53 core1 IRQ[87] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x28 22. " [86] ,A53 core1 IRQ[86] mask bit 22" "Not masked,Masked" bitfld.long 0x28 21. " [85] ,A53 core1 IRQ[85] mask bit 21" "Not masked,Masked" bitfld.long 0x28 20. " [84] ,A53 core1 IRQ[84] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x28 19. " [83] ,A53 core1 IRQ[83] mask bit 19" "Not masked,Masked" bitfld.long 0x28 18. " [82] ,A53 core1 IRQ[82] mask bit 18" "Not masked,Masked" bitfld.long 0x28 17. " [81] ,A53 core1 IRQ[81] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x28 16. " [80] ,A53 core1 IRQ[80] mask bit 16" "Not masked,Masked" bitfld.long 0x28 15. " [79] ,A53 core1 IRQ[79] mask bit 15" "Not masked,Masked" bitfld.long 0x28 14. " [78] ,A53 core1 IRQ[78] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x28 13. " [77] ,A53 core1 IRQ[77] mask bit 13" "Not masked,Masked" bitfld.long 0x28 12. " [76] ,A53 core1 IRQ[76] mask bit 12" "Not masked,Masked" bitfld.long 0x28 11. " [75] ,A53 core1 IRQ[75] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x28 10. " [74] ,A53 core1 IRQ[74] mask bit 10" "Not masked,Masked" bitfld.long 0x28 9. " [73] ,A53 core1 IRQ[73] mask bit 9" "Not masked,Masked" bitfld.long 0x28 8. " [72] ,A53 core1 IRQ[72] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x28 7. " [71] ,A53 core1 IRQ[71] mask bit 7" "Not masked,Masked" bitfld.long 0x28 6. " [70] ,A53 core1 IRQ[70] mask bit 6" "Not masked,Masked" bitfld.long 0x28 5. " [69] ,A53 core1 IRQ[69] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x28 4. " [68] ,A53 core1 IRQ[68] mask bit 4" "Not masked,Masked" bitfld.long 0x28 3. " [67] ,A53 core1 IRQ[67] mask bit 3" "Not masked,Masked" bitfld.long 0x28 2. " [66] ,A53 core1 IRQ[66] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x28 1. " [65] ,A53 core1 IRQ[65] mask bit 1" "Not masked,Masked" bitfld.long 0x28 0. " [64] ,A53 core1 IRQ[64] mask bit 0" "Not masked,Masked" line.long 0x2C "IMR4_CORE1_A53,IRQ masking register 4 of A53 core1" bitfld.long 0x2C 31. " IMR4_CORE1_A53[127] ,A53 core1 IRQ[127] mask bit 31" "Not masked,Masked" bitfld.long 0x2C 30. " [126] ,A53 core1 IRQ[126] mask bit 30" "Not masked,Masked" bitfld.long 0x2C 29. " [125] ,A53 core1 IRQ[125] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x2C 28. " [124] ,A53 core1 IRQ[124] mask bit 28" "Not masked,Masked" bitfld.long 0x2C 27. " [123] ,A53 core1 IRQ[123] mask bit 27" "Not masked,Masked" bitfld.long 0x2C 26. " [122] ,A53 core1 IRQ[122] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x2C 25. " [121] ,A53 core1 IRQ[121] mask bit 25" "Not masked,Masked" bitfld.long 0x2C 24. " [120] ,A53 core1 IRQ[120] mask bit 24" "Not masked,Masked" bitfld.long 0x2C 23. " [119] ,A53 core1 IRQ[119] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x2C 22. " [118] ,A53 core1 IRQ[118] mask bit 22" "Not masked,Masked" bitfld.long 0x2C 21. " [117] ,A53 core1 IRQ[117] mask bit 21" "Not masked,Masked" bitfld.long 0x2C 20. " [116] ,A53 core1 IRQ[116] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x2C 19. " [115] ,A53 core1 IRQ[115] mask bit 19" "Not masked,Masked" bitfld.long 0x2C 18. " [114] ,A53 core1 IRQ[114] mask bit 18" "Not masked,Masked" bitfld.long 0x2C 17. " [113] ,A53 core1 IRQ[113] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x2C 16. " [112] ,A53 core1 IRQ[112] mask bit 16" "Not masked,Masked" bitfld.long 0x2C 15. " [111] ,A53 core1 IRQ[111] mask bit 15" "Not masked,Masked" bitfld.long 0x2C 14. " [110] ,A53 core1 IRQ[110] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x2C 13. " [109] ,A53 core1 IRQ[109] mask bit 13" "Not masked,Masked" bitfld.long 0x2C 12. " [108] ,A53 core1 IRQ[108] mask bit 12" "Not masked,Masked" bitfld.long 0x2C 11. " [107] ,A53 core1 IRQ[107] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x2C 10. " [106] ,A53 core1 IRQ[106] mask bit 10" "Not masked,Masked" bitfld.long 0x2C 9. " [105] ,A53 core1 IRQ[105] mask bit 9" "Not masked,Masked" bitfld.long 0x2C 8. " [104] ,A53 core1 IRQ[104] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x2C 7. " [103] ,A53 core1 IRQ[103] mask bit 7" "Not masked,Masked" bitfld.long 0x2C 6. " [102] ,A53 core1 IRQ[102] mask bit 6" "Not masked,Masked" bitfld.long 0x2C 5. " [101] ,A53 core1 IRQ[101] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x2C 4. " [100] ,A53 core1 IRQ[100] mask bit 4" "Not masked,Masked" bitfld.long 0x2C 3. " [99] ,A53 core1 IRQ[99] mask bit 3" "Not masked,Masked" bitfld.long 0x2C 2. " [98] ,A53 core1 IRQ[98] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x2C 1. " [97] ,A53 core1 IRQ[97] mask bit 1" "Not masked,Masked" bitfld.long 0x2C 0. " [96] ,A53 core1 IRQ[96] mask bit 0" "Not masked,Masked" line.long 0x30 "IMR1_M4,IRQ masking register 1 of M4" bitfld.long 0x30 31. " IMR1_M4[31] ,M4 IRQ[31] mask bit 31" "Not masked,Masked" bitfld.long 0x30 30. " [30] ,M4 IRQ[30] mask bit 30" "Not masked,Masked" bitfld.long 0x30 29. " [29] ,M4 IRQ[29] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x30 28. " [28] ,M4 IRQ[28] mask bit 28" "Not masked,Masked" bitfld.long 0x30 27. " [27] ,M4 IRQ[27] mask bit 27" "Not masked,Masked" bitfld.long 0x30 26. " [26] ,M4 IRQ[26] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x30 25. " [25] ,M4 IRQ[25] mask bit 25" "Not masked,Masked" bitfld.long 0x30 24. " [24] ,M4 IRQ[24] mask bit 24" "Not masked,Masked" bitfld.long 0x30 23. " [23] ,M4 IRQ[23] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x30 22. " [22] ,M4 IRQ[22] mask bit 22" "Not masked,Masked" bitfld.long 0x30 21. " [21] ,M4 IRQ[21] mask bit 21" "Not masked,Masked" bitfld.long 0x30 20. " [20] ,M4 IRQ[20] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x30 19. " [19] ,M4 IRQ[19] mask bit 19" "Not masked,Masked" bitfld.long 0x30 18. " [18] ,M4 IRQ[18] mask bit 18" "Not masked,Masked" bitfld.long 0x30 17. " [17] ,M4 IRQ[17] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x30 16. " [16] ,M4 IRQ[16] mask bit 16" "Not masked,Masked" bitfld.long 0x30 15. " [15] ,M4 IRQ[15] mask bit 15" "Not masked,Masked" bitfld.long 0x30 14. " [14] ,M4 IRQ[14] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x30 13. " [13] ,M4 IRQ[13] mask bit 13" "Not masked,Masked" bitfld.long 0x30 12. " [12] ,M4 IRQ[12] mask bit 12" "Not masked,Masked" bitfld.long 0x30 11. " [11] ,M4 IRQ[11] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x30 10. " [10] ,M4 IRQ[10] mask bit 10" "Not masked,Masked" bitfld.long 0x30 9. " [9] ,M4 IRQ[9] mask bit 9" "Not masked,Masked" bitfld.long 0x30 8. " [8] ,M4 IRQ[8] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x30 7. " [7] ,M4 IRQ[7] mask bit 7" "Not masked,Masked" bitfld.long 0x30 6. " [6] ,M4 IRQ[6] mask bit 6" "Not masked,Masked" bitfld.long 0x30 5. " [5] ,M4 IRQ[5] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x30 4. " [4] ,M4 IRQ[4] mask bit 4" "Not masked,Masked" bitfld.long 0x30 3. " [3] ,M4 IRQ[3] mask bit 3" "Not masked,Masked" bitfld.long 0x30 2. " [2] ,M4 IRQ[2] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x30 1. " [1] ,M4 IRQ[1] mask bit 1" "Not masked,Masked" bitfld.long 0x30 0. " [0] ,M4 IRQ[0] mask bit 0" "Not masked,Masked" line.long 0x34 "IMR2_M4,IRQ masking register 2 of M4" bitfld.long 0x34 31. " IMR2_M4[63] ,M4 IRQ[63] mask bit 31" "Not masked,Masked" bitfld.long 0x34 30. " [62] ,M4 IRQ[62] mask bit 30" "Not masked,Masked" bitfld.long 0x34 29. " [61] ,M4 IRQ[61] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x34 28. " [60] ,M4 IRQ[60] mask bit 28" "Not masked,Masked" bitfld.long 0x34 27. " [59] ,M4 IRQ[59] mask bit 27" "Not masked,Masked" bitfld.long 0x34 26. " [58] ,M4 IRQ[58] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x34 25. " [57] ,M4 IRQ[57] mask bit 25" "Not masked,Masked" bitfld.long 0x34 24. " [56] ,M4 IRQ[56] mask bit 24" "Not masked,Masked" bitfld.long 0x34 23. " [55] ,M4 IRQ[55] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x34 22. " [54] ,M4 IRQ[54] mask bit 22" "Not masked,Masked" bitfld.long 0x34 21. " [53] ,M4 IRQ[53] mask bit 21" "Not masked,Masked" bitfld.long 0x34 20. " [52] ,M4 IRQ[52] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x34 19. " [51] ,M4 IRQ[51] mask bit 19" "Not masked,Masked" bitfld.long 0x34 18. " [50] ,M4 IRQ[50] mask bit 18" "Not masked,Masked" bitfld.long 0x34 17. " [49] ,M4 IRQ[49] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x34 16. " [48] ,M4 IRQ[48] mask bit 16" "Not masked,Masked" bitfld.long 0x34 15. " [47] ,M4 IRQ[47] mask bit 15" "Not masked,Masked" bitfld.long 0x34 14. " [46] ,M4 IRQ[46] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x34 13. " [45] ,M4 IRQ[45] mask bit 13" "Not masked,Masked" bitfld.long 0x34 12. " [44] ,M4 IRQ[44] mask bit 12" "Not masked,Masked" bitfld.long 0x34 11. " [43] ,M4 IRQ[43] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x34 10. " [42] ,M4 IRQ[42] mask bit 10" "Not masked,Masked" bitfld.long 0x34 9. " [41] ,M4 IRQ[41] mask bit 9" "Not masked,Masked" bitfld.long 0x34 8. " [40] ,M4 IRQ[40] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x34 7. " [39] ,M4 IRQ[39] mask bit 7" "Not masked,Masked" bitfld.long 0x34 6. " [38] ,M4 IRQ[38] mask bit 6" "Not masked,Masked" bitfld.long 0x34 5. " [37] ,M4 IRQ[37] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x34 4. " [36] ,M4 IRQ[36] mask bit 4" "Not masked,Masked" bitfld.long 0x34 3. " [35] ,M4 IRQ[35] mask bit 3" "Not masked,Masked" bitfld.long 0x34 2. " [34] ,M4 IRQ[34] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x34 1. " [33] ,M4 IRQ[33] mask bit 1" "Not masked,Masked" bitfld.long 0x34 0. " [32] ,M4 IRQ[32] mask bit 0" "Not masked,Masked" line.long 0x38 "IMR3_M4,IRQ masking register 3 of M4" bitfld.long 0x38 31. " IMR3_M4[95] ,M4 IRQ[95] mask bit 31" "Not masked,Masked" bitfld.long 0x38 30. " [94] ,M4 IRQ[94] mask bit 30" "Not masked,Masked" bitfld.long 0x38 29. " [93] ,M4 IRQ[93] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x38 28. " [92] ,M4 IRQ[92] mask bit 28" "Not masked,Masked" bitfld.long 0x38 27. " [91] ,M4 IRQ[91] mask bit 27" "Not masked,Masked" bitfld.long 0x38 26. " [90] ,M4 IRQ[90] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x38 25. " [89] ,M4 IRQ[89] mask bit 25" "Not masked,Masked" bitfld.long 0x38 24. " [88] ,M4 IRQ[88] mask bit 24" "Not masked,Masked" bitfld.long 0x38 23. " [87] ,M4 IRQ[87] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x38 22. " [86] ,M4 IRQ[86] mask bit 22" "Not masked,Masked" bitfld.long 0x38 21. " [85] ,M4 IRQ[85] mask bit 21" "Not masked,Masked" bitfld.long 0x38 20. " [84] ,M4 IRQ[84] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x38 19. " [83] ,M4 IRQ[83] mask bit 19" "Not masked,Masked" bitfld.long 0x38 18. " [82] ,M4 IRQ[82] mask bit 18" "Not masked,Masked" bitfld.long 0x38 17. " [81] ,M4 IRQ[81] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x38 16. " [80] ,M4 IRQ[80] mask bit 16" "Not masked,Masked" bitfld.long 0x38 15. " [79] ,M4 IRQ[79] mask bit 15" "Not masked,Masked" bitfld.long 0x38 14. " [78] ,M4 IRQ[78] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x38 13. " [77] ,M4 IRQ[77] mask bit 13" "Not masked,Masked" bitfld.long 0x38 12. " [76] ,M4 IRQ[76] mask bit 12" "Not masked,Masked" bitfld.long 0x38 11. " [75] ,M4 IRQ[75] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x38 10. " [74] ,M4 IRQ[74] mask bit 10" "Not masked,Masked" bitfld.long 0x38 9. " [73] ,M4 IRQ[73] mask bit 9" "Not masked,Masked" bitfld.long 0x38 8. " [72] ,M4 IRQ[72] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x38 7. " [71] ,M4 IRQ[71] mask bit 7" "Not masked,Masked" bitfld.long 0x38 6. " [70] ,M4 IRQ[70] mask bit 6" "Not masked,Masked" bitfld.long 0x38 5. " [69] ,M4 IRQ[69] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x38 4. " [68] ,M4 IRQ[68] mask bit 4" "Not masked,Masked" bitfld.long 0x38 3. " [67] ,M4 IRQ[67] mask bit 3" "Not masked,Masked" bitfld.long 0x38 2. " [66] ,M4 IRQ[66] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x38 1. " [65] ,M4 IRQ[65] mask bit 1" "Not masked,Masked" bitfld.long 0x38 0. " [64] ,M4 IRQ[64] mask bit 0" "Not masked,Masked" line.long 0x3C "IMR4_M4,IRQ masking register 4 of M4" bitfld.long 0x3C 31. " IMR4_M4[127] ,M4 IRQ[127] mask bit 31" "Not masked,Masked" bitfld.long 0x3C 30. " [126] ,M4 IRQ[126] mask bit 30" "Not masked,Masked" bitfld.long 0x3C 29. " [125] ,M4 IRQ[125] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x3C 28. " [124] ,M4 IRQ[124] mask bit 28" "Not masked,Masked" bitfld.long 0x3C 27. " [123] ,M4 IRQ[123] mask bit 27" "Not masked,Masked" bitfld.long 0x3C 26. " [122] ,M4 IRQ[122] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x3C 25. " [121] ,M4 IRQ[121] mask bit 25" "Not masked,Masked" bitfld.long 0x3C 24. " [120] ,M4 IRQ[120] mask bit 24" "Not masked,Masked" bitfld.long 0x3C 23. " [119] ,M4 IRQ[119] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x3C 22. " [118] ,M4 IRQ[118] mask bit 22" "Not masked,Masked" bitfld.long 0x3C 21. " [117] ,M4 IRQ[117] mask bit 21" "Not masked,Masked" bitfld.long 0x3C 20. " [116] ,M4 IRQ[116] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x3C 19. " [115] ,M4 IRQ[115] mask bit 19" "Not masked,Masked" bitfld.long 0x3C 18. " [114] ,M4 IRQ[114] mask bit 18" "Not masked,Masked" bitfld.long 0x3C 17. " [113] ,M4 IRQ[113] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x3C 16. " [112] ,M4 IRQ[112] mask bit 16" "Not masked,Masked" bitfld.long 0x3C 15. " [111] ,M4 IRQ[111] mask bit 15" "Not masked,Masked" bitfld.long 0x3C 14. " [110] ,M4 IRQ[110] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x3C 13. " [109] ,M4 IRQ[109] mask bit 13" "Not masked,Masked" bitfld.long 0x3C 12. " [108] ,M4 IRQ[108] mask bit 12" "Not masked,Masked" bitfld.long 0x3C 11. " [107] ,M4 IRQ[107] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x3C 10. " [106] ,M4 IRQ[106] mask bit 10" "Not masked,Masked" bitfld.long 0x3C 9. " [105] ,M4 IRQ[105] mask bit 9" "Not masked,Masked" bitfld.long 0x3C 8. " [104] ,M4 IRQ[104] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x3C 7. " [103] ,M4 IRQ[103] mask bit 7" "Not masked,Masked" bitfld.long 0x3C 6. " [102] ,M4 IRQ[102] mask bit 6" "Not masked,Masked" bitfld.long 0x3C 5. " [101] ,M4 IRQ[101] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x3C 4. " [100] ,M4 IRQ[100] mask bit 4" "Not masked,Masked" bitfld.long 0x3C 3. " [99] ,M4 IRQ[99] mask bit 3" "Not masked,Masked" bitfld.long 0x3C 2. " [98] ,M4 IRQ[98] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x3C 1. " [97] ,M4 IRQ[97] mask bit 1" "Not masked,Masked" bitfld.long 0x3C 0. " [96] ,M4 IRQ[96] mask bit 0" "Not masked,Masked" rgroup.long 0x70++0x1F line.long 0x00 "ISR1_A53,IRQ masking register 1 of A53" bitfld.long 0x00 31. " ISR1_A53[31] ,A53 IRQ[31] status" "0,1" bitfld.long 0x00 30. " [30] ,A53 IRQ[30] status" "0,1" bitfld.long 0x00 29. " [29] ,A53 IRQ[29] status" "0,1" textline " " bitfld.long 0x00 28. " [28] ,A53 IRQ[28] status" "0,1" bitfld.long 0x00 27. " [27] ,A53 IRQ[27] status" "0,1" bitfld.long 0x00 26. " [26] ,A53 IRQ[26] status" "0,1" textline " " bitfld.long 0x00 25. " [25] ,A53 IRQ[25] status" "0,1" bitfld.long 0x00 24. " [24] ,A53 IRQ[24] status" "0,1" bitfld.long 0x00 23. " [23] ,A53 IRQ[23] status" "0,1" textline " " bitfld.long 0x00 22. " [22] ,A53 IRQ[22] status" "0,1" bitfld.long 0x00 21. " [21] ,A53 IRQ[21] status" "0,1" bitfld.long 0x00 20. " [20] ,A53 IRQ[20] status" "0,1" textline " " bitfld.long 0x00 19. " [19] ,A53 IRQ[19] status" "0,1" bitfld.long 0x00 18. " [18] ,A53 IRQ[18] status" "0,1" bitfld.long 0x00 17. " [17] ,A53 IRQ[17] status" "0,1" textline " " bitfld.long 0x00 16. " [16] ,A53 IRQ[16] status" "0,1" bitfld.long 0x00 15. " [15] ,A53 IRQ[15] status" "0,1" bitfld.long 0x00 14. " [14] ,A53 IRQ[14] status" "0,1" textline " " bitfld.long 0x00 13. " [13] ,A53 IRQ[13] status" "0,1" bitfld.long 0x00 12. " [12] ,A53 IRQ[12] status" "0,1" bitfld.long 0x00 11. " [11] ,A53 IRQ[11] status" "0,1" textline " " bitfld.long 0x00 10. " [10] ,A53 IRQ[10] status" "0,1" bitfld.long 0x00 9. " [9] ,A53 IRQ[9] status" "0,1" bitfld.long 0x00 8. " [8] ,A53 IRQ[8] status" "0,1" textline " " bitfld.long 0x00 7. " [7] ,A53 IRQ[7] status" "0,1" bitfld.long 0x00 6. " [6] ,A53 IRQ[6] status" "0,1" bitfld.long 0x00 5. " [5] ,A53 IRQ[5] status" "0,1" textline " " bitfld.long 0x00 4. " [4] ,A53 IRQ[4] status" "0,1" bitfld.long 0x00 3. " [3] ,A53 IRQ[3] status" "0,1" bitfld.long 0x00 2. " [2] ,A53 IRQ[2] status" "0,1" textline " " bitfld.long 0x00 1. " [1] ,A53 IRQ[1] status" "0,1" bitfld.long 0x00 0. " [0] ,A53 IRQ[0] status" "0,1" line.long 0x04 "ISR2_A53,IRQ masking register 2 of A53" bitfld.long 0x04 31. " ISR2_A53[63] ,A53 IRQ[63] status" "0,1" bitfld.long 0x04 30. " [62] ,A53 IRQ[62] status" "0,1" bitfld.long 0x04 29. " [61] ,A53 IRQ[61] status" "0,1" textline " " bitfld.long 0x04 28. " [60] ,A53 IRQ[60] status" "0,1" bitfld.long 0x04 27. " [59] ,A53 IRQ[59] status" "0,1" bitfld.long 0x04 26. " [58] ,A53 IRQ[58] status" "0,1" textline " " bitfld.long 0x04 25. " [57] ,A53 IRQ[57] status" "0,1" bitfld.long 0x04 24. " [56] ,A53 IRQ[56] status" "0,1" bitfld.long 0x04 23. " [55] ,A53 IRQ[55] status" "0,1" textline " " bitfld.long 0x04 22. " [54] ,A53 IRQ[54] status" "0,1" bitfld.long 0x04 21. " [53] ,A53 IRQ[53] status" "0,1" bitfld.long 0x04 20. " [52] ,A53 IRQ[52] status" "0,1" textline " " bitfld.long 0x04 19. " [51] ,A53 IRQ[51] status" "0,1" bitfld.long 0x04 18. " [50] ,A53 IRQ[50] status" "0,1" bitfld.long 0x04 17. " [49] ,A53 IRQ[49] status" "0,1" textline " " bitfld.long 0x04 16. " [48] ,A53 IRQ[48] status" "0,1" bitfld.long 0x04 15. " [47] ,A53 IRQ[47] status" "0,1" bitfld.long 0x04 14. " [46] ,A53 IRQ[46] status" "0,1" textline " " bitfld.long 0x04 13. " [45] ,A53 IRQ[45] status" "0,1" bitfld.long 0x04 12. " [44] ,A53 IRQ[44] status" "0,1" bitfld.long 0x04 11. " [43] ,A53 IRQ[43] status" "0,1" textline " " bitfld.long 0x04 10. " [42] ,A53 IRQ[42] status" "0,1" bitfld.long 0x04 9. " [41] ,A53 IRQ[41] status" "0,1" bitfld.long 0x04 8. " [40] ,A53 IRQ[40] status" "0,1" textline " " bitfld.long 0x04 7. " [39] ,A53 IRQ[39] status" "0,1" bitfld.long 0x04 6. " [38] ,A53 IRQ[38] status" "0,1" bitfld.long 0x04 5. " [37] ,A53 IRQ[37] status" "0,1" textline " " bitfld.long 0x04 4. " [36] ,A53 IRQ[36] status" "0,1" bitfld.long 0x04 3. " [35] ,A53 IRQ[35] status" "0,1" bitfld.long 0x04 2. " [34] ,A53 IRQ[34] status" "0,1" textline " " bitfld.long 0x04 1. " [33] ,A53 IRQ[33] status" "0,1" bitfld.long 0x04 0. " [32] ,A53 IRQ[32] status" "0,1" line.long 0x08 "ISR3_A53,IRQ masking register 3 of A53" bitfld.long 0x08 31. " ISR3_A53[95] ,A53 IRQ[95] status" "0,1" bitfld.long 0x08 30. " [94] ,A53 IRQ[94] status" "0,1" bitfld.long 0x08 29. " [93] ,A53 IRQ[93] status" "0,1" textline " " bitfld.long 0x08 28. " [92] ,A53 IRQ[92] status" "0,1" bitfld.long 0x08 27. " [91] ,A53 IRQ[91] status" "0,1" bitfld.long 0x08 26. " [90] ,A53 IRQ[90] status" "0,1" textline " " bitfld.long 0x08 25. " [89] ,A53 IRQ[89] status" "0,1" bitfld.long 0x08 24. " [88] ,A53 IRQ[88] status" "0,1" bitfld.long 0x08 23. " [87] ,A53 IRQ[87] status" "0,1" textline " " bitfld.long 0x08 22. " [86] ,A53 IRQ[86] status" "0,1" bitfld.long 0x08 21. " [85] ,A53 IRQ[85] status" "0,1" bitfld.long 0x08 20. " [84] ,A53 IRQ[84] status" "0,1" textline " " bitfld.long 0x08 19. " [83] ,A53 IRQ[83] status" "0,1" bitfld.long 0x08 18. " [82] ,A53 IRQ[82] status" "0,1" bitfld.long 0x08 17. " [81] ,A53 IRQ[81] status" "0,1" textline " " bitfld.long 0x08 16. " [80] ,A53 IRQ[80] status" "0,1" bitfld.long 0x08 15. " [79] ,A53 IRQ[79] status" "0,1" bitfld.long 0x08 14. " [78] ,A53 IRQ[78] status" "0,1" textline " " bitfld.long 0x08 13. " [77] ,A53 IRQ[77] status" "0,1" bitfld.long 0x08 12. " [76] ,A53 IRQ[76] status" "0,1" bitfld.long 0x08 11. " [75] ,A53 IRQ[75] status" "0,1" textline " " bitfld.long 0x08 10. " [74] ,A53 IRQ[74] status" "0,1" bitfld.long 0x08 9. " [73] ,A53 IRQ[73] status" "0,1" bitfld.long 0x08 8. " [72] ,A53 IRQ[72] status" "0,1" textline " " bitfld.long 0x08 7. " [71] ,A53 IRQ[71] status" "0,1" bitfld.long 0x08 6. " [70] ,A53 IRQ[70] status" "0,1" bitfld.long 0x08 5. " [69] ,A53 IRQ[69] status" "0,1" textline " " bitfld.long 0x08 4. " [68] ,A53 IRQ[68] status" "0,1" bitfld.long 0x08 3. " [67] ,A53 IRQ[67] status" "0,1" bitfld.long 0x08 2. " [66] ,A53 IRQ[66] status" "0,1" textline " " bitfld.long 0x08 1. " [65] ,A53 IRQ[65] status" "0,1" bitfld.long 0x08 0. " [64] ,A53 IRQ[64] status" "0,1" line.long 0x0C "ISR4_A53,IRQ masking register 4 of A53" bitfld.long 0x0C 31. " ISR4_A53[127] ,A53 IRQ[127] status" "0,1" bitfld.long 0x0C 30. " [126] ,A53 IRQ[126] status" "0,1" bitfld.long 0x0C 29. " [125] ,A53 IRQ[125] status" "0,1" textline " " bitfld.long 0x0C 28. " [124] ,A53 IRQ[124] status" "0,1" bitfld.long 0x0C 27. " [123] ,A53 IRQ[123] status" "0,1" bitfld.long 0x0C 26. " [122] ,A53 IRQ[122] status" "0,1" textline " " bitfld.long 0x0C 25. " [121] ,A53 IRQ[121] status" "0,1" bitfld.long 0x0C 24. " [120] ,A53 IRQ[120] status" "0,1" bitfld.long 0x0C 23. " [119] ,A53 IRQ[119] status" "0,1" textline " " bitfld.long 0x0C 22. " [118] ,A53 IRQ[118] status" "0,1" bitfld.long 0x0C 21. " [117] ,A53 IRQ[117] status" "0,1" bitfld.long 0x0C 20. " [116] ,A53 IRQ[116] status" "0,1" textline " " bitfld.long 0x0C 19. " [115] ,A53 IRQ[115] status" "0,1" bitfld.long 0x0C 18. " [114] ,A53 IRQ[114] status" "0,1" bitfld.long 0x0C 17. " [113] ,A53 IRQ[113] status" "0,1" textline " " bitfld.long 0x0C 16. " [112] ,A53 IRQ[112] status" "0,1" bitfld.long 0x0C 15. " [111] ,A53 IRQ[111] status" "0,1" bitfld.long 0x0C 14. " [110] ,A53 IRQ[110] status" "0,1" textline " " bitfld.long 0x0C 13. " [109] ,A53 IRQ[109] status" "0,1" bitfld.long 0x0C 12. " [108] ,A53 IRQ[108] status" "0,1" bitfld.long 0x0C 11. " [107] ,A53 IRQ[107] status" "0,1" textline " " bitfld.long 0x0C 10. " [106] ,A53 IRQ[106] status" "0,1" bitfld.long 0x0C 9. " [105] ,A53 IRQ[105] status" "0,1" bitfld.long 0x0C 8. " [104] ,A53 IRQ[104] status" "0,1" textline " " bitfld.long 0x0C 7. " [103] ,A53 IRQ[103] status" "0,1" bitfld.long 0x0C 6. " [102] ,A53 IRQ[102] status" "0,1" bitfld.long 0x0C 5. " [101] ,A53 IRQ[101] status" "0,1" textline " " bitfld.long 0x0C 4. " [100] ,A53 IRQ[100] status" "0,1" bitfld.long 0x0C 3. " [99] ,A53 IRQ[99] status" "0,1" bitfld.long 0x0C 2. " [98] ,A53 IRQ[98] status" "0,1" textline " " bitfld.long 0x0C 1. " [97] ,A53 IRQ[97] status" "0,1" bitfld.long 0x0C 0. " [96] ,A53 IRQ[96] status" "0,1" line.long 0x10 "ISR1_M4,IRQ masking register 1 of M4" bitfld.long 0x10 31. " ISR1_M4[31] ,M4 IRQ[31] status" "0,1" bitfld.long 0x10 30. " [30] ,M4 IRQ[30] status" "0,1" bitfld.long 0x10 29. " [29] ,M4 IRQ[29] status" "0,1" textline " " bitfld.long 0x10 28. " [28] ,M4 IRQ[28] status" "0,1" bitfld.long 0x10 27. " [27] ,M4 IRQ[27] status" "0,1" bitfld.long 0x10 26. " [26] ,M4 IRQ[26] status" "0,1" textline " " bitfld.long 0x10 25. " [25] ,M4 IRQ[25] status" "0,1" bitfld.long 0x10 24. " [24] ,M4 IRQ[24] status" "0,1" bitfld.long 0x10 23. " [23] ,M4 IRQ[23] status" "0,1" textline " " bitfld.long 0x10 22. " [22] ,M4 IRQ[22] status" "0,1" bitfld.long 0x10 21. " [21] ,M4 IRQ[21] status" "0,1" bitfld.long 0x10 20. " [20] ,M4 IRQ[20] status" "0,1" textline " " bitfld.long 0x10 19. " [19] ,M4 IRQ[19] status" "0,1" bitfld.long 0x10 18. " [18] ,M4 IRQ[18] status" "0,1" bitfld.long 0x10 17. " [17] ,M4 IRQ[17] status" "0,1" textline " " bitfld.long 0x10 16. " [16] ,M4 IRQ[16] status" "0,1" bitfld.long 0x10 15. " [15] ,M4 IRQ[15] status" "0,1" bitfld.long 0x10 14. " [14] ,M4 IRQ[14] status" "0,1" textline " " bitfld.long 0x10 13. " [13] ,M4 IRQ[13] status" "0,1" bitfld.long 0x10 12. " [12] ,M4 IRQ[12] status" "0,1" bitfld.long 0x10 11. " [11] ,M4 IRQ[11] status" "0,1" textline " " bitfld.long 0x10 10. " [10] ,M4 IRQ[10] status" "0,1" bitfld.long 0x10 9. " [9] ,M4 IRQ[9] status" "0,1" bitfld.long 0x10 8. " [8] ,M4 IRQ[8] status" "0,1" textline " " bitfld.long 0x10 7. " [7] ,M4 IRQ[7] status" "0,1" bitfld.long 0x10 6. " [6] ,M4 IRQ[6] status" "0,1" bitfld.long 0x10 5. " [5] ,M4 IRQ[5] status" "0,1" textline " " bitfld.long 0x10 4. " [4] ,M4 IRQ[4] status" "0,1" bitfld.long 0x10 3. " [3] ,M4 IRQ[3] status" "0,1" bitfld.long 0x10 2. " [2] ,M4 IRQ[2] status" "0,1" textline " " bitfld.long 0x10 1. " [1] ,M4 IRQ[1] status" "0,1" bitfld.long 0x10 0. " [0] ,M4 IRQ[0] status" "0,1" line.long 0x14 "ISR2_M4,IRQ masking register 2 of M4" bitfld.long 0x14 31. " ISR2_M4[63] ,M4 IRQ[63] status" "0,1" bitfld.long 0x14 30. " [62] ,M4 IRQ[62] status" "0,1" bitfld.long 0x14 29. " [61] ,M4 IRQ[61] status" "0,1" textline " " bitfld.long 0x14 28. " [60] ,M4 IRQ[60] status" "0,1" bitfld.long 0x14 27. " [59] ,M4 IRQ[59] status" "0,1" bitfld.long 0x14 26. " [58] ,M4 IRQ[58] status" "0,1" textline " " bitfld.long 0x14 25. " [57] ,M4 IRQ[57] status" "0,1" bitfld.long 0x14 24. " [56] ,M4 IRQ[56] status" "0,1" bitfld.long 0x14 23. " [55] ,M4 IRQ[55] status" "0,1" textline " " bitfld.long 0x14 22. " [54] ,M4 IRQ[54] status" "0,1" bitfld.long 0x14 21. " [53] ,M4 IRQ[53] status" "0,1" bitfld.long 0x14 20. " [52] ,M4 IRQ[52] status" "0,1" textline " " bitfld.long 0x14 19. " [51] ,M4 IRQ[51] status" "0,1" bitfld.long 0x14 18. " [50] ,M4 IRQ[50] status" "0,1" bitfld.long 0x14 17. " [49] ,M4 IRQ[49] status" "0,1" textline " " bitfld.long 0x14 16. " [48] ,M4 IRQ[48] status" "0,1" bitfld.long 0x14 15. " [47] ,M4 IRQ[47] status" "0,1" bitfld.long 0x14 14. " [46] ,M4 IRQ[46] status" "0,1" textline " " bitfld.long 0x14 13. " [45] ,M4 IRQ[45] status" "0,1" bitfld.long 0x14 12. " [44] ,M4 IRQ[44] status" "0,1" bitfld.long 0x14 11. " [43] ,M4 IRQ[43] status" "0,1" textline " " bitfld.long 0x14 10. " [42] ,M4 IRQ[42] status" "0,1" bitfld.long 0x14 9. " [41] ,M4 IRQ[41] status" "0,1" bitfld.long 0x14 8. " [40] ,M4 IRQ[40] status" "0,1" textline " " bitfld.long 0x14 7. " [39] ,M4 IRQ[39] status" "0,1" bitfld.long 0x14 6. " [38] ,M4 IRQ[38] status" "0,1" bitfld.long 0x14 5. " [37] ,M4 IRQ[37] status" "0,1" textline " " bitfld.long 0x14 4. " [36] ,M4 IRQ[36] status" "0,1" bitfld.long 0x14 3. " [35] ,M4 IRQ[35] status" "0,1" bitfld.long 0x14 2. " [34] ,M4 IRQ[34] status" "0,1" textline " " bitfld.long 0x14 1. " [33] ,M4 IRQ[33] status" "0,1" bitfld.long 0x14 0. " [32] ,M4 IRQ[32] status" "0,1" line.long 0x18 "ISR3_M4,IRQ masking register 3 of M4" bitfld.long 0x18 31. " ISR3_M4[95] ,M4 IRQ[95] status" "0,1" bitfld.long 0x18 30. " [94] ,M4 IRQ[94] status" "0,1" bitfld.long 0x18 29. " [93] ,M4 IRQ[93] status" "0,1" textline " " bitfld.long 0x18 28. " [92] ,M4 IRQ[92] status" "0,1" bitfld.long 0x18 27. " [91] ,M4 IRQ[91] status" "0,1" bitfld.long 0x18 26. " [90] ,M4 IRQ[90] status" "0,1" textline " " bitfld.long 0x18 25. " [89] ,M4 IRQ[89] status" "0,1" bitfld.long 0x18 24. " [88] ,M4 IRQ[88] status" "0,1" bitfld.long 0x18 23. " [87] ,M4 IRQ[87] status" "0,1" textline " " bitfld.long 0x18 22. " [86] ,M4 IRQ[86] status" "0,1" bitfld.long 0x18 21. " [85] ,M4 IRQ[85] status" "0,1" bitfld.long 0x18 20. " [84] ,M4 IRQ[84] status" "0,1" textline " " bitfld.long 0x18 19. " [83] ,M4 IRQ[83] status" "0,1" bitfld.long 0x18 18. " [82] ,M4 IRQ[82] status" "0,1" bitfld.long 0x18 17. " [81] ,M4 IRQ[81] status" "0,1" textline " " bitfld.long 0x18 16. " [80] ,M4 IRQ[80] status" "0,1" bitfld.long 0x18 15. " [79] ,M4 IRQ[79] status" "0,1" bitfld.long 0x18 14. " [78] ,M4 IRQ[78] status" "0,1" textline " " bitfld.long 0x18 13. " [77] ,M4 IRQ[77] status" "0,1" bitfld.long 0x18 12. " [76] ,M4 IRQ[76] status" "0,1" bitfld.long 0x18 11. " [75] ,M4 IRQ[75] status" "0,1" textline " " bitfld.long 0x18 10. " [74] ,M4 IRQ[74] status" "0,1" bitfld.long 0x18 9. " [73] ,M4 IRQ[73] status" "0,1" bitfld.long 0x18 8. " [72] ,M4 IRQ[72] status" "0,1" textline " " bitfld.long 0x18 7. " [71] ,M4 IRQ[71] status" "0,1" bitfld.long 0x18 6. " [70] ,M4 IRQ[70] status" "0,1" bitfld.long 0x18 5. " [69] ,M4 IRQ[69] status" "0,1" textline " " bitfld.long 0x18 4. " [68] ,M4 IRQ[68] status" "0,1" bitfld.long 0x18 3. " [67] ,M4 IRQ[67] status" "0,1" bitfld.long 0x18 2. " [66] ,M4 IRQ[66] status" "0,1" textline " " bitfld.long 0x18 1. " [65] ,M4 IRQ[65] status" "0,1" bitfld.long 0x18 0. " [64] ,M4 IRQ[64] status" "0,1" line.long 0x1C "ISR4_M4,IRQ masking register 4 of M4" bitfld.long 0x1C 31. " ISR4_M4[127] ,M4 IRQ[127] status" "0,1" bitfld.long 0x1C 30. " [126] ,M4 IRQ[126] status" "0,1" bitfld.long 0x1C 29. " [125] ,M4 IRQ[125] status" "0,1" textline " " bitfld.long 0x1C 28. " [124] ,M4 IRQ[124] status" "0,1" bitfld.long 0x1C 27. " [123] ,M4 IRQ[123] status" "0,1" bitfld.long 0x1C 26. " [122] ,M4 IRQ[122] status" "0,1" textline " " bitfld.long 0x1C 25. " [121] ,M4 IRQ[121] status" "0,1" bitfld.long 0x1C 24. " [120] ,M4 IRQ[120] status" "0,1" bitfld.long 0x1C 23. " [119] ,M4 IRQ[119] status" "0,1" textline " " bitfld.long 0x1C 22. " [118] ,M4 IRQ[118] status" "0,1" bitfld.long 0x1C 21. " [117] ,M4 IRQ[117] status" "0,1" bitfld.long 0x1C 20. " [116] ,M4 IRQ[116] status" "0,1" textline " " bitfld.long 0x1C 19. " [115] ,M4 IRQ[115] status" "0,1" bitfld.long 0x1C 18. " [114] ,M4 IRQ[114] status" "0,1" bitfld.long 0x1C 17. " [113] ,M4 IRQ[113] status" "0,1" textline " " bitfld.long 0x1C 16. " [112] ,M4 IRQ[112] status" "0,1" bitfld.long 0x1C 15. " [111] ,M4 IRQ[111] status" "0,1" bitfld.long 0x1C 14. " [110] ,M4 IRQ[110] status" "0,1" textline " " bitfld.long 0x1C 13. " [109] ,M4 IRQ[109] status" "0,1" bitfld.long 0x1C 12. " [108] ,M4 IRQ[108] status" "0,1" bitfld.long 0x1C 11. " [107] ,M4 IRQ[107] status" "0,1" textline " " bitfld.long 0x1C 10. " [106] ,M4 IRQ[106] status" "0,1" bitfld.long 0x1C 9. " [105] ,M4 IRQ[105] status" "0,1" bitfld.long 0x1C 8. " [104] ,M4 IRQ[104] status" "0,1" textline " " bitfld.long 0x1C 7. " [103] ,M4 IRQ[103] status" "0,1" bitfld.long 0x1C 6. " [102] ,M4 IRQ[102] status" "0,1" bitfld.long 0x1C 5. " [101] ,M4 IRQ[101] status" "0,1" textline " " bitfld.long 0x1C 4. " [100] ,M4 IRQ[100] status" "0,1" bitfld.long 0x1C 3. " [99] ,M4 IRQ[99] status" "0,1" bitfld.long 0x1C 2. " [98] ,M4 IRQ[98] status" "0,1" textline " " bitfld.long 0x1C 1. " [97] ,M4 IRQ[97] status" "0,1" bitfld.long 0x1C 0. " [96] ,M4 IRQ[96] status" "0,1" group.long 0xB0++0x03 line.long 0x00 "SLT0_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xB4++0x03 line.long 0x00 "SLT1_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xB8++0x03 line.long 0x00 "SLT2_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xBC++0x03 line.long 0x00 "SLT3_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xC0++0x03 line.long 0x00 "SLT4_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xC4++0x03 line.long 0x00 "SLT5_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xC8++0x03 line.long 0x00 "SLT6_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xCC++0x03 line.long 0x00 "SLT7_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xD0++0x03 line.long 0x00 "SLT8_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xD4++0x03 line.long 0x00 "SLT9_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xD8++0x03 line.long 0x00 "SLT10_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xDC++0x03 line.long 0x00 "SLT11_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xE0++0x03 line.long 0x00 "SLT12_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xE4++0x03 line.long 0x00 "SLT13_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xE8++0x03 line.long 0x00 "SLT14_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Disabled,Enabled" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Disabled,Enabled" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Disabled,Enabled" group.long 0xEC++0x1F line.long 0x00 "PGC_CPU_0_1_MAPPAING,PGC CPU mapping" bitfld.long 0x00 31. " PCIE2_M4_DOMAIN ,PCIE2 M4 domain" "Not mapped,Mapped" bitfld.long 0x00 30. " MIPI_CSI2_M4_DOMAIN ,MIPI CSI2 M4 domain" "Not mapped,Mapped" bitfld.long 0x00 29. " MIPI_CSI1_M4_DOMAIN ,MIPI CSI1 M4 domain" "Not mapped,Mapped" textline " " bitfld.long 0x00 28. " DISP_M4_DOMAIN ,DISP M4 domain" "Not mapped,Mapped" bitfld.long 0x00 27. " HDMI_M4_DOMAIN ,HDMI M4 domain" "Not mapped,Mapped" bitfld.long 0x00 26. " VPU_M4_DOMAIN ,VPU M4 domain" "Not mapped,Mapped" textline " " bitfld.long 0x00 25. " GPU_M4_DOMAIN ,GPU M4 domain" "Not mapped,Mapped" bitfld.long 0x00 24. " DDR2_M4_DOMAIN ,DDR2 M4 domain" "Not mapped,Mapped" bitfld.long 0x00 23. " DDR1_M4_DOMAIN ,DDR1 M4 domain" "Not mapped,Mapped" textline " " bitfld.long 0x00 21. " OTG2_M4_DOMAIN ,OTG2 M4 domain" "Not mapped,Mapped" bitfld.long 0x00 20. " OTG1_M4_DOMAIN ,OTG1 M4 domain" "Not mapped,Mapped" bitfld.long 0x00 19. " PCIE_M4_DOMAIN ,PCIE2 M4 domain" "Not mapped,Mapped" textline " " bitfld.long 0x00 18. " MIPI_M4_DOMAIN ,MIPI M4 domain" "Not mapped,Mapped" bitfld.long 0x00 16. " MF_M4_DOMAIN ,MF M4 domain" "Not mapped,Mapped" bitfld.long 0x00 15. " PCIE2_A53_DOMAIN ,PCIE2 A53 domain" "Not mapped,Mapped" textline " " bitfld.long 0x00 14. " MIPI_CSI2_A53_DOMAIN ,MIPI CSI2 A53 domain" "Not mapped,Mapped" bitfld.long 0x00 13. " MIPI_CSI1_A53_DOMAIN ,MIPI CSI1 A53 domain" "Not mapped,Mapped" bitfld.long 0x00 12. " DISP_A53_DOMAIN ,DISP A53 domain" "Not mapped,Mapped" textline " " bitfld.long 0x00 11. " HDMI_A53_DOMAIN ,HDMI A53 domain" "Not mapped,Mapped" bitfld.long 0x00 10. " VPU_A53_DOMAIN ,VPU A53 domain" "Not mapped,Mapped" bitfld.long 0x00 9. " GPU_A53_DOMAIN ,GPU A53 domain" "Not mapped,Mapped" textline " " bitfld.long 0x00 8. " DDR2_A53_DOMAIN ,DDR2 A53 domain" "Not mapped,Mapped" bitfld.long 0x00 7. " DDR1_A53_DOMAIN ,DDR1 A53 domain" "Not mapped,Mapped" bitfld.long 0x00 5. " OTG2_A53_DOMAIN ,OTG2 A53 domain" "Not mapped,Mapped" textline " " bitfld.long 0x00 4. " OTG1_A53_DOMAIN ,OTG1 A53 domain" "Not mapped,Mapped" bitfld.long 0x00 3. " PCIE_A53_DOMAIN ,PCIE2 A53 domain" "Not mapped,Mapped" bitfld.long 0x00 2. " MIPI_A53_DOMAIN ,MIPI A53 domain" "Not mapped,Mapped" textline " " bitfld.long 0x00 0. " MF_A53_DOMAIN ,MF A53 domain" "Not mapped,Mapped" line.long 0x04 "CPU_PGC_SW_PUP_REQ,CPU PGC software power up trigger" bitfld.long 0x04 4. " CORE3_A53_SW_PUP_REQ ,Software power up trigger for core3 A53 PGC" "No effect,Trigger" bitfld.long 0x04 3. " CORE2_A53_SW_PUP_REQ ,Software power up trigger for core2 A53 PGC" "No effect,Trigger" bitfld.long 0x04 2. " SCU_A53_SW_PUP_REQ ,Software power up trigger for SCU A53" "No effect,Trigger" textline " " bitfld.long 0x04 1. " CORE1_A53_SW_PUP_REQ ,Software power up trigger for core1 A53 PGC" "No effect,Trigger" bitfld.long 0x04 0. " CORE0_A53_SW_PUP_REQ ,Software power up trigger for core0 A53 PGC" "No effect,Trigger" line.long 0x08 "MIX_PGC_SW_PUP_REQ,MIX PGC software power up trigger" bitfld.long 0x08 0. " MIX_SW_PUP_REQ ,Software power up trigger for MIX PGC" "No effect,Trigger" line.long 0x0C "PU_PGC_SW_PUP_REQ,PU PGC Software Up Trigger" bitfld.long 0x0C 13. " PCIE2_SW_PUP_REQ ,Software power up trigger for PCIE2" "No effect,Trigger" bitfld.long 0x0C 12. " MIPI_CSI2_SW_PUP_REQ ,Software power up trigger for MIPI CSI2" "No effect,Trigger" bitfld.long 0x0C 11. " MIPI_CSI1_SW_PUP_REQ ,Software power up trigger for MIPI CSI1" "No effect,Trigger" textline " " bitfld.long 0x0C 10. " DISP_OTG1_SW_PUP_REQ ,Software power up trigger for DISP" "No effect,Trigger" bitfld.long 0x0C 9. " HDMI_SW_PUP_REQ ,Software power up trigger for HDMI" "No effect,Trigger" bitfld.long 0x0C 8. " VPU_SW_PUP_REQ ,Software power up trigger for VPU" "No effect,Trigger" textline " " bitfld.long 0x0C 7. " GPU_OTG1_SW_PUP_REQ ,Software power up trigger for GPU" "No effect,Trigger" bitfld.long 0x0C 6. " DDR2_SW_PUP_REQ ,Software power up trigger for DDR2" "No effect,Trigger" bitfld.long 0x0C 5. " DDR1_SW_PUP_REQ ,Software power up trigger for DDR1" "No effect,Trigger" textline " " bitfld.long 0x0C 3. " USB_OTG2_SW_PUP_REQ ,Software power up trigger for USB_OTG2" "No effect,Trigger" bitfld.long 0x0C 2. " USB_OTG1_SW_PUP_REQ ,Software power up trigger for USB_OTG1" "No effect,Trigger" bitfld.long 0x0C 1. " PCIE_SW_PUP_REQ ,Software power up trigger for PCIE" "No effect,Trigger" textline " " bitfld.long 0x0C 0. " MIPI_SW_PUP_REQ ,Software power up trigger for MIPI" "No effect,Trigger" line.long 0x10 "CPU_PGC_SW_PDN_REQ,CPU PGC Software Down Trigger" bitfld.long 0x10 4. " CORE3_A53_SW_PDN_REQ ,Software power down trigger for core1 A53 PGC" "No effect,Trigger" bitfld.long 0x10 3. " CORE2_A53_SW_PDN_REQ ,Software power down trigger for core0 A53 PGC" "No effect,Trigger" bitfld.long 0x10 2. " SCU_A53_SW_PDN_REQ ,Software power down trigger for SCU A53" "No effect,Trigger" textline " " bitfld.long 0x10 1. " CORE1_A53_SW_PDN_REQ ,Software power down trigger for core1 A53 PGC" "No effect,Trigger" bitfld.long 0x10 0. " CORE0_A53_SW_PDN_REQ ,Software power down trigger for core0 A53 PGC" "No effect,Trigger" line.long 0x14 "MIX_PGC_SW_PDN_REQ,MIX PGC software power down trigger" bitfld.long 0x14 0. " MIX_SW_PDN_REQ ,Software power down trigger for MIX PGC" "No effect,Trigger" line.long 0x18 "PU_PGC_SW_PDN_REQ,PU PGC software down trigger" bitfld.long 0x18 13. " PCIE2_SW_PUP_REQ ,Software power up trigger for PCIE2" "No effect,Trigger" bitfld.long 0x18 12. " MIPI_CSI2_SW_PUP_REQ ,Software power up trigger for MIPI CSI2" "No effect,Trigger" bitfld.long 0x18 11. " MIPI_CSI1_SW_PUP_REQ ,Software power up trigger for MIPI CSI1" "No effect,Trigger" textline " " bitfld.long 0x18 10. " DISP_OTG1_SW_PUP_REQ ,Software power up trigger for DISP" "No effect,Trigger" bitfld.long 0x18 9. " HDMI_SW_PUP_REQ ,Software power up trigger for HDMI" "No effect,Trigger" bitfld.long 0x18 8. " VPU_SW_PUP_REQ ,Software power up trigger for VPU" "No effect,Trigger" textline " " bitfld.long 0x18 7. " GPU_OTG1_SW_PUP_REQ ,Software power up trigger for GPU" "No effect,Trigger" bitfld.long 0x18 6. " DDR2_SW_PUP_REQ ,Software power up trigger for DDR2" "No effect,Trigger" bitfld.long 0x18 5. " DDR1_SW_PUP_REQ ,Software power up trigger for DDR1" "No effect,Trigger" textline " " bitfld.long 0x18 3. " USB_OTG2_SW_PUP_REQ ,Software power up trigger for USB_OTG2" "No effect,Trigger" bitfld.long 0x18 2. " USB_OTG1_SW_PUP_REQ ,Software power up trigger for USB_OTG1" "No effect,Trigger" bitfld.long 0x18 1. " PCIE_SW_PUP_REQ ,Software power up trigger for PCIE" "No effect,Trigger" textline " " bitfld.long 0x18 0. " MIPI_SW_PUP_REQ ,Software power up trigger for MIPI" "No effect,Trigger" line.long 0x1C "LPCR_A53_BSC2,Basic Low power control register o A53 platform" bitfld.long 0x1C 2.--3. " LPM3 ,CORE3 Setting the low power mode" "Remain in RUN,Transfer to WAIT,Transfer to STOP,?..." bitfld.long 0x1C 0.--1. " LPM2 ,CORE2 Setting the low power mode" "Remain in RUN,Transfer to WAIT,Transfer to STOP,?..." group.long 0x130++0x03 line.long 0x00 "CPU_PGC_PUP_STATUS1,CPU PGC Software Up Trigger Status1" bitfld.long 0x00 4. " CORE3_A53_PUP_STATUS ,Results for power up software trigger for CORE3 A53" "Succeeded,Failed" bitfld.long 0x00 3. " CORE2_A53_PUP_STATUS ,Results for power up software trigger for CORE2 A53" "Succeeded,Failed" rbitfld.long 0x00 2. " SCU_A53_PUP_STATUS ,Results for power up software trigger for SCU A53" "Succeeded,Failed" textline " " rbitfld.long 0x00 1. " CORE1_A53_PUP_STATUS ,Results for power up software trigger for CORE1 A53" "Succeeded,Failed" rbitfld.long 0x00 0. " CORE0_A53_PUP_STATUS ,Results for power up software trigger for CORE0 A53" "Succeeded,Failed" rgroup.long 0x134++0x03 line.long 0x00 "A53_MIX_PGC_PUP_STATUS0,A53 MIX software up trigger status register" bitfld.long 0x00 0. " A53_MIX_PGC_PUP_STATUS ,A53 MIX PGC power up status" "Succeeded,Failed" rgroup.long 0x138++0x03 line.long 0x00 "A53_MIX_PGC_PUP_STATUS1,A53 MIX software up trigger status register" bitfld.long 0x00 0. " A53_MIX_PGC_PUP_STATUS ,A53 MIX PGC power up status" "Succeeded,Failed" rgroup.long 0x13C++0x03 line.long 0x00 "A53_MIX_PGC_PUP_STATUS2,A53 MIX software up trigger status register" bitfld.long 0x00 0. " A53_MIX_PGC_PUP_STATUS ,A53 MIX PGC power up status" "Succeeded,Failed" rgroup.long 0x140++0x03 line.long 0x00 "M4_MIX_PGC_PUP_STATUS0,M4 MIX software up trigger status register" bitfld.long 0x00 0. " M4_MIX_PGC_PUP_STATUS ,M4 MIX PGC power up status" "Succeeded,Failed" rgroup.long 0x144++0x03 line.long 0x00 "M4_MIX_PGC_PUP_STATUS1,M4 MIX software up trigger status register" bitfld.long 0x00 0. " M4_MIX_PGC_PUP_STATUS ,M4 MIX PGC power up status" "Succeeded,Failed" rgroup.long 0x148++0x03 line.long 0x00 "M4_MIX_PGC_PUP_STATUS2,M4 MIX software up trigger status register" bitfld.long 0x00 0. " M4_MIX_PGC_PUP_STATUS ,M4 MIX PGC power up status" "Succeeded,Failed" rgroup.long 0x14C++0x03 line.long 0x00 "A53_MIX_PGC_PUP_STATUS0,M4 MIX software up trigger status register" bitfld.long 0x00 13. " A53_PCIE2_PGC_PUP_STATUS ,A53 PCIE2 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 12. " A53_MIPI_CSI2_PGC_PUP_STATUS ,A53 MIPI CSI2 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 11. " A53_MIPI_CSI1_PGC_PUP_STATUS ,A53 MIPI CSI1 PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 10. " A53_DISP_PGC_PUP_STATUS ,A53 DISP PGC power up status" "Succeeded,Failed" bitfld.long 0x00 9. " A53_HDMI_PGC_PUP_STATUS ,A53 HDMI PGC power up status" "Succeeded,Failed" bitfld.long 0x00 8. " A53_VPU_PGC_PUP_STATUS ,A53 VPU PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 7. " A53_GPU_PGC_PUP_STATUS ,A53 GPU PGC power up status" "Succeeded,Failed" bitfld.long 0x00 5. " A53_DDR1_PGC_PUP_STATUS ,A53 DDR1 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 3. " A53_USB_OTG2_PGC_PUP_STATUS , A53 USB_OTG2 PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 2. " A53_USB_OTG1_PGC_PUP_STATUS ,A53 USB_OTG1 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 1. " A53_PCIE_PGC_PUP_STATUS ,A53 PCIE PGC power up status" "Succeeded,Failed" bitfld.long 0x00 0. " A53_MIPI_PGC_PUP_STATUS ,A53 MIPI PGC power up status" "Succeeded,Failed" rgroup.long 0x150++0x03 line.long 0x00 "A53_MIX_PGC_PUP_STATUS1,M4 MIX software up trigger status register" bitfld.long 0x00 13. " A53_PCIE2_PGC_PUP_STATUS ,A53 PCIE2 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 12. " A53_MIPI_CSI2_PGC_PUP_STATUS ,A53 MIPI CSI2 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 11. " A53_MIPI_CSI1_PGC_PUP_STATUS ,A53 MIPI CSI1 PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 10. " A53_DISP_PGC_PUP_STATUS ,A53 DISP PGC power up status" "Succeeded,Failed" bitfld.long 0x00 9. " A53_HDMI_PGC_PUP_STATUS ,A53 HDMI PGC power up status" "Succeeded,Failed" bitfld.long 0x00 8. " A53_VPU_PGC_PUP_STATUS ,A53 VPU PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 7. " A53_GPU_PGC_PUP_STATUS ,A53 GPU PGC power up status" "Succeeded,Failed" bitfld.long 0x00 5. " A53_DDR1_PGC_PUP_STATUS ,A53 DDR1 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 3. " A53_USB_OTG2_PGC_PUP_STATUS , A53 USB_OTG2 PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 2. " A53_USB_OTG1_PGC_PUP_STATUS ,A53 USB_OTG1 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 1. " A53_PCIE_PGC_PUP_STATUS ,A53 PCIE PGC power up status" "Succeeded,Failed" bitfld.long 0x00 0. " A53_MIPI_PGC_PUP_STATUS ,A53 MIPI PGC power up status" "Succeeded,Failed" rgroup.long 0x154++0x03 line.long 0x00 "A53_MIX_PGC_PUP_STATUS2,M4 MIX software up trigger status register" bitfld.long 0x00 13. " A53_PCIE2_PGC_PUP_STATUS ,A53 PCIE2 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 12. " A53_MIPI_CSI2_PGC_PUP_STATUS ,A53 MIPI CSI2 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 11. " A53_MIPI_CSI1_PGC_PUP_STATUS ,A53 MIPI CSI1 PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 10. " A53_DISP_PGC_PUP_STATUS ,A53 DISP PGC power up status" "Succeeded,Failed" bitfld.long 0x00 9. " A53_HDMI_PGC_PUP_STATUS ,A53 HDMI PGC power up status" "Succeeded,Failed" bitfld.long 0x00 8. " A53_VPU_PGC_PUP_STATUS ,A53 VPU PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 7. " A53_GPU_PGC_PUP_STATUS ,A53 GPU PGC power up status" "Succeeded,Failed" bitfld.long 0x00 5. " A53_DDR1_PGC_PUP_STATUS ,A53 DDR1 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 3. " A53_USB_OTG2_PGC_PUP_STATUS , A53 USB_OTG2 PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 2. " A53_USB_OTG1_PGC_PUP_STATUS ,A53 USB_OTG1 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 1. " A53_PCIE_PGC_PUP_STATUS ,A53 PCIE PGC power up status" "Succeeded,Failed" bitfld.long 0x00 0. " A53_MIPI_PGC_PUP_STATUS ,A53 MIPI PGC power up status" "Succeeded,Failed" rgroup.long 0x158++0x03 line.long 0x00 "M4_MIX_PGC_PUP_STATUS0,M4 MIX software up trigger status register" bitfld.long 0x00 13. " M4_PCIE2_PGC_PUP_STATUS ,M4 PCIE2 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 12. " M4_MIPI_CSI2_PGC_PUP_STATUS ,M4 MIPI CSI2 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 11. " M4_MIPI_CSI1_PGC_PUP_STATUS ,M4 MIPI CSI1 PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 10. " M4_DISP_PGC_PUP_STATUS ,M4 DISP PGC power up status" "Succeeded,Failed" bitfld.long 0x00 9. " M4_HDMI_PGC_PUP_STATUS ,M4 HDMI PGC power up status" "Succeeded,Failed" bitfld.long 0x00 8. " M4_VPU_PGC_PUP_STATUS ,M4 VPU PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 7. " M4_GPU_PGC_PUP_STATUS ,M4 GPU PGC power up status" "Succeeded,Failed" bitfld.long 0x00 5. " M4_DDR1_PGC_PUP_STATUS ,M4 DDR1 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 3. " M4_USB_OTG2_PGC_PUP_STATUS , M4 USB_OTG2 PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 2. " M4_USB_OTG1_PGC_PUP_STATUS ,M4 USB_OTG1 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 1. " M4_PCIE_PGC_PUP_STATUS ,M4 PCIE PGC power up status" "Succeeded,Failed" bitfld.long 0x00 0. " M4_MIPI_PGC_PUP_STATUS ,M4 MIPI PGC power up status" "Succeeded,Failed" rgroup.long 0x15C++0x03 line.long 0x00 "M4_MIX_PGC_PUP_STATUS1,M4 MIX software up trigger status register" bitfld.long 0x00 13. " M4_PCIE2_PGC_PUP_STATUS ,M4 PCIE2 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 12. " M4_MIPI_CSI2_PGC_PUP_STATUS ,M4 MIPI CSI2 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 11. " M4_MIPI_CSI1_PGC_PUP_STATUS ,M4 MIPI CSI1 PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 10. " M4_DISP_PGC_PUP_STATUS ,M4 DISP PGC power up status" "Succeeded,Failed" bitfld.long 0x00 9. " M4_HDMI_PGC_PUP_STATUS ,M4 HDMI PGC power up status" "Succeeded,Failed" bitfld.long 0x00 8. " M4_VPU_PGC_PUP_STATUS ,M4 VPU PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 7. " M4_GPU_PGC_PUP_STATUS ,M4 GPU PGC power up status" "Succeeded,Failed" bitfld.long 0x00 5. " M4_DDR1_PGC_PUP_STATUS ,M4 DDR1 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 3. " M4_USB_OTG2_PGC_PUP_STATUS , M4 USB_OTG2 PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 2. " M4_USB_OTG1_PGC_PUP_STATUS ,M4 USB_OTG1 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 1. " M4_PCIE_PGC_PUP_STATUS ,M4 PCIE PGC power up status" "Succeeded,Failed" bitfld.long 0x00 0. " M4_MIPI_PGC_PUP_STATUS ,M4 MIPI PGC power up status" "Succeeded,Failed" rgroup.long 0x160++0x03 line.long 0x00 "M4_MIX_PGC_PUP_STATUS2,M4 MIX software up trigger status register" bitfld.long 0x00 13. " M4_PCIE2_PGC_PUP_STATUS ,M4 PCIE2 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 12. " M4_MIPI_CSI2_PGC_PUP_STATUS ,M4 MIPI CSI2 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 11. " M4_MIPI_CSI1_PGC_PUP_STATUS ,M4 MIPI CSI1 PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 10. " M4_DISP_PGC_PUP_STATUS ,M4 DISP PGC power up status" "Succeeded,Failed" bitfld.long 0x00 9. " M4_HDMI_PGC_PUP_STATUS ,M4 HDMI PGC power up status" "Succeeded,Failed" bitfld.long 0x00 8. " M4_VPU_PGC_PUP_STATUS ,M4 VPU PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 7. " M4_GPU_PGC_PUP_STATUS ,M4 GPU PGC power up status" "Succeeded,Failed" bitfld.long 0x00 5. " M4_DDR1_PGC_PUP_STATUS ,M4 DDR1 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 3. " M4_USB_OTG2_PGC_PUP_STATUS , M4 USB_OTG2 PGC power up status" "Succeeded,Failed" textline " " bitfld.long 0x00 2. " M4_USB_OTG1_PGC_PUP_STATUS ,M4 USB_OTG1 PGC power up status" "Succeeded,Failed" bitfld.long 0x00 1. " M4_PCIE_PGC_PUP_STATUS ,M4 PCIE PGC power up status" "Succeeded,Failed" bitfld.long 0x00 0. " M4_MIPI_PGC_PUP_STATUS ,M4 MIPI PGC power up status" "Succeeded,Failed" group.long 0x170++0x03 line.long 0x00 "CPU_PGC_PDN_STATUS1,CPU PGC Software Down Trigger Status1" bitfld.long 0x00 4. " CORE3_A53_PDN_STATUS ,Results for power down software trigger for CORE3 A53" "Succeeded,Failed" bitfld.long 0x00 3. " CORE2_A53_PDN_STATUS ,Results for power down software trigger for CORE2 A53" "Succeeded,Failed" rbitfld.long 0x00 2. " SCU_A53_PDN_STATUS ,Results for power down software trigger for SCU A53" "Succeeded,Failed" textline " " rbitfld.long 0x00 1. " CORE1_A53_PDN_STATUS ,Results for power down software trigger for CORE1 A53" "Succeeded,Failed" rbitfld.long 0x00 0. " CORE0_A53_PDN_STATUS ,Results for power down software trigger for CORE0 A53" "Succeeded,Failed" rgroup.long 0x174++0x03 line.long 0x00 "A53_MIX_PGC_PDN_STATUS0,A53 MIX software down trigger status register" bitfld.long 0x00 0. " A53_MIX_PGC_PDN_STATUS ,A53 MIX PGC power down status" "Succeeded,Failed" rgroup.long 0x178++0x03 line.long 0x00 "A53_MIX_PGC_PDN_STATUS1,A53 MIX software down trigger status register" bitfld.long 0x00 0. " A53_MIX_PGC_PDN_STATUS ,A53 MIX PGC power down status" "Succeeded,Failed" rgroup.long 0x17C++0x03 line.long 0x00 "A53_MIX_PGC_PDN_STATUS2,A53 MIX software down trigger status register" bitfld.long 0x00 0. " A53_MIX_PGC_PDN_STATUS ,A53 MIX PGC power down status" "Succeeded,Failed" rgroup.long 0x180++0x03 line.long 0x00 "M4_MIX_PGC_PDN_STATUS0,M4 MIX software down trigger status register" bitfld.long 0x00 0. " M4_MIX_PGC_PDN_STATUS ,M4 MIX PGC power down status" "Succeeded,Failed" rgroup.long 0x184++0x03 line.long 0x00 "M4_MIX_PGC_PDN_STATUS1,M4 MIX software down trigger status register" bitfld.long 0x00 0. " M4_MIX_PGC_PDN_STATUS ,M4 MIX PGC power down status" "Succeeded,Failed" rgroup.long 0x188++0x03 line.long 0x00 "M4_MIX_PGC_PDN_STATUS2,M4 MIX software down trigger status register" bitfld.long 0x00 0. " M4_MIX_PGC_PDN_STATUS ,M4 MIX PGC power down status" "Succeeded,Failed" rgroup.long 0x18C++0x03 line.long 0x00 "A53_MIX_PGC_PDN_STATUS0,M4 MIX software down trigger status register" bitfld.long 0x00 13. " A53_PCIE2_PGC_PDN_STATUS ,A53 PCIE2 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 12. " A53_MIPI_CSI2_PGC_PDN_STATUS ,A53 MIPI CSI2 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 11. " A53_MIPI_CSI1_PGC_PDN_STATUS ,A53 MIPI CSI1 PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 10. " A53_DISP_PGC_PDN_STATUS ,A53 DISP PGC power down status" "Succeeded,Failed" bitfld.long 0x00 9. " A53_HDMI_PGC_PDN_STATUS ,A53 HDMI PGC power down status" "Succeeded,Failed" bitfld.long 0x00 8. " A53_VPU_PGC_PDN_STATUS ,A53 VPU PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 7. " A53_GPU_PGC_PDN_STATUS ,A53 GPU PGC power down status" "Succeeded,Failed" bitfld.long 0x00 5. " A53_DDR1_PGC_PDN_STATUS ,A53 DDR1 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 3. " A53_USB_OTG2_PGC_PDN_STATUS , A53 USB_OTG2 PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 2. " A53_USB_OTG1_PGC_PDN_STATUS ,A53 USB_OTG1 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 1. " A53_PCIE_PGC_PDN_STATUS ,A53 PCIE PGC power down status" "Succeeded,Failed" bitfld.long 0x00 0. " A53_MIPI_PGC_PDN_STATUS ,A53 MIPI PGC power down status" "Succeeded,Failed" rgroup.long 0x190++0x03 line.long 0x00 "A53_MIX_PGC_PDN_STATUS1,M4 MIX software down trigger status register" bitfld.long 0x00 13. " A53_PCIE2_PGC_PDN_STATUS ,A53 PCIE2 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 12. " A53_MIPI_CSI2_PGC_PDN_STATUS ,A53 MIPI CSI2 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 11. " A53_MIPI_CSI1_PGC_PDN_STATUS ,A53 MIPI CSI1 PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 10. " A53_DISP_PGC_PDN_STATUS ,A53 DISP PGC power down status" "Succeeded,Failed" bitfld.long 0x00 9. " A53_HDMI_PGC_PDN_STATUS ,A53 HDMI PGC power down status" "Succeeded,Failed" bitfld.long 0x00 8. " A53_VPU_PGC_PDN_STATUS ,A53 VPU PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 7. " A53_GPU_PGC_PDN_STATUS ,A53 GPU PGC power down status" "Succeeded,Failed" bitfld.long 0x00 5. " A53_DDR1_PGC_PDN_STATUS ,A53 DDR1 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 3. " A53_USB_OTG2_PGC_PDN_STATUS , A53 USB_OTG2 PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 2. " A53_USB_OTG1_PGC_PDN_STATUS ,A53 USB_OTG1 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 1. " A53_PCIE_PGC_PDN_STATUS ,A53 PCIE PGC power down status" "Succeeded,Failed" bitfld.long 0x00 0. " A53_MIPI_PGC_PDN_STATUS ,A53 MIPI PGC power down status" "Succeeded,Failed" rgroup.long 0x194++0x03 line.long 0x00 "A53_MIX_PGC_PDN_STATUS2,M4 MIX software down trigger status register" bitfld.long 0x00 13. " A53_PCIE2_PGC_PDN_STATUS ,A53 PCIE2 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 12. " A53_MIPI_CSI2_PGC_PDN_STATUS ,A53 MIPI CSI2 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 11. " A53_MIPI_CSI1_PGC_PDN_STATUS ,A53 MIPI CSI1 PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 10. " A53_DISP_PGC_PDN_STATUS ,A53 DISP PGC power down status" "Succeeded,Failed" bitfld.long 0x00 9. " A53_HDMI_PGC_PDN_STATUS ,A53 HDMI PGC power down status" "Succeeded,Failed" bitfld.long 0x00 8. " A53_VPU_PGC_PDN_STATUS ,A53 VPU PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 7. " A53_GPU_PGC_PDN_STATUS ,A53 GPU PGC power down status" "Succeeded,Failed" bitfld.long 0x00 5. " A53_DDR1_PGC_PDN_STATUS ,A53 DDR1 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 3. " A53_USB_OTG2_PGC_PDN_STATUS , A53 USB_OTG2 PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 2. " A53_USB_OTG1_PGC_PDN_STATUS ,A53 USB_OTG1 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 1. " A53_PCIE_PGC_PDN_STATUS ,A53 PCIE PGC power down status" "Succeeded,Failed" bitfld.long 0x00 0. " A53_MIPI_PGC_PDN_STATUS ,A53 MIPI PGC power down status" "Succeeded,Failed" rgroup.long 0x198++0x03 line.long 0x00 "M4_MIX_PGC_PDN_STATUS0,M4 MIX software down trigger status register" bitfld.long 0x00 13. " M4_PCIE2_PGC_PDN_STATUS ,M4 PCIE2 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 12. " M4_MIPI_CSI2_PGC_PDN_STATUS ,M4 MIPI CSI2 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 11. " M4_MIPI_CSI1_PGC_PDN_STATUS ,M4 MIPI CSI1 PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 10. " M4_DISP_PGC_PDN_STATUS ,M4 DISP PGC power down status" "Succeeded,Failed" bitfld.long 0x00 9. " M4_HDMI_PGC_PDN_STATUS ,M4 HDMI PGC power down status" "Succeeded,Failed" bitfld.long 0x00 8. " M4_VPU_PGC_PDN_STATUS ,M4 VPU PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 7. " M4_GPU_PGC_PDN_STATUS ,M4 GPU PGC power down status" "Succeeded,Failed" bitfld.long 0x00 5. " M4_DDR1_PGC_PDN_STATUS ,M4 DDR1 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 3. " M4_USB_OTG2_PGC_PDN_STATUS , M4 USB_OTG2 PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 2. " M4_USB_OTG1_PGC_PDN_STATUS ,M4 USB_OTG1 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 1. " M4_PCIE_PGC_PDN_STATUS ,M4 PCIE PGC power down status" "Succeeded,Failed" bitfld.long 0x00 0. " M4_MIPI_PGC_PDN_STATUS ,M4 MIPI PGC power down status" "Succeeded,Failed" rgroup.long 0x19C++0x03 line.long 0x00 "M4_MIX_PGC_PDN_STATUS1,M4 MIX software down trigger status register" bitfld.long 0x00 13. " M4_PCIE2_PGC_PDN_STATUS ,M4 PCIE2 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 12. " M4_MIPI_CSI2_PGC_PDN_STATUS ,M4 MIPI CSI2 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 11. " M4_MIPI_CSI1_PGC_PDN_STATUS ,M4 MIPI CSI1 PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 10. " M4_DISP_PGC_PDN_STATUS ,M4 DISP PGC power down status" "Succeeded,Failed" bitfld.long 0x00 9. " M4_HDMI_PGC_PDN_STATUS ,M4 HDMI PGC power down status" "Succeeded,Failed" bitfld.long 0x00 8. " M4_VPU_PGC_PDN_STATUS ,M4 VPU PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 7. " M4_GPU_PGC_PDN_STATUS ,M4 GPU PGC power down status" "Succeeded,Failed" bitfld.long 0x00 5. " M4_DDR1_PGC_PDN_STATUS ,M4 DDR1 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 3. " M4_USB_OTG2_PGC_PDN_STATUS , M4 USB_OTG2 PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 2. " M4_USB_OTG1_PGC_PDN_STATUS ,M4 USB_OTG1 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 1. " M4_PCIE_PGC_PDN_STATUS ,M4 PCIE PGC power down status" "Succeeded,Failed" bitfld.long 0x00 0. " M4_MIPI_PGC_PDN_STATUS ,M4 MIPI PGC power down status" "Succeeded,Failed" rgroup.long 0x1A0++0x03 line.long 0x00 "M4_MIX_PGC_PDN_STATUS2,M4 MIX software down trigger status register" bitfld.long 0x00 13. " M4_PCIE2_PGC_PDN_STATUS ,M4 PCIE2 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 12. " M4_MIPI_CSI2_PGC_PDN_STATUS ,M4 MIPI CSI2 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 11. " M4_MIPI_CSI1_PGC_PDN_STATUS ,M4 MIPI CSI1 PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 10. " M4_DISP_PGC_PDN_STATUS ,M4 DISP PGC power down status" "Succeeded,Failed" bitfld.long 0x00 9. " M4_HDMI_PGC_PDN_STATUS ,M4 HDMI PGC power down status" "Succeeded,Failed" bitfld.long 0x00 8. " M4_VPU_PGC_PDN_STATUS ,M4 VPU PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 7. " M4_GPU_PGC_PDN_STATUS ,M4 GPU PGC power down status" "Succeeded,Failed" bitfld.long 0x00 5. " M4_DDR1_PGC_PDN_STATUS ,M4 DDR1 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 3. " M4_USB_OTG2_PGC_PDN_STATUS , M4 USB_OTG2 PGC power down status" "Succeeded,Failed" textline " " bitfld.long 0x00 2. " M4_USB_OTG1_PGC_PDN_STATUS ,M4 USB_OTG1 PGC power down status" "Succeeded,Failed" bitfld.long 0x00 1. " M4_PCIE_PGC_PDN_STATUS ,M4 PCIE PGC power down status" "Succeeded,Failed" bitfld.long 0x00 0. " M4_MIPI_PGC_PDN_STATUS ,M4 MIPI PGC power down status" "Succeeded,Failed" group.long 0x1B0++0x0F line.long 0x00 "A53_MIX_PDN_FLG,A53 MIX PDN FLG" bitfld.long 0x00 0. " A53_MIX_PDN_FLAG ,A53 MIX power-down flag" "Not powered down,Powered down" line.long 0x04 "A53_PU_PDN_FLG,A53 PU PDN FLG" hexmask.long.word 0x04 0.--13. 1. " A53_PU_PDN_FLG ,A53 PGC power-down flag" line.long 0x08 "M4_MIX_PDN_FLG,M4 MIX PDN FLG" bitfld.long 0x08 0. " M4_MIX_PDN_FLAG ,M4 MIX power-down flag" "Not powered down,Powered down" line.long 0x0C "A53_PU_PDN_FLG,A53 PU PDN FLG" hexmask.long.word 0x0C 0.--13. 1. " M4_PU_PDN_FLG ,M4 PGC power-down flag" group.long 0x1C0++0x27 line.long 0x00 "IMR1_CORE2_A53,IRQ masking register 1 of A53 core2" bitfld.long 0x00 31. " IMR1_CORE2_A53[31] ,A53 core2 IRQ[31] mask bit 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,A53 core2 IRQ[30] mask bit 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,A53 core2 IRQ[29] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x00 28. " [28] ,A53 core2 IRQ[28] mask bit 28" "Not masked,Masked" bitfld.long 0x00 27. " [27] ,A53 core2 IRQ[27] mask bit 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,A53 core2 IRQ[26] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " [25] ,A53 core2 IRQ[25] mask bit 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,A53 core2 IRQ[24] mask bit 24" "Not masked,Masked" bitfld.long 0x00 23. " [23] ,A53 core2 IRQ[23] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " [22] ,A53 core2 IRQ[22] mask bit 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,A53 core2 IRQ[21] mask bit 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,A53 core2 IRQ[20] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " [19] ,A53 core2 IRQ[19] mask bit 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,A53 core2 IRQ[18] mask bit 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,A53 core2 IRQ[17] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " [16] ,A53 core2 IRQ[16] mask bit 16" "Not masked,Masked" bitfld.long 0x00 15. " [15] ,A53 core2 IRQ[15] mask bit 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,A53 core2 IRQ[14] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " [13] ,A53 core2 IRQ[13] mask bit 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,A53 core2 IRQ[12] mask bit 12" "Not masked,Masked" bitfld.long 0x00 11. " [11] ,A53 core2 IRQ[11] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " [10] ,A53 core2 IRQ[10] mask bit 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,A53 core2 IRQ[9] mask bit 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,A53 core2 IRQ[8] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " [7] ,A53 core2 IRQ[7] mask bit 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,A53 core2 IRQ[6] mask bit 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,A53 core2 IRQ[5] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " [4] ,A53 core2 IRQ[4] mask bit 4" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,A53 core2 IRQ[3] mask bit 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,A53 core2 IRQ[2] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " [1] ,A53 core2 IRQ[1] mask bit 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,A53 core2 IRQ[0] mask bit 0" "Not masked,Masked" line.long 0x04 "IMR2_CORE2_A53,IRQ masking register 2 of A53 core2" bitfld.long 0x04 31. " IMR2_CORE2_A53[63] ,A53 core2 IRQ[63] mask bit 31" "Not masked,Masked" bitfld.long 0x04 30. " [62] ,A53 core2 IRQ[62] mask bit 30" "Not masked,Masked" bitfld.long 0x04 29. " [61] ,A53 core2 IRQ[61] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x04 28. " [60] ,A53 core2 IRQ[60] mask bit 28" "Not masked,Masked" bitfld.long 0x04 27. " [59] ,A53 core2 IRQ[59] mask bit 27" "Not masked,Masked" bitfld.long 0x04 26. " [58] ,A53 core2 IRQ[58] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [57] ,A53 core2 IRQ[57] mask bit 25" "Not masked,Masked" bitfld.long 0x04 24. " [56] ,A53 core2 IRQ[56] mask bit 24" "Not masked,Masked" bitfld.long 0x04 23. " [55] ,A53 core2 IRQ[55] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x04 22. " [54] ,A53 core2 IRQ[54] mask bit 22" "Not masked,Masked" bitfld.long 0x04 21. " [53] ,A53 core2 IRQ[53] mask bit 21" "Not masked,Masked" bitfld.long 0x04 20. " [52] ,A53 core2 IRQ[52] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [51] ,A53 core2 IRQ[51] mask bit 19" "Not masked,Masked" bitfld.long 0x04 18. " [50] ,A53 core2 IRQ[50] mask bit 18" "Not masked,Masked" bitfld.long 0x04 17. " [49] ,A53 core2 IRQ[49] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x04 16. " [48] ,A53 core2 IRQ[48] mask bit 16" "Not masked,Masked" bitfld.long 0x04 15. " [47] ,A53 core2 IRQ[47] mask bit 15" "Not masked,Masked" bitfld.long 0x04 14. " [46] ,A53 core2 IRQ[46] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [45] ,A53 core2 IRQ[45] mask bit 13" "Not masked,Masked" bitfld.long 0x04 12. " [44] ,A53 core2 IRQ[44] mask bit 12" "Not masked,Masked" bitfld.long 0x04 11. " [43] ,A53 core2 IRQ[43] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x04 10. " [42] ,A53 core2 IRQ[42] mask bit 10" "Not masked,Masked" bitfld.long 0x04 9. " [41] ,A53 core2 IRQ[41] mask bit 9" "Not masked,Masked" bitfld.long 0x04 8. " [40] ,A53 core2 IRQ[40] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [39] ,A53 core2 IRQ[39] mask bit 7" "Not masked,Masked" bitfld.long 0x04 6. " [38] ,A53 core2 IRQ[38] mask bit 6" "Not masked,Masked" bitfld.long 0x04 5. " [37] ,A53 core2 IRQ[37] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x04 4. " [36] ,A53 core2 IRQ[36] mask bit 4" "Not masked,Masked" bitfld.long 0x04 3. " [35] ,A53 core2 IRQ[35] mask bit 3" "Not masked,Masked" bitfld.long 0x04 2. " [34] ,A53 core2 IRQ[34] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [33] ,A53 core2 IRQ[33] mask bit 1" "Not masked,Masked" bitfld.long 0x04 0. " [32] ,A53 core2 IRQ[32] mask bit 0" "Not masked,Masked" line.long 0x08 "IMR3_CORE2_A53,IRQ masking register 3 of A53 core2" bitfld.long 0x08 31. " IMR3_CORE2_A53[95] ,A53 core2 IRQ[95] mask bit 31" "Not masked,Masked" bitfld.long 0x08 30. " [94] ,A53 core2 IRQ[94] mask bit 30" "Not masked,Masked" bitfld.long 0x08 29. " [93] ,A53 core2 IRQ[93] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x08 28. " [92] ,A53 core2 IRQ[92] mask bit 28" "Not masked,Masked" bitfld.long 0x08 27. " [91] ,A53 core2 IRQ[91] mask bit 27" "Not masked,Masked" bitfld.long 0x08 26. " [90] ,A53 core2 IRQ[90] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x08 25. " [89] ,A53 core2 IRQ[89] mask bit 25" "Not masked,Masked" bitfld.long 0x08 24. " [88] ,A53 core2 IRQ[88] mask bit 24" "Not masked,Masked" bitfld.long 0x08 23. " [87] ,A53 core2 IRQ[87] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x08 22. " [86] ,A53 core2 IRQ[86] mask bit 22" "Not masked,Masked" bitfld.long 0x08 21. " [85] ,A53 core2 IRQ[85] mask bit 21" "Not masked,Masked" bitfld.long 0x08 20. " [84] ,A53 core2 IRQ[84] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x08 19. " [83] ,A53 core2 IRQ[83] mask bit 19" "Not masked,Masked" bitfld.long 0x08 18. " [82] ,A53 core2 IRQ[82] mask bit 18" "Not masked,Masked" bitfld.long 0x08 17. " [81] ,A53 core2 IRQ[81] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x08 16. " [80] ,A53 core2 IRQ[80] mask bit 16" "Not masked,Masked" bitfld.long 0x08 15. " [79] ,A53 core2 IRQ[79] mask bit 15" "Not masked,Masked" bitfld.long 0x08 14. " [78] ,A53 core2 IRQ[78] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x08 13. " [77] ,A53 core2 IRQ[77] mask bit 13" "Not masked,Masked" bitfld.long 0x08 12. " [76] ,A53 core2 IRQ[76] mask bit 12" "Not masked,Masked" bitfld.long 0x08 11. " [75] ,A53 core2 IRQ[75] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x08 10. " [74] ,A53 core2 IRQ[74] mask bit 10" "Not masked,Masked" bitfld.long 0x08 9. " [73] ,A53 core2 IRQ[73] mask bit 9" "Not masked,Masked" bitfld.long 0x08 8. " [72] ,A53 core2 IRQ[72] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x08 7. " [71] ,A53 core2 IRQ[71] mask bit 7" "Not masked,Masked" bitfld.long 0x08 6. " [70] ,A53 core2 IRQ[70] mask bit 6" "Not masked,Masked" bitfld.long 0x08 5. " [69] ,A53 core2 IRQ[69] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x08 4. " [68] ,A53 core2 IRQ[68] mask bit 4" "Not masked,Masked" bitfld.long 0x08 3. " [67] ,A53 core2 IRQ[67] mask bit 3" "Not masked,Masked" bitfld.long 0x08 2. " [66] ,A53 core2 IRQ[66] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x08 1. " [65] ,A53 core2 IRQ[65] mask bit 1" "Not masked,Masked" bitfld.long 0x08 0. " [64] ,A53 core2 IRQ[64] mask bit 0" "Not masked,Masked" line.long 0x0C "IMR4_CORE2_A53,IRQ masking register 4 of A53 core2" bitfld.long 0x0C 31. " IMR4_CORE2_A53[127] ,A53 core2 IRQ[127] mask bit 31" "Not masked,Masked" bitfld.long 0x0C 30. " [126] ,A53 core2 IRQ[126] mask bit 30" "Not masked,Masked" bitfld.long 0x0C 29. " [125] ,A53 core2 IRQ[125] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x0C 28. " [124] ,A53 core2 IRQ[124] mask bit 28" "Not masked,Masked" bitfld.long 0x0C 27. " [123] ,A53 core2 IRQ[123] mask bit 27" "Not masked,Masked" bitfld.long 0x0C 26. " [122] ,A53 core2 IRQ[122] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x0C 25. " [121] ,A53 core2 IRQ[121] mask bit 25" "Not masked,Masked" bitfld.long 0x0C 24. " [120] ,A53 core2 IRQ[120] mask bit 24" "Not masked,Masked" bitfld.long 0x0C 23. " [119] ,A53 core2 IRQ[119] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x0C 22. " [118] ,A53 core2 IRQ[118] mask bit 22" "Not masked,Masked" bitfld.long 0x0C 21. " [117] ,A53 core2 IRQ[117] mask bit 21" "Not masked,Masked" bitfld.long 0x0C 20. " [116] ,A53 core2 IRQ[116] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x0C 19. " [115] ,A53 core2 IRQ[115] mask bit 19" "Not masked,Masked" bitfld.long 0x0C 18. " [114] ,A53 core2 IRQ[114] mask bit 18" "Not masked,Masked" bitfld.long 0x0C 17. " [113] ,A53 core2 IRQ[113] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x0C 16. " [112] ,A53 core2 IRQ[112] mask bit 16" "Not masked,Masked" bitfld.long 0x0C 15. " [111] ,A53 core2 IRQ[111] mask bit 15" "Not masked,Masked" bitfld.long 0x0C 14. " [110] ,A53 core2 IRQ[110] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x0C 13. " [109] ,A53 core2 IRQ[109] mask bit 13" "Not masked,Masked" bitfld.long 0x0C 12. " [108] ,A53 core2 IRQ[108] mask bit 12" "Not masked,Masked" bitfld.long 0x0C 11. " [107] ,A53 core2 IRQ[107] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x0C 10. " [106] ,A53 core2 IRQ[106] mask bit 10" "Not masked,Masked" bitfld.long 0x0C 9. " [105] ,A53 core2 IRQ[105] mask bit 9" "Not masked,Masked" bitfld.long 0x0C 8. " [104] ,A53 core2 IRQ[104] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x0C 7. " [103] ,A53 core2 IRQ[103] mask bit 7" "Not masked,Masked" bitfld.long 0x0C 6. " [102] ,A53 core2 IRQ[102] mask bit 6" "Not masked,Masked" bitfld.long 0x0C 5. " [101] ,A53 core2 IRQ[101] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x0C 4. " [100] ,A53 core2 IRQ[100] mask bit 4" "Not masked,Masked" bitfld.long 0x0C 3. " [99] ,A53 core2 IRQ[99] mask bit 3" "Not masked,Masked" bitfld.long 0x0C 2. " [98] ,A53 core2 IRQ[98] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x0C 1. " [97] ,A53 core2 IRQ[97] mask bit 1" "Not masked,Masked" bitfld.long 0x0C 0. " [96] ,A53 core2 IRQ[96] mask bit 0" "Not masked,Masked" line.long 0x10 "IMR1_CORE3_A53,IRQ masking register 1 of A53 core3" bitfld.long 0x10 31. " IMR1_CORE3_A53[31] ,A53 core3 IRQ[31] mask bit 31" "Not masked,Masked" bitfld.long 0x10 30. " [30] ,A53 core3 IRQ[30] mask bit 30" "Not masked,Masked" bitfld.long 0x10 29. " [29] ,A53 core3 IRQ[29] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x10 28. " [28] ,A53 core3 IRQ[28] mask bit 28" "Not masked,Masked" bitfld.long 0x10 27. " [27] ,A53 core3 IRQ[27] mask bit 27" "Not masked,Masked" bitfld.long 0x10 26. " [26] ,A53 core3 IRQ[26] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x10 25. " [25] ,A53 core3 IRQ[25] mask bit 25" "Not masked,Masked" bitfld.long 0x10 24. " [24] ,A53 core3 IRQ[24] mask bit 24" "Not masked,Masked" bitfld.long 0x10 23. " [23] ,A53 core3 IRQ[23] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x10 22. " [22] ,A53 core3 IRQ[22] mask bit 22" "Not masked,Masked" bitfld.long 0x10 21. " [21] ,A53 core3 IRQ[21] mask bit 21" "Not masked,Masked" bitfld.long 0x10 20. " [20] ,A53 core3 IRQ[20] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x10 19. " [19] ,A53 core3 IRQ[19] mask bit 19" "Not masked,Masked" bitfld.long 0x10 18. " [18] ,A53 core3 IRQ[18] mask bit 18" "Not masked,Masked" bitfld.long 0x10 17. " [17] ,A53 core3 IRQ[17] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x10 16. " [16] ,A53 core3 IRQ[16] mask bit 16" "Not masked,Masked" bitfld.long 0x10 15. " [15] ,A53 core3 IRQ[15] mask bit 15" "Not masked,Masked" bitfld.long 0x10 14. " [14] ,A53 core3 IRQ[14] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x10 13. " [13] ,A53 core3 IRQ[13] mask bit 13" "Not masked,Masked" bitfld.long 0x10 12. " [12] ,A53 core3 IRQ[12] mask bit 12" "Not masked,Masked" bitfld.long 0x10 11. " [11] ,A53 core3 IRQ[11] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x10 10. " [10] ,A53 core3 IRQ[10] mask bit 10" "Not masked,Masked" bitfld.long 0x10 9. " [9] ,A53 core3 IRQ[9] mask bit 9" "Not masked,Masked" bitfld.long 0x10 8. " [8] ,A53 core3 IRQ[8] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x10 7. " [7] ,A53 core3 IRQ[7] mask bit 7" "Not masked,Masked" bitfld.long 0x10 6. " [6] ,A53 core3 IRQ[6] mask bit 6" "Not masked,Masked" bitfld.long 0x10 5. " [5] ,A53 core3 IRQ[5] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x10 4. " [4] ,A53 core3 IRQ[4] mask bit 4" "Not masked,Masked" bitfld.long 0x10 3. " [3] ,A53 core3 IRQ[3] mask bit 3" "Not masked,Masked" bitfld.long 0x10 2. " [2] ,A53 core3 IRQ[2] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x10 1. " [1] ,A53 core3 IRQ[1] mask bit 1" "Not masked,Masked" bitfld.long 0x10 0. " [0] ,A53 core3 IRQ[0] mask bit 0" "Not masked,Masked" line.long 0x14 "IMR2_CORE3_A53,IRQ masking register 2 of A53 core3" bitfld.long 0x14 31. " IMR2_CORE3_A53[63] ,A53 core3 IRQ[63] mask bit 31" "Not masked,Masked" bitfld.long 0x14 30. " [62] ,A53 core3 IRQ[62] mask bit 30" "Not masked,Masked" bitfld.long 0x14 29. " [61] ,A53 core3 IRQ[61] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x14 28. " [60] ,A53 core3 IRQ[60] mask bit 28" "Not masked,Masked" bitfld.long 0x14 27. " [59] ,A53 core3 IRQ[59] mask bit 27" "Not masked,Masked" bitfld.long 0x14 26. " [58] ,A53 core3 IRQ[58] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x14 25. " [57] ,A53 core3 IRQ[57] mask bit 25" "Not masked,Masked" bitfld.long 0x14 24. " [56] ,A53 core3 IRQ[56] mask bit 24" "Not masked,Masked" bitfld.long 0x14 23. " [55] ,A53 core3 IRQ[55] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x14 22. " [54] ,A53 core3 IRQ[54] mask bit 22" "Not masked,Masked" bitfld.long 0x14 21. " [53] ,A53 core3 IRQ[53] mask bit 21" "Not masked,Masked" bitfld.long 0x14 20. " [52] ,A53 core3 IRQ[52] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x14 19. " [51] ,A53 core3 IRQ[51] mask bit 19" "Not masked,Masked" bitfld.long 0x14 18. " [50] ,A53 core3 IRQ[50] mask bit 18" "Not masked,Masked" bitfld.long 0x14 17. " [49] ,A53 core3 IRQ[49] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x14 16. " [48] ,A53 core3 IRQ[48] mask bit 16" "Not masked,Masked" bitfld.long 0x14 15. " [47] ,A53 core3 IRQ[47] mask bit 15" "Not masked,Masked" bitfld.long 0x14 14. " [46] ,A53 core3 IRQ[46] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x14 13. " [45] ,A53 core3 IRQ[45] mask bit 13" "Not masked,Masked" bitfld.long 0x14 12. " [44] ,A53 core3 IRQ[44] mask bit 12" "Not masked,Masked" bitfld.long 0x14 11. " [43] ,A53 core3 IRQ[43] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x14 10. " [42] ,A53 core3 IRQ[42] mask bit 10" "Not masked,Masked" bitfld.long 0x14 9. " [41] ,A53 core3 IRQ[41] mask bit 9" "Not masked,Masked" bitfld.long 0x14 8. " [40] ,A53 core3 IRQ[40] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x14 7. " [39] ,A53 core3 IRQ[39] mask bit 7" "Not masked,Masked" bitfld.long 0x14 6. " [38] ,A53 core3 IRQ[38] mask bit 6" "Not masked,Masked" bitfld.long 0x14 5. " [37] ,A53 core3 IRQ[37] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x14 4. " [36] ,A53 core3 IRQ[36] mask bit 4" "Not masked,Masked" bitfld.long 0x14 3. " [35] ,A53 core3 IRQ[35] mask bit 3" "Not masked,Masked" bitfld.long 0x14 2. " [34] ,A53 core3 IRQ[34] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x14 1. " [33] ,A53 core3 IRQ[33] mask bit 1" "Not masked,Masked" bitfld.long 0x14 0. " [32] ,A53 core3 IRQ[32] mask bit 0" "Not masked,Masked" line.long 0x18 "IMR3_CORE3_A53,IRQ masking register 3 of A53 core3" bitfld.long 0x18 31. " IMR3_CORE3_A53[95] ,A53 core3 IRQ[95] mask bit 31" "Not masked,Masked" bitfld.long 0x18 30. " [94] ,A53 core3 IRQ[94] mask bit 30" "Not masked,Masked" bitfld.long 0x18 29. " [93] ,A53 core3 IRQ[93] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x18 28. " [92] ,A53 core3 IRQ[92] mask bit 28" "Not masked,Masked" bitfld.long 0x18 27. " [91] ,A53 core3 IRQ[91] mask bit 27" "Not masked,Masked" bitfld.long 0x18 26. " [90] ,A53 core3 IRQ[90] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x18 25. " [89] ,A53 core3 IRQ[89] mask bit 25" "Not masked,Masked" bitfld.long 0x18 24. " [88] ,A53 core3 IRQ[88] mask bit 24" "Not masked,Masked" bitfld.long 0x18 23. " [87] ,A53 core3 IRQ[87] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x18 22. " [86] ,A53 core3 IRQ[86] mask bit 22" "Not masked,Masked" bitfld.long 0x18 21. " [85] ,A53 core3 IRQ[85] mask bit 21" "Not masked,Masked" bitfld.long 0x18 20. " [84] ,A53 core3 IRQ[84] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x18 19. " [83] ,A53 core3 IRQ[83] mask bit 19" "Not masked,Masked" bitfld.long 0x18 18. " [82] ,A53 core3 IRQ[82] mask bit 18" "Not masked,Masked" bitfld.long 0x18 17. " [81] ,A53 core3 IRQ[81] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x18 16. " [80] ,A53 core3 IRQ[80] mask bit 16" "Not masked,Masked" bitfld.long 0x18 15. " [79] ,A53 core3 IRQ[79] mask bit 15" "Not masked,Masked" bitfld.long 0x18 14. " [78] ,A53 core3 IRQ[78] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x18 13. " [77] ,A53 core3 IRQ[77] mask bit 13" "Not masked,Masked" bitfld.long 0x18 12. " [76] ,A53 core3 IRQ[76] mask bit 12" "Not masked,Masked" bitfld.long 0x18 11. " [75] ,A53 core3 IRQ[75] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x18 10. " [74] ,A53 core3 IRQ[74] mask bit 10" "Not masked,Masked" bitfld.long 0x18 9. " [73] ,A53 core3 IRQ[73] mask bit 9" "Not masked,Masked" bitfld.long 0x18 8. " [72] ,A53 core3 IRQ[72] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x18 7. " [71] ,A53 core3 IRQ[71] mask bit 7" "Not masked,Masked" bitfld.long 0x18 6. " [70] ,A53 core3 IRQ[70] mask bit 6" "Not masked,Masked" bitfld.long 0x18 5. " [69] ,A53 core3 IRQ[69] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x18 4. " [68] ,A53 core3 IRQ[68] mask bit 4" "Not masked,Masked" bitfld.long 0x18 3. " [67] ,A53 core3 IRQ[67] mask bit 3" "Not masked,Masked" bitfld.long 0x18 2. " [66] ,A53 core3 IRQ[66] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x18 1. " [65] ,A53 core3 IRQ[65] mask bit 1" "Not masked,Masked" bitfld.long 0x18 0. " [64] ,A53 core3 IRQ[64] mask bit 0" "Not masked,Masked" line.long 0x1C "IMR4_CORE3_A53,IRQ masking register 4 of A53 core3" bitfld.long 0x1C 31. " IMR4_CORE3_A53[127] ,A53 core3 IRQ[127] mask bit 31" "Not masked,Masked" bitfld.long 0x1C 30. " [126] ,A53 core3 IRQ[126] mask bit 30" "Not masked,Masked" bitfld.long 0x1C 29. " [125] ,A53 core3 IRQ[125] mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x1C 28. " [124] ,A53 core3 IRQ[124] mask bit 28" "Not masked,Masked" bitfld.long 0x1C 27. " [123] ,A53 core3 IRQ[123] mask bit 27" "Not masked,Masked" bitfld.long 0x1C 26. " [122] ,A53 core3 IRQ[122] mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x1C 25. " [121] ,A53 core3 IRQ[121] mask bit 25" "Not masked,Masked" bitfld.long 0x1C 24. " [120] ,A53 core3 IRQ[120] mask bit 24" "Not masked,Masked" bitfld.long 0x1C 23. " [119] ,A53 core3 IRQ[119] mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x1C 22. " [118] ,A53 core3 IRQ[118] mask bit 22" "Not masked,Masked" bitfld.long 0x1C 21. " [117] ,A53 core3 IRQ[117] mask bit 21" "Not masked,Masked" bitfld.long 0x1C 20. " [116] ,A53 core3 IRQ[116] mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x1C 19. " [115] ,A53 core3 IRQ[115] mask bit 19" "Not masked,Masked" bitfld.long 0x1C 18. " [114] ,A53 core3 IRQ[114] mask bit 18" "Not masked,Masked" bitfld.long 0x1C 17. " [113] ,A53 core3 IRQ[113] mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x1C 16. " [112] ,A53 core3 IRQ[112] mask bit 16" "Not masked,Masked" bitfld.long 0x1C 15. " [111] ,A53 core3 IRQ[111] mask bit 15" "Not masked,Masked" bitfld.long 0x1C 14. " [110] ,A53 core3 IRQ[110] mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x1C 13. " [109] ,A53 core3 IRQ[109] mask bit 13" "Not masked,Masked" bitfld.long 0x1C 12. " [108] ,A53 core3 IRQ[108] mask bit 12" "Not masked,Masked" bitfld.long 0x1C 11. " [107] ,A53 core3 IRQ[107] mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x1C 10. " [106] ,A53 core3 IRQ[106] mask bit 10" "Not masked,Masked" bitfld.long 0x1C 9. " [105] ,A53 core3 IRQ[105] mask bit 9" "Not masked,Masked" bitfld.long 0x1C 8. " [104] ,A53 core3 IRQ[104] mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x1C 7. " [103] ,A53 core3 IRQ[103] mask bit 7" "Not masked,Masked" bitfld.long 0x1C 6. " [102] ,A53 core3 IRQ[102] mask bit 6" "Not masked,Masked" bitfld.long 0x1C 5. " [101] ,A53 core3 IRQ[101] mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x1C 4. " [100] ,A53 core3 IRQ[100] mask bit 4" "Not masked,Masked" bitfld.long 0x1C 3. " [99] ,A53 core3 IRQ[99] mask bit 3" "Not masked,Masked" bitfld.long 0x1C 2. " [98] ,A53 core3 IRQ[98] mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x1C 1. " [97] ,A53 core3 IRQ[97] mask bit 1" "Not masked,Masked" bitfld.long 0x1C 0. " [96] ,A53 core3 IRQ[96] mask bit 0" "Not masked,Masked" line.long 0x20 "ACK_SEL_A53_PU,PGC acknowledge signal selection of A53 platform for PUs" bitfld.long 0x20 31. " PCIE2_PGC_PUP_ACK ,Power down acknowledge signal of PCIE2 PGC" "Disabled,Enabled" bitfld.long 0x20 30. " MIPI_CSI2_PGC_PUP_ACK ,Power down acknowledge signal of MIPI_CSI2 PGC" "Disabled,Enabled" bitfld.long 0x20 29. " MIPI_CSI1_PGC_PUP_ACK ,Power down acknowledge signal of MIPI_CSI1 PGC" "Disabled,Enabled" textline " " bitfld.long 0x20 28. " DISP_PGC_PUP_ACK ,Power down acknowledge signal of DISP PGC" "Disabled,Enabled" bitfld.long 0x20 27. " HDMI_PGC_PUP_ACK ,Power down acknowledge signal of HDMI PGC" "Disabled,Enabled" bitfld.long 0x20 26. " VPU_PGC_PUP_ACK ,Power down acknowledge signal of VPU PGC" "Disabled,Enabled" textline " " bitfld.long 0x20 25. " GPU_PGC_PUP_ACK ,Power down acknowledge signal of GPU PGC" "Disabled,Enabled" bitfld.long 0x20 24. " DDR2_PGC_PUP_ACK ,Power down acknowledge signal of DDR2 PGC" "Disabled,Enabled" bitfld.long 0x20 23. " DDR1_PGC_PUP_ACK ,Power down acknowledge signal of DDR1 PGC" "Disabled,Enabled" textline " " bitfld.long 0x20 21. " USB_OTG2_PGC_PUP_ACK ,Power down acknowledge signal of USB_OTG2 PGC" "Disabled,Enabled" bitfld.long 0x20 20. " USB_OTG1_PGC_PUP_ACK ,Power down acknowledge signal of USB_OTG1 PGC" "Disabled,Enabled" bitfld.long 0x20 19. " PCIE_PGC_PUP_ACK ,Power down acknowledge signal of PCIE PGC" "Disabled,Enabled" textline " " bitfld.long 0x20 18. " MIPI_PGC_PUP_ACK ,Power down acknowledge signal of MIPI PGC" "Disabled,Enabled" bitfld.long 0x20 16. " MF_PGC_PUP_ACK ,Power down acknowledge signal of MF PGC" "Disabled,Enabled" bitfld.long 0x20 15. " PCIE2_PGC_PDN_ACK ,Power down acknowledge signal of PCIE2 PGC" "Disabled,Enabled" textline " " bitfld.long 0x20 14. " MIPI_CSI2_PGC_PDN_ACK ,Power down acknowledge signal of MIPI_CSI2 PGC" "Disabled,Enabled" bitfld.long 0x20 13. " MIPI_CSI1_PGC_PDN_ACK ,Power down acknowledge signal of MIPI_CSI1 PGC" "Disabled,Enabled" bitfld.long 0x20 12. " DISP_PGC_PDN_ACK ,Power down acknowledge signal of DISP PGC" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " HDMI_PGC_PDN_ACK ,Power down acknowledge signal of HDMI PGC" "Disabled,Enabled" bitfld.long 0x20 10. " VPU_PGC_PDN_ACK ,Power down acknowledge signal of VPU PGC" "Disabled,Enabled" bitfld.long 0x20 9. " GPU_PGC_PDN_ACK ,Power down acknowledge signal of GPU PGC" "Disabled,Enabled" textline " " bitfld.long 0x20 8. " DDR2_PGC_PDN_ACK ,Power down acknowledge signal of DDR2 PGC" "Disabled,Enabled" bitfld.long 0x20 7. " DDR1_PGC_PDN_ACK ,Power down acknowledge signal of DDR1 PGC" "Disabled,Enabled" bitfld.long 0x20 5. " USB_OTG2_PGC_PDN_ACK ,Power down acknowledge signal of USB_OTG2 PGC" "Disabled,Enabled" textline " " bitfld.long 0x20 4. " USB_OTG1_PGC_PDN_ACK ,Power down acknowledge signal of USB_OTG1 PGC" "Disabled,Enabled" bitfld.long 0x20 3. " PCIE_PGC_PDN_ACK ,Power down acknowledge signal of PCIE PGC" "Disabled,Enabled" bitfld.long 0x20 2. " MIPI_PGC_PDN_ACK ,Power down acknowledge signal of MIPI PGC" "Disabled,Enabled" textline " " bitfld.long 0x20 0. " MF_PGC_PDN_ACK ,Power down acknowledge signal of MF PGC" "Disabled,Enabled" line.long 0x24 "ACK_SEL_M4_PU,PGC acknowledge signal selection of M4 platform for PUs" bitfld.long 0x24 31. " PCIE2_PGC_PUP_ACK ,Power down acknowledge signal of PCIE2 PGC" "Disabled,Enabled" bitfld.long 0x24 30. " MIPI_CSI2_PGC_PUP_ACK ,Power down acknowledge signal of MIPI_CSI2 PGC" "Disabled,Enabled" bitfld.long 0x24 29. " MIPI_CSI1_PGC_PUP_ACK ,Power down acknowledge signal of MIPI_CSI1 PGC" "Disabled,Enabled" textline " " bitfld.long 0x24 28. " DISP_PGC_PUP_ACK ,Power down acknowledge signal of DISP PGC" "Disabled,Enabled" bitfld.long 0x24 27. " HDMI_PGC_PUP_ACK ,Power down acknowledge signal of HDMI PGC" "Disabled,Enabled" bitfld.long 0x24 26. " VPU_PGC_PUP_ACK ,Power down acknowledge signal of VPU PGC" "Disabled,Enabled" textline " " bitfld.long 0x24 25. " GPU_PGC_PUP_ACK ,Power down acknowledge signal of GPU PGC" "Disabled,Enabled" bitfld.long 0x24 24. " DDR2_PGC_PUP_ACK ,Power down acknowledge signal of DDR2 PGC" "Disabled,Enabled" bitfld.long 0x24 23. " DDR1_PGC_PUP_ACK ,Power down acknowledge signal of DDR1 PGC" "Disabled,Enabled" textline " " bitfld.long 0x24 21. " USB_OTG2_PGC_PUP_ACK ,Power down acknowledge signal of USB_OTG2 PGC" "Disabled,Enabled" bitfld.long 0x24 20. " USB_OTG1_PGC_PUP_ACK ,Power down acknowledge signal of USB_OTG1 PGC" "Disabled,Enabled" bitfld.long 0x24 19. " PCIE_PGC_PUP_ACK ,Power down acknowledge signal of PCIE PGC" "Disabled,Enabled" textline " " bitfld.long 0x24 18. " MIPI_PGC_PUP_ACK ,Power down acknowledge signal of MIPI PGC" "Disabled,Enabled" bitfld.long 0x24 16. " MF_PGC_PUP_ACK ,Power down acknowledge signal of MF PGC" "Disabled,Enabled" bitfld.long 0x24 15. " PCIE2_PGC_PDN_ACK ,Power down acknowledge signal of PCIE2 PGC" "Disabled,Enabled" textline " " bitfld.long 0x24 14. " MIPI_CSI2_PGC_PDN_ACK ,Power down acknowledge signal of MIPI_CSI2 PGC" "Disabled,Enabled" bitfld.long 0x24 13. " MIPI_CSI1_PGC_PDN_ACK ,Power down acknowledge signal of MIPI_CSI1 PGC" "Disabled,Enabled" bitfld.long 0x24 12. " DISP_PGC_PDN_ACK ,Power down acknowledge signal of DISP PGC" "Disabled,Enabled" textline " " bitfld.long 0x24 11. " HDMI_PGC_PDN_ACK ,Power down acknowledge signal of HDMI PGC" "Disabled,Enabled" bitfld.long 0x24 10. " VPU_PGC_PDN_ACK ,Power down acknowledge signal of VPU PGC" "Disabled,Enabled" bitfld.long 0x24 9. " GPU_PGC_PDN_ACK ,Power down acknowledge signal of GPU PGC" "Disabled,Enabled" textline " " bitfld.long 0x24 8. " DDR2_PGC_PDN_ACK ,Power down acknowledge signal of DDR2 PGC" "Disabled,Enabled" bitfld.long 0x24 7. " DDR1_PGC_PDN_ACK ,Power down acknowledge signal of DDR1 PGC" "Disabled,Enabled" bitfld.long 0x24 5. " USB_OTG2_PGC_PDN_ACK ,Power down acknowledge signal of USB_OTG2 PGC" "Disabled,Enabled" textline " " bitfld.long 0x24 4. " USB_OTG1_PGC_PDN_ACK ,Power down acknowledge signal of USB_OTG1 PGC" "Disabled,Enabled" bitfld.long 0x24 3. " PCIE_PGC_PDN_ACK ,Power down acknowledge signal of PCIE PGC" "Disabled,Enabled" bitfld.long 0x24 2. " MIPI_PGC_PDN_ACK ,Power down acknowledge signal of MIPI PGC" "Disabled,Enabled" textline " " bitfld.long 0x24 0. " MF_PGC_PDN_ACK ,Power down acknowledge signal of MF PGC" "Disabled,Enabled" group.long 0x1E8++0x03 line.long 0x00 "SLT0_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Not powered-down,Powered-down" group.long 0x1EC++0x03 line.long 0x00 "SLT1_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Not powered-down,Powered-down" group.long 0x1F0++0x03 line.long 0x00 "SLT2_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Not powered-down,Powered-down" group.long 0x1F4++0x03 line.long 0x00 "SLT3_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Not powered-down,Powered-down" group.long 0x1F8++0x03 line.long 0x00 "SLT4_CFG,Slot configure register for A53 core" bitfld.long 0x00 9. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 8. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " CORE3_A53_PUP_SLOT_CONTROL ,CORE3 A53 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 6. " CORE3_A53_DN_SLOT_CONTROL ,CORE3 A53 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 5. " CORE2_A53__PUP_SLOT_CONTROL ,CORE2 A53 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " CORE2_A53__PDN_SLOT_CONTROL ,CORE2 A53 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 3. " CORE1_A53_PUP_SLOT_CONTROL ,CORE1 A53 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A53_PDN_SLOT_CONTROL ,CORE1 A53 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " CORE0_A53_PUP_SLOT_CONTROL ,CORE0 A53 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 0. " CORE0_A53_PDN_SLOT_CONTROL ,CORE0 A53 Power-down slot control" "Not powered-down,Powered-down" group.long 0x1FC++0x03 line.long 0x00 "PU_PWRHSK,Power handshake register" bitfld.long 0x00 26. " GPC_GPUMIX_PWRDNACKN ,GPU ADB400 power down ack" "Activated,Not activated" bitfld.long 0x00 25. " GPC_VPUMIX_PWRDNACKN ,VPU ADB400 power down ack" "Activated,Not activated" bitfld.long 0x00 24. " GPC_DISPMIX_PWRDNACKN ,DSIP ADB400 power down ack" "Activated,Not activated" textline " " bitfld.long 0x00 23. " GPC_DDR2_AXI_CACTIVE ,DDR2 AXI Clock" "Not activated,Activated" bitfld.long 0x00 22. " GPC_DDR2_AXI_CSYSACK ,DDR2 AXI Low-Power Request ack" "Not activated,Activated" bitfld.long 0x00 21. " GPC_DDR2_CORE_CACTIVE ,DDR2 controller Hardware Low-Power Clock" "Not activated,Activated" textline " " bitfld.long 0x00 20. " GPC_DDR2_CORE_CSYSACK ,DDR2 controller Hardware Low-Power ack" "Not activated,Activated" bitfld.long 0x00 19. " GPC_DDR1_AXI_CACTIVE ,DDR1 AXI Clock" "Not activated,Activated" bitfld.long 0x00 18. " GPC_DDR1_AXI_CSYSACK ,DDR1 AXI Low-Power Request ack" "Not activated,Activated" textline " " bitfld.long 0x00 17. " GPC_DDR1_CORE_CACTIVE ,DDR1 controller Hardware Low-Power Clock" "Not activated,Activated" bitfld.long 0x00 16. " GPC_DDR1_CORE_CSYSACK ,DDR1 controller Hardware Low-Power ack" "Not activated,Activated" bitfld.long 0x00 6. " GPC_GPUMIX_PWRDNREQN ,GPU ADB400 power down request" "Activated,Not activated" textline " " bitfld.long 0x00 5. " GPC_VPUMIX_PWRDNREQN ,VPU ADB400 power down request" "Activated,Not activated" bitfld.long 0x00 4. " GPC_DISPMIX_PWRDNREQN ,DSIP ADB400 power down request" "Activated,Not activated" bitfld.long 0x00 3. " GPC_DDR2_AXI_CSYSREQU ,DDR2 AXI Low-Power Request" "Not requested,Requested" textline " " bitfld.long 0x00 2. " GPC_DDR2_CORE_CSYSREQU ,DDR2 controller Hardware Low-Power Request" "Not requested,Requested" bitfld.long 0x00 1. " GPC_DDR1_AXI_CSYSREQU ,DDR1 AXI Low-Power Request" "Not requested,Requested" bitfld.long 0x00 0. " GPC_DDR1_CORE_CSYSREQU ,DDR1 controller Hardware Low-Power Request" "Not requested,Requested" group.long 0x200++0x03 line.long 0x00 "SLT0_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x204++0x03 line.long 0x00 "SLT1_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x208++0x03 line.long 0x00 "SLT2_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x20C++0x03 line.long 0x00 "SLT3_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x210++0x03 line.long 0x00 "SLT4_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x214++0x03 line.long 0x00 "SLT5_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x218++0x03 line.long 0x00 "SLT6_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x21C++0x03 line.long 0x00 "SLT7_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x220++0x03 line.long 0x00 "SLT8_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x224++0x03 line.long 0x00 "SLT9_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x228++0x03 line.long 0x00 "SLT10_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x22C++0x03 line.long 0x00 "SLT11_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x230++0x03 line.long 0x00 "SLT12_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x234++0x03 line.long 0x00 "SLT13_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x238++0x03 line.long 0x00 "SLT14_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x23C++0x03 line.long 0x00 "SLT15_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x240++0x03 line.long 0x00 "SLT16_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x244++0x03 line.long 0x00 "SLT17_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x248++0x03 line.long 0x00 "SLT18_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" group.long 0x24C++0x03 line.long 0x00 "SLT19_CFG,Slot configure register for PUs" bitfld.long 0x00 31. " PCIE2_PUP_SLOT_CONTROL ,PCIE2 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 30. " PCIE2_PDN_SLOT_CONTROL ,PCIE2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 29. " MIPI_CSI2_PUP_SLOT_CONTROL ,MIPI CSI2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 28. " MIPI_CSI2_DN_SLOT_CONTROL ,MIPI CSI2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 27. " MIPI_CSI1_PUP_SLOT_CONTROL ,MIPI CSI1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 26. " MIPI_CSI1_PDN_SLOT_CONTROL ,MIPI CSI1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 25. " DISP_PUP_SLOT_CONTROL ,DISP Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 24. " DISP_PDN_SLOT_CONTROL ,DISP Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 23. " HDMI_PUP_SLOT_CONTROL ,HDMI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 22. " HDMI_PDN_SLOT_CONTROL ,HDMI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 21. " VPU_PUP_SLOT_CONTROL ,VPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 20. " VPU_PDN_SLOT_CONTROL ,VPU Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 19. " GPU_PUP_SLOT_CONTROL ,GPU Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 18. " GPU_DN_SLOT_CONTROL ,GPU Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 17. " DDR2_PUP_SLOT_CONTROL ,DDR2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 16. " DDR2_PDN_SLOT_CONTROL ,DDR2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 15. " DDR1_PUP_SLOT_CONTROL ,DDR1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 14. " DDR1_PDN_SLOT_CONTROL ,DDR1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 13. " M4_PUP_SLOT_CONTROL ,M4 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 12. " M4_PDN_SLOT_CONTROL ,M4 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 9. " OTG2_PUP_SLOT_CONTROL ,OTG2 Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 8. " OTG2_DN_SLOT_CONTROL ,OTG2 Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 7. " OTG1_PUP_SLOT_CONTROL ,OTG1 Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 6. " OTG1_PDN_SLOT_CONTROL ,OTG1 Power-down slot control" "Not powered-down,Powered-down" textline " " bitfld.long 0x00 5. " PCIE_PUP_SLOT_CONTROL ,PCIE Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 4. " PCIE_PDN_SLOT_CONTROL ,PCIE Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 3. " MIPI_PUP_SLOT_CONTROL ,MIPI Power-up slot control" "Not powered-up,Powered-up" textline " " bitfld.long 0x00 2. " MIPI_PDN_SLOT_CONTROL ,MIPI Power-down slot control" "Not powered-down,Powered-down" bitfld.long 0x00 1. " MF_PUP_SLOT_CONTROL ,MF Power-up slot control" "Not powered-up,Powered-up" bitfld.long 0x00 0. " MF_PDN_SLOT_CONTROL ,MF Power-down slot control" "Not powered-down,Powered-down" width 0x0B tree.end tree "GPC_PGC (General Power Controller - Power Gating Controller)" base ad:0x303A0000 width 16. group.long 0x800++0x03 line.long 0x00 "0CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0x800+0x04)&0x40)==0x40)) group.long (0x800+0x04)++0x03 line.long 0x00 "0PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,APUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x800+0x04)++0x03 line.long 0x00 "0PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x800+0x04)++0x0B line.long 0x00 "0PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "0SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,Clock divider select for the clock of power up counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "0AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,Clock divider select for the clock of power down counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x840++0x03 line.long 0x00 "1CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0x840+0x04)&0x40)==0x40)) group.long (0x840+0x04)++0x03 line.long 0x00 "1PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,APUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x840+0x04)++0x03 line.long 0x00 "1PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x840+0x04)++0x0B line.long 0x00 "1PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "1SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,Clock divider select for the clock of power up counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "1AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,Clock divider select for the clock of power down counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x880++0x03 line.long 0x00 "2CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0x880+0x04)&0x40)==0x40)) group.long (0x880+0x04)++0x03 line.long 0x00 "2PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,APUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x880+0x04)++0x03 line.long 0x00 "2PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x880+0x04)++0x0B line.long 0x00 "2PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "2SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,Clock divider select for the clock of power up counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "2AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,Clock divider select for the clock of power down counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C0++0x03 line.long 0x00 "3CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0x8C0+0x04)&0x40)==0x40)) group.long (0x8C0+0x04)++0x03 line.long 0x00 "3PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,APUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x8C0+0x04)++0x03 line.long 0x00 "3PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x8C0+0x04)++0x0B line.long 0x00 "3PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "3SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,Clock divider select for the clock of power up counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "3AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,Clock divider select for the clock of power down counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x900++0x03 line.long 0x00 "4CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0x900+0x04)&0x40)==0x40)) group.long (0x900+0x04)++0x03 line.long 0x00 "4PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,APUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x900+0x04)++0x03 line.long 0x00 "4PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x900+0x04)++0x0B line.long 0x00 "4PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "4SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,Clock divider select for the clock of power up counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "4AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,Clock divider select for the clock of power down counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA00++0x03 line.long 0x00 "MIX_CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " MIX_PCR ,Power Control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xA04)&0x40)==0x40)) group.long 0xA04++0x03 line.long 0x00 "MIX_PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT , PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0xA04++0x03 line.long 0x00 "MIX_PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x08++0x0B line.long 0x00 "MIX_PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MIX_SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "MIX_AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC00++0x13 line.long 0x00 "PU_0CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xC00+0x04)&0x40)==0x40)) group.long (0xC00+0x04)++0x03 line.long 0x00 "PU_0PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xC00+0x04)++0x03 line.long 0x00 "PU_0PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xC00+0x08)++0x0B line.long 0x00 "PU_0PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_0SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_0AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC40++0x13 line.long 0x00 "PU_1CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xC40+0x04)&0x40)==0x40)) group.long (0xC40+0x04)++0x03 line.long 0x00 "PU_1PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xC40+0x04)++0x03 line.long 0x00 "PU_1PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xC40+0x08)++0x0B line.long 0x00 "PU_1PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_1SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_1AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC80++0x13 line.long 0x00 "PU_2CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xC80+0x04)&0x40)==0x40)) group.long (0xC80+0x04)++0x03 line.long 0x00 "PU_2PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xC80+0x04)++0x03 line.long 0x00 "PU_2PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xC80+0x08)++0x0B line.long 0x00 "PU_2PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_2SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_2AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xCC0++0x13 line.long 0x00 "PU_3CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xCC0+0x04)&0x40)==0x40)) group.long (0xCC0+0x04)++0x03 line.long 0x00 "PU_3PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xCC0+0x04)++0x03 line.long 0x00 "PU_3PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xCC0+0x08)++0x0B line.long 0x00 "PU_3PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_3SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_3AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD00++0x13 line.long 0x00 "PU_4CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xD00+0x04)&0x40)==0x40)) group.long (0xD00+0x04)++0x03 line.long 0x00 "PU_4PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xD00+0x04)++0x03 line.long 0x00 "PU_4PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xD00+0x08)++0x0B line.long 0x00 "PU_4PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_4SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_4AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD40++0x13 line.long 0x00 "PU_5CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xD40+0x04)&0x40)==0x40)) group.long (0xD40+0x04)++0x03 line.long 0x00 "PU_5PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xD40+0x04)++0x03 line.long 0x00 "PU_5PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xD40+0x08)++0x0B line.long 0x00 "PU_5PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_5SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_5AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD80++0x13 line.long 0x00 "PU_6CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xD80+0x04)&0x40)==0x40)) group.long (0xD80+0x04)++0x03 line.long 0x00 "PU_6PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xD80+0x04)++0x03 line.long 0x00 "PU_6PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xD80+0x08)++0x0B line.long 0x00 "PU_6PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_6SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_6AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xDC0++0x13 line.long 0x00 "PU_7CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xDC0+0x04)&0x40)==0x40)) group.long (0xDC0+0x04)++0x03 line.long 0x00 "PU_7PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xDC0+0x04)++0x03 line.long 0x00 "PU_7PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xDC0+0x08)++0x0B line.long 0x00 "PU_7PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_7SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_7AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE00++0x13 line.long 0x00 "PU_8CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xE00+0x04)&0x40)==0x40)) group.long (0xE00+0x04)++0x03 line.long 0x00 "PU_8PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xE00+0x04)++0x03 line.long 0x00 "PU_8PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xE00+0x08)++0x0B line.long 0x00 "PU_8PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_8SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_8AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE40++0x13 line.long 0x00 "PU_9CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xE40+0x04)&0x40)==0x40)) group.long (0xE40+0x04)++0x03 line.long 0x00 "PU_9PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xE40+0x04)++0x03 line.long 0x00 "PU_9PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xE40+0x08)++0x0B line.long 0x00 "PU_9PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_9SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_9AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE80++0x13 line.long 0x00 "PU_10CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xE80+0x04)&0x40)==0x40)) group.long (0xE80+0x04)++0x03 line.long 0x00 "PU_10PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xE80+0x04)++0x03 line.long 0x00 "PU_10PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xE80+0x08)++0x0B line.long 0x00 "PU_10PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_10SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_10AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xEC0++0x13 line.long 0x00 "PU_11CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xEC0+0x04)&0x40)==0x40)) group.long (0xEC0+0x04)++0x03 line.long 0x00 "PU_11PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xEC0+0x04)++0x03 line.long 0x00 "PU_11PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xEC0+0x08)++0x0B line.long 0x00 "PU_11PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_11SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_11AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF00++0x13 line.long 0x00 "PU_12CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xF00+0x04)&0x40)==0x40)) group.long (0xF00+0x04)++0x03 line.long 0x00 "PU_12PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xF00+0x04)++0x03 line.long 0x00 "PU_12PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xF00+0x08)++0x0B line.long 0x00 "PU_12PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_12SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_12AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF40++0x13 line.long 0x00 "PU_13CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,MEMPWR_TCD1_TDR_TRM" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,L2RETN_TCD1_TDR" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,DFTRAM_TCD1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--6. " L2RSTDIS ,L2RSTDIS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PCR ,Power control" "Disabled,Enabled" if (((per.w(ad:0x303A0000+0xF40+0x04)&0x40)==0x40)) group.long (0xF40+0x04)++0x03 line.long 0x00 "PU_13PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,PUP_SCALL_SCALLOUT_CNT" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0xF40+0x04)++0x03 line.long 0x00 "PU_13PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x00 7.--22. 1. " SW2ISO ,SW2ISO" bitfld.long 0x00 6. " PUP_WAIT_SCALL_OUT ,PUP_WAIT_SCALL_OUT" "0,1" bitfld.long 0x00 0.--5. " SW ,SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0xF40+0x08)++0x0B line.long 0x00 "PU_13PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x00 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,PUP_SCPRE_SCALL_CNT" hexmask.long.byte 0x00 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,PDN_SCALL_SCALLOUT_CNT" bitfld.long 0x00 8.--13. " ISO2SW ,ISO2SW" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " PDN_WAIT_SCALL_OUT ,PDN_WAIT_SCALL_OUT" "0,1" textline " " bitfld.long 0x00 0.--5. " ISO ,ISO" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PU_13SR,GPC PGC Status Register" hexmask.long.word 0x04 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,L2RSTDIS_DEASSERT_CNT" bitfld.long 0x04 3.--6. " PUP_CLK_DIV_SEL ,PUP_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x04 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" rbitfld.long 0x04 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" textline " " rbitfld.long 0x04 0. " PSR ,Power status" "Power up,Power down" line.long 0x08 "PU_13AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x08 16.--19. " PDN_CLK_DIV_SEL ,PDN_CLK_DIV_SEL" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x08 8.--13. " ISO2SW2 ,ISO2SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW2 ,SW2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree.open "XTALOSC (Crystal Oscillator)" tree "XTALOSC_OSC25M (25M Oscillator)" base ad:0x30270000 width 17. group.long 0x00++0x07 line.long 0x00 "OSC25M_CTL_CFG,25M Oscillator Control Configuration Register" bitfld.long 0x00 31. " OSC_BYPSS ,Crystal Oscillator bypass" "Oscillator,EXTAL" bitfld.long 0x00 30. " OSC_GM_TST_SEL ,Test mode GM measurement" "Normal,Test" hexmask.long.byte 0x00 16.--23. 1. " OSC_EOCV ,End of Cont Value" textline " " bitfld.long 0x00 15. " OSC_INT_MASK ,Crystal oscillator clock interrupt mask" "Masked,Enabled" bitfld.long 0x00 13. " OSC_OK_BYPASS ,OSC ok output bypass" "0,1" bitfld.long 0x00 8.--12. " OSC_DIV ,Crystal oscillator clock division factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " eventfld.long 0x00 7. " OSC_INT_STU ,Crystal oscillator clock interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 4.--6. " OSC_GM_SEL ,Crystal overdrive protection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " OSC_HYST_CTL ,Hysteresis Control" "Enabled,Disabled" textline " " bitfld.long 0x00 2. " OSC_ALC_CTL ,Automatic Level Controller Enable" "Enabled,Disabled" line.long 0x04 "OSC25M_TWAT_CFG,25M Oscillator Test Configuration Register" bitfld.long 0x04 31. " XOSC_TESTEN ,25M Oscillator Test Enable" "Disabled,Enabled" group.long 0x8000++0x07 line.long 0x00 "OSC27M_CTL_CFG,27M Oscillator Control Configuration Register" bitfld.long 0x00 31. " OSC_BYPSS ,Crystal Oscillator bypass" "Oscillator,EXTAL" bitfld.long 0x00 30. " OSC_GM_TST_SEL ,Test mode GM measurement" "Normal,Test" hexmask.long.byte 0x00 16.--23. 1. " OSC_EOCV ,End of Cont Value" textline " " bitfld.long 0x00 15. " OSC_INT_MASK ,Crystal oscillator clock interrupt mask" "Masked,Enabled" bitfld.long 0x00 13. " OSC_OK_BYPASS ,OSC ok output bypass" "0,1" bitfld.long 0x00 8.--12. " OSC_DIV ,Crystal oscillator clock division factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " eventfld.long 0x00 7. " OSC_INT_STU ,Crystal oscillator clock interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 4.--6. " OSC_GM_SEL ,Crystal overdrive protection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " OSC_HYST_CTL ,Hysteresis Control" "Enabled,Disabled" textline " " bitfld.long 0x00 2. " OSC_ALC_CTL ,Automatic Level Controller Enable" "Enabled,Disabled" line.long 0x04 "OSC27M_TWAT_CFG,27M Oscillator Test Configuration Register" bitfld.long 0x04 31. " XOSC_TESTEN ,25M Oscillator Test Enable" "Disabled,Enabled" width 0x0B tree.end tree "XTALOSC_OSC27M (27M Oscillator)" base ad:0x30278000 width 17. group.long 0x00++0x07 line.long 0x00 "OSC25M_CTL_CFG,25M Oscillator Control Configuration Register" bitfld.long 0x00 31. " OSC_BYPSS ,Crystal Oscillator bypass" "Oscillator,EXTAL" bitfld.long 0x00 30. " OSC_GM_TST_SEL ,Test mode GM measurement" "Normal,Test" hexmask.long.byte 0x00 16.--23. 1. " OSC_EOCV ,End of Cont Value" textline " " bitfld.long 0x00 15. " OSC_INT_MASK ,Crystal oscillator clock interrupt mask" "Masked,Enabled" bitfld.long 0x00 13. " OSC_OK_BYPASS ,OSC ok output bypass" "0,1" bitfld.long 0x00 8.--12. " OSC_DIV ,Crystal oscillator clock division factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " eventfld.long 0x00 7. " OSC_INT_STU ,Crystal oscillator clock interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 4.--6. " OSC_GM_SEL ,Crystal overdrive protection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " OSC_HYST_CTL ,Hysteresis Control" "Enabled,Disabled" textline " " bitfld.long 0x00 2. " OSC_ALC_CTL ,Automatic Level Controller Enable" "Enabled,Disabled" line.long 0x04 "OSC25M_TWAT_CFG,25M Oscillator Test Configuration Register" bitfld.long 0x04 31. " XOSC_TESTEN ,25M Oscillator Test Enable" "Disabled,Enabled" group.long 0x8000++0x07 line.long 0x00 "OSC27M_CTL_CFG,27M Oscillator Control Configuration Register" bitfld.long 0x00 31. " OSC_BYPSS ,Crystal Oscillator bypass" "Oscillator,EXTAL" bitfld.long 0x00 30. " OSC_GM_TST_SEL ,Test mode GM measurement" "Normal,Test" hexmask.long.byte 0x00 16.--23. 1. " OSC_EOCV ,End of Cont Value" textline " " bitfld.long 0x00 15. " OSC_INT_MASK ,Crystal oscillator clock interrupt mask" "Masked,Enabled" bitfld.long 0x00 13. " OSC_OK_BYPASS ,OSC ok output bypass" "0,1" bitfld.long 0x00 8.--12. " OSC_DIV ,Crystal oscillator clock division factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " eventfld.long 0x00 7. " OSC_INT_STU ,Crystal oscillator clock interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 4.--6. " OSC_GM_SEL ,Crystal overdrive protection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " OSC_HYST_CTL ,Hysteresis Control" "Enabled,Disabled" textline " " bitfld.long 0x00 2. " OSC_ALC_CTL ,Automatic Level Controller Enable" "Enabled,Disabled" line.long 0x04 "OSC27M_TWAT_CFG,27M Oscillator Test Configuration Register" bitfld.long 0x04 31. " XOSC_TESTEN ,25M Oscillator Test Enable" "Disabled,Enabled" width 0x0B tree.end tree.end tree "TMU (Thermal Management Unit)" base ad:0x30260000 width 14. if (((per.l(ad:0x30260000)&0x80000000)==0x00)) group.long 0x00++0x03 line.long 0x00 "TMR,TMU Mode Register" bitfld.long 0x00 31. " ME ,Monitor mode enable" "Disabled,Enabled" bitfld.long 0x00 26.--27. " ALPF ,Average low pass filter setting" "1.0,0.5,0.25,0.125" bitfld.long 0x00 15. " MSITE[15] ,Monitoring site select 15 or 0 near ARM Cortex A7" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " [14] ,Monitoring site select 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Monitoring site select 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Monitoring site select 12 or 3" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,Monitoring site select 11 or 4" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Monitoring site select 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Monitoring site select 9" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " [8] ,Monitoring site select 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Monitoring site select 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Monitoring site select 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,Monitoring site select 5" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "TMR,TMU Mode Register" bitfld.long 0x00 31. " ME ,Monitor mode enable" "Disabled,Enabled" bitfld.long 0x00 26.--27. " ALPF ,Average low pass filter setting" "1.0,0.5,0.25,0.125" rbitfld.long 0x00 15. " MSITE[15] ,Monitoring site select 15 or 0 near ARM Cortex A7" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " [14] ,Monitoring site select 14" "Disabled,Enabled" rbitfld.long 0x00 13. " [13] ,Monitoring site select 13" "Disabled,Enabled" rbitfld.long 0x00 12. " [12] ,Monitoring site select 12 or 3" "Disabled,Enabled" textline " " rbitfld.long 0x00 11. " [11] ,Monitoring site select 11 or 4" "Disabled,Enabled" rbitfld.long 0x00 10. " [10] ,Monitoring site select 10" "Disabled,Enabled" rbitfld.long 0x00 9. " [9] ,Monitoring site select 9" "Disabled,Enabled" textline " " rbitfld.long 0x00 8. " [8] ,Monitoring site select 8" "Disabled,Enabled" rbitfld.long 0x00 7. " [7] ,Monitoring site select 7" "Disabled,Enabled" rbitfld.long 0x00 6. " [6] ,Monitoring site select 6" "Disabled,Enabled" textline " " rbitfld.long 0x00 5. " [5] ,Monitoring site select 5" "Disabled,Enabled" endif rgroup.long 0x04++0x03 line.long 0x00 "TSR,TMU Status Register" bitfld.long 0x00 30. " MIE ,Monitoring interval exceeded" "Not exceeded,Exceeded" bitfld.long 0x00 29. " ORL ,Out-of-range low temperature measurement detected" "Not detected,Detected" bitfld.long 0x00 28. " ORH ,Out-of-range high temperature measurement detected" "Not detected,Detected" if (((per.l(ad:0x30260000)&0x80000000)==0x00)) group.long 0x08++0x03 line.long 0x00 "TMU_TMTMIR,TMU Monitor Temperature Measurement Interval Register" bitfld.long 0x00 0.--3. " TMI ,Temperature monitoring interval in seconds" "0.026,0.052,0.11,0.22,0.44,0.87,1.74,3.5,7,14,28,56,112,224,448,Disabled" else rgroup.long 0x08++0x03 line.long 0x00 "TMU_TMTMIR,TMU Monitor Temperature Measurement Interval Register" bitfld.long 0x00 0.--3. " TMI ,Temperature monitoring interval in seconds" "0.026,0.052,0.11,0.22,0.44,0.87,1.74,3.5,7,14,28,56,112,224,448,Disabled" endif group.long 0x20++0x03 line.long 0x00 "TMU_TIER,TMU Interrupt Enable Register" bitfld.long 0x00 31. " ITTEIE ,Immediate temperature threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " ATTEIE ,Average temperature threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " ATCTEIE ,Average temperature critical threshold exceeded interrupt enable" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "TMU_TIDR,TMU Interrupt Detect Register" eventfld.long 0x00 31. " ITTE ,Immediate temperature threshold exceeded interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 30. " ATTE ,Average temperature threshold exceeded interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 29. " ATCTE ,Average temperature critical threshold exceeded interrupt status" "No interrupt,Interrupt" group.long 0x28++0x03 line.long 0x00 "TMU_TISCR,TMU Interrupt Site Capture Register" bitfld.long 0x00 31. " ISITE[15] ,Temperature sensor site 15 or 0 near ARM Cortex A7" "Not interrupt,Interrupt" bitfld.long 0x00 30. " [14] ,Temperature sensor site 14" "Disabled,Enabled" bitfld.long 0x00 29. " [13] ,Temperature sensor site 13" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " [12] ,Temperature sensor site 12 or 3" "Disabled,Enabled" bitfld.long 0x00 27. " [11] ,Temperature sensor site 11 or 4" "Disabled,Enabled" bitfld.long 0x00 26. " [10] ,Temperature sensor site 10" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [9] ,Temperature sensor site 9" "Disabled,Enabled" bitfld.long 0x00 24. " [8] ,Temperature sensor site 8" "Disabled,Enabled" bitfld.long 0x00 23. " [7] ,Temperature sensor site 7" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " [6] ,Temperature sensor site 6" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Temperature sensor site 5" "Disabled,Enabled" bitfld.long 0x00 15. " ASITE[15] ,Temperature sensor site 15 or 0 near ARM Cortex A7" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " [14] ,Temperature sensor site 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Temperature sensor site 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Temperature sensor site 12 or 3" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,Temperature sensor site 11 or 4" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Temperature sensor site 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Temperature sensor site 9" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " [8] ,Temperature sensor site 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Temperature sensor site 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Temperature sensor site 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,Temperature sensor site select 5" "Disabled,Enabled" group.long 0x2C++0x03 line.long 0x00 "TMU_TICSCR,TMU Interrupt Critical Site Capture Register" bitfld.long 0x00 15. " CASITE[15] ,Temperature sensor site 15 or 0 near ARM Cortex A7" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Temperature sensor site 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Temperature sensor site 13" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " [12] ,Temperature sensor site 12 or 3" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Temperature sensor site 11 or 4" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Temperature sensor site 10" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,Temperature sensor site 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Temperature sensor site 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Temperature sensor site 7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " [6] ,Temperature sensor site 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Temperature sensor site select 5" "Disabled,Enabled" rgroup.long 0x40++0x07 line.long 0x00 "TMU_TMHTCRH,TMU Monitor High Temperature Capture Register" bitfld.long 0x00 31. " V ,Valid reading" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Highest temperature recorded in degrees Celsius" line.long 0x04 "TMU_TMHTCRL,TMU Monitor Low Temperature Capture Register" bitfld.long 0x04 31. " V ,Valid reading" "Not valid,Valid" hexmask.long.byte 0x04 0.--7. 1. " TEMP ,Lowest temperature recorded in degrees Celsius" group.long 0x50++0x0B line.long 0x00 "TMU_TMHTITR,TMU Monitor High Temperature Immediate Threshold Register" bitfld.long 0x00 31. " EN ,Enable threshold" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,High temperature immediate threshold value" line.long 0x04 "TMU_TMHTATR,TMU Monitor High Temperature Average Threshold Register" bitfld.long 0x04 31. " EN ,Enable threshold" "Disabled,Enabled" hexmask.long.byte 0x04 0.--7. 1. " TEMP ,High temperature average threshold value" line.long 0x08 "TMU_TMHTACTR,TMU Monitor High Temperature Average Critical Threshold Register" bitfld.long 0x08 31. " EN ,Enable threshold" "Disabled,Enabled" hexmask.long.byte 0x08 0.--7. 1. " TEMP ,High temperature average critical threshold value" group.long 0x80++0x07 line.long 0x00 "TMU_TTCFGR,TMU Temperature Configuration Register" line.long 0x04 "TMU_TSCFGR,TMU Sensor Configuration Register" if (((per.l(ad:0x30260000+0x100)&0x80000000)==0x00)) group.long 0x100++0x03 line.long 0x00 "TMU_TRITSR0,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x100++0x03 line.long 0x00 "TMU_TRITSR0,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x100+0x04)&0x80000000)==0x00)) group.long (0x100+0x04)++0x03 line.long 0x00 "TMU_TRATSR0,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x100+0x04)++0x03 line.long 0x00 "TMU_TRATSR0,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x110)&0x80000000)==0x00)) group.long 0x110++0x03 line.long 0x00 "TMU_TRITSR1,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x110++0x03 line.long 0x00 "TMU_TRITSR1,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x110+0x04)&0x80000000)==0x00)) group.long (0x110+0x04)++0x03 line.long 0x00 "TMU_TRATSR1,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x110+0x04)++0x03 line.long 0x00 "TMU_TRATSR1,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x120)&0x80000000)==0x00)) group.long 0x120++0x03 line.long 0x00 "TMU_TRITSR2,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x120++0x03 line.long 0x00 "TMU_TRITSR2,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x120+0x04)&0x80000000)==0x00)) group.long (0x120+0x04)++0x03 line.long 0x00 "TMU_TRATSR2,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x120+0x04)++0x03 line.long 0x00 "TMU_TRATSR2,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x130)&0x80000000)==0x00)) group.long 0x130++0x03 line.long 0x00 "TMU_TRITSR3,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x130++0x03 line.long 0x00 "TMU_TRITSR3,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x130+0x04)&0x80000000)==0x00)) group.long (0x130+0x04)++0x03 line.long 0x00 "TMU_TRATSR3,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x130+0x04)++0x03 line.long 0x00 "TMU_TRATSR3,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x140)&0x80000000)==0x00)) group.long 0x140++0x03 line.long 0x00 "TMU_TRITSR4,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x140++0x03 line.long 0x00 "TMU_TRITSR4,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x140+0x04)&0x80000000)==0x00)) group.long (0x140+0x04)++0x03 line.long 0x00 "TMU_TRATSR4,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x140+0x04)++0x03 line.long 0x00 "TMU_TRATSR4,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x150)&0x80000000)==0x00)) group.long 0x150++0x03 line.long 0x00 "TMU_TRITSR5,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x150++0x03 line.long 0x00 "TMU_TRITSR5,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x150+0x04)&0x80000000)==0x00)) group.long (0x150+0x04)++0x03 line.long 0x00 "TMU_TRATSR5,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x150+0x04)++0x03 line.long 0x00 "TMU_TRATSR5,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x160)&0x80000000)==0x00)) group.long 0x160++0x03 line.long 0x00 "TMU_TRITSR6,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x160++0x03 line.long 0x00 "TMU_TRITSR6,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x160+0x04)&0x80000000)==0x00)) group.long (0x160+0x04)++0x03 line.long 0x00 "TMU_TRATSR6,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x160+0x04)++0x03 line.long 0x00 "TMU_TRATSR6,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x170)&0x80000000)==0x00)) group.long 0x170++0x03 line.long 0x00 "TMU_TRITSR7,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x170++0x03 line.long 0x00 "TMU_TRITSR7,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x170+0x04)&0x80000000)==0x00)) group.long (0x170+0x04)++0x03 line.long 0x00 "TMU_TRATSR7,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x170+0x04)++0x03 line.long 0x00 "TMU_TRATSR7,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x180)&0x80000000)==0x00)) group.long 0x180++0x03 line.long 0x00 "TMU_TRITSR8,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x180++0x03 line.long 0x00 "TMU_TRITSR8,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x180+0x04)&0x80000000)==0x00)) group.long (0x180+0x04)++0x03 line.long 0x00 "TMU_TRATSR8,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x180+0x04)++0x03 line.long 0x00 "TMU_TRATSR8,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x190)&0x80000000)==0x00)) group.long 0x190++0x03 line.long 0x00 "TMU_TRITSR9,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x190++0x03 line.long 0x00 "TMU_TRITSR9,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x190+0x04)&0x80000000)==0x00)) group.long (0x190+0x04)++0x03 line.long 0x00 "TMU_TRATSR9,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x190+0x04)++0x03 line.long 0x00 "TMU_TRATSR9,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x1A0)&0x80000000)==0x00)) group.long 0x1A0++0x03 line.long 0x00 "TMU_TRITSR10,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x1A0++0x03 line.long 0x00 "TMU_TRITSR10,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x1A0+0x04)&0x80000000)==0x00)) group.long (0x1A0+0x04)++0x03 line.long 0x00 "TMU_TRATSR10,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x1A0+0x04)++0x03 line.long 0x00 "TMU_TRATSR10,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x1B0)&0x80000000)==0x00)) group.long 0x1B0++0x03 line.long 0x00 "TMU_TRITSR11,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x1B0++0x03 line.long 0x00 "TMU_TRITSR11,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x1B0+0x04)&0x80000000)==0x00)) group.long (0x1B0+0x04)++0x03 line.long 0x00 "TMU_TRATSR11,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x1B0+0x04)++0x03 line.long 0x00 "TMU_TRATSR11,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x1C0)&0x80000000)==0x00)) group.long 0x1C0++0x03 line.long 0x00 "TMU_TRITSR12,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x1C0++0x03 line.long 0x00 "TMU_TRITSR12,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x1C0+0x04)&0x80000000)==0x00)) group.long (0x1C0+0x04)++0x03 line.long 0x00 "TMU_TRATSR12,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x1C0+0x04)++0x03 line.long 0x00 "TMU_TRATSR12,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x1D0)&0x80000000)==0x00)) group.long 0x1D0++0x03 line.long 0x00 "TMU_TRITSR13,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x1D0++0x03 line.long 0x00 "TMU_TRITSR13,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x1D0+0x04)&0x80000000)==0x00)) group.long (0x1D0+0x04)++0x03 line.long 0x00 "TMU_TRATSR13,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x1D0+0x04)++0x03 line.long 0x00 "TMU_TRATSR13,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x1E0)&0x80000000)==0x00)) group.long 0x1E0++0x03 line.long 0x00 "TMU_TRITSR14,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x1E0++0x03 line.long 0x00 "TMU_TRITSR14,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x1E0+0x04)&0x80000000)==0x00)) group.long (0x1E0+0x04)++0x03 line.long 0x00 "TMU_TRATSR14,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x1E0+0x04)++0x03 line.long 0x00 "TMU_TRATSR14,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif if (((per.l(ad:0x30260000+0x1F0)&0x80000000)==0x00)) group.long 0x1F0++0x03 line.long 0x00 "TMU_TRITSR15,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long 0x1F0++0x03 line.long 0x00 "TMU_TRITSR15,TMU Report Immediate Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" endif if (((per.l(ad:0x30260000+0x1F0+0x04)&0x80000000)==0x00)) group.long (0x1F0+0x04)++0x03 line.long 0x00 "TMU_TRATSR15,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" else group.long (0x1F0+0x04)++0x03 line.long 0x00 "TMU_TRATSR15,TMU Report Average Temperature Site Register" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" endif rgroup.long 0xBF8++0x07 line.long 0x00 "TMU_IPBRR0,IP Block Revision Register 0" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,IP block ID" hexmask.long.byte 0x00 8.--15. 1. " IP_MJ ,Major revision" hexmask.long.byte 0x00 0.--7. 1. " IP_MN ,Minor revision" group.long 0xF10++0x03 line.long 0x00 "TMU_TTR0CR,TMU Temperature Range 0 Control Register" bitfld.long 0x00 16.--19. " CAL_PTS ,Temperature calibration points" "1 point,2 points,3 points,4 points,5 points,6 points,7 points,8 points,9 points,10 points,11 points,12 points,13 points,14 points,15 points,16 points" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Starting temperature in Celsius for range 0" group.long 0xF14++0x03 line.long 0x00 "TMU_TTR1CR,TMU Temperature Range 1 Control Register" bitfld.long 0x00 16.--19. " CAL_PTS ,Temperature calibration points" "1 point,2 points,3 points,4 points,5 points,6 points,7 points,8 points,9 points,10 points,11 points,12 points,13 points,14 points,15 points,16 points" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Starting temperature in Celsius for range 1" group.long 0xF18++0x03 line.long 0x00 "TMU_TTR2CR,TMU Temperature Range 2 Control Register" bitfld.long 0x00 16.--19. " CAL_PTS ,Temperature calibration points" "1 point,2 points,3 points,4 points,5 points,6 points,7 points,8 points,9 points,10 points,11 points,12 points,13 points,14 points,15 points,16 points" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Starting temperature in Celsius for range 2" group.long 0xF1C++0x03 line.long 0x00 "TMU_TTR3CR,TMU Temperature Range 3 Control Register" bitfld.long 0x00 16.--19. " CAL_PTS ,Temperature calibration points" "1 point,2 points,3 points,4 points,5 points,6 points,7 points,8 points,9 points,10 points,11 points,12 points,13 points,14 points,15 points,16 points" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Starting temperature in Celsius for range 3" width 0x0B tree.end tree.end tree.open "SNVS/Reset/Fuse/Boot" tree "OCOTP (On-chip OTP Controller)" base ad:0x30350000 width 21. group.long 0x00++0x4F line.long 0x00 "CTRL,OTP Controller Control Register" hexmask.long.word 0x00 16.--31. 1. " WR_UNLOCK ,Write 0x3E77 to enable OTP write access" bitfld.long 0x00 10. " RELOAD_SHADOWS ,Re-loading the shadow" "Not forced,Forced" textline " " bitfld.long 0x00 9. " ERROR ,Error" "No error,Error" rbitfld.long 0x00 8. " BUSY ,OTP controller status bit" "Not busy,Busy" textline " " hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,OTP write and read access address register" line.long 0x04 "CTRL_SET,OPT Controller Control SET Register" hexmask.long.word 0x04 16.--31. 1. " WR_UNLOCK ,Write 0x3E77 to enable OTP write access" bitfld.long 0x04 10. " RELOAD_SHADOWS ,Re-loading the shadow" "Not forced,Forced" textline " " bitfld.long 0x04 9. " ERROR ,Error" "No error,Error" rbitfld.long 0x04 8. " BUSY ,OTP controller status bit" "Not busy,Busy" textline " " hexmask.long.byte 0x04 0.--7. 0x01 " ADDR ,OTP write and read access address register" line.long 0x08 "CTRL_CLR,OPT Controller Control CLR Register" hexmask.long.word 0x08 16.--31. 1. " WR_UNLOCK ,Write 0x3E77 to enable OTP write access" bitfld.long 0x08 10. " RELOAD_SHADOWS ,Re-loading the shadow" "Not forced,Forced" textline " " bitfld.long 0x08 9. " ERROR ,Error" "No error,Error" rbitfld.long 0x08 8. " BUSY ,OTP controller status bit" "Not busy,Busy" textline " " hexmask.long.byte 0x08 0.--7. 0x01 " ADDR ,OTP write and read access address register" line.long 0x0C "CTRL_TOG,OTP Controller Control TOGGLE Register" hexmask.long.word 0x0C 16.--31. 1. " WR_UNLOCK ,Write 0x3E77 to enable OTP write access" bitfld.long 0x0C 10. " RELOAD_SHADOWS ,Re-loading the shadow" "Not forced,Forced" textline " " bitfld.long 0x0C 9. " ERROR ,Error" "No error,Error" rbitfld.long 0x0C 8. " BUSY ,OTP controller status bit" "Not busy,Busy" textline " " hexmask.long.byte 0x0C 0.--7. 0x01 " ADDR ,OTP write and read access address register" line.long 0x10 "TIMING,OTP Controller Timing Register" bitfld.long 0x10 22.--27. " WAIT ,Time interval between auto read and write access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 16.--21. " STROBE_READ ,Strobe period in one time read OTP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x10 12.--15. " RELAX ,Time to add to all default timing parameters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x10 0.--10. 1. " STROBE_PROG ,Strobe period in one time write OTP" line.long 0x14 "TIMING_SET,OTP Controller Timing Register" bitfld.long 0x14 22.--27. " WAIT ,Time interval between auto read and write access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 16.--21. " STROBE_READ ,Strobe period in one time read OTP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x14 12.--15. " RELAX ,Time to add to all default timing parameters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x14 0.--10. 1. " STROBE_PROG ,Strobe period in one time write OTP" line.long 0x18 "TIMING_CLR,OTP Controller Timing Register" bitfld.long 0x18 22.--27. " WAIT ,Time interval between auto read and write access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " STROBE_READ ,Strobe period in one time read OTP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x18 12.--15. " RELAX ,Time to add to all default timing parameters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x18 0.--10. 1. " STROBE_PROG ,Strobe period in one time write OTP" line.long 0x1C "TIMING_TOG,OTP Controller Timing Register" bitfld.long 0x1C 22.--27. " WAIT ,Time interval between auto read and write access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 16.--21. " STROBE_READ ,Strobe period in one time read OTP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x1C 12.--15. " RELAX ,Time to add to all default timing parameters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 0.--10. 1. " STROBE_PROG ,Strobe period in one time write OTP" line.long 0x20 "DATA,OTP Controller Write Data Register" line.long 0x24 "DATA_SET,OTP Controller Write Data Register" line.long 0x28 "DATA_CLR,OTP Controller Write Data Register" line.long 0x2C "DATA_TOG,OTP Controller Write Data Register" line.long 0x30 "READ_CTRL,OTP Controller Write Data Register" bitfld.long 0x30 0. " READ_FUSE ,Initiate a read to OTP" "Disabled,Enabled" line.long 0x34 "READ_CTRL_SET,OTP Controller Write Data Register" bitfld.long 0x34 0. " READ_FUSE ,Initiate a read to OTP" "Disabled,Enabled" line.long 0x38 "READ_CTRL_CLR,OTP Controller Write Data Register" bitfld.long 0x38 0. " READ_FUSE ,Initiate a read to OTP" "Disabled,Enabled" line.long 0x3C "READ_CTRL_TOG,OTP Controller Write Data Register" bitfld.long 0x3C 0. " READ_FUSE ,Initiate a read to OTP" "Disabled,Enabled" line.long 0x40 "READ_FUSE_DATA,OTP Controller Read Data Register" line.long 0x44 "READ_FUSE_DATA_SET,OTP Controller Read Data Register" line.long 0x48 "READ_FUSE_DATA_CLR,OTP Controller Read Data Register" line.long 0x4C "READ_FUSE_DATA_TOG,OTP Controller Read Data Register" group.long 0x50++0x03 line.long 0x00 "SW_STICKY0,Sticky bit Register" bitfld.long 0x00 10. " DISABLE_READ_HDCP_DEVICE_KEY ,Disable read HDCP DEVICE HDCP" "No,Yes" bitfld.long 0x00 9. " DISABLE_READ_HDCP_TX_CERT ,Disable read HDCP TX CERT" "No,Yes" textline " " bitfld.long 0x00 8. " DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT ,Disable read HDCP TX GLOBAL CONSTANT" "No,Yes" bitfld.long 0x00 7. " DISABLE_READ_HDCP_KMEK ,Disable read HDMI KMEK" "No,Yes" textline " " bitfld.long 0x00 6. " DISABLE_READ_HDCP_FW_SRK ,Disable read HDMI FW_SRK" "No,Yes" bitfld.long 0x00 5. " DISABLE_READ_HDCP_GROUP_MASK ,Disable read GROUP MASK" "No,Yes" textline " " bitfld.long 0x00 4. " JTAG_BLOCK_RELEASE ,JTAG block release" "Blocked,Released" bitfld.long 0x00 3. " BLOCK_ROM_PART ,Block ROM part" "Not hidden,Hidden" textline " " bitfld.long 0x00 2. " FIELD_RETURN_LOCK ,Field return lock bit" "Unlocked,Locked" bitfld.long 0x00 1. " SRK_REVOKE_LOCK ,SRK revoke lock bit" "Unlocked,Locked" group.long 0x54++0x03 line.long 0x00 "SW_STICKY1,Sticky bit Register" bitfld.long 0x00 10. " DISABLE_READ_HDCP_DEVICE_KEY ,Disable read HDCP DEVICE HDCP" "No,Yes" bitfld.long 0x00 9. " DISABLE_READ_HDCP_TX_CERT ,Disable read HDCP TX CERT" "No,Yes" textline " " bitfld.long 0x00 8. " DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT ,Disable read HDCP TX GLOBAL CONSTANT" "No,Yes" bitfld.long 0x00 7. " DISABLE_READ_HDCP_KMEK ,Disable read HDMI KMEK" "No,Yes" textline " " bitfld.long 0x00 6. " DISABLE_READ_HDCP_FW_SRK ,Disable read HDMI FW_SRK" "No,Yes" bitfld.long 0x00 5. " DISABLE_READ_HDCP_GROUP_MASK ,Disable read GROUP MASK" "No,Yes" textline " " bitfld.long 0x00 4. " JTAG_BLOCK_RELEASE ,JTAG block release" "Blocked,Released" bitfld.long 0x00 3. " BLOCK_ROM_PART ,Block ROM part" "Not hidden,Hidden" textline " " bitfld.long 0x00 2. " FIELD_RETURN_LOCK ,Field return lock bit" "Unlocked,Locked" bitfld.long 0x00 1. " SRK_REVOKE_LOCK ,SRK revoke lock bit" "Unlocked,Locked" group.long 0x58++0x03 line.long 0x00 "SW_STICKY2,Sticky bit Register" bitfld.long 0x00 10. " DISABLE_READ_HDCP_DEVICE_KEY ,Disable read HDCP DEVICE HDCP" "No,Yes" bitfld.long 0x00 9. " DISABLE_READ_HDCP_TX_CERT ,Disable read HDCP TX CERT" "No,Yes" textline " " bitfld.long 0x00 8. " DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT ,Disable read HDCP TX GLOBAL CONSTANT" "No,Yes" bitfld.long 0x00 7. " DISABLE_READ_HDCP_KMEK ,Disable read HDMI KMEK" "No,Yes" textline " " bitfld.long 0x00 6. " DISABLE_READ_HDCP_FW_SRK ,Disable read HDMI FW_SRK" "No,Yes" bitfld.long 0x00 5. " DISABLE_READ_HDCP_GROUP_MASK ,Disable read GROUP MASK" "No,Yes" textline " " bitfld.long 0x00 4. " JTAG_BLOCK_RELEASE ,JTAG block release" "Blocked,Released" bitfld.long 0x00 3. " BLOCK_ROM_PART ,Block ROM part" "Not hidden,Hidden" textline " " bitfld.long 0x00 2. " FIELD_RETURN_LOCK ,Field return lock bit" "Unlocked,Locked" bitfld.long 0x00 1. " SRK_REVOKE_LOCK ,SRK revoke lock bit" "Unlocked,Locked" group.long 0x5C++0x03 line.long 0x00 "SW_STICKY3,Sticky bit Register" bitfld.long 0x00 10. " DISABLE_READ_HDCP_DEVICE_KEY ,Disable read HDCP DEVICE HDCP" "No,Yes" bitfld.long 0x00 9. " DISABLE_READ_HDCP_TX_CERT ,Disable read HDCP TX CERT" "No,Yes" textline " " bitfld.long 0x00 8. " DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT ,Disable read HDCP TX GLOBAL CONSTANT" "No,Yes" bitfld.long 0x00 7. " DISABLE_READ_HDCP_KMEK ,Disable read HDMI KMEK" "No,Yes" textline " " bitfld.long 0x00 6. " DISABLE_READ_HDCP_FW_SRK ,Disable read HDMI FW_SRK" "No,Yes" bitfld.long 0x00 5. " DISABLE_READ_HDCP_GROUP_MASK ,Disable read GROUP MASK" "No,Yes" textline " " bitfld.long 0x00 4. " JTAG_BLOCK_RELEASE ,JTAG block release" "Blocked,Released" bitfld.long 0x00 3. " BLOCK_ROM_PART ,Block ROM part" "Not hidden,Hidden" textline " " bitfld.long 0x00 2. " FIELD_RETURN_LOCK ,Field return lock bit" "Unlocked,Locked" bitfld.long 0x00 1. " SRK_REVOKE_LOCK ,SRK revoke lock bit" "Unlocked,Locked" if (((per.l(ad:0x30350000+0x60))&0x80000000)==0x00) group.long 0x60++0x03 line.long 0x00 "SCS,Software Controllable Signals Register" bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked" hexmask.long 0x00 1.--30. 1. " SPARE ,SPARE" textline " " bitfld.long 0x00 0. " HAB_JDE ,HAB JTAG debug enable" "Disabled,Enabled" else rgroup.long 0x60++0x03 line.long 0x00 "SCS,Software Controllable Signals Register" bitfld.long 0x00 31. " LOCK ,Write lock" "Not locked,Locked" hexmask.long 0x00 1.--30. 1. " SPARE ,SPARE" textline " " bitfld.long 0x00 0. " HAB_JDE ,HAB JTAG debug enable" "Disabled,Enabled" endif if (((per.l(ad:0x30350000+0x64))&0x80000000)==0x00) group.long 0x64++0x03 line.long 0x00 "SCS_SET,Software Controllable Signals SET Register" bitfld.long 0x00 31. " LOCK ,Write lock" "Unlocked,Locked" hexmask.long 0x00 1.--30. 1. " SPARE ,SPARE" textline " " bitfld.long 0x00 0. " HAB_JDE ,HAB JTAG debug enable" "Disabled,Enabled" else rgroup.long 0x64++0x03 line.long 0x00 "SCS_SET,Software Controllable Signals SET Register" bitfld.long 0x00 31. " LOCK ,Write lock" "Unlocked,Locked" hexmask.long 0x00 1.--30. 1. " SPARE ,SPARE" textline " " bitfld.long 0x00 0. " HAB_JDE ,HAB JTAG debug enable" "Disabled,Enabled" endif if (((per.l(ad:0x30350000+0x68))&0x80000000)==0x00) group.long 0x68++0x03 line.long 0x00 "SCS_CLR,Software Controllable Signals CLR Register" bitfld.long 0x00 31. " LOCK ,Write lock" "Unlocked,Locked" hexmask.long 0x00 1.--30. 1. " SPARE ,SPARE" textline " " bitfld.long 0x00 0. " HAB_JDE ,HAB JTAG debug enable" "Disabled,Enabled" else rgroup.long 0x68++0x03 line.long 0x00 "SCS_CLR,Software Controllable Signals CLR Register" bitfld.long 0x00 31. " LOCK ,Write lock" "Unlocked,Locked" hexmask.long 0x00 1.--30. 1. " SPARE ,SPARE" textline " " bitfld.long 0x00 0. " HAB_JDE ,HAB JTAG debug enable" "Disabled,Enabled" endif if (((per.l(ad:0x30350000+0x6C))&0x80000000)==0x00) group.long 0x6C++0x03 line.long 0x00 "SCS_TGL,Software Controllable Signals TOGGLE Register" bitfld.long 0x00 31. " LOCK ,Write lock" "Unlocked,Locked" hexmask.long 0x00 1.--30. 1. " SPARE ,SPARE" textline " " bitfld.long 0x00 0. " HAB_JDE ,HAB JTAG debug enable" "No effect,Toggle" else rgroup.long 0x6C++0x03 line.long 0x00 "SCS_TGL,Software Controllable Signals TOGGLE Register" bitfld.long 0x00 31. " LOCK ,Write lock" "Unlocked,Locked" hexmask.long 0x00 1.--30. 1. " SPARE ,SPARE" textline " " bitfld.long 0x00 0. " HAB_JDE ,HAB JTAG debug enable" "No effect,Toggle" endif rgroup.long 0x90++0x0F line.long 0x00 "VERSION,OTP Controller Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Stepping of the RTL version" line.long 0x04 "VERSION_SET,OTP Controller Version Register" hexmask.long.byte 0x04 24.--31. 1. " MAJOR ,MAJOR field of the RTL version" hexmask.long.byte 0x04 16.--23. 1. " MINOR ,MINOR field of the RTL version" textline " " hexmask.long.word 0x04 0.--15. 1. " STEP ,Stepping of the RTL version" line.long 0x08 "VERSION_CLR,OTP Controller Version Register" hexmask.long.byte 0x08 24.--31. 1. " MAJOR ,MAJOR field of the RTL version" hexmask.long.byte 0x08 16.--23. 1. " MINOR ,MINOR field of the RTL version" textline " " hexmask.long.word 0x08 0.--15. 1. " STEP ,Stepping of the RTL version" line.long 0x0C "VERSION_TOG,OTP Controller Version Register" hexmask.long.byte 0x0C 24.--31. 1. " MAJOR ,MAJOR field of the RTL version" hexmask.long.byte 0x0C 16.--23. 1. " MINOR ,MINOR field of the RTL version" textline " " hexmask.long.word 0x0C 0.--15. 1. " STEP ,Stepping of the RTL version" rgroup.long 0x400++0x0F line.long 0x00 "LOCK,Value of OTP Bank0 Word0 (Lock controls)" bitfld.long 0x00 31. " HDCP_CRC[1] ,HDCP CRC bit 1" "Not blocked,Blocked" bitfld.long 0x00 30. " HDCP_CRC[0] ,HDCP CRC bit 0" "Not blocked,Blocked" textline " " bitfld.long 0x00 29. " HDCP_KEY[1] ,HDCP KEY bit 1" "Not blocked,Blocked" bitfld.long 0x00 28. " HDCP_KEY[0] ,HDCP KEY bit 0" "Not blocked,Blocked" textline " " bitfld.long 0x00 27. " HDMI_CRC[1] ,HDMI CRC bit 1" "Not blocked,Blocked" bitfld.long 0x00 26. " HDMI_CRC[0] ,HDMI CRC bit 0" "Not blocked,Blocked" textline " " bitfld.long 0x00 25. " HDMI_KEY[1] ,HDMI KEY bit 1" "Not blocked,Blocked" bitfld.long 0x00 24. " HDMI_KEY[0] ,HDMI KEY bit 0" "Not blocked,Blocked" textline " " bitfld.long 0x00 23. " GP2[1] ,GP2 bit 1" "Not blocked,Blocked" bitfld.long 0x00 22. " GP2[0] ,GP2 bit 0" "Not blocked,Blocked" textline " " bitfld.long 0x00 21. " GP1[1] ,GP1 bit 1" "Not blocked,Blocked" bitfld.long 0x00 20. " GP1[0] ,GP1 bit 0" "Not blocked,Blocked" textline " " bitfld.long 0x00 19. " GP_CRC[1] ,GP CRC bit 1" "Not blocked,Blocked" bitfld.long 0x00 18. " GP_CRC[0] ,GP CRC bit 0" "Not blocked,Blocked" textline " " bitfld.long 0x00 17. " ROM_PATCH ,ROM patch" "Not blocked,Blocked" bitfld.long 0x00 16. " MAU_KEY ,MAU KEY" "Not blocked,Blocked" textline " " bitfld.long 0x00 15. " MAC_ADDR[1] ,MAC ADDR bit 1" "Not blocked,Blocked" bitfld.long 0x00 14. " MAC_ADDR[0] ,MAC ADDR bit 0" "Not blocked,Blocked" textline " " bitfld.long 0x00 13. " USB_ID[1] ,USB_ID bit 1" "Not blocked,Blocked" bitfld.long 0x00 12. " USB_ID[0] ,USB_ID bit 0" "Not blocked,Blocked" textline " " bitfld.long 0x00 11. " MAU_KEY ,MAU KEY" "Not blocked,Blocked" bitfld.long 0x00 10. " SJC_RESP ,SJC RESP" "Not blocked,Blocked" textline " " bitfld.long 0x00 9. " SRK ,SRK" "Not blocked,Blocked" bitfld.long 0x00 8. " OPTMK ,OTPMK" "Not blocked,Blocked" textline " " bitfld.long 0x00 7. " ANALOG[1] ,Analog bit 1" "Not blocked,Blocked" bitfld.long 0x00 6. " ANALOG[0] ,Analog bit 0" "Not blocked,Blocked" textline " " bitfld.long 0x00 5. " MEM_TRIM[1] ,MEM TRIM bit 1" "Not blocked,Blocked" bitfld.long 0x00 4. " MEM_TRIM[0] ,MEM TRIM bit 0" "Not blocked,Blocked" textline " " bitfld.long 0x00 3. " BOOT_CFG[1] ,BOOT CFG bit 1" "Not blocked,Blocked" bitfld.long 0x00 2. " BOOT_CFG[0] ,BOOT CFG bit 0" "Not blocked,Blocked" textline " " bitfld.long 0x00 1. " TESTER[1] ,TESTER bit 1" "Not blocked,Blocked" bitfld.long 0x00 0. " TESTER[0] ,TESTER bit 0" "Not blocked,Blocked" if (((per.l(ad:0x30350000+0x400))&0x2)==0x00) group.long 0x410++0x0F line.long 0x00 "TESTER0,Value of OTP Bank0 Word1 Register" line.long 0x04 "TESTER0_SET,Value of OTP Bank0 Word1 Register" line.long 0x08 "TESTER0_CLR,Value of OTP Bank0 Word1 Register" line.long 0x0C "TESTER0_TOG,Value of OTP Bank0 Word1 Register" else rgroup.long 0x410++0x0F line.long 0x00 "TESTER0,Value of OTP Bank0 Word1 Register" line.long 0x04 "TESTER0_SET,Value of OTP Bank0 Word1 Register" line.long 0x08 "TESTER0_CLR,Value of OTP Bank0 Word1 Register" line.long 0x0C "TESTER0_TOG,Value of OTP Bank0 Word1 Register" endif if (((per.l(ad:0x30350000+0x400))&0x2)==0x00) group.long 0x420++0x0F line.long 0x00 "TESTER1,Value of OTP Bank0 Word2 Register" line.long 0x04 "TESTER1_SET,Value of OTP Bank0 Word2 Register" line.long 0x08 "TESTER1_CLR,Value of OTP Bank0 Word2 Register" line.long 0x0C "TESTER1_TOG,Value of OTP Bank0 Word2 Register" else rgroup.long 0x420++0x0F line.long 0x00 "TESTER1,Value of OTP Bank0 Word2 Register" line.long 0x04 "TESTER1_SET,Value of OTP Bank0 Word2 Register" line.long 0x08 "TESTER1_CLR,Value of OTP Bank0 Word2 Register" line.long 0x0C "TESTER1_TOG,Value of OTP Bank0 Word2 Register" endif if (((per.l(ad:0x30350000+0x400))&0x2)==0x00) group.long 0x430++0x0F line.long 0x00 "TESTER2,Value of OTP Bank0 Word3 Register" line.long 0x04 "TESTER2_SET,Value of OTP Bank0 Word3 Register" line.long 0x08 "TESTER2_CLR,Value of OTP Bank0 Word3 Register" line.long 0x0C "TESTER2_TOG,Value of OTP Bank0 Word3 Register" else rgroup.long 0x430++0x0F line.long 0x00 "TESTER2,Value of OTP Bank0 Word3 Register" line.long 0x04 "TESTER2_SET,Value of OTP Bank0 Word3 Register" line.long 0x08 "TESTER2_CLR,Value of OTP Bank0 Word3 Register" line.long 0x0C "TESTER2_TOG,Value of OTP Bank0 Word3 Register" endif if (((per.l(ad:0x30350000+0x400))&0x2)==0x00) group.long 0x440++0x0F line.long 0x00 "TESTER3,Value of OTP Bank1 Word0 Register" line.long 0x04 "TESTER3_SET,Value of OTP Bank1 Word0 Register" line.long 0x08 "TESTER3_CLR,Value of OTP Bank1 Word0 Register" line.long 0x0C "TESTER3_TOG,Value of OTP Bank1 Word0 Register" else rgroup.long 0x440++0x0F line.long 0x00 "TESTER3,Value of OTP Bank1 Word0 Register" line.long 0x04 "TESTER3_SET,Value of OTP Bank1 Word0 Register" line.long 0x08 "TESTER3_CLR,Value of OTP Bank1 Word0 Register" line.long 0x0C "TESTER3_TOG,Value of OTP Bank1 Word0 Register" endif if (((per.l(ad:0x30350000+0x400))&0x2)==0x00) group.long 0x450++0x0F line.long 0x00 "TESTER4,Value of OTP Bank1 Word1 Register" line.long 0x04 "TESTER4_SET,Value of OTP Bank1 Word1 Register" line.long 0x08 "TESTER4_CLR,Value of OTP Bank1 Word1 Register" line.long 0x0C "TESTER4_TOG,Value of OTP Bank1 Word1 Register" else rgroup.long 0x450++0x0F line.long 0x00 "TESTER4,Value of OTP Bank1 Word1 Register" line.long 0x04 "TESTER4_SET,Value of OTP Bank1 Word1 Register" line.long 0x08 "TESTER4_CLR,Value of OTP Bank1 Word1 Register" line.long 0x0C "TESTER4_TOG,Value of OTP Bank1 Word1 Register" endif if (((per.l(ad:0x30350000+0x400))&0x2)==0x00) group.long 0x460++0x0F line.long 0x00 "TESTER5,Value of OTP Bank1 Word2 Register" line.long 0x04 "TESTER5_SET,Value of OTP Bank1 Word2 Register" line.long 0x08 "TESTER5_CLR,Value of OTP Bank1 Word2 Register" line.long 0x0C "TESTER5_TOG,Value of OTP Bank1 Word2 Register" else rgroup.long 0x460++0x0F line.long 0x00 "TESTER5,Value of OTP Bank1 Word2 Register" line.long 0x04 "TESTER5_SET,Value of OTP Bank1 Word2 Register" line.long 0x08 "TESTER5_CLR,Value of OTP Bank1 Word2 Register" line.long 0x0C "TESTER5_TOG,Value of OTP Bank1 Word2 Register" endif if (((per.l(ad:0x30350000+0x400))&0x8)==0x00) group.long 0x470++0x0F line.long 0x00 "BOOT_CFG0,Value of OTP Bank1 Word3 Register" line.long 0x04 "BOOT_CFG0_SET,Value of OTP Bank1 Word3 Register" line.long 0x08 "BOOT_CFG0_CLR,Value of OTP Bank1 Word3 Register" line.long 0x0C "BOOT_CFG0_TOG,Value of OTP Bank1 Word3 Register" else rgroup.long 0x470++0x0F line.long 0x00 "BOOT_CFG0,Value of OTP Bank1 Word3 Register" line.long 0x04 "BOOT_CFG0_SET,Value of OTP Bank1 Word3 Register" line.long 0x08 "BOOT_CFG0_CLR,Value of OTP Bank1 Word3 Register" line.long 0x0C "BOOT_CFG0_TOG,Value of OTP Bank1 Word3 Register" endif if (((per.l(ad:0x30350000+0x400))&0x8)==0x00) group.long 0x480++0x0F line.long 0x00 "BOOT_CFG1,Value of OTP Bank2 Word0 Register" line.long 0x04 "BOOT_CFG1_SET,Value of OTP Bank2 Word0 Register" line.long 0x08 "BOOT_CFG1_CLR,Value of OTP Bank2 Word0 Register" line.long 0x0C "BOOT_CFG1_TOG,Value of OTP Bank2 Word0 Register" else rgroup.long 0x480++0x0F line.long 0x00 "BOOT_CFG1,Value of OTP Bank2 Word0 Register" line.long 0x04 "BOOT_CFG1_SET,Value of OTP Bank2 Word0 Register" line.long 0x08 "BOOT_CFG1_CLR,Value of OTP Bank2 Word0 Register" line.long 0x0C "BOOT_CFG1_TOG,Value of OTP Bank2 Word0 Register" endif if (((per.l(ad:0x30350000+0x400))&0x8)==0x00) group.long 0x490++0x0F line.long 0x00 "BOOT_CFG2,Value of OTP Bank2 Word1 Register" line.long 0x04 "BOOT_CFG2_SET,Value of OTP Bank2 Word1 Register" line.long 0x08 "BOOT_CFG2_CLR,Value of OTP Bank2 Word1 Register" line.long 0x0C "BOOT_CFG2_TOG,Value of OTP Bank2 Word1 Register" else rgroup.long 0x490++0x0F line.long 0x00 "BOOT_CFG2,Value of OTP Bank2 Word1 Register" line.long 0x04 "BOOT_CFG2_SET,Value of OTP Bank2 Word1 Register" line.long 0x08 "BOOT_CFG2_CLR,Value of OTP Bank2 Word1 Register" line.long 0x0C "BOOT_CFG2_TOG,Value of OTP Bank2 Word1 Register" endif if (((per.l(ad:0x30350000+0x400))&0x8)==0x00) group.long 0x4A0++0x0F line.long 0x00 "BOOT_CFG3,Value of OTP Bank2 Word2 Register" line.long 0x04 "BOOT_CFG3_SET,Value of OTP Bank2 Word2 Register" line.long 0x08 "BOOT_CFG3_CLR,Value of OTP Bank2 Word2 Register" line.long 0x0C "BOOT_CFG3_TOG,Value of OTP Bank2 Word2 Register" else rgroup.long 0x4A0++0x0F line.long 0x00 "BOOT_CFG3,Value of OTP Bank2 Word2 Register" line.long 0x04 "BOOT_CFG3_SET,Value of OTP Bank2 Word2 Register" line.long 0x08 "BOOT_CFG3_CLR,Value of OTP Bank2 Word2 Register" line.long 0x0C "BOOT_CFG3_TOG,Value of OTP Bank2 Word2 Register" endif if (((per.l(ad:0x30350000+0x400))&0x8)==0x00) group.long 0x4B0++0x0F line.long 0x00 "BOOT_CFG4,Value of OTP Bank2 Word3 Register" line.long 0x04 "BOOT_CFG4_SET,Value of OTP Bank2 Word3 Register" line.long 0x08 "BOOT_CFG4_CLR,Value of OTP Bank2 Word3 Register" line.long 0x0C "BOOT_CFG4_TOG,Value of OTP Bank2 Word3 Register" else rgroup.long 0x4B0++0x0F line.long 0x00 "BOOT_CFG4,Value of OTP Bank2 Word3 Register" line.long 0x04 "BOOT_CFG4_SET,Value of OTP Bank2 Word3 Register" line.long 0x08 "BOOT_CFG4_CLR,Value of OTP Bank2 Word3 Register" line.long 0x0C "BOOT_CFG4_TOG,Value of OTP Bank2 Word3 Register" endif if (((per.l(ad:0x30350000+0x400))&0x20)==0x00) group.long 0x4C0++0x0F line.long 0x00 "MEM_TRIM0,Value of OTP Bank3 Word0 Register" line.long 0x04 "MEM_TRIM0_SET,Value of OTP Bank3 Word0 Register" line.long 0x08 "MEM_TRIM0_CLR,Value of OTP Bank3 Word0 Register" line.long 0x0C "MEM_TRIM0_TOG,Value of OTP Bank3 Word0 Register" else rgroup.long 0x4C0++0x0F line.long 0x00 "MEM_TRIM0,Value of OTP Bank3 Word0 Register" line.long 0x04 "MEM_TRIM0_SET,Value of OTP Bank3 Word0 Register" line.long 0x08 "MEM_TRIM0_CLR,Value of OTP Bank3 Word0 Register" line.long 0x0C "MEM_TRIM0_TOG,Value of OTP Bank3 Word0 Register" endif if (((per.l(ad:0x30350000+0x400))&0x20)==0x00) group.long 0x4D0++0x0F line.long 0x00 "MEM_TRIM1,Value of OTP Bank3 Word1 Register" line.long 0x04 "MEM_TRIM1_SET,Value of OTP Bank3 Word1 Register" line.long 0x08 "MEM_TRIM1_CLR,Value of OTP Bank3 Word1 Register" line.long 0x0C "MEM_TRIM1_TOG,Value of OTP Bank3 Word1 Register" else rgroup.long 0x4D0++0x0F line.long 0x00 "MEM_TRIM1,Value of OTP Bank3 Word1 Register" line.long 0x04 "MEM_TRIM1_SET,Value of OTP Bank3 Word1 Register" line.long 0x08 "MEM_TRIM1_CLR,Value of OTP Bank3 Word1 Register" line.long 0x0C "MEM_TRIM1_TOG,Value of OTP Bank3 Word1 Register" endif if (((per.l(ad:0x30350000+0x400))&0x40)==0x00) group.long 0x4E0++0x0F line.long 0x00 "ANA0,Value of OTP Bank3 Word0 Register" line.long 0x04 "ANA0_SET,Value of OTP Bank3 Word0 Register" line.long 0x08 "ANA0_CLR,Value of OTP Bank3 Word0 Register" line.long 0x0C "ANA0_TOG,Value of OTP Bank3 Word0 Register" else rgroup.long 0x4E0++0x0F line.long 0x00 "ANA0,Value of OTP Bank3 Word0 Register" line.long 0x04 "ANA0_SET,Value of OTP Bank3 Word0 Register" line.long 0x08 "ANA0_CLR,Value of OTP Bank3 Word0 Register" line.long 0x0C "ANA0_TOG,Value of OTP Bank3 Word0 Register" endif if (((per.l(ad:0x30350000+0x400))&0x40)==0x00) group.long 0x4F0++0x0F line.long 0x00 "ANA1,Value of OTP Bank3 Word1 Register" line.long 0x04 "ANA1_SET,Value of OTP Bank3 Word1 Register" line.long 0x08 "ANA1_CLR,Value of OTP Bank3 Word1 Register" line.long 0x0C "ANA1_TOG,Value of OTP Bank3 Word1 Register" else rgroup.long 0x4F0++0x0F line.long 0x00 "ANA1,Value of OTP Bank3 Word1 Register" line.long 0x04 "ANA1_SET,Value of OTP Bank3 Word1 Register" line.long 0x08 "ANA1_CLR,Value of OTP Bank3 Word1 Register" line.long 0x0C "ANA1_TOG,Value of OTP Bank3 Word1 Register" endif if (((per.l(ad:0x30350000+0x400))&0x40)==0x00) group.long 0x470++0x0F line.long 0x00 "SRK0,Shadow Register for OTP Bank6 Word0 (SRK Hash)" line.long 0x04 "SRK0_SET,Shadow Register for OTP Bank6 Word0 (SRK Hash)" line.long 0x08 "SRK0_CLR,Shadow Register for OTP Bank6 Word0 (SRK Hash)" line.long 0x0C "SRK0_TOG,Shadow Register for OTP Bank6 Word0 (SRK Hash)" else rgroup.long 0x470++0x0F line.long 0x00 "SRK0,Shadow Register for OTP Bank6 Word0 (SRK Hash)" line.long 0x04 "SRK0_SET,Shadow Register for OTP Bank6 Word0 (SRK Hash)" line.long 0x08 "SRK0_CLR,Shadow Register for OTP Bank6 Word0 (SRK Hash)" line.long 0x0C "SRK0_TOG,Shadow Register for OTP Bank6 Word0 (SRK Hash)" endif if (((per.l(ad:0x30350000+0x400))&0x40)==0x00) group.long 0x480++0x0F line.long 0x00 "SRK1,Shadow Register for OTP Bank6 Word1 (SRK Hash)" line.long 0x04 "SRK1_SET,Shadow Register for OTP Bank6 Word1 (SRK Hash)" line.long 0x08 "SRK1_CLR,Shadow Register for OTP Bank6 Word1 (SRK Hash)" line.long 0x0C "SRK1_TOG,Shadow Register for OTP Bank6 Word1 (SRK Hash)" else rgroup.long 0x480++0x0F line.long 0x00 "SRK1,Shadow Register for OTP Bank6 Word1 (SRK Hash)" line.long 0x04 "SRK1_SET,Shadow Register for OTP Bank6 Word1 (SRK Hash)" line.long 0x08 "SRK1_CLR,Shadow Register for OTP Bank6 Word1 (SRK Hash)" line.long 0x0C "SRK1_TOG,Shadow Register for OTP Bank6 Word1 (SRK Hash)" endif if (((per.l(ad:0x30350000+0x400))&0x40)==0x00) group.long 0x490++0x0F line.long 0x00 "SRK2,Shadow Register for OTP Bank6 Word2 (SRK Hash)" line.long 0x04 "SRK2_SET,Shadow Register for OTP Bank6 Word2 (SRK Hash)" line.long 0x08 "SRK2_CLR,Shadow Register for OTP Bank6 Word2 (SRK Hash)" line.long 0x0C "SRK2_TOG,Shadow Register for OTP Bank6 Word2 (SRK Hash)" else rgroup.long 0x490++0x0F line.long 0x00 "SRK2,Shadow Register for OTP Bank6 Word2 (SRK Hash)" line.long 0x04 "SRK2_SET,Shadow Register for OTP Bank6 Word2 (SRK Hash)" line.long 0x08 "SRK2_CLR,Shadow Register for OTP Bank6 Word2 (SRK Hash)" line.long 0x0C "SRK2_TOG,Shadow Register for OTP Bank6 Word2 (SRK Hash)" endif if (((per.l(ad:0x30350000+0x400))&0x40)==0x00) group.long 0x4A0++0x0F line.long 0x00 "SRK3,Shadow Register for OTP Bank6 Word3 (SRK Hash)" line.long 0x04 "SRK3_SET,Shadow Register for OTP Bank6 Word3 (SRK Hash)" line.long 0x08 "SRK3_CLR,Shadow Register for OTP Bank6 Word3 (SRK Hash)" line.long 0x0C "SRK3_TOG,Shadow Register for OTP Bank6 Word3 (SRK Hash)" else rgroup.long 0x4A0++0x0F line.long 0x00 "SRK3,Shadow Register for OTP Bank6 Word3 (SRK Hash)" line.long 0x04 "SRK3_SET,Shadow Register for OTP Bank6 Word3 (SRK Hash)" line.long 0x08 "SRK3_CLR,Shadow Register for OTP Bank6 Word3 (SRK Hash)" line.long 0x0C "SRK3_TOG,Shadow Register for OTP Bank6 Word3 (SRK Hash)" endif if (((per.l(ad:0x30350000+0x400))&0x40)==0x00) group.long 0x4B0++0x0F line.long 0x00 "SRK4,Shadow Register for OTP Bank7 Word0 (SRK Hash)" line.long 0x04 "SRK4_SET,Shadow Register for OTP Bank7 Word0 (SRK Hash)" line.long 0x08 "SRK4_CLR,Shadow Register for OTP Bank7 Word0 (SRK Hash)" line.long 0x0C "SRK4_TOG,Shadow Register for OTP Bank7 Word0 (SRK Hash)" else rgroup.long 0x4B0++0x0F line.long 0x00 "SRK4,Shadow Register for OTP Bank7 Word0 (SRK Hash)" line.long 0x04 "SRK4_SET,Shadow Register for OTP Bank7 Word0 (SRK Hash)" line.long 0x08 "SRK4_CLR,Shadow Register for OTP Bank7 Word0 (SRK Hash)" line.long 0x0C "SRK4_TOG,Shadow Register for OTP Bank7 Word0 (SRK Hash)" endif if (((per.l(ad:0x30350000+0x400))&0x40)==0x00) group.long 0x4C0++0x0F line.long 0x00 "SRK5,Shadow Register for OTP Bank7 Word1 (SRK Hash)" line.long 0x04 "SRK5_SET,Shadow Register for OTP Bank7 Word1 (SRK Hash)" line.long 0x08 "SRK5_CLR,Shadow Register for OTP Bank7 Word1 (SRK Hash)" line.long 0x0C "SRK5_TOG,Shadow Register for OTP Bank7 Word1 (SRK Hash)" else rgroup.long 0x4C0++0x0F line.long 0x00 "SRK5,Shadow Register for OTP Bank7 Word1 (SRK Hash)" line.long 0x04 "SRK5_SET,Shadow Register for OTP Bank7 Word1 (SRK Hash)" line.long 0x08 "SRK5_CLR,Shadow Register for OTP Bank7 Word1 (SRK Hash)" line.long 0x0C "SRK5_TOG,Shadow Register for OTP Bank7 Word1 (SRK Hash)" endif if (((per.l(ad:0x30350000+0x400))&0x40)==0x00) group.long 0x4D0++0x0F line.long 0x00 "SRK6,Shadow Register for OTP Bank7 Word2 (SRK Hash)" line.long 0x04 "SRK6_SET,Shadow Register for OTP Bank7 Word2 (SRK Hash)" line.long 0x08 "SRK6_CLR,Shadow Register for OTP Bank7 Word2 (SRK Hash)" line.long 0x0C "SRK6_TOG,Shadow Register for OTP Bank7 Word2 (SRK Hash)" else rgroup.long 0x4D0++0x0F line.long 0x00 "SRK6,Shadow Register for OTP Bank7 Word2 (SRK Hash)" line.long 0x04 "SRK6_SET,Shadow Register for OTP Bank7 Word2 (SRK Hash)" line.long 0x08 "SRK6_CLR,Shadow Register for OTP Bank7 Word2 (SRK Hash)" line.long 0x0C "SRK6_TOG,Shadow Register for OTP Bank7 Word2 (SRK Hash)" endif if (((per.l(ad:0x30350000+0x400))&0x40)==0x00) group.long 0x4E0++0x0F line.long 0x00 "SRK7,Shadow Register for OTP Bank7 Word3 (SRK Hash)" line.long 0x04 "SRK7_SET,Shadow Register for OTP Bank7 Word3 (SRK Hash)" line.long 0x08 "SRK7_CLR,Shadow Register for OTP Bank7 Word3 (SRK Hash)" line.long 0x0C "SRK7_TOG,Shadow Register for OTP Bank7 Word3 (SRK Hash)" else rgroup.long 0x4E0++0x0F line.long 0x00 "SRK7,Shadow Register for OTP Bank7 Word3 (SRK Hash)" line.long 0x04 "SRK7_SET,Shadow Register for OTP Bank7 Word3 (SRK Hash)" line.long 0x08 "SRK7_CLR,Shadow Register for OTP Bank7 Word3 (SRK Hash)" line.long 0x0C "SRK7_TOG,Shadow Register for OTP Bank7 Word3 (SRK Hash)" endif if (((per.l(ad:0x30350000+0x400))&0x200)==0x00) group.long 0x600++0x0F line.long 0x00 "SJC_RESP0,Value of OTP Bank8 Word0 (Secure JTAG Response Field)" line.long 0x04 "SJC_RESP0_SET,Value of OTP Bank8 Word0 (Secure JTAG Response Field)" line.long 0x08 "SJC_RESP0_CLR,Value of OTP Bank8 Word0 (Secure JTAG Response Field)" line.long 0x0C "SJC_RESP0_TOG,Value of OTP Bank8 Word0 (Secure JTAG Response Field)" else rgroup.long 0x600++0x0F line.long 0x00 "SJC_RESP0,Value of OTP Bank8 Word0 (Secure JTAG Response Field)" line.long 0x04 "SJC_RESP0_SET,Value of OTP Bank8 Word0 (Secure JTAG Response Field)" line.long 0x08 "SJC_RESP0_CLR,Value of OTP Bank8 Word0 (Secure JTAG Response Field)" line.long 0x0C "SJC_RESP0_TOG,Value of OTP Bank8 Word0 (Secure JTAG Response Field)" endif if (((per.l(ad:0x30350000+0x400))&0x200)==0x00) group.long 0x610++0x0F line.long 0x00 "SJC_RESP1,Value of OTP Bank8 Word1 (Secure JTAG Response Field)" line.long 0x04 "SJC_RESP1_SET,Value of OTP Bank8 Word1 (Secure JTAG Response Field)" line.long 0x08 "SJC_RESP1_CLR,Value of OTP Bank8 Word1 (Secure JTAG Response Field)" line.long 0x0C "SJC_RESP1_TOG,Value of OTP Bank8 Word1 (Secure JTAG Response Field)" else rgroup.long 0x610++0x0F line.long 0x00 "SJC_RESP1,Value of OTP Bank8 Word1 (Secure JTAG Response Field)" line.long 0x04 "SJC_RESP1_SET,Value of OTP Bank8 Word1 (Secure JTAG Response Field)" line.long 0x08 "SJC_RESP1_CLR,Value of OTP Bank8 Word1 (Secure JTAG Response Field)" line.long 0x0C "SJC_RESP1_TOG,Value of OTP Bank8 Word1 (Secure JTAG Response Field)" endif group.long 0x620++0x0F line.long 0x00 "USB_ID,Value of OTP Bank8 Word2 (USB ID info)" line.long 0x04 "USB_ID_SET,Value of OTP Bank8 Word2 (USB ID info)" line.long 0x08 "USB_ID_CLR,Value of OTP Bank8 Word2 (USB ID info)" line.long 0x0C "USB_ID_TOG,Value of OTP Bank8 Word2 (USB ID info)" group.long 0x630++0x0F line.long 0x00 "FIELD_RETURN,Value of OTP Bank8 Word3 (FIELD Return)" line.long 0x04 "FIELD_RETURN_SET,Value of OTP Bank8 Word3 (FIELD Return)" line.long 0x08 "FIELD_RETURN_CLR,Value of OTP Bank8 Word3 (FIELD Return)" line.long 0x0C "FIELD_RETURN_TOG,Value of OTP Bank8 Word3 (FIELD Return)" group.long 0x640++0x0F line.long 0x00 "MAC_ADDR0,Value of OTP Bank9 Word0 (MAC Address)" line.long 0x04 "MAC_ADDR0_SET,Value of OTP Bank9 Word0 (MAC Address)" line.long 0x08 "MAC_ADDR0_CLR,Value of OTP Bank9 Word0 (MAC Address)" line.long 0x0C "MAC_ADDR0_TOG,Value of OTP Bank9 Word0 (MAC Address)" group.long 0x650++0x0F line.long 0x00 "MAC_ADDR1,Value of OTP Bank9 Word1 (MAC Address)" line.long 0x04 "MAC_ADDR1_SET,Value of OTP Bank9 Word1 (MAC Address)" line.long 0x08 "MAC_ADDR1_CLR,Value of OTP Bank9 Word1 (MAC Address)" line.long 0x0C "MAC_ADDR1_TOG,Value of OTP Bank9 Word1 (MAC Address)" group.long 0x660++0x0F line.long 0x00 "MAC_ADDR2,Value of OTP Bank9 Word2 (MAC Address)" line.long 0x04 "MAC_ADDR2_SET,Value of OTP Bank9 Word2 (MAC Address)" line.long 0x08 "MAC_ADDR2_CLR,Value of OTP Bank9 Word2 (MAC Address)" line.long 0x0C "MAC_ADDR2_TOG,Value of OTP Bank9 Word2 (MAC Address)" group.long 0x670++0x0F line.long 0x00 "SRK_REVOKE,Value of OTP Bank9 Word3 (SRK Revoke)" line.long 0x04 "SRK_REVOKE_SET,Value of OTP Bank9 Word3 (SRK Revoke)" line.long 0x08 "SRK_REVOKE_CLR,Value of OTP Bank9 Word3 (SRK Revoke)" line.long 0x0C "SRK_REVOKE_TOG,Value of OTP Bank9 Word3 (SRK Revoke)" if (((per.l(ad:0x30350000+0x400))&0x400)==0x00) group.long 0x680++0x0F line.long 0x00 "MAU_KEY0,Value of OTP Bank10 Word0 (MAU Key)" line.long 0x04 "MAU_KEY0_SET,Value of OTP Bank10 Word0 (MAU Key)" line.long 0x08 "MAU_KEY0_CLR,Value of OTP Bank10 Word0 (MAU Key)" line.long 0x0C "MAU_KEY0_TOG,Value of OTP Bank10 Word0 (MAU Key)" else rgroup.long 0x680++0x0F line.long 0x00 "MAU_KEY0,Value of OTP Bank10 Word0 (MAU Key)" line.long 0x04 "MAU_KEY0_SET,Value of OTP Bank10 Word0 (MAU Key)" line.long 0x08 "MAU_KEY0_CLR,Value of OTP Bank10 Word0 (MAU Key)" line.long 0x0C "MAU_KEY0_TOG,Value of OTP Bank10 Word0 (MAU Key)" endif if (((per.l(ad:0x30350000+0x400))&0x400)==0x00) group.long 0x690++0x0F line.long 0x00 "MAU_KEY1,Value of OTP Bank10 Word1 (MAU Key)" line.long 0x04 "MAU_KEY1_SET,Value of OTP Bank10 Word1 (MAU Key)" line.long 0x08 "MAU_KEY1_CLR,Value of OTP Bank10 Word1 (MAU Key)" line.long 0x0C "MAU_KEY1_TOG,Value of OTP Bank10 Word1 (MAU Key)" else rgroup.long 0x690++0x0F line.long 0x00 "MAU_KEY1,Value of OTP Bank10 Word1 (MAU Key)" line.long 0x04 "MAU_KEY1_SET,Value of OTP Bank10 Word1 (MAU Key)" line.long 0x08 "MAU_KEY1_CLR,Value of OTP Bank10 Word1 (MAU Key)" line.long 0x0C "MAU_KEY1_TOG,Value of OTP Bank10 Word1 (MAU Key)" endif if (((per.l(ad:0x30350000+0x400))&0x400)==0x00) group.long 0x6A0++0x0F line.long 0x00 "MAU_KEY2,Value of OTP Bank10 Word2 (MAU Key)" line.long 0x04 "MAU_KEY2_SET,Value of OTP Bank10 Word2 (MAU Key)" line.long 0x08 "MAU_KEY2_CLR,Value of OTP Bank10 Word2 (MAU Key)" line.long 0x0C "MAU_KEY2_TOG,Value of OTP Bank10 Word2 (MAU Key)" else rgroup.long 0x6A0++0x0F line.long 0x00 "MAU_KEY2,Value of OTP Bank10 Word2 (MAU Key)" line.long 0x04 "MAU_KEY2_SET,Value of OTP Bank10 Word2 (MAU Key)" line.long 0x08 "MAU_KEY2_CLR,Value of OTP Bank10 Word2 (MAU Key)" line.long 0x0C "MAU_KEY2_TOG,Value of OTP Bank10 Word2 (MAU Key)" endif if (((per.l(ad:0x30350000+0x400))&0x400)==0x00) group.long 0x6B0++0x0F line.long 0x00 "MAU_KEY3,Value of OTP Bank10 Word3 (MAU Key)" line.long 0x04 "MAU_KEY3_SET,Value of OTP Bank10 Word3 (MAU Key)" line.long 0x08 "MAU_KEY3_CLR,Value of OTP Bank10 Word3 (MAU Key)" line.long 0x0C "MAU_KEY3_TOG,Value of OTP Bank10 Word3 (MAU Key)" else rgroup.long 0x6B0++0x0F line.long 0x00 "MAU_KEY3,Value of OTP Bank10 Word3 (MAU Key)" line.long 0x04 "MAU_KEY3_SET,Value of OTP Bank10 Word3 (MAU Key)" line.long 0x08 "MAU_KEY3_CLR,Value of OTP Bank10 Word3 (MAU Key)" line.long 0x0C "MAU_KEY3_TOG,Value of OTP Bank10 Word3 (MAU Key)" endif if (((per.l(ad:0x30350000+0x400))&0x400)==0x00) group.long 0x6C0++0x0F line.long 0x00 "MAU_KEY4,Value of OTP Bank11 Word0 (MAU Key)" line.long 0x04 "MAU_KEY4_SET,Value of OTP Bank11 Word0 (MAU Key)" line.long 0x08 "MAU_KEY4_CLR,Value of OTP Bank11 Word0 (MAU Key)" line.long 0x0C "MAU_KEY4_TOG,Value of OTP Bank11 Word0 (MAU Key)" else rgroup.long 0x6C0++0x0F line.long 0x00 "MAU_KEY4,Value of OTP Bank11 Word0 (MAU Key)" line.long 0x04 "MAU_KEY4_SET,Value of OTP Bank11 Word0 (MAU Key)" line.long 0x08 "MAU_KEY4_CLR,Value of OTP Bank11 Word0 (MAU Key)" line.long 0x0C "MAU_KEY4_TOG,Value of OTP Bank11 Word0 (MAU Key)" endif if (((per.l(ad:0x30350000+0x400))&0x400)==0x00) group.long 0x6D0++0x0F line.long 0x00 "MAU_KEY5,Value of OTP Bank11 Word1 (MAU Key)" line.long 0x04 "MAU_KEY5_SET,Value of OTP Bank11 Word1 (MAU Key)" line.long 0x08 "MAU_KEY5_CLR,Value of OTP Bank11 Word1 (MAU Key)" line.long 0x0C "MAU_KEY5_TOG,Value of OTP Bank11 Word1 (MAU Key)" else rgroup.long 0x6D0++0x0F line.long 0x00 "MAU_KEY5,Value of OTP Bank11 Word1 (MAU Key)" line.long 0x04 "MAU_KEY5_SET,Value of OTP Bank11 Word1 (MAU Key)" line.long 0x08 "MAU_KEY5_CLR,Value of OTP Bank11 Word1 (MAU Key)" line.long 0x0C "MAU_KEY5_TOG,Value of OTP Bank11 Word1 (MAU Key)" endif if (((per.l(ad:0x30350000+0x400))&0x400)==0x00) group.long 0x6E0++0x0F line.long 0x00 "MAU_KEY6,Value of OTP Bank11 Word2 (MAU Key)" line.long 0x04 "MAU_KEY6_SET,Value of OTP Bank11 Word2 (MAU Key)" line.long 0x08 "MAU_KEY6_CLR,Value of OTP Bank11 Word2 (MAU Key)" line.long 0x0C "MAU_KEY6_TOG,Value of OTP Bank11 Word2 (MAU Key)" else rgroup.long 0x6E0++0x0F line.long 0x00 "MAU_KEY6,Value of OTP Bank11 Word2 (MAU Key)" line.long 0x04 "MAU_KEY6_SET,Value of OTP Bank11 Word2 (MAU Key)" line.long 0x08 "MAU_KEY6_CLR,Value of OTP Bank11 Word2 (MAU Key)" line.long 0x0C "MAU_KEY6_TOG,Value of OTP Bank11 Word2 (MAU Key)" endif if (((per.l(ad:0x30350000+0x400))&0x400)==0x00) group.long 0x6F0++0x0F line.long 0x00 "MAU_KEY7,Value of OTP Bank11 Word3 (MAU Key)" line.long 0x04 "MAU_KEY7_SET,Value of OTP Bank11 Word3 (MAU Key)" line.long 0x08 "MAU_KEY7_CLR,Value of OTP Bank11 Word3 (MAU Key)" line.long 0x0C "MAU_KEY7_TOG,Value of OTP Bank11 Word3 (MAU Key)" else rgroup.long 0x6F0++0x0F line.long 0x00 "MAU_KEY7,Value of OTP Bank11 Word3 (MAU Key)" line.long 0x04 "MAU_KEY7_SET,Value of OTP Bank11 Word3 (MAU Key)" line.long 0x08 "MAU_KEY7_CLR,Value of OTP Bank11 Word3 (MAU Key)" line.long 0x0C "MAU_KEY7_TOG,Value of OTP Bank11 Word3 (MAU Key)" endif group.long 0x780++0x0F line.long 0x00 "GP10,Value of OTP Bank14 Word0" line.long 0x04 "GP10_SET,Value of OTP Bank14 Word0" line.long 0x08 "GP10_CLR,Value of OTP Bank14 Word0" line.long 0x0C "GP10_TOG,Value of OTP Bank14 Word0" group.long 0x790++0x0F line.long 0x00 "GP11,Value of OTP Bank14 Word1" line.long 0x04 "GP11_SET,Value of OTP Bank14 Word1" line.long 0x08 "GP11_CLR,Value of OTP Bank14 Word1" line.long 0x0C "GP11_TOG,Value of OTP Bank14 Word1" group.long 0x7A0++0x0F line.long 0x00 "GP20,Value of OTP Bank14 Word2" line.long 0x04 "GP20_SET,Value of OTP Bank14 Word2" line.long 0x08 "GP20_CLR,Value of OTP Bank14 Word2" line.long 0x0C "GP20_TOG,Value of OTP Bank14 Word2" group.long 0x7B0++0x0F line.long 0x00 "GP21,Value of OTP Bank14 Word3" line.long 0x04 "GP21_SET,Value of OTP Bank14 Word3" line.long 0x08 "GP21_CLR,Value of OTP Bank14 Word3" line.long 0x0C "GP21_TOG,Value of OTP Bank14 Word3" group.long 0x7C0++0x0F line.long 0x00 "GP_CRC0,Value of OTP Bank15 Word0 (CRC Key)" line.long 0x04 "GP_CRC0_SET,Value of OTP Bank15 Word0 (CRC Key)" line.long 0x08 "GP_CRC0_CLR,Value of OTP Bank15 Word0 (CRC Key)" line.long 0x0C "GP_CRC0_TOG,Value of OTP Bank15 Word0 (CRC Key)" group.long 0x7D0++0x0F line.long 0x00 "GP_CRC1,Value of OTP Bank15 Word1 (CRC Key)" line.long 0x04 "GP_CRC1_SET,Value of OTP Bank15 Word1 (CRC Key)" line.long 0x08 "GP_CRC1_CLR,Value of OTP Bank15 Word1 (CRC Key)" line.long 0x0C "GP_CRC1_TOG,Value of OTP Bank15 Word1 (CRC Key)" group.long 0x7E0++0x0F line.long 0x00 "GP_CRC2,Value of OTP Bank15 Word2 (CRC Key)" line.long 0x04 "GP_CRC2_SET,Value of OTP Bank15 Word2 (CRC Key)" line.long 0x08 "GP_CRC2_CLR,Value of OTP Bank15 Word2 (CRC Key)" line.long 0x0C "GP_CRC2_TOG,Value of OTP Bank15 Word2 (CRC Key)" group.long 0x7F0++0x0F line.long 0x00 "GROUP_MASK,Value of OTP Bank15 Word3 (CRC Key)" line.long 0x04 "GROUP_MASK_SET,Value of OTP Bank15 Word3 (CRC Key)" line.long 0x08 "GROUP_MASK_CLR,Value of OTP Bank15 Word3 (CRC Key)" line.long 0x0C "GROUP_MASK_TOG,Value of OTP Bank15 Word3 (CRC Key)" group.long 0x800++0x0F line.long 0x00 "HDMI_FW_SRK0,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDMI_FW_SRK0_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDMI_FW_SRK0_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDMI_FW_SRK0_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x810++0x0F line.long 0x00 "HDMI_FW_SRK1,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x04 "HDMI_FW_SRK1_SET,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x08 "HDMI_FW_SRK1_CLR,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x0C "HDMI_FW_SRK1_TOG,Value of OTP Bank16 Word1 (HDCP Key)" group.long 0x820++0x0F line.long 0x00 "HDMI_FW_SRK2,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x04 "HDMI_FW_SRK2_SET,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x08 "HDMI_FW_SRK2_CLR,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x0C "HDMI_FW_SRK2_TOG,Value of OTP Bank16 Word2 (HDCP Key)" group.long 0x830++0x0F line.long 0x00 "HDMI_FW_SRK3,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDMI_FW_SRK3_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDMI_FW_SRK3_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDMI_FW_SRK3_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0x840++0x0F line.long 0x00 "HDMI_FW_SRK4,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDMI_FW_SRK4_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDMI_FW_SRK4_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDMI_FW_SRK4_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0x850++0x0F line.long 0x00 "HDMI_FW_SRK5,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDMI_FW_SRK5_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDMI_FW_SRK5_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDMI_FW_SRK5_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0x860++0x0F line.long 0x00 "HDMI_FW_SRK6,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDMI_FW_SRK6_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDMI_FW_SRK6_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDMI_FW_SRK6_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x870++0x0F line.long 0x00 "HDMI_FW_SRK7,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDMI_FW_SRK7_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDMI_FW_SRK7_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDMI_FW_SRK7_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x880++0x0F line.long 0x00 "HDMI_KMEK0,Value of OTP Bank9 Word0 (HDCP Key)" line.long 0x04 "HDMI_KMEK0_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDMI_KMEK0_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDMI_KMEK0_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x890++0x0F line.long 0x00 "HDMI_KMEK1,Value of OTP Bank9 Word0 (HDCP Key)" line.long 0x04 "HDMI_KMEK1_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDMI_KMEK1_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDMI_KMEK1_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x8A0++0x0F line.long 0x00 "HDMI_KMEK2,Value of OTP Bank9 Word0 (HDCP Key)" line.long 0x04 "HDMI_KMEK2_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDMI_KMEK2_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDMI_KMEK2_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x8B0++0x0F line.long 0x00 "HDMI_KMEK3,Value of OTP Bank9 Word3 (HDCP Key)" line.long 0x04 "HDMI_KMEK3_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDMI_KMEK3_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDMI_KMEK3_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0x900++0x0F line.long 0x00 "HDCP_TX_CONS0,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CONS0_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CONS0_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CONS0_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x910++0x0F line.long 0x00 "HDCP_TX_CONS1,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CONS1_SET,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CONS1_CLR,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CONS1_TOG,Value of OTP Bank16 Word1 (HDCP Key)" group.long 0x920++0x0F line.long 0x00 "HDCP_TX_CONS2,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x04 "HDCP_TX_CONS2_SET,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x08 "HDCP_TX_CONS2_CLR,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x0C "HDCP_TX_CONS2_TOG,Value of OTP Bank16 Word2 (HDCP Key)" group.long 0x930++0x0F line.long 0x00 "HDCP_TX_CONS3,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_TX_CONS3_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_TX_CONS3_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_TX_CONS3_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0x940++0x0F line.long 0x00 "HDCP_TX_CERT0,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT0_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT0_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT0_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0x950++0x0F line.long 0x00 "HDCP_TX_CERT1,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT1_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT1_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT1_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0x960++0x0F line.long 0x00 "HDCP_TX_CERT2,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT2_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT2_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT2_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x970++0x0F line.long 0x00 "HDCP_TX_CERT3,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT3_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT3_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT3_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x980++0x0F line.long 0x00 "HDCP_TX_CERT4,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT4_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT4_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT4_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x990++0x0F line.long 0x00 "HDCP_TX_CERT5,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT5_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT5_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT5_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x9A0++0x0F line.long 0x00 "HDCP_TX_CERT6,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT6_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT6_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT6_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x9B0++0x0F line.long 0x00 "HDCP_TX_CERT7,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT7_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT7_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT7_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0x9C0++0x0F line.long 0x00 "HDCP_TX_CERT8,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT8_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT8_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT8_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0x9D0++0x0F line.long 0x00 "HDCP_TX_CERT9,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT9_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT9_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT9_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0x9E0++0x0F line.long 0x00 "HDCP_TX_CERT10,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT10_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT10_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT10_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x9F0++0x0F line.long 0x00 "HDCP_TX_CERT11,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT11_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT11_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT11_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xA00++0x0F line.long 0x00 "HDCP_TX_CERT12,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT12_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT12_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT12_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xA10++0x0F line.long 0x00 "HDCP_TX_CERT13,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT13_SET,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT13_CLR,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT13_TOG,Value of OTP Bank16 Word1 (HDCP Key)" group.long 0xA20++0x0F line.long 0x00 "HDCP_TX_CERT14,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT14_SET,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT14_CLR,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT14_TOG,Value of OTP Bank16 Word2 (HDCP Key)" group.long 0xA30++0x0F line.long 0x00 "HDCP_TX_CERT15,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT15_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT15_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT15_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0xA40++0x0F line.long 0x00 "HDCP_TX_CERT16,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT16_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT16_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT16_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0xA50++0x0F line.long 0x00 "HDCP_TX_CERT17,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT17_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT17_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT17_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0xA60++0x0F line.long 0x00 "HDCP_TX_CERT18,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT18_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT18_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT18_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xA70++0x0F line.long 0x00 "HDCP_TX_CERT19,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT19_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT19_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT19_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xA80++0x0F line.long 0x00 "HDCP_TX_CERT20,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT20_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT20_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT20_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xA90++0x0F line.long 0x00 "HDCP_TX_CERT21,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT21_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT21_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT21_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xAA0++0x0F line.long 0x00 "HDCP_TX_CERT22,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT22_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT22_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT22_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xAB0++0x0F line.long 0x00 "HDCP_TX_CERT23,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT23_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT23_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT23_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0xAC0++0x0F line.long 0x00 "HDCP_TX_CERT24,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT24_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT24_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT24_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0xAD0++0x0F line.long 0x00 "HDCP_TX_CERT25,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT25_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT25_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT25_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0xAE0++0x0F line.long 0x00 "HDCP_TX_CERT26,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT26_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT26_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT26_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xAF0++0x0F line.long 0x00 "HDCP_TX_CERT27,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT27_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT27_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT27_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xB00++0x0F line.long 0x00 "HDCP_TX_CERT28,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT28_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT28_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT28_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xB10++0x0F line.long 0x00 "HDCP_TX_CERT29,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT29_SET,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT29_CLR,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT29_TOG,Value of OTP Bank16 Word1 (HDCP Key)" group.long 0xB20++0x0F line.long 0x00 "HDCP_TX_CERT30,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT30_SET,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT30_CLR,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT30_TOG,Value of OTP Bank16 Word2 (HDCP Key)" group.long 0xB30++0x0F line.long 0x00 "HDCP_TX_CERT31,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT31_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT31_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT31_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0xB40++0x0F line.long 0x00 "HDCP_TX_CERT32,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT32_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT32_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT32_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0xB50++0x0F line.long 0x00 "HDCP_TX_CERT33,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT33_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT33_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT33_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0xB60++0x0F line.long 0x00 "HDCP_TX_CERT34,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT34_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT34_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT34_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xB70++0x0F line.long 0x00 "HDCP_TX_CERT35,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT35_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT35_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT35_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xB80++0x0F line.long 0x00 "HDCP_TX_CERT36,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT36_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT36_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT36_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xB90++0x0F line.long 0x00 "HDCP_TX_CERT37,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT37_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT37_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT37_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xBA0++0x0F line.long 0x00 "HDCP_TX_CERT38,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT38_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT38_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT38_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xBB0++0x0F line.long 0x00 "HDCP_TX_CERT39,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT39_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT39_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT39_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0xBC0++0x0F line.long 0x00 "HDCP_TX_CERT40,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT40_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT40_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT40_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0xBD0++0x0F line.long 0x00 "HDCP_TX_CERT41,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT41_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT41_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT41_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0xBE0++0x0F line.long 0x00 "HDCP_TX_CERT42,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT42_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT42_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT42_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xBF0++0x0F line.long 0x00 "HDCP_TX_CERT43,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT43_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT43_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT43_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xC00++0x0F line.long 0x00 "HDCP_TX_CERT44,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT44_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT44_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT44_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xC10++0x0F line.long 0x00 "HDCP_TX_CERT45,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT45_SET,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT45_CLR,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT45_TOG,Value of OTP Bank16 Word1 (HDCP Key)" group.long 0xC20++0x0F line.long 0x00 "HDCP_TX_CERT46,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT46_SET,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT46_CLR,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT46_TOG,Value of OTP Bank16 Word2 (HDCP Key)" group.long 0xC30++0x0F line.long 0x00 "HDCP_TX_CERT47,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT47_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT47_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT47_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0xC40++0x0F line.long 0x00 "HDCP_TX_CERT48,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT48_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT48_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT48_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0xC50++0x0F line.long 0x00 "HDCP_TX_CERT49,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT49_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT49_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT49_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0xC60++0x0F line.long 0x00 "HDCP_TX_CERT50,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT50_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT50_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT50_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xC70++0x0F line.long 0x00 "HDCP_TX_CERT51,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT51_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT51_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT51_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xC80++0x0F line.long 0x00 "HDCP_TX_CERT52,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT52_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT52_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT52_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xC90++0x0F line.long 0x00 "HDCP_TX_CERT53,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT53_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT53_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT53_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xCA0++0x0F line.long 0x00 "HDCP_TX_CERT54,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT54_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT54_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT54_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xCB0++0x0F line.long 0x00 "HDCP_TX_CERT55,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT55_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT55_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT55_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0xCC0++0x0F line.long 0x00 "HDCP_TX_CERT56,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT56_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT56_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT56_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0xCD0++0x0F line.long 0x00 "HDCP_TX_CERT57,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT57_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT57_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT57_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0xCE0++0x0F line.long 0x00 "HDCP_TX_CERT58,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT58_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT58_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT58_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xCF0++0x0F line.long 0x00 "HDCP_TX_CERT59,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT59_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT59_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT59_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xD00++0x0F line.long 0x00 "HDCP_TX_CERT60,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT60_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT60_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT60_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xD10++0x0F line.long 0x00 "HDCP_TX_CERT61,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT61_SET,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT61_CLR,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT61_TOG,Value of OTP Bank16 Word1 (HDCP Key)" group.long 0xD20++0x0F line.long 0x00 "HDCP_TX_CERT62,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT62_SET,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT62_CLR,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT62_TOG,Value of OTP Bank16 Word2 (HDCP Key)" group.long 0xD30++0x0F line.long 0x00 "HDCP_TX_CERT63,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT63_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT63_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT63_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0xD40++0x0F line.long 0x00 "HDCP_TX_CERT64,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT64_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT64_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT64_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0xD50++0x0F line.long 0x00 "HDCP_TX_CERT65,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT65_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT65_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT65_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0xD60++0x0F line.long 0x00 "HDCP_TX_CERT66,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT66_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT66_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT66_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xD70++0x0F line.long 0x00 "HDCP_TX_CERT67,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT67_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT67_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT67_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xD80++0x0F line.long 0x00 "HDCP_TX_CERT68,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT68_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT68_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT68_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xD90++0x0F line.long 0x00 "HDCP_TX_CERT69,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT69_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT69_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT69_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xDA0++0x0F line.long 0x00 "HDCP_TX_CERT70,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT70_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT70_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT70_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xDB0++0x0F line.long 0x00 "HDCP_TX_CERT71,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT71_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT71_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT71_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0xDC0++0x0F line.long 0x00 "HDCP_TX_CERT72,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT72_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT72_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT72_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0xDD0++0x0F line.long 0x00 "HDCP_TX_CERT73,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT73_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT73_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT73_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0xDE0++0x0F line.long 0x00 "HDCP_TX_CERT74,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT74_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT74_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT74_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xDF0++0x0F line.long 0x00 "HDCP_TX_CERT75,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT75_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT75_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT75_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xE00++0x0F line.long 0x00 "HDCP_TX_CERT76,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT76_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT76_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT76_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xE10++0x0F line.long 0x00 "HDCP_TX_CERT77,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT77_SET,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT77_CLR,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT77_TOG,Value of OTP Bank16 Word1 (HDCP Key)" group.long 0xE20++0x0F line.long 0x00 "HDCP_TX_CERT78,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT78_SET,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT78_CLR,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT78_TOG,Value of OTP Bank16 Word2 (HDCP Key)" group.long 0xE30++0x0F line.long 0x00 "HDCP_TX_CERT79,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT79_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT79_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT79_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0xE40++0x0F line.long 0x00 "HDCP_TX_CERT80,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT80_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT80_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT80_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0xE50++0x0F line.long 0x00 "HDCP_TX_CERT81,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT81_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT81_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT81_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0xE60++0x0F line.long 0x00 "HDCP_TX_CERT82,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT82_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT82_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT82_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xE70++0x0F line.long 0x00 "HDCP_TX_CERT83,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT83_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT83_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT83_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xE80++0x0F line.long 0x00 "HDCP_TX_CERT84,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT84_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT84_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT84_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xE90++0x0F line.long 0x00 "HDCP_TX_CERT85,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT85_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT85_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT85_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xEA0++0x0F line.long 0x00 "HDCP_TX_CERT86,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT86_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT86_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT86_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xEB0++0x0F line.long 0x00 "HDCP_TX_CERT87,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT87_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT87_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT87_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0xEC0++0x0F line.long 0x00 "HDCP_TX_CERT88,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT88_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT88_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT88_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0xED0++0x0F line.long 0x00 "HDCP_TX_CERT89,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT89_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT89_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT89_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0xEE0++0x0F line.long 0x00 "HDCP_TX_CERT90,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT90_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT90_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT90_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xEF0++0x0F line.long 0x00 "HDCP_TX_CERT91,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT91_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT91_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT91_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xF00++0x0F line.long 0x00 "HDCP_TX_CERT92,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT92_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT92_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT92_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xF10++0x0F line.long 0x00 "HDCP_TX_CERT93,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT93_SET,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT93_CLR,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT93_TOG,Value of OTP Bank16 Word1 (HDCP Key)" group.long 0xF20++0x0F line.long 0x00 "HDCP_TX_CERT94,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT94_SET,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT94_CLR,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT94_TOG,Value of OTP Bank16 Word2 (HDCP Key)" group.long 0xF30++0x0F line.long 0x00 "HDCP_TX_CERT95,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_TX_CERT95_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_TX_CERT95_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_TX_CERT95_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0xF40++0x0F line.long 0x00 "HDCP_KEY0,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY0_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY0_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY0_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0xF50++0x0F line.long 0x00 "HDCP_KEY1,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_KEY1_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_KEY1_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_KEY1_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0xF60++0x0F line.long 0x00 "HDCP_KEY2,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY2_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY2_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY2_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xF70++0x0F line.long 0x00 "HDCP_KEY3,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY3_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY3_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY3_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xF80++0x0F line.long 0x00 "HDCP_KEY4,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY4_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY4_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY4_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xF90++0x0F line.long 0x00 "HDCP_KEY5,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY5_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY5_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY5_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xFA0++0x0F line.long 0x00 "HDCP_KEY6,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY6_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY6_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY6_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xFB0++0x0F line.long 0x00 "HDCP_KEY7,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_KEY7_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_KEY7_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_KEY7_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0xFC0++0x0F line.long 0x00 "HDCP_KEY8,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY8_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY8_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY8_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0xFD0++0x0F line.long 0x00 "HDCP_KEY9,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_KEY9_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_KEY9_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_KEY9_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0xFE0++0x0F line.long 0x00 "HDCP_KEY10,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY10_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY10_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY10_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0xFF0++0x0F line.long 0x00 "HDCP_KEY11,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY11_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY11_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY11_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1000++0x0F line.long 0x00 "HDCP_KEY12,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY12_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY12_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY12_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1010++0x0F line.long 0x00 "HDCP_KEY13,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x04 "HDCP_KEY13_SET,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x08 "HDCP_KEY13_CLR,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x0C "HDCP_KEY13_TOG,Value of OTP Bank16 Word1 (HDCP Key)" group.long 0x1020++0x0F line.long 0x00 "HDCP_KEY14,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x04 "HDCP_KEY14_SET,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x08 "HDCP_KEY14_CLR,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x0C "HDCP_KEY14_TOG,Value of OTP Bank16 Word2 (HDCP Key)" group.long 0x1030++0x0F line.long 0x00 "HDCP_KEY15,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_KEY15_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_KEY15_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_KEY15_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0x1040++0x0F line.long 0x00 "HDCP_KEY16,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY16_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY16_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY16_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0x1050++0x0F line.long 0x00 "HDCP_KEY17,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_KEY17_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_KEY17_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_KEY17_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0x1060++0x0F line.long 0x00 "HDCP_KEY18,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY18_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY18_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY18_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1070++0x0F line.long 0x00 "HDCP_KEY19,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY19_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY19_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY19_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1080++0x0F line.long 0x00 "HDCP_KEY20,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY20_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY20_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY20_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1090++0x0F line.long 0x00 "HDCP_KEY21,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY21_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY21_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY21_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x10A0++0x0F line.long 0x00 "HDCP_KEY22,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY22_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY22_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY22_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x10B0++0x0F line.long 0x00 "HDCP_KEY23,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_KEY23_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_KEY23_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_KEY23_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0x10C0++0x0F line.long 0x00 "HDCP_KEY24,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY24_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY24_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY24_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0x10D0++0x0F line.long 0x00 "HDCP_KEY25,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_KEY25_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_KEY25_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_KEY25_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0x10E0++0x0F line.long 0x00 "HDCP_KEY26,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY26_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY26_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY26_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x10F0++0x0F line.long 0x00 "HDCP_KEY27,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY27_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY27_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY27_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1100++0x0F line.long 0x00 "HDCP_KEY28,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY28_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY28_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY28_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1110++0x0F line.long 0x00 "HDCP_KEY29,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x04 "HDCP_KEY29_SET,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x08 "HDCP_KEY29_CLR,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x0C "HDCP_KEY29_TOG,Value of OTP Bank16 Word1 (HDCP Key)" group.long 0x1120++0x0F line.long 0x00 "HDCP_KEY30,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x04 "HDCP_KEY30_SET,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x08 "HDCP_KEY30_CLR,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x0C "HDCP_KEY30_TOG,Value of OTP Bank16 Word2 (HDCP Key)" group.long 0x1130++0x0F line.long 0x00 "HDCP_KEY31,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_KEY31_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_KEY31_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_KEY31_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0x1140++0x0F line.long 0x00 "HDCP_KEY32,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY32_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY32_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY32_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0x1150++0x0F line.long 0x00 "HDCP_KEY33,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_KEY33_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_KEY33_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_KEY33_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0x1160++0x0F line.long 0x00 "HDCP_KEY34,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY34_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY34_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY34_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1170++0x0F line.long 0x00 "HDCP_KEY35,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY35_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY35_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY35_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1180++0x0F line.long 0x00 "HDCP_KEY36,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY36_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY36_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY36_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1190++0x0F line.long 0x00 "HDCP_KEY37,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY37_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY37_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY37_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x11A0++0x0F line.long 0x00 "HDCP_KEY38,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY38_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY38_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY38_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x11B0++0x0F line.long 0x00 "HDCP_KEY39,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_KEY39_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_KEY39_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_KEY39_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0x11C0++0x0F line.long 0x00 "HDCP_KEY40,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY40_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY40_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY40_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0x11D0++0x0F line.long 0x00 "HDCP_KEY41,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_KEY41_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_KEY41_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_KEY41_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0x11E0++0x0F line.long 0x00 "HDCP_KEY42,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY42_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY42_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY42_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x11F0++0x0F line.long 0x00 "HDCP_KEY43,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY43_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY43_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY43_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1200++0x0F line.long 0x00 "HDCP_KEY44,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY44_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY44_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY44_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1210++0x0F line.long 0x00 "HDCP_KEY45,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x04 "HDCP_KEY45_SET,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x08 "HDCP_KEY45_CLR,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x0C "HDCP_KEY45_TOG,Value of OTP Bank16 Word1 (HDCP Key)" group.long 0x1220++0x0F line.long 0x00 "HDCP_KEY46,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x04 "HDCP_KEY46_SET,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x08 "HDCP_KEY46_CLR,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x0C "HDCP_KEY46_TOG,Value of OTP Bank16 Word2 (HDCP Key)" group.long 0x1230++0x0F line.long 0x00 "HDCP_KEY47,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_KEY47_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_KEY47_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_KEY47_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0x1240++0x0F line.long 0x00 "HDCP_KEY48,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY48_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY48_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY48_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0x1250++0x0F line.long 0x00 "HDCP_KEY49,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_KEY49_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_KEY49_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_KEY49_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0x1260++0x0F line.long 0x00 "HDCP_KEY50,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY50_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY50_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY50_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1270++0x0F line.long 0x00 "HDCP_KEY51,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY51_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY51_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY51_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1280++0x0F line.long 0x00 "HDCP_KEY52,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY52_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY52_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY52_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1290++0x0F line.long 0x00 "HDCP_KEY53,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY53_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY53_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY53_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x12A0++0x0F line.long 0x00 "HDCP_KEY54,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY54_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY54_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY54_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x12B0++0x0F line.long 0x00 "HDCP_KEY55,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_KEY55_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_KEY55_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_KEY55_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0x12C0++0x0F line.long 0x00 "HDCP_KEY56,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY56_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY56_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY56_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0x12D0++0x0F line.long 0x00 "HDCP_KEY57,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_KEY57_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_KEY57_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_KEY57_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0x12E0++0x0F line.long 0x00 "HDCP_KEY58,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY58_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY58_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY58_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x12F0++0x0F line.long 0x00 "HDCP_KEY59,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY59_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY59_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY59_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1300++0x0F line.long 0x00 "HDCP_KEY60,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY60_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY60_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY60_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1310++0x0F line.long 0x00 "HDCP_KEY61,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x04 "HDCP_KEY61_SET,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x08 "HDCP_KEY61_CLR,Value of OTP Bank16 Word1 (HDCP Key)" line.long 0x0C "HDCP_KEY61_TOG,Value of OTP Bank16 Word1 (HDCP Key)" group.long 0x1320++0x0F line.long 0x00 "HDCP_KEY62,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x04 "HDCP_KEY62_SET,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x08 "HDCP_KEY62_CLR,Value of OTP Bank16 Word2 (HDCP Key)" line.long 0x0C "HDCP_KEY62_TOG,Value of OTP Bank16 Word2 (HDCP Key)" group.long 0x1330++0x0F line.long 0x00 "HDCP_KEY63,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_KEY63_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_KEY63_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_KEY63_TOG,Value of OTP Bank16 Word3 (HDCP Key)" group.long 0x1340++0x0F line.long 0x00 "HDCP_KEY64,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY64_SET,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY64_CLR,Value of OTP Bank17 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY64_TOG,Value of OTP Bank17 Word0 (HDCP Key)" group.long 0x1350++0x0F line.long 0x00 "HDCP_KEY65,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x04 "HDCP_KEY65_SET,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x08 "HDCP_KEY65_CLR,Value of OTP Bank17 Word1 (HDCP Key)" line.long 0x0C "HDCP_KEY65_TOG,Value of OTP Bank17 Word1 (HDCP Key)" group.long 0x1360++0x0F line.long 0x00 "HDCP_KEY66,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY66_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY66_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY66_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1370++0x0F line.long 0x00 "HDCP_KEY67,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY67_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY67_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY67_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1380++0x0F line.long 0x00 "HDCP_KEY68,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY68_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY68_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY68_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x1390++0x0F line.long 0x00 "HDCP_KEY69,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY69_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY69_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY69_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x13A0++0x0F line.long 0x00 "HDCP_KEY70,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x04 "HDCP_KEY70_SET,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x08 "HDCP_KEY70_CLR,Value of OTP Bank16 Word0 (HDCP Key)" line.long 0x0C "HDCP_KEY70_TOG,Value of OTP Bank16 Word0 (HDCP Key)" group.long 0x13B0++0x0F line.long 0x00 "HDCP_KEY71,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x04 "HDCP_KEY71_SET,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x08 "HDCP_KEY71_CLR,Value of OTP Bank16 Word3 (HDCP Key)" line.long 0x0C "HDCP_KEY71_TOG,Value of OTP Bank16 Word3 (HDCP Key)" width 0x0B tree.end tree "SNVS (Secure Non-Volatile Storage)" base ad:0x30370000 width 12. group.long 0x00++0x07 line.long 0x00 "HPLR,HP Lock Register" bitfld.long 0x00 28. " AT5_SL ,Active tamper 5 soft lock" "Not locked,Locked" bitfld.long 0x00 27. " AT4_SL ,Active tamper 4 soft lock" "Not locked,Locked" bitfld.long 0x00 26. " AT3_SL ,Active tamper 3 soft lock" "Not locked,Locked" bitfld.long 0x00 25. " AT2_SL ,Active tamper 2 soft lock" "Not locked,Locked" textline " " bitfld.long 0x00 24. " AT1_SL ,Active tamper 1 soft lock" "Not locked,Locked" bitfld.long 0x00 18. " HAC_L ,High assurance configuration lock" "Not locked,Locked" bitfld.long 0x00 17. " HPSICR_L ,HP security interrupt control register lock" "Not locked,Locked" bitfld.long 0x00 16. " HPSVCR_L ,HP security violation control register lock" "Not locked,Locked" textline " " bitfld.long 0x00 9. " MKS_SL ,Master key select soft lock" "Not locked,Locked" bitfld.long 0x00 8. " LPTDCR_SL ,LP tamper detectors configuration register soft lock" "Not locked,Locked" bitfld.long 0x00 7. " LPTGFCR_SL ,LP tamper glitch filter configuration register soft lock" "Not locked,Locked" bitfld.long 0x00 6. " LPSVCR_SL ,LP security violation control register soft lock" "Not locked,Locked" textline " " bitfld.long 0x00 5. " GPR_SL ,General purpose register soft lock" "Not locked,Locked" bitfld.long 0x00 4. " MC_SL ,Monotonic counter soft lock" "Not locked,Locked" bitfld.long 0x00 3. " LPCALB_SL ,LP calibration soft lock" "Not locked,Locked" bitfld.long 0x00 2. " SRTC_SL ,Secure real time counter soft lock" "Not locked,Locked" textline " " bitfld.long 0x00 1. " ZMK_RSL ,Zeroizable master key read soft lock" "Not locked,Locked" bitfld.long 0x00 0. " ZMK_WSL ,Zeroizable master key write soft lock" "Not locked,Locked" line.long 0x04 "HPCOMR,HP Command Register" bitfld.long 0x04 31. " NPSWA_EN ,Non-Privileged software access enable" "Disabled,Enabled" bitfld.long 0x04 19. " HAC_STOP ,High assurance counter stop" "Not stopped,Stopped" bitfld.long 0x04 18. " HAC_CLEAR ,High assurance counter clear" "No effect,Clear" bitfld.long 0x04 17. " HAC_LOAD ,High assurance counter load" "No effect,Loaded" textline " " bitfld.long 0x04 16. " HAC_EN ,High assurance configuration enable" "Disabled,Enabled" bitfld.long 0x04 13. " MKS_EN ,Master key select enable" "Disabled,Enabled" bitfld.long 0x04 12. " PROG_ZMK ,Program zeroizable master key" "No effect,Activated" bitfld.long 0x04 10. " SW_LPSV ,LP software security violation" "Not violated,Violated" textline " " bitfld.long 0x04 9. " SW_FSV ,Software fatal security violation" "Not violated,Violated" bitfld.long 0x04 8. " SW_SV ,Software security violation" "Not violated,Violated" bitfld.long 0x04 5. " LP_SWR_DIS ,LP software reset disable" "No,Yes" bitfld.long 0x04 4. " LP_SWR ,LP software reset" "No effect,Reset" textline " " bitfld.long 0x04 2. " SSM_SFNS_DIS ,SSM soft fail to Non-Secure state transition disable" "No,Yes" bitfld.long 0x04 1. " SSM_ST_DIS ,SSM secure to trusted state transition disable" "No,Yes" bitfld.long 0x04 0. " SSM_ST ,SSM state transition" "No effect,Transition" if (((per.l(ad:0x30370000+0x08))&0x100)==0x00) group.long 0x08++0x03 line.long 0x00 "HPCR,HP Control Register" bitfld.long 0x00 27. " BTN_MASK ,Button interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--26. " BTN_CONFIG ,Button configuration" "Low,High,Rising edge,Falling edge,Both edges,?..." bitfld.long 0x00 16. " HP_TS ,HP time synchronize" "Not updated,Updated" bitfld.long 0x00 10.--14. " HPCALB_VAL ,HP calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" textline " " bitfld.long 0x00 8. " HPCALB_EN ,HP real time counter calibration enabled" "Disabled,Enabled" bitfld.long 0x00 4.--7. " PI_FREQ ,Number of bit responsible for generating periodic interrupt during its transition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " PI_EN ,HP periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " HPTA_EN ,HP time alarm interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RTC_EN ,HP real time counter enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "HPCR,HP Control Register" bitfld.long 0x00 27. " BTN_MASK ,Button interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--26. " BTN_CONFIG ,Button configuration" "Low,High,Rising edge,Falling edge,Both edges,?..." bitfld.long 0x00 16. " HP_TS ,HP time synchronize" "Not updated,Updated" rbitfld.long 0x00 10.--14. " HPCALB_VAL ,HP calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" textline " " bitfld.long 0x00 8. " HPCALB_EN ,HP real time counter calibration enabled" "Disabled,Enabled" bitfld.long 0x00 4.--7. " PI_FREQ ,Number of bit responsible for generating periodic interrupt during its transition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " PI_EN ,HP periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " HPTA_EN ,HP time alarm interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RTC_EN ,HP real time counter enable" "Disabled,Enabled" endif group.long 0x0C++0x07 line.long 0x00 "HPSICR,Security Interrupt Control Register" bitfld.long 0x00 31. " LPSVI_EN ,LP security violation interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SVI_EN5 ,Security violation interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SVI_EN4 ,Security violation interrupt 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " SVI_EN3 ,Security violation interrupt 3 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SVI_EN2 ,Security violation interrupt 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " SVI_EN1 ,Security violation interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SVI_EN0 ,Security violation interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "HPSVCR,Security Violation Control Register" bitfld.long 0x04 30.--31. " LPSV_CFG ,LP security violation configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x04 5.--6. " SV_CFG5 ,Security violation input 5 configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x04 4. " SV_CFG4 ,Security violation input 4 configuration" "Non-fatal,Fatal" bitfld.long 0x04 3. " SV_CFG3 ,Security violation input 3 configuration" "Non-fatal,Fatal" textline " " bitfld.long 0x04 2. " SV_CFG2 ,Security violation input 2 configuration" "Non-fatal,Fatal" bitfld.long 0x04 1. " SV_CFG1 ,Security violation input 1 configuration" "Non-fatal,Fatal" bitfld.long 0x04 0. " SV_CFG0 ,Security violation input 0 configuration" "Non-fatal,Fatal" group.long 0x14++0x0B line.long 0x00 "HPSR,HP Status Register" rbitfld.long 0x00 31. " ZMK_ZERO ,Zeroizable master key is equal to zero" "Not zero,Zero" rbitfld.long 0x00 27. " OTPMK_ZERO ,One time programmable master key is equal to zero" "Not zero,Zero" hexmask.long.word 0x00 16.--24. 1. " OTPMK_SYNDROME ,One time programmable master key syndrome" rbitfld.long 0x00 15. " SYS_SECURE_BOOT ,System secure boot" "Normal,ROM" textline " " sif cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4") rbitfld.long 0x00 12.--14. " SYS_SECURITY_CFG ,System security configuration" "Fab,Open,,Closed,,,,Field return" rbitfld.long 0x00 8.--11. " SSM_STATE ,System security monitor state" "Init,Hard fail,,Soft fail,,,,,Init intermediate,Check,,Non-secure,,Trusted,,Secure" textline " " else rbitfld.long 0x00 12.--14. " SYS_SECURITY_CFG ,System security configuration" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 8.--11. " SSM_STATE ,System security monitor state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " endif eventfld.long 0x00 7. " BI ,Button interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 6. " BTN ,BTN input state" "Not pressed,Pressed" textline " " eventfld.long 0x00 1. " PI ,Periodic interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " HPTA ,HP time alarm" "No interrupt,Interrupt" line.long 0x04 "HPSVSR,HP Security Violation Status" rbitfld.long 0x04 31. " LP_SEC_VIO ,LP security violation" "Not detected,Detected" eventfld.long 0x04 27. " ZMK_ECC_FAIL ,Zeroizable master key error correcting code check failure" "Not failed,Failed" hexmask.long.word 0x04 16.--24. 1. " ZMK_SYNDROME ,Zeroizable master key syndrome" rbitfld.long 0x04 15. " SW_LPSV ,LP software security violation" "Not violated,Violated" textline " " rbitfld.long 0x04 14. " SW_FSV ,Software fatal security violation" "Not violated,Violated" rbitfld.long 0x04 13. " SW_SV ,Software security violation" "Not violated,Violated" eventfld.long 0x04 5. " SEC_VIO5 ,Security volation on input 5 was detected" "Not detected,Detected" eventfld.long 0x04 4. " SEC_VIO4 ,Security volation on input 4 was detected" "Not detected,Detected" textline " " eventfld.long 0x04 3. " SEC_VIO3 ,Security volation on input 3 was detected" "Not detected,Detected" eventfld.long 0x04 2. " SEC_VIO2 ,Security volation on input 2 was detected" "Not detected,Detected" eventfld.long 0x04 1. " SEC_VIO1 ,Security volation on input 1 was detected" "Not detected,Detected" eventfld.long 0x04 0. " SEC_VIO0 ,Security volation on input 0 was detected" "Not detected,Detected" textline " " line.long 0x08 "HPHACIVR,HP High Assurance Counter IV" rgroup.long 0x20++0x03 line.long 0x00 "HPHACR,HP High Assurance Counter" if (((per.l(ad:0x30370000+0x08))&0x01)==0x01) rgroup.long 0x24++0x07 line.long 0x00 "HPRTCMR,HP Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " RTC ,HP real time counter" line.long 0x04 "HPRTCLR,HP Real Time Counter LSB Register" else group.long 0x24++0x07 line.long 0x00 "HPRTCMR,HP Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " RTC ,HP real time counter" line.long 0x04 "HPRTCLR,HP Real Time Counter LSB Register" endif if (((per.l(ad:0x30370000+0x08)&0x02)==0x02)) rgroup.long 0x2C++0x07 line.long 0x00 "HPTAMR,HP Time Alarm MSB Register" hexmask.long.word 0x00 0.--14. 1. " HPTA ,HP time alarm" line.long 0x04 "HPTALR,HP Time Alarm LSB Register" else group.long 0x2C++0x07 line.long 0x00 "HPTAMR,HP Time Alarm MSB Register" hexmask.long.word 0x00 0.--14. 1. " HPTA ,HP time alarm" line.long 0x04 "HPTALR,HP Time Alarm LSB Register" endif group.long 0x34++0x03 line.long 0x00 "LPLR,LP Lock Register" bitfld.long 0x00 28. " AT5_HL ,Active tamper 5 hard lock" "Not locked,Locked" bitfld.long 0x00 27. " AT4_HL ,Active tamper 4 hard lock" "Not locked,Locked" bitfld.long 0x00 26. " AT3_HL ,Active tamper 3 hard lock" "Not locked,Locked" bitfld.long 0x00 25. " AT2_HL ,Active tamper 2 hard lock" "Not locked,Locked" textline " " bitfld.long 0x00 24. " AT1_HL ,Active tamper 1 hard lock" "Not locked,Locked" bitfld.long 0x00 9. " MKS_HL ,Master key select hard lock" "Not locked,Locked" bitfld.long 0x00 8. " LPTDCR_HL ,LP tamper detectors configuration register hard lock" "Not locked,Locked" bitfld.long 0x00 7. " LPTGFCR_HL ,LP tamper glitch filter configuration register hard lock" "Not locked,Locked" textline " " bitfld.long 0x00 6. " LPSVCR_HL ,LP security violation control register hard lock" "Not locked,Locked" bitfld.long 0x00 5. " GPR_HL ,General purpose register hard lock" "Not locked,Locked" bitfld.long 0x00 4. " MC_HL ,Monotonic counter hard lock" "Not locked,Locked" bitfld.long 0x00 3. " LPCALB_HL ,LP calibration hard lock" "Not locked,Locked" textline " " bitfld.long 0x00 2. " SRTC_HL ,Secure real time counter hard lock" "Not locked,Locked" bitfld.long 0x00 1. " ZMK_RHL ,Zeroizable master key read hard lock" "Not locked,Locked" bitfld.long 0x00 0. " ZMK_WHL ,Zeroizable master key write hard lock" "Not locked,Locked" if ((per.l(ad:0x30370000+0x38)&0x20)==0x20) group.long 0x38++0x03 line.long 0x00 "LPCR,LP Control Register" bitfld.long 0x00 24. " GPR_Z_DIS ,General purpose registers zeroization disable" "No,Yes" bitfld.long 0x00 23. " PK_OVERRIDE ,PMIC on request override" "Not overridden,Overridden" bitfld.long 0x00 22. " PK_EN ,PMIC on request enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ON_TIME ,Period of time after BTN is asserted before pmic_en_b is asserted to turn on the socpower" "500 msec,50 msec,100 msec,0 msec" textline " " bitfld.long 0x00 18.--19. " DEBOUNCE ,Amount of debounce time for the BTN input signal" "50 msec,100 msec,500 msec,0 msec" bitfld.long 0x00 16.--17. " BTN_PRESS_TIME ,Button press time out values for PMIC logic" "5 sec,10 sec,15 sec,Disabled" bitfld.long 0x00 10.--14. " LPCALB_VAL ,LP calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" bitfld.long 0x00 8. " LPCALB_EN ,LP calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " PWR_GLITCH_EN ,Power glitch enable" "Disabled,Enabled" bitfld.long 0x00 6. " TOP ,Turn off system power" "Power on,Power off" bitfld.long 0x00 5. " DP_EN ,Decides whether dumb or smart PMIC is enabled" "Disabled,Enabled" bitfld.long 0x00 4. " SRTC_INV_EN ,SRTC stops counting and the SRTC is invalidated" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LPWUI_EN ,LP Wake-Up interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " MC_ENV ,Monotonic counter enable and valid" "Disabled/invalid,Enabled/valid" bitfld.long 0x00 1. " LPTA_EN ,LP time alarm enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRTC_ENV ,Secure real time counter enabled and valid" "Disabled,Enabled" else group.long 0x38++0x03 line.long 0x00 "LPCR,LP Control Register" bitfld.long 0x00 24. " GPR_Z_DIS ,General purpose registers zeroization disable" "No,Yes" bitfld.long 0x00 23. " PK_OVERRIDE ,PMIC on request override" "Not overridden,Overridden" bitfld.long 0x00 22. " PK_EN ,PMIC on request enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ON_TIME ,Period of time after BTN is asserted before pmic_en_b is asserted to turn on the socpower" "500 msec,50 msec,100 msec,0 msec" textline " " bitfld.long 0x00 18.--19. " DEBOUNCE ,Amount of debounce time for the BTN input signal" "50 msec,100 msec,500 msec,0 msec" bitfld.long 0x00 16.--17. " BTN_PRESS_TIME ,Button press time out values for PMIC logic" "5 sec,10 sec,15 sec,Disabled" bitfld.long 0x00 10.--14. " LPCALB_VAL ,LP calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" bitfld.long 0x00 8. " LPCALB_EN ,LP calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " PWR_GLITCH_EN ,Power glitch enable" "Disabled,Enabled" bitfld.long 0x00 5. " DP_EN ,Decides whether dumb or smart PMIC is enabled" "Disabled,Enabled" bitfld.long 0x00 4. " SRTC_INV_EN ,SRTC stops counting and the SRTC is invalidated" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LPWUI_EN ,LP Wake-Up interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " MC_ENV ,Monotonic counter enable and valid" "Disabled/invalid,Enabled/valid" bitfld.long 0x00 1. " LPTA_EN ,LP time alarm enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRTC_ENV ,Secure real time counter enabled and valid" "Disabled,Enabled" endif if (((per.l(ad:0x30370000)&0x01)==0x00)&&((per.l(ad:0x30370000+0x34)&0x01)==0x00)&&((per.l(ad:0x30370000)&0x200)==0x00)&&((per.l(ad:0x30370000+0x34)&0x200)==0x00)) group.long 0x3C++0x03 line.long 0x00 "LPMKCR,LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "0,1" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key hardware programming mode" "Software,Hardware" textline " " bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "0,1,Zeroizable,Hardware" elif (((per.l(ad:0x30370000)&0x01)==0x00)&&((per.l(ad:0x30370000+0x34)&0x01)==0x00))&&(((per.l(ad:0x30370000)&0x200)==0x200)||((per.l(ad:0x30370000+0x34)&0x200)==0x200)) group.long 0x3C++0x03 line.long 0x00 "LPMKCR,LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "0,1" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key hardware programming mode" "Software,Hardware" textline " " rbitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "0,1,Zeroizable,Hardware" elif (((per.l(ad:0x30370000)&0x01)==0x01)||((per.l(ad:0x30370000+0x34)&0x01)==0x01))&&(((per.l(ad:0x30370000)&0x200)==0x00)&&((per.l(ad:0x30370000+0x34)&0x200)==0x00)) group.long 0x3C++0x03 line.long 0x00 "LPMKCR,LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" rbitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" rbitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "0,1" rbitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key hardware programming mode" "Software,Hardware" textline " " bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "0,1,Zeroizable,Hardware" else rgroup.long 0x3C++0x03 line.long 0x00 "LPMKCR,LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "0,1" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key hardware programming mode" "Software,Hardware" textline " " bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "0,1,Zeroizable,Hardware" endif if (((per.l(ad:0x30370000)&0x40)==0x00)&&((per.l(ad:0x30370000+0x34)&0x40)==0x00)) group.long 0x40++0x03 line.long 0x00 "LPSVCR,LP Security Violation Control" bitfld.long 0x00 5. " SV_EN5 ,Security violation 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SV_EN4 ,Security violation 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " SV_EN3 ,Security violation 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SV_EN2 ,Security violation 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SV_EN1 ,Security violation 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SV_EN0 ,Security violation 0 enable" "Disabled,Enabled" else rgroup.long 0x40++0x03 line.long 0x00 "LPSVCR,LP Security Violation Control" bitfld.long 0x00 5. " SV_EN5 ,Security violation 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SV_EN4 ,Security violation 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " SV_EN3 ,Security violation 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SV_EN2 ,Security violation 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SV_EN1 ,Security violation 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SV_EN0 ,Security violation 0 enable" "Disabled,Enabled" endif if (((per.l(ad:0x30370000)&0x80)==0x00)&&((per.l(ad:0x30370000+0x34)&0x80)==0x00)) group.long 0x44++0x03 line.long 0x00 "LPTGFCR,LP Tamper Glitch Filters Configuration" bitfld.long 0x00 31. " ETGF2_EN ,External tamper glitch filter 2 enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " ETGF2 ,External tamper glitch filter 2" bitfld.long 0x00 23. " ETGF1_EN ,External tamper glitch filter 1 enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--22. 1. " ETGF1 ,External tamper glitch filter 1" textline " " bitfld.long 0x00 7. " WMTGF_EN ,Wire-Mesh tamper glitch filter enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WMTGF ,Wire-Mesh tamper glitch filter" "1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31,33,35,37,39,41,43,45,47,49,51,53,55,57,59,61,63" else rgroup.long 0x44++0x03 line.long 0x00 "LPTGFCR,LP Tamper Glitch Filters Configuration" bitfld.long 0x00 31. " ETGF2_EN ,External tamper glitch filter 2 enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " ETGF2 ,External tamper glitch filter 2" bitfld.long 0x00 23. " ETGF1_EN ,External tamper glitch filter 1 enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--22. 1. " ETGF1 ,External tamper glitch filter 1" textline " " bitfld.long 0x00 7. " WMTGF_EN ,Wire-Mesh tamper glitch filter enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WMTGF ,Wire-Mesh tamper glitch filter" "1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31,33,35,37,39,41,43,45,47,49,51,53,55,57,59,61,63" endif if (((per.l(ad:0x30370000)&0x100)==0x00)&&((per.l(ad:0x30370000+0x34)&0x100)==0x00)) group.long 0x48++0x03 line.long 0x00 "LPTDCR,LP Tamper Detectors Configuration" bitfld.long 0x00 28. " OSCB ,Oscillator bypass" "Not asserted,Asserted" bitfld.long 0x00 24.--26. " VRC ,Voltage reference configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " HTDC ,High temperature detect configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " LTDC ,Low temp detect configuration" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15. " POR_OBSERV ,Power on reset (Por) observability flop" "Not detected,Detected" bitfld.long 0x00 14. " PFD_OBSERV ,System power fail detector (Pfd) observability flop" "Not detected,Detected" bitfld.long 0x00 12. " ET2P ,External tampering 2 polarity" "0,1" bitfld.long 0x00 11. " ET1P ,External tampering 1 polarity" "0,1" textline " " bitfld.long 0x00 10. " ET2_EN ,External tampering 2 enable" "Disabled,Enabled" bitfld.long 0x00 9. " ET1_EN ,External tampering 1 enable" "Disabled,Enabled" bitfld.long 0x00 8. " WMT2_EN ,Wire-Mesh tampering 2 enable" "Disabled,Enabled" bitfld.long 0x00 7. " WMT1_EN ,Wire-Mesh tampering 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " VT_EN ,Voltage tamper enable" "Disabled,Enabled" bitfld.long 0x00 5. " TT_EN ,Temperature tamper enable" "Disabled,Enabled" bitfld.long 0x00 4. " CT_EN ,Clock tamper enable" "Disabled,Enabled" bitfld.long 0x00 2. " MCR_EN ,MC rollover enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SRTCR_EN ,SRTC rollover enable" "Disabled,Enabled" else rgroup.long 0x48++0x03 line.long 0x00 "LPTDCR,LP Tamper Detectors Configuration" bitfld.long 0x00 28. " OSCB ,Oscillator bypass" "Not asserted,Asserted" bitfld.long 0x00 24.--26. " VRC ,Voltage reference configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " HTDC ,High temperature detect configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " LTDC ,Low temp detect configuration" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15. " POR_OBSERV ,Power on reset (Por) observability flop" "Not detected,Detected" bitfld.long 0x00 14. " PFD_OBSERV ,System power fail detector (Pfd) observability flop" "Not detected,Detected" bitfld.long 0x00 12. " ET2P ,External tampering 2 polarity" "0,1" bitfld.long 0x00 11. " ET1P ,External tampering 1 polarity" "0,1" textline " " bitfld.long 0x00 10. " ET2_EN ,External tampering 2 enable" "Disabled,Enabled" bitfld.long 0x00 9. " ET1_EN ,External tampering 1 enable" "Disabled,Enabled" bitfld.long 0x00 8. " WMT2_EN ,Wire-Mesh tampering 2 enable" "Disabled,Enabled" bitfld.long 0x00 7. " WMT1_EN ,Wire-Mesh tampering 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " VT_EN ,Voltage tamper enable" "Disabled,Enabled" bitfld.long 0x00 5. " TT_EN ,Temperature tamper enable" "Disabled,Enabled" bitfld.long 0x00 4. " CT_EN ,Clock tamper enable" "Disabled,Enabled" bitfld.long 0x00 2. " MCR_EN ,MC rollover enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SRTCR_EN ,SRTC rollover enable" "Disabled,Enabled" endif group.long 0x4C++0x03 line.long 0x00 "LPSR,LP Status Register" rbitfld.long 0x00 31. " LPS ,LP section is secured" "Not secured,Secured" rbitfld.long 0x00 30. " LPNS ,LP section is Non-Secured" "No,Yes" eventfld.long 0x00 20. " SED ,Scan exit detected" "Not detected,Detected" eventfld.long 0x00 18. " SPO ,Set power off" "No effect,Clear" textline " " eventfld.long 0x00 17. " EO ,Power off request" "Not requested,Requested" eventfld.long 0x00 16. " ESVD ,External security violation detected" "Not detected,Detected" eventfld.long 0x00 10. " ET2D ,External tampering 2 detected" "Not detected,Detected" eventfld.long 0x00 9. " ET1D ,External tampering 1 detected" "Not detected,Detected" textline " " eventfld.long 0x00 8. " WMT2D ,Wire-Mesh tampering 2 detected" "Not detected,Detected" eventfld.long 0x00 7. " WMT1D ,Wire-Mesh tampering 1 detected" "Not detected,Detected" eventfld.long 0x00 6. " VTD ,Voltage tampering detected" "Not detected,Detected" eventfld.long 0x00 5. " TTD ,Temperature tamper detected" "Not detected,Detected" textline " " eventfld.long 0x00 4. " CTD ,Clock tampering detected" "Not detected,Detected" eventfld.long 0x00 3. " PGD ,Power supply glitch detected" "Not detected,Detected" eventfld.long 0x00 2. " MCR ,Monotonic counter rollover" "No rollover,Rollover" eventfld.long 0x00 1. " SRTCR ,Monotonic counter rollover" "No rollover,Rollover" textline " " eventfld.long 0x00 0. " LPTA ,LP time alarm" "No interrupt,Interrupt" if (((per.l(ad:0x30370000)&0x04)==0x00)&&((per.l(ad:0x30370000+0x34)&0x04)==0x00)&&((per.l(ad:0x30370000+0x38)&0x01)==0x00)) group.long 0x50++0x07 line.long 0x00 "LPSRTCMR,LP Secure Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " SRTC ,LP secure real time counter" line.long 0x04 "LPSRTCLR,LP Secure Real Time Counter LSB Register" else rgroup.long 0x50++0x07 line.long 0x00 "LPSRTCMR,LP Secure Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " SRTC ,LP secure real time counter" line.long 0x04 "LPSRTCLR,LP Secure Real Time Counter LSB Register" endif if ((per.l(ad:0x30370000+0x38)&0x02)==0x00) group.long 0x58++0x03 line.long 0x00 "LPTAR,LP Time Alarm Register" else rgroup.long 0x58++0x03 line.long 0x00 "LPTAR,LP Time Alarm Register" endif rgroup.long 0x5C++0x07 line.long 0x00 "LPSMCMR,LP Secure Monotonic Counter MSB Register" hexmask.long.word 0x00 16.--31. 1. " MC_ERA_BITS ,Monotonic counter era bits" hexmask.long.word 0x00 0.--15. 1. " MON_COUNTER ,Monotonic counter most-significant 16 bits" line.long 0x04 "LPSMCLR,LP Secure Monotonic Counter LSB Register" group.long 0x64++0x03 line.long 0x00 "LPPGDR,LP Power Glitch Detector Register" if (((per.l(ad:0x30370000)&0x20)==0x00)&&((per.l(ad:0x30370000+0x34)&0x20)==0x00)) group.long 0x68++0x03 line.long 0x00 "LPGPR,LP General Purpose Register" else rgroup.long 0x68++0x03 line.long 0x00 "LPGPR,LP General Purpose Register" endif sif cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4") if (((per.l(ad:0x30370000+0x3C)&0x04)==0x00)&&((per.l(ad:0x30370000)&0x02)==0x00)&&((per.l(ad:0x30370000+0x34)&0x02)==0x00)) group.byte 0x6C++0x03 line.byte 0x00 "LPZMKR0,LP Zeroizable Master Key Register 0" group.byte 0x70++0x03 line.byte 0x00 "LPZMKR1,LP Zeroizable Master Key Register 1" group.byte 0x74++0x03 line.byte 0x00 "LPZMKR2,LP Zeroizable Master Key Register 2" group.byte 0x78++0x03 line.byte 0x00 "LPZMKR3,LP Zeroizable Master Key Register 3" group.byte 0x7C++0x03 line.byte 0x00 "LPZMKR4,LP Zeroizable Master Key Register 4" group.byte 0x80++0x03 line.byte 0x00 "LPZMKR5,LP Zeroizable Master Key Register 5" group.byte 0x84++0x03 line.byte 0x00 "LPZMKR6,LP Zeroizable Master Key Register 6" group.byte 0x88++0x03 line.byte 0x00 "LPZMKR7,LP Zeroizable Master Key Register 7" else rgroup.byte 0x6C++0x03 line.byte 0x00 "LPZMKR0,LP Zeroizable Master Key Register 0" rgroup.byte 0x70++0x03 line.byte 0x00 "LPZMKR1,LP Zeroizable Master Key Register 1" rgroup.byte 0x74++0x03 line.byte 0x00 "LPZMKR2,LP Zeroizable Master Key Register 2" rgroup.byte 0x78++0x03 line.byte 0x00 "LPZMKR3,LP Zeroizable Master Key Register 3" rgroup.byte 0x7C++0x03 line.byte 0x00 "LPZMKR4,LP Zeroizable Master Key Register 4" rgroup.byte 0x80++0x03 line.byte 0x00 "LPZMKR5,LP Zeroizable Master Key Register 5" rgroup.byte 0x84++0x03 line.byte 0x00 "LPZMKR6,LP Zeroizable Master Key Register 6" rgroup.byte 0x88++0x03 line.byte 0x00 "LPZMKR7,LP Zeroizable Master Key Register 7" endif else if (((per.l(ad:0x30370000+0x3C)&0x04)==0x00)&&((per.l(ad:0x30370000)&0x02)==0x00)&&((per.l(ad:0x30370000+0x34)&0x02)==0x00)) group.byte 0x6C++0x31 line.byte 0x0 "LPZMKR0,LP Zeroizable Master Key Register 0" line.byte 0x1 "LPZMKR1,LP Zeroizable Master Key Register 1" line.byte 0x2 "LPZMKR2,LP Zeroizable Master Key Register 2" line.byte 0x3 "LPZMKR3,LP Zeroizable Master Key Register 3" line.byte 0x4 "LPZMKR4,LP Zeroizable Master Key Register 4" line.byte 0x5 "LPZMKR5,LP Zeroizable Master Key Register 5" line.byte 0x6 "LPZMKR6,LP Zeroizable Master Key Register 6" line.byte 0x7 "LPZMKR7,LP Zeroizable Master Key Register 7" line.byte 0x8 "LPZMKR8,LP Zeroizable Master Key Register 8" line.byte 0x9 "LPZMKR9,LP Zeroizable Master Key Register 9" line.byte 0xA "LPZMKR10,LP Zeroizable Master Key Register 10" line.byte 0xB "LPZMKR11,LP Zeroizable Master Key Register 11" line.byte 0xC "LPZMKR12,LP Zeroizable Master Key Register 12" line.byte 0xD "LPZMKR13,LP Zeroizable Master Key Register 13" line.byte 0xE "LPZMKR14,LP Zeroizable Master Key Register 14" line.byte 0xF "LPZMKR15,LP Zeroizable Master Key Register 15" line.byte 0x10 "LPZMKR16,LP Zeroizable Master Key Register 16" line.byte 0x11 "LPZMKR17,LP Zeroizable Master Key Register 17" line.byte 0x12 "LPZMKR18,LP Zeroizable Master Key Register 18" line.byte 0x13 "LPZMKR19,LP Zeroizable Master Key Register 19" line.byte 0x14 "LPZMKR20,LP Zeroizable Master Key Register 20" line.byte 0x15 "LPZMKR21,LP Zeroizable Master Key Register 21" line.byte 0x16 "LPZMKR22,LP Zeroizable Master Key Register 22" line.byte 0x17 "LPZMKR23,LP Zeroizable Master Key Register 23" line.byte 0x18 "LPZMKR24,LP Zeroizable Master Key Register 24" line.byte 0x19 "LPZMKR25,LP Zeroizable Master Key Register 25" line.byte 0x1A "LPZMKR26,LP Zeroizable Master Key Register 26" line.byte 0x1B "LPZMKR27,LP Zeroizable Master Key Register 27" line.byte 0x1C "LPZMKR28,LP Zeroizable Master Key Register 28" line.byte 0x1D "LPZMKR29,LP Zeroizable Master Key Register 29" line.byte 0x1E "LPZMKR30,LP Zeroizable Master Key Register 30" line.byte 0x1F "LPZMKR31,LP Zeroizable Master Key Register 31" else rgroup.byte 0x6C++0x31 line.byte 0x0 "LPZMKR0,LP Zeroizable Master Key Register 0" line.byte 0x1 "LPZMKR1,LP Zeroizable Master Key Register 1" line.byte 0x2 "LPZMKR2,LP Zeroizable Master Key Register 2" line.byte 0x3 "LPZMKR3,LP Zeroizable Master Key Register 3" line.byte 0x4 "LPZMKR4,LP Zeroizable Master Key Register 4" line.byte 0x5 "LPZMKR5,LP Zeroizable Master Key Register 5" line.byte 0x6 "LPZMKR6,LP Zeroizable Master Key Register 6" line.byte 0x7 "LPZMKR7,LP Zeroizable Master Key Register 7" line.byte 0x8 "LPZMKR8,LP Zeroizable Master Key Register 8" line.byte 0x9 "LPZMKR9,LP Zeroizable Master Key Register 9" line.byte 0xA "LPZMKR10,LP Zeroizable Master Key Register 10" line.byte 0xB "LPZMKR11,LP Zeroizable Master Key Register 11" line.byte 0xC "LPZMKR12,LP Zeroizable Master Key Register 12" line.byte 0xD "LPZMKR13,LP Zeroizable Master Key Register 13" line.byte 0xE "LPZMKR14,LP Zeroizable Master Key Register 14" line.byte 0xF "LPZMKR15,LP Zeroizable Master Key Register 15" line.byte 0x10 "LPZMKR16,LP Zeroizable Master Key Register 16" line.byte 0x11 "LPZMKR17,LP Zeroizable Master Key Register 17" line.byte 0x12 "LPZMKR18,LP Zeroizable Master Key Register 18" line.byte 0x13 "LPZMKR19,LP Zeroizable Master Key Register 19" line.byte 0x14 "LPZMKR20,LP Zeroizable Master Key Register 20" line.byte 0x15 "LPZMKR21,LP Zeroizable Master Key Register 21" line.byte 0x16 "LPZMKR22,LP Zeroizable Master Key Register 22" line.byte 0x17 "LPZMKR23,LP Zeroizable Master Key Register 23" line.byte 0x18 "LPZMKR24,LP Zeroizable Master Key Register 24" line.byte 0x19 "LPZMKR25,LP Zeroizable Master Key Register 25" line.byte 0x1A "LPZMKR26,LP Zeroizable Master Key Register 26" line.byte 0x1B "LPZMKR27,LP Zeroizable Master Key Register 27" line.byte 0x1C "LPZMKR28,LP Zeroizable Master Key Register 28" line.byte 0x1D "LPZMKR29,LP Zeroizable Master Key Register 29" line.byte 0x1E "LPZMKR30,LP Zeroizable Master Key Register 30" line.byte 0x1F "LPZMKR31,LP Zeroizable Master Key Register 31" endif endif if (((per.l(ad:0x30370000)&0x20)==0x00)&&((per.l(ad:0x30370000+0x34)&0x20)==0x00)) group.long 0x90++0x03 line.long 0x00 "LPGPR0_30,SNVS_LP General Purposes 0" group.long 0x94++0x03 line.long 0x00 "LPGPR0_31,SNVS_LP General Purposes 1" group.long 0x98++0x03 line.long 0x00 "LPGPR0_32,SNVS_LP General Purposes 2" group.long 0x9C++0x03 line.long 0x00 "LPGPR0_33,SNVS_LP General Purposes 3" else rgroup.long 0x90++0x03 line.long 0x00 "LPGPR0_30,SNVS_LP General Purposes 0" rgroup.long 0x94++0x03 line.long 0x00 "LPGPR0_31,SNVS_LP General Purposes 1" rgroup.long 0x98++0x03 line.long 0x00 "LPGPR0_32,SNVS_LP General Purposes 2" rgroup.long 0x9C++0x03 line.long 0x00 "LPGPR0_33,SNVS_LP General Purposes 3" endif if (((per.l(ad:0x30370000)&0x100)==0x00)&&((per.l(ad:0x30370000+0x34)&0x100)==0x00)) group.long 0xA0++0x03 line.long 0x00 "LPTDC2R,LP Tamper Detectors Config 2" bitfld.long 0x00 23. " ET10P ,External tampering 10 polarity" "Low,High" bitfld.long 0x00 22. " ET9P ,External tampering 9 polarity" "Low,High" bitfld.long 0x00 21. " ET8P ,External tampering 8 polarity" "Low,High" bitfld.long 0x00 20. " ET7P ,External tampering 7 polarity" "Low,High" textline " " bitfld.long 0x00 19. " ET6P ,External tampering 6 polarity" "Low,High" bitfld.long 0x00 18. " ET5P ,External tampering 5 polarity" "Low,High" bitfld.long 0x00 17. " ET4P ,External tampering 4 polarity" "Low,High" bitfld.long 0x00 16. " ET3P ,External tampering 3 polarity" "Low,High" textline " " bitfld.long 0x00 7. " ET10_EN ,External tampering 10 enable" "Disabled,Enabled" bitfld.long 0x00 6. " ET9_EN ,External tampering 9 enable" "Disabled,Enabled" bitfld.long 0x00 5. " ET8_EN ,External tampering 8 enable" "Disabled,Enabled" bitfld.long 0x00 4. " ET7_EN ,External tampering 7 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ET6_EN ,External tampering 6 enable" "Disabled,Enabled" bitfld.long 0x00 2. " ET5_EN ,External tampering 5 enable" "Disabled,Enabled" bitfld.long 0x00 1. " ET4_EN ,External tampering 4 enable" "Disabled,Enabled" bitfld.long 0x00 0. " ET3_EN ,External tampering 3 enable" "Disabled,Enabled" else rgroup.long 0xA0++0x03 line.long 0x00 "LPTDC2R,LP Tamper Detectors Config 2" bitfld.long 0x00 23. " ET10P ,External tampering 10 polarity" "Low,High" bitfld.long 0x00 22. " ET9P ,External tampering 9 polarity" "Low,High" bitfld.long 0x00 21. " ET8P ,External tampering 8 polarity" "Low,High" bitfld.long 0x00 20. " ET7P ,External tampering 7 polarity" "Low,High" textline " " bitfld.long 0x00 19. " ET6P ,External tampering 6 polarity" "Low,High" bitfld.long 0x00 18. " ET5P ,External tampering 5 polarity" "Low,High" bitfld.long 0x00 17. " ET4P ,External tampering 4 polarity" "Low,High" bitfld.long 0x00 16. " ET3P ,External tampering 3 polarity" "Low,High" textline " " bitfld.long 0x00 7. " ET10_EN ,External tampering 10 enable" "Disabled,Enabled" bitfld.long 0x00 6. " ET9_EN ,External tampering 9 enable" "Disabled,Enabled" bitfld.long 0x00 5. " ET8_EN ,External tampering 8 enable" "Disabled,Enabled" bitfld.long 0x00 4. " ET7_EN ,External tampering 7 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ET6_EN ,External tampering 6 enable" "Disabled,Enabled" bitfld.long 0x00 2. " ET5_EN ,External tampering 5 enable" "Disabled,Enabled" bitfld.long 0x00 1. " ET4_EN ,External tampering 4 enable" "Disabled,Enabled" bitfld.long 0x00 0. " ET3_EN ,External tampering 3 enable" "Disabled,Enabled" endif group.long 0xA4++0x03 line.long 0x00 "LPTDSR,LP Tamper Detectors Status" eventfld.long 0x00 7. " ET10D ,External tampering 10 detected" "Not detected,Detected" eventfld.long 0x00 6. " ET9D ,External tampering 9 detected" "Not detected,Detected" eventfld.long 0x00 5. " ET8D ,External tampering 8 detected" "Not detected,Detected" eventfld.long 0x00 4. " ET7D ,External tampering 7 detected" "Not detected,Detected" textline " " eventfld.long 0x00 3. " ET6D ,External tampering 6 detected" "Not detected,Detected" eventfld.long 0x00 2. " ET5D ,External tampering 5 detected" "Not detected,Detected" eventfld.long 0x00 1. " ET4D ,External tampering 4 detected" "Not detected,Detected" eventfld.long 0x00 0. " ET3D ,External tampering 3 detected" "Not detected,Detected" if (((per.l(ad:0x30370000)&0x80)==0x00)&&((per.l(ad:0x30370000+0x34)&0x80)==0x00)) group.long 0xA8++0x07 line.long 0x00 "LPTGF1CR,LP Tamper Glitch Filter 1 Configuration" bitfld.long 0x00 31. " ETGF6_EN ,External tamper glitch filter 6 enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " ETGF6 ,External tamper glitch filter 6" bitfld.long 0x00 23. " ETGF5_EN ,External tamper glitch filter 5 enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--22. 1. " ETGF5 ,External tamper glitch filter 5" textline " " bitfld.long 0x00 15. " ETGF4_EN ,External tamper glitch filter 4 enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " ETGF4 ,External tamper glitch filter 4" bitfld.long 0x00 7. " ETGF3_EN ,External tamper glitch filter 3 enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " ETGF3 ,External tamper glitch filter 3" line.long 0x04 "LPTGF2CR,LP Tamper Glitch Filter 2 Configuration" bitfld.long 0x04 31. " ETGF10_EN ,External tamper glitch filter 10 enable" "Disabled,Enabled" hexmask.long.byte 0x04 24.--30. 1. " ETGF10 ,External tamper glitch filter 10" bitfld.long 0x04 23. " ETGF9_EN ,External tamper glitch filter 9 enable" "Disabled,Enabled" hexmask.long.byte 0x04 16.--22. 1. " ETGF9 ,External tamper glitch filter 9" textline " " bitfld.long 0x04 15. " ETGF8_EN ,External tamper glitch filter 8 enable" "Disabled,Enabled" hexmask.long.byte 0x04 8.--14. 1. " ETGF8 ,External tamper glitch filter 8" bitfld.long 0x04 7. " ETGF7_EN ,External tamper glitch filter 7 enable" "Disabled,Enabled" hexmask.long.byte 0x04 0.--6. 1. " ETGF7 ,External tamper glitch filter 7" else rgroup.long 0xA8++0x07 line.long 0x00 "LPTGF1CR,LP Tamper Glitch Filter 1 Configuration" bitfld.long 0x00 31. " ETGF6_EN ,External tamper glitch filter 6 enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " ETGF6 ,External tamper glitch filter 6" bitfld.long 0x00 23. " ETGF5_EN ,External tamper glitch filter 5 enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--22. 1. " ETGF5 ,External tamper glitch filter 5" textline " " bitfld.long 0x00 15. " ETGF4_EN ,External tamper glitch filter 4 enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " ETGF4 ,External tamper glitch filter 4" bitfld.long 0x00 7. " ETGF3_EN ,External tamper glitch filter 3 enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " ETGF3 ,External tamper glitch filter 3" line.long 0x04 "LPTGF2CR,LP Tamper Glitch Filter 2 Configuration" bitfld.long 0x04 31. " ETGF10_EN ,External tamper glitch filter 10 enable" "Disabled,Enabled" hexmask.long.byte 0x04 24.--30. 1. " ETGF10 ,External tamper glitch filter 10" bitfld.long 0x04 23. " ETGF9_EN ,External tamper glitch filter 9 enable" "Disabled,Enabled" hexmask.long.byte 0x04 16.--22. 1. " ETGF9 ,External tamper glitch filter 9" textline " " bitfld.long 0x04 15. " ETGF8_EN ,External tamper glitch filter 8 enable" "Disabled,Enabled" hexmask.long.byte 0x04 8.--14. 1. " ETGF8 ,External tamper glitch filter 8" bitfld.long 0x04 7. " ETGF7_EN ,External tamper glitch filter 7 enable" "Disabled,Enabled" hexmask.long.byte 0x04 0.--6. 1. " ETGF7 ,External tamper glitch filter 7" endif if ((per.l(ad:0x30370000+0x38)&0x02)==0x00) wgroup.long 0xC0++0x13 line.long 0x0 "LPAT1CR,LP Active Tamper 1 Configuration" hexmask.long.word 0x0 16.--31. 1. " POLYNOMIAL ,Active tamper 1 polynomial" hexmask.long.word 0x0 0.--15. 1. " SEED ,Active tamper 1 initial seed" line.long 0x4 "LPAT2CR,LP Active Tamper 2 Configuration" hexmask.long.word 0x4 16.--31. 1. " POLYNOMIAL ,Active tamper 2 polynomial" hexmask.long.word 0x4 0.--15. 1. " SEED ,Active tamper 2 initial seed" line.long 0x8 "LPAT3CR,LP Active Tamper 3 Configuration" hexmask.long.word 0x8 16.--31. 1. " POLYNOMIAL ,Active tamper 3 polynomial" hexmask.long.word 0x8 0.--15. 1. " SEED ,Active tamper 3 initial seed" line.long 0xC "LPAT4CR,LP Active Tamper 4 Configuration" hexmask.long.word 0xC 16.--31. 1. " POLYNOMIAL ,Active tamper 4 polynomial" hexmask.long.word 0xC 0.--15. 1. " SEED ,Active tamper 4 initial seed" line.long 0x10 "LPAT5CR,LP Active Tamper 5 Configuration" hexmask.long.word 0x10 16.--31. 1. " POLYNOMIAL ,Active tamper 5 polynomial" hexmask.long.word 0x10 0.--15. 1. " SEED ,Active tamper 5 initial seed" else rgroup.long 0xC0++0x13 line.long 0x0 "LPAT1CR,LP Active Tamper 1 Configuration" hexmask.long.word 0x0 16.--31. 1. " POLYNOMIAL ,Active tamper 1 polynomial" hexmask.long.word 0x0 0.--15. 1. " SEED ,Active tamper 1 initial seed" line.long 0x4 "LPAT2CR,LP Active Tamper 2 Configuration" hexmask.long.word 0x4 16.--31. 1. " POLYNOMIAL ,Active tamper 2 polynomial" hexmask.long.word 0x4 0.--15. 1. " SEED ,Active tamper 2 initial seed" line.long 0x8 "LPAT3CR,LP Active Tamper 3 Configuration" hexmask.long.word 0x8 16.--31. 1. " POLYNOMIAL ,Active tamper 3 polynomial" hexmask.long.word 0x8 0.--15. 1. " SEED ,Active tamper 3 initial seed" line.long 0xC "LPAT4CR,LP Active Tamper 4 Configuration" hexmask.long.word 0xC 16.--31. 1. " POLYNOMIAL ,Active tamper 4 polynomial" hexmask.long.word 0xC 0.--15. 1. " SEED ,Active tamper 4 initial seed" line.long 0x10 "LPAT5CR,LP Active Tamper 5 Configuration" hexmask.long.word 0x10 16.--31. 1. " POLYNOMIAL ,Active tamper 5 polynomial" hexmask.long.word 0x10 0.--15. 1. " SEED ,Active tamper 5 initial seed" endif group.long 0xE0++0x0F line.long 0x00 "LPATCTLR,LP Active Tamper Control" bitfld.long 0x00 20. " AT5_PAD_EN ,Active tamper 5 pad out enable" "Disabled,Enabled" bitfld.long 0x00 19. " AT4_PAD_EN ,Active tamper 4 pad out enable" "Disabled,Enabled" bitfld.long 0x00 18. " AT3_PAD_EN ,Active tamper 3 pad out enable" "Disabled,Enabled" bitfld.long 0x00 17. " AT2_PAD_EN ,Active tamper 2 pad out enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " AT1_PAD_EN ,Active tamper 1 pad out enable" "Disabled,Enabled" bitfld.long 0x00 4. " AT5_EN ,Active tamper 5 enable" "Disabled,Enabled" bitfld.long 0x00 3. " AT5_EN ,Active tamper 4 enable" "Disabled,Enabled" bitfld.long 0x00 2. " AT5_EN ,Active tamper 3 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " AT5_EN ,Active tamper 2 enable" "Disabled,Enabled" bitfld.long 0x00 0. " AT5_EN ,Active tamper 1 enable" "Disabled,Enabled" line.long 0x04 "LPATCLKR,LP Active Tamper Clock Control" bitfld.long 0x04 16.--17. " AT5_CLK_CTL ,Active tamper 5 clock control" "16hz,8hz,4hz,2hz" bitfld.long 0x04 12.--13. " AT4_CLK_CTL ,Active tamper 4 clock control" "16hz,8hz,4hz,2hz" bitfld.long 0x04 8.--9. " AT3_CLK_CTL ,Active tamper 3 clock control" "16hz,8hz,4hz,2hz" bitfld.long 0x04 4.--5. " AT2_CLK_CTL ,Active tamper 2 clock control" "16hz,8hz,4hz,2hz" textline " " bitfld.long 0x04 0.--1. " AT1_CLK_CTL ,Active tamper 1 clock control" "16hz,8hz,4hz,2hz" line.long 0x08 "LPATRC1R,LP Active Tamper Routing Control 1" bitfld.long 0x08 28.--30. " ET8RCTL ,External tamper 8 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x08 24.--26. " ET7RCTL ,External tamper 7 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x08 20.--22. " ET6RCTL ,External tamper 6 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x08 16.--18. " ET5RCTL ,External tamper 5 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." textline " " bitfld.long 0x08 12.--14. " ET4RCTL ,External tamper 4 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x08 8.--10. " ET3RCTL ,External tamper 3 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x08 4.--6. " ET2RCTL ,External tamper 2 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x08 0.--2. " ET1RCTL ,External tamper 1 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." line.long 0x0C "LPATRC2R,LP Active Tamper Routing Control 2" bitfld.long 0x0C 4.--6. " ET10RCTL ,External tamper 10 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x0C 0.--2. " ET9RCTL ,External tamper 9 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." rgroup.long 0xBF8++0x07 line.long 0x00 "HPVIDR1,HP Version ID Register 1" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,SNVS block ID" hexmask.long.byte 0x00 8.--15. 1. " MAJOR_REV ,SNVS block major version number" hexmask.long.byte 0x00 0.--7. 1. " MINOR_REV ,SNVS block minor version number" line.long 0x04 "HPVIDR2,HP Version ID Register 2" hexmask.long.byte 0x04 24.--31. 1. " IP_ERA ,Era of the IP design" hexmask.long.byte 0x04 16.--23. 1. " INTG_OPT ,SNVS integration option" hexmask.long.byte 0x04 8.--15. 1. " ECO_REV ,SNVS ECO revision" hexmask.long.byte 0x04 0.--7. 1. " CONFIG_OPT ,SNVS configuration option" width 0x0B tree.end tree "SRC (System Reset Controller)" base ad:0x30390000 width 14. if ((per.l(ad:0x30390000)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "SCR,SRC Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 4.--7. " MASK_TEMPSENSE_RESET ,Mask tempsense_reset source" ",,,,,Masked,,,,,Not masked,?..." else group.long 0x00++0x03 line.long 0x00 "SCR,SRC Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 4.--7. " MASK_TEMPSENSE_RESET ,Mask tempsense_reset source" ",,,,,Masked,,,,,Not masked,?..." endif if ((per.l(ad:0x30390000+0x04)&0x40000000)==0x40000000) group.long 0x04++0x03 line.long 0x00 "A53RCR0,A53 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 21. " A53_L2RESET ,Software reset for A53 snoop control unit" "No reset,Reset" bitfld.long 0x00 20. " A53_SOC_DBG_RESET ,Software reset for system level debug reset" "No reset,Reset" bitfld.long 0x00 16.--19. " MASK_WDOG1_RST ,Mask wdog1_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 15. " A53_ETM_RESET3 ,Software reset for core3 ETM only" "No reset,Reset" bitfld.long 0x00 14. " A53_ETM_RESET2 ,Software reset for core2 ETM only" "No reset,Reset" bitfld.long 0x00 13. " A53_ETM_RESET1 ,Software reset for core1 ETM only" "No reset,Reset" textline " " bitfld.long 0x00 12. " A53_ETM_RESET0 ,Software reset for core0 ETM only" "No reset,Reset" bitfld.long 0x00 11. " A53_DBG_RESET3 ,Software reset for core3 debug only" "No reset,Reset" bitfld.long 0x00 10. " A53_DBG_RESET2 ,Software reset for core2 debug only" "No reset,Reset" textline " " bitfld.long 0x00 9. " A53_DBG_RESET1 ,Software reset for core1 debug only" "No reset,Reset" bitfld.long 0x00 8. " A53_DBG_RESET0 ,Software reset for core0 debug only" "No reset,Reset" bitfld.long 0x00 7. " A53_CORE_RESET3 ,Software reset for core3 only" "No reset,Reset" textline " " bitfld.long 0x00 6. " A53_CORE_RESET2 ,Software reset for core2 only" "No reset,Reset" bitfld.long 0x00 5. " A53_CORE_RESET1 ,Software reset for core1 only" "No reset,Reset" bitfld.long 0x00 4. " A53_CORE_RESET0 ,Software reset for core0 only" "No reset,Reset" textline " " bitfld.long 0x00 3. " A53_CORE_POR_RESET3 ,POR reset for A53 core3 only" "No reset,Reset" bitfld.long 0x00 2. " A53_CORE_POR_RESET2 ,POR reset for A53 core2 only" "No reset,Reset" bitfld.long 0x00 1. " A53_CORE_POR_RESET1 ,POR reset for A53 core1 only" "No reset,Reset" textline " " bitfld.long 0x00 0. " A53_CORE_POR_RESET0 ,POR reset for A53 core0 only" "No reset,Reset" else group.long 0x04++0x03 line.long 0x00 "A53RCR0,A53 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 21. " A53_L2RESET ,Software reset for A53 snoop control unit" "No reset,Reset" bitfld.long 0x00 20. " A53_SOC_DBG_RESET ,Software reset for system level debug reset" "No reset,Reset" bitfld.long 0x00 16.--19. " MASK_WDOG1_RST ,Mask wdog1_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 15. " A53_ETM_RESET3 ,Software reset for core3 ETM only" "No reset,Reset" bitfld.long 0x00 14. " A53_ETM_RESET2 ,Software reset for core2 ETM only" "No reset,Reset" bitfld.long 0x00 13. " A53_ETM_RESET1 ,Software reset for core1 ETM only" "No reset,Reset" textline " " bitfld.long 0x00 12. " A53_ETM_RESET0 ,Software reset for core0 ETM only" "No reset,Reset" bitfld.long 0x00 11. " A53_DBG_RESET3 ,Software reset for core3 debug only" "No reset,Reset" bitfld.long 0x00 10. " A53_DBG_RESET2 ,Software reset for core2 debug only" "No reset,Reset" textline " " bitfld.long 0x00 9. " A53_DBG_RESET1 ,Software reset for core1 debug only" "No reset,Reset" bitfld.long 0x00 8. " A53_DBG_RESET0 ,Software reset for core0 debug only" "No reset,Reset" bitfld.long 0x00 7. " A53_CORE_RESET3 ,Software reset for core3 only" "No reset,Reset" textline " " bitfld.long 0x00 6. " A53_CORE_RESET2 ,Software reset for core2 only" "No reset,Reset" bitfld.long 0x00 5. " A53_CORE_RESET1 ,Software reset for core1 only" "No reset,Reset" bitfld.long 0x00 4. " A53_CORE_RESET0 ,Software reset for core0 only" "No reset,Reset" textline " " bitfld.long 0x00 3. " A53_CORE_POR_RESET3 ,POR reset for A53 core3 only" "No reset,Reset" bitfld.long 0x00 2. " A53_CORE_POR_RESET2 ,POR reset for A53 core2 only" "No reset,Reset" bitfld.long 0x00 1. " A53_CORE_POR_RESET1 ,POR reset for A53 core1 only" "No reset,Reset" textline " " bitfld.long 0x00 0. " A53_CORE_POR_RESET0 ,POR reset for A53 core0 only" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x08)&0x40000000)==0x40000000) group.long 0x08++0x03 line.long 0x00 "A53RCR1,A53 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 4.--6. " A35_RST_SLOW ,Slow reset" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " A53_CORE3_ENABLE ,Core 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " A53_CORE2_ENABLE ,Core 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " A53_CORE1_ENABLE ,Core 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " A53_CORE0_ENABLE ,Core 0 enable" ",Enabled" else group.long 0x08++0x03 line.long 0x00 "A53RCR1,A53 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 4.--6. " A35_RST_SLOW ,Slow reset" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " A53_CORE3_ENABLE ,Core 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " A53_CORE2_ENABLE ,Core 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " A53_CORE1_ENABLE ,Core 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " A53_CORE0_ENABLE ,Core 0 enable" ",Enabled" endif if ((per.l(ad:0x30390000+0x0C)&0x40000200)==0x40000200) group.long 0x0C++0x03 line.long 0x00 "M4RCR,M4 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 9. " WDOG3_RST_OPTION ,Wdog3_rst_b option" "M4 reset,Global reset" bitfld.long 0x00 8. " WDOG3_RST_OPTION_M4 ,Wdog3_rst_b option for M4" "M4 core reset,M4 core and platform reset" bitfld.long 0x00 4.--7. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 3. " ENABLE_M4 ,Enable M4" "Disabled,Enabled" bitfld.long 0x00 2. " SW_M4P_RST ,Self-clearing SW reset for M4 platform" "No reset,Reset" bitfld.long 0x00 1. " SW_M4C_RST ,Self-clearing SW reset for M4 core" "No reset,Reset" textline " " bitfld.long 0x00 0. " SW_M4C_MON_SCLR_RST ,Non-self-clearing SW reset for M4 core" "No reset,Reset" elif ((per.l(ad:0x30390000+0x0C)&0x40000200)==0x40000000) group.long 0x0C++0x03 line.long 0x00 "M4RCR,M4 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 9. " WDOG3_RST_OPTION ,Wdog3_rst_b option" "M4 reset,Global reset" bitfld.long 0x00 4.--7. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 3. " ENABLE_M4 ,Enable M4" "Disabled,Enabled" bitfld.long 0x00 2. " SW_M4P_RST ,Self-clearing SW reset for M4 platform" "No reset,Reset" bitfld.long 0x00 1. " SW_M4C_RST ,Self-clearing SW reset for M4 core" "No reset,Reset" textline " " bitfld.long 0x00 0. " SW_M4C_MON_SCLR_RST ,Non-self-clearing SW reset for M4 core" "No reset,Reset" elif ((per.l(ad:0x30390000+0x0C)&0x40000200)==0x200) group.long 0x0C++0x03 line.long 0x00 "M4RCR,M4 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 9. " WDOG3_RST_OPTION ,Wdog3_rst_b option" "M4 reset,Global reset" bitfld.long 0x00 8. " WDOG3_RST_OPTION_M4 ,Wdog3_rst_b option for M4" "M4 core reset,M4 core and platform reset" bitfld.long 0x00 4.--7. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 3. " ENABLE_M4 ,Enable M4" "Disabled,Enabled" bitfld.long 0x00 2. " SW_M4P_RST ,Self-clearing SW reset for M4 platform" "No reset,Reset" bitfld.long 0x00 1. " SW_M4C_RST ,Self-clearing SW reset for M4 core" "No reset,Reset" textline " " bitfld.long 0x00 0. " SW_M4C_MON_SCLR_RST ,Non-self-clearing SW reset for M4 core" "No reset,Reset" else group.long 0x0C++0x03 line.long 0x00 "M4RCR,M4 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 9. " WDOG3_RST_OPTION ,Wdog3_rst_b option" "M4 reset,Global reset" bitfld.long 0x00 4.--7. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 3. " ENABLE_M4 ,Enable M4" "Disabled,Enabled" bitfld.long 0x00 2. " SW_M4P_RST ,Self-clearing SW reset for M4 platform" "No reset,Reset" bitfld.long 0x00 1. " SW_M4C_RST ,Self-clearing SW reset for M4 core" "No reset,Reset" textline " " bitfld.long 0x00 0. " SW_M4C_MON_SCLR_RST ,Non-self-clearing SW reset for M4 core" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x20)&0x40000000)==0x40000000) group.long 0x20++0x03 line.long 0x00 "USBOPHY1_RCR,USB OTG PHY1 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 0. " OTG1_PHY_RESET ,USB OTG PHY 1 POR" "No reset,Reset" else group.long 0x20++0x03 line.long 0x00 "USBOPHY1_RCR,USB OTG PHY1 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 0. " OTG1_PHY_RESET ,USB OTG PHY 1 POR" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x24)&0x40000000)==0x40000000) group.long 0x24++0x03 line.long 0x00 "USBOPHY1_RCR,USB OTG PHY1 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 0. " OTG1_PHY_RESET ,USB OTG PHY 1 POR" "No reset,Reset" else group.long 0x24++0x03 line.long 0x00 "USBOPHY1_RCR,USB OTG PHY1 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 0. " OTG2_PHY_RESET ,USB OTG PHY 2 POR" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x28)&0x40000000)==0x40000000) group.long 0x28++0x03 line.long 0x00 "MIPIPHY_RCR,MIPI PHY Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 5. " MIPI_DIS_PCLK_RESET_N ,MIPI DIS PCLK reset N" "Reset,No reset" bitfld.long 0x00 4. " MIPI_DIS_ESC_RESET_N ,MIPI DIS ESC reset N" "Reset,No reset" bitfld.long 0x00 3. " MIPI_DIS_DPI_RESET_N ,MIPI DIS DPI reset N" "Reset,No reset" textline " " bitfld.long 0x00 2. " MIPI_DIS_DSI_RESET_N ,MIPI DIS DSI reset N" "Reset,No reset" bitfld.long 0x00 1. " MIPI_DIS_RESET_BYTE_N ,MIPI DIS reset byte N" "Reset,No reset" else group.long 0x28++0x03 line.long 0x00 "MIPIPHY_RCR,MIPI PHY Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 5. " MIPI_DIS_PCLK_RESET_N ,MIPI DIS PCLK reset N" "Reset,No reset" bitfld.long 0x00 4. " MIPI_DIS_ESC_RESET_N ,MIPI DIS ESC reset N" "Reset,No reset" bitfld.long 0x00 3. " MIPI_DIS_DPI_RESET_N ,MIPI DIS DPI reset N" "Reset,No reset" textline " " bitfld.long 0x00 2. " MIPI_DIS_DSI_RESET_N ,MIPI DIS DSI reset N" "Reset,No reset" bitfld.long 0x00 1. " MIPI_DIS_RESET_BYTE_N ,MIPI DIS reset byte N" "Reset,No reset" endif if ((per.l(ad:0x30390000+0x2C)&0x40000000)==0x40000000) group.long 0x2C++0x03 line.long 0x00 "PCIEPHY_RCR,PCIE PHY Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 16. " PCIE_CTRL_APP_XFRE_PENDIND ,PCIE_CTRL_APP_XFRE_PENDIND" "Not pending,Pending" bitfld.long 0x00 15. " PCIE_CTRL_APP_UNLOCK_MSG ,PCIE_CTRL_APP_UNLOCK_MSG" "Locked,Unlocked" bitfld.long 0x00 14. " PCIE_CTRL_SYS_INT ,PCIE_CTRL_SYS_INT" "0,1" textline " " bitfld.long 0x00 12. " PCIE_CTRL_CFG_L1_AUX ,Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en" "Disabled,Enabled" bitfld.long 0x00 11. " PCIE_CTRL_APPS_TURNOFF ,Pcie_ctrl_apps_pm_xmt_turnoff" "Turned on,Turned off" bitfld.long 0x00 10. " PCIE_CTRL_APPS_PME ,Pcie_ctrl_apps_pm_xmt_pme" "0,1" textline " " bitfld.long 0x00 9. " PCIE_CTRL_APPS_EXIT ,Pcie_ctrl_app_req_exit_l1" "0,1" bitfld.long 0x00 8. " PCIE_CTRL_APPS_ENTER ,Pcie_ctrl_app_req_entr_l1" "Not requested,Requested" bitfld.long 0x00 7. " PCIE_CTRL_APPS_READY ,Pcie_ctrl_app_ready_entr_l23" "Not ready,Ready" textline " " bitfld.long 0x00 6. " PCIE_CTRL_APPS_EN ,Pcie_ctrl_app_ltssm_enable" "Disabled,Enabled" bitfld.long 0x00 5. " PCIE_CTRL_APPS_RST ,Pcie_ctrl_app_init_rst" "No reset,Reset" bitfld.long 0x00 4. " PCIE_CTRL_APPS_CLK_REQ ,Pcie_ctrl_app_clk_req_n" "Not requested,Requested" textline " " bitfld.long 0x00 3. " PCIEPHY_PERST ,Pciephy_perst" "0,1" bitfld.long 0x00 2. " PCIEPHY_BTN ,PCIE PHY button" "0,1" bitfld.long 0x00 1. " PCIEPHY_G_RST ,PCIE PHY global reset" "No reset,Reset" textline " " bitfld.long 0x00 0. " PCIE_PHY_POWER_ON_RESET_N ,PCIE_PHY_POWER_ON_RESET_N" "No reset,Reset" else group.long 0x2C++0x03 line.long 0x00 "PCIEPHY_RCR,PCIE PHY Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 16. " PCIE_CTRL_APP_XFRE_PENDIND ,PCIE_CTRL_APP_XFRE_PENDIND" "Not pending,Pending" bitfld.long 0x00 15. " PCIE_CTRL_APP_UNLOCK_MSG ,PCIE_CTRL_APP_UNLOCK_MSG" "Locked,Unlocked" bitfld.long 0x00 14. " PCIE_CTRL_SYS_INT ,PCIE_CTRL_SYS_INT" "0,1" textline " " bitfld.long 0x00 12. " PCIE_CTRL_CFG_L1_AUX ,Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en" "Disabled,Enabled" bitfld.long 0x00 11. " PCIE_CTRL_APPS_TURNOFF ,Pcie_ctrl_apps_pm_xmt_turnoff" "Turned on,Turned off" bitfld.long 0x00 10. " PCIE_CTRL_APPS_PME ,Pcie_ctrl_apps_pm_xmt_pme" "0,1" textline " " bitfld.long 0x00 9. " PCIE_CTRL_APPS_EXIT ,Pcie_ctrl_app_req_exit_l1" "0,1" bitfld.long 0x00 8. " PCIE_CTRL_APPS_ENTER ,Pcie_ctrl_app_req_entr_l1" "Not requested,Requested" bitfld.long 0x00 7. " PCIE_CTRL_APPS_READY ,Pcie_ctrl_app_ready_entr_l23" "Not ready,Ready" textline " " bitfld.long 0x00 6. " PCIE_CTRL_APPS_EN ,Pcie_ctrl_app_ltssm_enable" "Disabled,Enabled" bitfld.long 0x00 5. " PCIE_CTRL_APPS_RST ,Pcie_ctrl_app_init_rst" "No reset,Reset" bitfld.long 0x00 4. " PCIE_CTRL_APPS_CLK_REQ ,Pcie_ctrl_app_clk_req_n" "Not requested,Requested" textline " " bitfld.long 0x00 3. " PCIEPHY_PERST ,Pciephy_perst" "0,1" bitfld.long 0x00 2. " PCIEPHY_BTN ,PCIE PHY button" "0,1" bitfld.long 0x00 1. " PCIEPHY_G_RST ,PCIE PHY global reset" "No reset,Reset" textline " " bitfld.long 0x00 0. " PCIE_PHY_POWER_ON_RESET_N ,PCIE_PHY_POWER_ON_RESET_N" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x30)&0x40000000)==0x40000000) group.long 0x30++0x03 line.long 0x00 "HDMI_RCR,HDMI Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 0. " HDMI_PHY_APB_RESET ,HDMI PHY APB reset" "No reset,Reset" else group.long 0x30++0x03 line.long 0x00 "HDMI_RCR,HDMI Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 0. " HDMI_PHY_APB_RESET ,HDMI PHY APB reset" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x34)&0x40000000)==0x40000000) group.long 0x34++0x03 line.long 0x00 "DISP_RCR,DISP Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 0. " DISP_RESET ,DISP reset" "No reset,Reset" else group.long 0x34++0x03 line.long 0x00 "DISP_RCR,DISP Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 0. " DISP_RESET ,DISP reset" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x40)&0x40000000)==0x40000000) group.long 0x40++0x03 line.long 0x00 "GPU_RCR,GPU Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 0. " GPU_RESET ,GPU reset" "No reset,Reset" else group.long 0x40++0x03 line.long 0x00 "GPU_RCR,GPU Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 0. " GPU_RESET ,GPU reset" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x44)&0x40000000)==0x40000000) group.long 0x44++0x03 line.long 0x00 "VPU_RCR,VPU Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 0. " VPU_RESET ,VPU reset" "No reset,Reset" else group.long 0x44++0x03 line.long 0x00 "VPU_RCR,VPU Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 0. " VPU_RESET ,VPU reset" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x48)&0x40000000)==0x40000000) group.long 0x48++0x03 line.long 0x00 "PCIE2_RCR,PCIE2 PHY Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 16. " PCIE_CTRL_APP_XFRE_PENDIND ,PCIE_CTRL_APP_XFRE_PENDIND" "Not pending,Pending" bitfld.long 0x00 15. " PCIE_CTRL_APP_UNLOCK_MSG ,PCIE_CTRL_APP_UNLOCK_MSG" "Locked,Unlocked" bitfld.long 0x00 14. " PCIE_CTRL_SYS_INT ,PCIE_CTRL_SYS_INT" "0,1" textline " " bitfld.long 0x00 12. " PCIE_CTRL_CFG_L1_AUX ,Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en" "Disabled,Enabled" bitfld.long 0x00 11. " PCIE_CTRL_APPS_TURNOFF ,Pcie_ctrl_apps_pm_xmt_turnoff" "Turned on,Turned off" bitfld.long 0x00 10. " PCIE_CTRL_APPS_PME ,Pcie_ctrl_apps_pm_xmt_pme" "0,1" textline " " bitfld.long 0x00 9. " PCIE_CTRL_APPS_EXIT ,Pcie_ctrl_app_req_exit_l1" "0,1" bitfld.long 0x00 8. " PCIE_CTRL_APPS_ENTER ,Pcie_ctrl_app_req_entr_l1" "Not requested,Requested" bitfld.long 0x00 7. " PCIE_CTRL_APPS_READY ,Pcie_ctrl_app_ready_entr_l23" "Not ready,Ready" textline " " bitfld.long 0x00 6. " PCIE_CTRL_APPS_EN ,Pcie_ctrl_app_ltssm_enable" "Disabled,Enabled" bitfld.long 0x00 5. " PCIE_CTRL_APPS_RST ,Pcie_ctrl_app_init_rst" "No reset,Reset" bitfld.long 0x00 4. " PCIE_CTRL_APPS_CLK_REQ ,Pcie_ctrl_app_clk_req_n" "Not requested,Requested" textline " " bitfld.long 0x00 3. " PCIE_PERST ,Pcie_perst" "0,1" bitfld.long 0x00 2. " PCIE_BTN ,PCIE2 button" "0,1" bitfld.long 0x00 1. " PCIE_G_RST ,PCIE global reset" "No reset,Reset" textline " " bitfld.long 0x00 0. " PCIE_PHY_POWER_ON_RESET_N ,PCIE_PHY_POWER_ON_RESET_N" "No reset,Reset" else group.long 0x48++0x03 line.long 0x00 "PCIE2_RCR,PCIE2 PHY Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 16. " PCIE_CTRL_APP_XFRE_PENDIND ,PCIE_CTRL_APP_XFRE_PENDIND" "Not pending,Pending" bitfld.long 0x00 15. " PCIE_CTRL_APP_UNLOCK_MSG ,PCIE_CTRL_APP_UNLOCK_MSG" "Locked,Unlocked" bitfld.long 0x00 14. " PCIE_CTRL_SYS_INT ,PCIE_CTRL_SYS_INT" "0,1" textline " " bitfld.long 0x00 12. " PCIE_CTRL_CFG_L1_AUX ,Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en" "Disabled,Enabled" bitfld.long 0x00 11. " PCIE_CTRL_APPS_TURNOFF ,Pcie_ctrl_apps_pm_xmt_turnoff" "Turned on,Turned off" bitfld.long 0x00 10. " PCIE_CTRL_APPS_PME ,Pcie_ctrl_apps_pm_xmt_pme" "0,1" textline " " bitfld.long 0x00 9. " PCIE_CTRL_APPS_EXIT ,Pcie_ctrl_app_req_exit_l1" "0,1" bitfld.long 0x00 8. " PCIE_CTRL_APPS_ENTER ,Pcie_ctrl_app_req_entr_l1" "Not requested,Requested" bitfld.long 0x00 7. " PCIE_CTRL_APPS_READY ,Pcie_ctrl_app_ready_entr_l23" "Not ready,Ready" textline " " bitfld.long 0x00 6. " PCIE_CTRL_APPS_EN ,Pcie_ctrl_app_ltssm_enable" "Disabled,Enabled" bitfld.long 0x00 5. " PCIE_CTRL_APPS_RST ,Pcie_ctrl_app_init_rst" "No reset,Reset" bitfld.long 0x00 4. " PCIE_CTRL_APPS_CLK_REQ ,Pcie_ctrl_app_clk_req_n" "Not requested,Requested" textline " " bitfld.long 0x00 3. " PCIE_PERST ,Pcie_perst" "0,1" bitfld.long 0x00 2. " PCIE_BTN ,PCIE2 button" "0,1" bitfld.long 0x00 1. " PCIE_G_RST ,PCIE global reset" "No reset,Reset" textline " " bitfld.long 0x00 0. " PCIE_PHY_POWER_ON_RESET_N ,PCIE_PHY_POWER_ON_RESET_N" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x4C)&0x40000000)==0x40000000) group.long 0x4C++0x03 line.long 0x00 "MIPIPHY1_RCR,MIPI CSI1 PHY Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 2. " MIPI_CSI1_ESC_RESET ,MPI_CSI1_ESC_RESET" "0,1" bitfld.long 0x00 1. " MIPI_CSI1_PHY_REF_RESET ,MPI_CSI1_PHY_REF_RESET" "No reset,Reset" bitfld.long 0x00 0. " MIPI_CSI1_CORE_RESET ,MIPI_CSI1_CORE_RESET" "No reset,Reset" else group.long 0x4C++0x03 line.long 0x00 "MIPIPHY1_RCR,MIPI CSI1 PHY Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 2. " MIPI_CSI1_ESC_RESET ,MPI_CSI1_ESC_RESET" "0,1" bitfld.long 0x00 1. " MIPI_CSI1_PHY_REF_RESET ,MPI_CSI1_PHY_REF_RESET" "No reset,Reset" bitfld.long 0x00 0. " MIPI_CSI1_CORE_RESET ,MIPI_CSI1_CORE_RESET" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x50)&0x40000000)==0x40000000) group.long 0x50++0x03 line.long 0x00 "MIPIPHY2_RCR,MIPI CSI2 PHY Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 2. " MIPI_CSI2_ESC_RESET ,MPI_CSI1_ESC_RESET" "0,1" bitfld.long 0x00 1. " MIPI_CSI2_PHY_REF_RESET ,MPI_CSI1_PHY_REF_RESET" "No reset,Reset" bitfld.long 0x00 0. " MIPI_CSI2_CORE_RESET ,MIPI_CSI1_CORE_RESET" "No reset,Reset" else group.long 0x50++0x03 line.long 0x00 "MIPIPHY2_RCR,MIPI CSI2 PHY Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 2. " MIPI_CSI2_ESC_RESET ,MPI_CSI2_ESC_RESET" "0,1" bitfld.long 0x00 1. " MIPI_CSI2_PHY_REF_RESET ,MPI_CSI2_PHY_REF_RESET" "No reset,Reset" bitfld.long 0x00 0. " MIPI_CSI2_CORE_RESET ,MIPI_CSI2_CORE_RESET" "No reset,Reset" endif rgroup.long 0x58++0x03 line.long 0x00 "SBMR1,SRC Boot Mode Register 1" group.long 0x5C++0x03 line.long 0x00 "SRSR,SRC Reset Status Register" bitfld.long 0x00 9. " TEMPSENSE_RST_B ,Temper sensor software reset" "No reset,Reset" eventfld.long 0x00 8. " WDOG4_RST_B ,IC watchdog4 Time-out reset" "No reset,Reset" eventfld.long 0x00 7. " WDOG3_RST_B ,IC watchdog3 Time-out reset" "No reset,Reset" textline " " eventfld.long 0x00 6. " JTAG_SW_RST ,JTAG software reset" "No reset,Reset" eventfld.long 0x00 5. " JTAG-_RST_B ,HIGH - Z JTAG reset" "No reset,Reset" eventfld.long 0x00 4. " WDOG1_RST_B ,IC watchdog1 Time-out reset" "No reset,Reset" textline " " eventfld.long 0x00 3. " IPP_USER_RESET_B ,Ipp_user_reset_b qualified reset" "No reset,Reset" eventfld.long 0x00 2. " CSU_RESET_B ,Csu_reset_b input" "No reset,Reset" rgroup.long 0x68++0x07 line.long 0x00 "SISR,SRC Interrupt Status Register" bitfld.long 0x00 14. " MIPI_CSI2_PHY_PASSED_RESET ,MIPI CSI2 PHY passed software reset" "No interrupt,Interrupt" bitfld.long 0x00 13. " MIPI_CSI1_PHY_PASSED_RESET ,MIPI CSI1 PHY passed software reset" "No interrupt,Interrupt" bitfld.long 0x00 12. " PCIE2_PHY_RESET ,PCIE2 PHY passed software reset" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " VPU_PASSED_RESET ,VPU passed software reset" "No interrupt,Interrupt" bitfld.long 0x00 10. " GPU_PHY_PASSED_RESET ,GPU passed software reset" "No interrupt,Interrupt" bitfld.long 0x00 9. " M4P_PASSED_RESET ,M4 platform passed software reset" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " M4C_PASSED_RESET ,M4 core passed software reset" "No interrupt,Interrupt" bitfld.long 0x00 7. " DISPLAY_PASSED_RESET ,DISPLAY passed software reset" "No interrupt,Interrupt" bitfld.long 0x00 6. " HDMI_PASSED_RESET ,HDMI passed software reset" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " PCIE1_PHY_PASSED_RESET ,PCIE1 PHY passed software reset" "No interrupt,Interrupt" bitfld.long 0x00 4. " MIPIPHY_PASSED_RESET ,MIPI PHY passed software reset" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " OTGPHY2_PASSED_RESET ,OTG PHY2 passed software reset" "No interrupt,Interrupt" bitfld.long 0x00 2. " OTGPHY1_PASSED_RESET ,OTG PHY1 passed software reset" "No interrupt,Interrupt" bitfld.long 0x00 1. " HSICPHY_PASSED_RESET ,HSIC PHY passed software reset" "No interrupt,Interrupt" line.long 0x04 "SIMR,SRC Interrupt Mask Register" bitfld.long 0x04 14. " MASK_MIPI_CSI2_PHY_PASSED_RESET ,Mask interrupt generation due to MIPI CSI2 PHY passed reset" "No masked,Masked" bitfld.long 0x04 13. " MASK_MIPI_CSI1_PHY_PASSED_RESET ,Mask interrupt generation due to MIPI CSI1 PHY passed reset" "No masked,Masked" bitfld.long 0x04 12. " MASK_PCIE2_PHY_RESET ,Mask interrupt generation due to PCIE2 PHY passed reset" "No masked,Masked" textline " " bitfld.long 0x04 11. " MASK_VPU_PASSED_RESET ,Mask interrupt generation due to VPU passed reset" "No masked,Masked" bitfld.long 0x04 10. " MASK_GPU_PHY_PASSED_RESET ,Mask interrupt generation due to GPU passed reset" "No masked,Masked" bitfld.long 0x04 9. " MASK_M4P_PASSED_RESET ,Mask interrupt generation due to m4 platform passed reset" "No masked,Masked" textline " " bitfld.long 0x04 8. " MASK_M4C_PASSED_RESET ,Mask interrupt generation due to m4 core passed reset" "No masked,Masked" bitfld.long 0x04 7. " MASK_DISPLAY_PASSED_RESET ,Mask interrupt generation due to DISPLAY passed reset" "No masked,Masked" bitfld.long 0x04 6. " MASK_HDMI_PASSED_RESET ,Mask interrupt generation due to HDMI passed reset" "No masked,Masked" textline " " bitfld.long 0x04 5. " MASK_PCIE1_PHY_PASSED_RESET ,Mask interrupt generation due to PCIE1 PHY passed reset" "No masked,Masked" bitfld.long 0x04 4. " MASK_MIPIPHY_PASSED_RESET ,Mask interrupt generation due to MIPI PHY passed reset" "No masked,Masked" textline " " bitfld.long 0x04 3. " MASK_OTGPHY2_PASSED_RESET ,Mask interrupt generation due to OTG PHY2 passed reset" "No masked,Masked" bitfld.long 0x04 2. " MASK_OTGPHY1_PASSED_RESET ,Mask interrupt generation due to OTG PHY1 passed reset" "No masked,Masked" bitfld.long 0x04 1. " MASK_HSICPHY_PASSED_RESET ,Mask interrupt generation due to HSIC PHY passed reset" "No masked,Masked" if ((per.l(ad:0x30390000+0x70)&0x3000000)==0x2000000) group.long 0x70++0x03 line.long 0x00 "SBMR2,SRC Boot Mode Register 2" bitfld.long 0x00 24.--25. " BMOD ,Boot mode pin settings" "Boot from fuses,Serial downloader,Internal boot,?..." bitfld.long 0x00 5. " FORCE_COLD_BOOT(SBMR) ,Force cold boor" "Allowed fast recovery,Not allowed fast recovery" bitfld.long 0x00 4. " BT_FUSE_SEL ,Determines whether using fuses for boot configuration or gpio/serial loader" "Serial loader,Fuses" textline " " bitfld.long 0x00 3. " DIR_BT_DIS ,Direct external memory boot disable" "No,Yes" bitfld.long 0x00 0.--1. " SEC_CONFIG ,Security configuration" "FAB (Open),Open,Closed,Closed" elif ((per.l(ad:0x30390000+0x70)&0x3000000)==0x00) group.long 0x70++0x03 line.long 0x00 "SBMR2,SRC Boot Mode Register 2" bitfld.long 0x00 24.--25. " BMOD ,Boot mode pin settings" "Boot from fuses,Serial downloader,Internal boot,?..." bitfld.long 0x00 5. " FORCE_COLD_BOOT(SBMR) ,Force cold boor" "Allowed fast recovery,Not allowed fast recovery" bitfld.long 0x00 4. " BT_FUSE_SEL ,Determines whether using fuses for boot configuration or GPIO /serial loader" "GPIO,Fuses" textline " " bitfld.long 0x00 3. " DIR_BT_DIS ,Direct external memory boot disable" "No,Yes" bitfld.long 0x00 0.--1. " SEC_CONFIG ,Security configuration" "FAB (Open),Open,Closed,Closed" else group.long 0x70++0x03 line.long 0x00 "SBMR2,SRC Boot Mode Register 2" bitfld.long 0x00 24.--25. " BMOD ,Boot mode pin settings" "Boot from fuses,Serial downloader,Internal boot,?..." bitfld.long 0x00 5. " FORCE_COLD_BOOT(SBMR) ,Force cold boor" "Allowed fast recovery,Not allowed fast recovery" textline " " bitfld.long 0x00 3. " DIR_BT_DIS ,Direct external memory boot disable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " SEC_CONFIG ,Security configuration" "FAB (Open),Open,Closed,Closed" endif group.long 0x74++0x1F line.long 0x00 "GPR1,SRC General Purpose Register 1" line.long 0x04 "GPR2,SRC General Purpose Register 2" line.long 0x08 "GPR3,SRC General Purpose Register 3" line.long 0x0C "GPR4,SRC General Purpose Register 4" line.long 0x10 "GPR5,SRC General Purpose Register 5" line.long 0x14 "GPR6,SRC General Purpose Register 6" line.long 0x18 "GPR7,SRC General Purpose Register 7" line.long 0x1C "GPR8,SRC General Purpose Register 8" if ((per.l(ad:0x30390000+0x1000)&0x40000000)==0x40000000) group.long 0x1000++0x03 line.long 0x00 "DDRC_RCR,SRC DDR Controller Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 3. " DDRC1_CORE_RST ,DDR controller phy_pwrokin_ddrc1_rstn and aresetn" "No reset,Reset" bitfld.long 0x00 2. " DDRC1_CORE_RST ,DDR controller phy_ddrc1_rstn and aresetn" "No reset,Reset" bitfld.long 0x00 1. " DDRC1_CORE_RST ,DDR controller core_ddrc1_rstn and aresetn" "No reset,Reset" textline " " bitfld.long 0x00 0. " DDRC1_PRST ,DDR controller preset and DDR PHY reset" "No reset,Reset" else group.long 0x1000++0x03 line.long 0x00 "DDRC_RCR,SRC DDR Controller Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 3. " DDRC1_CORE_RST ,DDR controller phy_pwrokin_ddrc1_rstn and aresetn" "No reset,Reset" bitfld.long 0x00 2. " DDRC1_CORE_RST ,DDR controller phy_ddrc1_rstn and aresetn" "No reset,Reset" bitfld.long 0x00 1. " DDRC_CORE_RST ,DDR controller core_ddrc_rstn and aresetn" "No reset,Reset" textline " " bitfld.long 0x00 0. " DDRC_PRST ,DDR controller preset and DDR PHY reset" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x1004)&0x40000000)==0x40000000) group.long 0x1004++0x03 line.long 0x00 "DDRC_RCR,SRC DDRC2 Controller Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 3. " DDRC1_CORE_RST ,DDR controller phy_pwrokin_ddrc1_rstn and aresetn" "No reset,Reset" bitfld.long 0x00 2. " DDRC1_CORE_RST ,DDR controller phy_ddrc1_rstn and aresetn" "No reset,Reset" bitfld.long 0x00 1. " DDRC1_CORE_RST ,DDR controller core_ddrc1_rstn and aresetn" "No reset,Reset" textline " " bitfld.long 0x00 0. " DDRC1_PRST ,DDR controller preset and DDR PHY reset" "No reset,Reset" else group.long 0x1004++0x03 line.long 0x00 "DDRC_RCR,SRC DDRC2 Controller Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 3. " DDRC1_CORE_RST ,DDR controller phy_pwrokin_ddrc1_rstn and aresetn" "No reset,Reset" bitfld.long 0x00 2. " DDRC1_CORE_RST ,DDR controller phy_ddrc1_rstn and aresetn" "No reset,Reset" bitfld.long 0x00 1. " DDRC2_CORE_RST ,DDRC2 controller core_ddrc_rstn and aresetn" "No reset,Reset" textline " " bitfld.long 0x00 0. " DDRC2_PRST ,DDRC2 controller preset and DDR PHY reset" "No reset,Reset" endif width 0x0B tree.end tree.end tree.open "SDMAARM (Smart Direct Memory Access - Arm Platform)" tree "SDMAARM1" base ad:0x30BD0000 width 15. group.long 0x00++0x13 line.long 0x00 "MC0PTR,ARM Platform Channel 0 Pointer Register" line.long 0x04 "INTR,Channel Interrupts Register" eventfld.long 0x04 31. " HI[31] ,Channel interrupt 31" "No interrupt,Interrupt" eventfld.long 0x04 30. " [30] ,Channel interrupt 30" "No interrupt,Interrupt" eventfld.long 0x04 29. " [29] ,Channel interrupt 29" "No interrupt,Interrupt" eventfld.long 0x04 28. " [28] ,Channel interrupt 28" "No interrupt,Interrupt" textline " " eventfld.long 0x04 27. " [27] ,Channel interrupt 27" "No interrupt,Interrupt" eventfld.long 0x04 26. " [26] ,Channel interrupt 26" "No interrupt,Interrupt" eventfld.long 0x04 25. " [25] ,Channel interrupt 25" "No interrupt,Interrupt" eventfld.long 0x04 24. " [24] ,Channel interrupt 24" "No interrupt,Interrupt" textline " " eventfld.long 0x04 23. " [23] ,Channel interrupt 23" "No interrupt,Interrupt" eventfld.long 0x04 22. " [22] ,Channel interrupt 22" "No interrupt,Interrupt" eventfld.long 0x04 21. " [21] ,Channel interrupt 21" "No interrupt,Interrupt" eventfld.long 0x04 20. " [20] ,Channel interrupt 20" "No interrupt,Interrupt" textline " " eventfld.long 0x04 19. " [19] ,Channel interrupt 19" "No interrupt,Interrupt" eventfld.long 0x04 18. " [18] ,Channel interrupt 18" "No interrupt,Interrupt" eventfld.long 0x04 17. " [17] ,Channel interrupt 17" "No interrupt,Interrupt" eventfld.long 0x04 16. " [16] ,Channel interrupt 16" "No interrupt,Interrupt" textline " " eventfld.long 0x04 15. " [15] ,Channel interrupt 15" "No interrupt,Interrupt" eventfld.long 0x04 14. " [14] ,Channel interrupt 14" "No interrupt,Interrupt" eventfld.long 0x04 13. " [13] ,Channel interrupt 13" "No interrupt,Interrupt" eventfld.long 0x04 12. " [12] ,Channel interrupt 12" "No interrupt,Interrupt" textline " " eventfld.long 0x04 11. " [11] ,Channel interrupt 11" "No interrupt,Interrupt" eventfld.long 0x04 10. " [10] ,Channel interrupt 10" "No interrupt,Interrupt" eventfld.long 0x04 9. " [9] ,Channel interrupt 9" "No interrupt,Interrupt" eventfld.long 0x04 8. " [8] ,Channel interrupt 8" "No interrupt,Interrupt" textline " " eventfld.long 0x04 7. " [7] ,Channel interrupt 7" "No interrupt,Interrupt" eventfld.long 0x04 6. " [6] ,Channel interrupt 6" "No interrupt,Interrupt" eventfld.long 0x04 5. " [5] ,Channel interrupt 5" "No interrupt,Interrupt" eventfld.long 0x04 4. " [4] ,Channel interrupt 4" "No interrupt,Interrupt" textline " " eventfld.long 0x04 3. " [3] ,Channel interrupt 3" "No interrupt,Interrupt" eventfld.long 0x04 2. " [2] ,Channel interrupt 2" "No interrupt,Interrupt" eventfld.long 0x04 1. " [1] ,Channel interrupt 1" "No interrupt,Interrupt" eventfld.long 0x04 0. " [0] ,Channel interrupt 0" "No interrupt,Interrupt" line.long 0x08 "STOP_STAT,Channel Stop/channel Status Register" eventfld.long 0x08 31. " HE[31] ,Channel 31 stop/status" "No access,Access" eventfld.long 0x08 30. " [30] ,Channel 30 stop/status" "No access,Access" eventfld.long 0x08 29. " [29] ,Channel 29 stop/status" "No access,Access" eventfld.long 0x08 28. " [28] ,Channel 28 stop/status" "No access,Access" textline " " eventfld.long 0x08 27. " [27] ,Channel 27 stop/status" "No access,Access" eventfld.long 0x08 26. " [26] ,Channel 26 stop/status" "No access,Access" eventfld.long 0x08 25. " [25] ,Channel 25 stop/status" "No access,Access" eventfld.long 0x08 24. " [24] ,Channel 24 stop/status" "No access,Access" textline " " eventfld.long 0x08 23. " [23] ,Channel 23 stop/status" "No access,Access" eventfld.long 0x08 22. " [22] ,Channel 22 stop/status" "No access,Access" eventfld.long 0x08 21. " [21] ,Channel 21 stop/status" "No access,Access" eventfld.long 0x08 20. " [20] ,Channel 20 stop/status" "No access,Access" textline " " eventfld.long 0x08 19. " [19] ,Channel 19 stop/status" "No access,Access" eventfld.long 0x08 18. " [18] ,Channel 18 stop/status" "No access,Access" eventfld.long 0x08 17. " [17] ,Channel 17 stop/status" "No access,Access" eventfld.long 0x08 16. " [16] ,Channel 16 stop/status" "No access,Access" textline " " eventfld.long 0x08 15. " [15] ,Channel 15 stop/status" "No access,Access" eventfld.long 0x08 14. " [14] ,Channel 14 stop/status" "No access,Access" eventfld.long 0x08 13. " [13] ,Channel 13 stop/status" "No access,Access" eventfld.long 0x08 12. " [12] ,Channel 12 stop/status" "No access,Access" textline " " eventfld.long 0x08 11. " [11] ,Channel 11 stop/status" "No access,Access" eventfld.long 0x08 10. " [10] ,Channel 10 stop/status" "No access,Access" eventfld.long 0x08 9. " [9] ,Channel 9 stop/status" "No access,Access" eventfld.long 0x08 8. " [8] ,Channel 8 stop/status" "No access,Access" textline " " eventfld.long 0x08 7. " [7] ,Channel 7 stop/status" "No access,Access" eventfld.long 0x08 6. " [6] ,Channel 6 stop/status" "No access,Access" eventfld.long 0x08 5. " [5] ,Channel 5 stop/status" "No access,Access" eventfld.long 0x08 4. " [4] ,Channel 4 stop/status" "No access,Access" textline " " eventfld.long 0x08 3. " [3] ,Channel 3 stop/status" "No access,Access" eventfld.long 0x08 2. " [2] ,Channel 2 stop/status" "No access,Access" eventfld.long 0x08 1. " [1] ,Channel 1 stop/status" "No access,Access" eventfld.long 0x08 0. " [0] ,Channel 0 stop/status" "No access,Access" line.long 0x0C "HSTART,Channel Start Register" eventfld.long 0x0C 31. " HSTART[31] ,Channel 31 enable" "Disabled,Enabled" eventfld.long 0x0C 30. " [30] ,Channel 30 enable" "Disabled,Enabled" eventfld.long 0x0C 29. " [29] ,Channel 29 enable" "Disabled,Enabled" eventfld.long 0x0C 28. " [28] ,Channel 28 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 27. " [27] ,Channel 27 enable" "Disabled,Enabled" eventfld.long 0x0C 26. " [26] ,Channel 26 enable" "Disabled,Enabled" eventfld.long 0x0C 25. " [25] ,Channel 25 enable" "Disabled,Enabled" eventfld.long 0x0C 24. " [24] ,Channel 24 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 23. " [23] ,Channel 23 enable" "Disabled,Enabled" eventfld.long 0x0C 22. " [22] ,Channel 22 enable" "Disabled,Enabled" eventfld.long 0x0C 21. " [21] ,Channel 21 enable" "Disabled,Enabled" eventfld.long 0x0C 20. " [20] ,Channel 20 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 19. " [19] ,Channel 19 enable" "Disabled,Enabled" eventfld.long 0x0C 18. " [18] ,Channel 18 enable" "Disabled,Enabled" eventfld.long 0x0C 17. " [17] ,Channel 17 enable" "Disabled,Enabled" eventfld.long 0x0C 16. " [16] ,Channel 16 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 15. " [15] ,Channel 15 enable" "Disabled,Enabled" eventfld.long 0x0C 14. " [14] ,Channel 14 enable" "Disabled,Enabled" eventfld.long 0x0C 13. " [13] ,Channel 13 enable" "Disabled,Enabled" eventfld.long 0x0C 12. " [12] ,Channel 12 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 11. " [11] ,Channel 11 enable" "Disabled,Enabled" eventfld.long 0x0C 10. " [10] ,Channel 10 enable" "Disabled,Enabled" eventfld.long 0x0C 9. " [9] ,Channel 9 enable" "Disabled,Enabled" eventfld.long 0x0C 8. " [8] ,Channel 8 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 7. " [7] ,Channel 7 enable" "Disabled,Enabled" eventfld.long 0x0C 6. " [6] ,Channel 6 enable" "Disabled,Enabled" eventfld.long 0x0C 5. " [5] ,Channel 5 enable" "Disabled,Enabled" eventfld.long 0x0C 4. " [4] ,Channel 4 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 3. " [3] ,Channel 3 enable" "Disabled,Enabled" eventfld.long 0x0C 2. " [2] ,Channel 2 enable" "Disabled,Enabled" eventfld.long 0x0C 1. " [1] ,Channel 1 enable" "Disabled,Enabled" eventfld.long 0x0C 0. " [0] ,Channel 0 enable" "Disabled,Enabled" line.long 0x10 "EVTOVR,Channel Event Override Register" bitfld.long 0x10 31. " EO[31] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 30. " [30] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 29. " [29] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 28. " [28] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 27. " [27] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 26. " [26] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 25. " [25] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 24. " [24] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 23. " [23] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 22. " [22] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 21. " [21] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 20. " [20] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 19. " [19] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 18. " [18] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 17. " [17] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 16. " [16] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 15. " [15] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 14. " [14] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 13. " [13] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 12. " [12] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 11. " [11] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 10. " [10] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 9. " [9] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 8. " [8] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 7. " [7] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 6. " [6] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 5. " [5] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 4. " [4] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 3. " [3] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 2. " [2] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 1. " [1] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 0. " [0] ,DMA request ignored by SDMA" "Not ignored,Ignored" group.long 0x18++0x07 line.long 0x00 "HOSTOVR,Channel AP Override Register" bitfld.long 0x00 31. " HO[31] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 30. " [30] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 29. " [29] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 28. " [28] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 27. " [27] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 26. " [26] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 25. " [25] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 24. " [24] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 23. " [23] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 22. " [22] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 21. " [21] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 20. " [20] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 19. " [19] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 18. " [18] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 17. " [17] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 16. " [16] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 15. " [15] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 14. " [14] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 13. " [13] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 12. " [12] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 11. " [11] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 10. " [10] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 9. " [9] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 8. " [8] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 7. " [7] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 6. " [6] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 5. " [5] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 4. " [4] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 3. " [3] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 2. " [2] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 1. " [1] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 0. " [0] ,AP enable ignored by SDMA" "Not ignored,Ignored" line.long 0x04 "EVTPEND,Channel Event Pending Register" eventfld.long 0x04 31. " EP[31] ,Channel 31 event pending" "Not pending,Pending" eventfld.long 0x04 30. " [30] ,Channel 30 event pending" "Not pending,Pending" eventfld.long 0x04 29. " [29] ,Channel 29 event pending" "Not pending,Pending" eventfld.long 0x04 28. " [28] ,Channel 28 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 27. " [27] ,Channel 27 event pending" "Not pending,Pending" eventfld.long 0x04 26. " [26] ,Channel 26 event pending" "Not pending,Pending" eventfld.long 0x04 25. " [25] ,Channel 25 event pending" "Not pending,Pending" eventfld.long 0x04 24. " [24] ,Channel 24 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 23. " [23] ,Channel 23 event pending" "Not pending,Pending" eventfld.long 0x04 22. " [22] ,Channel 22 event pending" "Not pending,Pending" eventfld.long 0x04 21. " [21] ,Channel 21 event pending" "Not pending,Pending" eventfld.long 0x04 20. " [20] ,Channel 20 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 19. " [19] ,Channel 19 event pending" "Not pending,Pending" eventfld.long 0x04 18. " [18] ,Channel 18 event pending" "Not pending,Pending" eventfld.long 0x04 17. " [17] ,Channel 17 event pending" "Not pending,Pending" eventfld.long 0x04 16. " [16] ,Channel 16 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 15. " [15] ,Channel 15 event pending" "Not pending,Pending" eventfld.long 0x04 14. " [14] ,Channel 14 event pending" "Not pending,Pending" eventfld.long 0x04 13. " [13] ,Channel 13 event pending" "Not pending,Pending" eventfld.long 0x04 12. " [12] ,Channel 12 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 11. " [11] ,Channel 11 event pending" "Not pending,Pending" eventfld.long 0x04 10. " [10] ,Channel 10 event pending" "Not pending,Pending" eventfld.long 0x04 9. " [9] ,Channel 9 event pending" "Not pending,Pending" eventfld.long 0x04 8. " [8] ,Channel 8 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 7. " [7] ,Channel 7 event pending" "Not pending,Pending" eventfld.long 0x04 6. " [6] ,Channel 6 event pending" "Not pending,Pending" eventfld.long 0x04 5. " [5] ,Channel 5 event pending" "Not pending,Pending" eventfld.long 0x04 4. " [4] ,Channel 4 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 3. " [3] ,Channel 3 event pending" "Not pending,Pending" eventfld.long 0x04 2. " [2] ,Channel 2 event pending" "Not pending,Pending" eventfld.long 0x04 1. " [1] ,Channel 1 event pending" "Not pending,Pending" eventfld.long 0x04 0. " [0] ,Channel 0 event pending" "Not pending,Pending" rgroup.long 0x24++0x03 line.long 0x00 "RESET,Reset Register" bitfld.long 0x00 1. " RESCHED ,Forces the SDMA to reschedule as if a script had executed a done instruction" "Not forced,Forced" bitfld.long 0x00 0. " RESET ,Causes the SDMA to be held in a software reset" "No software reset,Software reset" hgroup.long 0x28++0x03 hide.long 0x00 "EVTERR,DMA Request Error Register" in group.long 0x2C++0x03 line.long 0x00 "INTRMASK,Channel ARM Platform Interrupt Mask Register" bitfld.long 0x00 31. " HIMASK[31] ,Interrupt generation mask bit 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Interrupt generation mask bit 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Interrupt generation mask bit 29" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Interrupt generation mask bit 28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Interrupt generation mask bit 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Interrupt generation mask bit 26" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Interrupt generation mask bit 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Interrupt generation mask bit 24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Interrupt generation mask bit 23" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Interrupt generation mask bit 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Interrupt generation mask bit 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Interrupt generation mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Interrupt generation mask bit 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Interrupt generation mask bit 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Interrupt generation mask bit 17" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Interrupt generation mask bit 16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Interrupt generation mask bit 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Interrupt generation mask bit 14" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Interrupt generation mask bit 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Interrupt generation mask bit 12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Interrupt generation mask bit 11" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Interrupt generation mask bit 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Interrupt generation mask bit 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Interrupt generation mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Interrupt generation mask bit 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Interrupt generation mask bit 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Interrupt generation mask bit 5" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Interrupt generation mask bit 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Interrupt generation mask bit 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Interrupt generation mask bit 2" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Interrupt generation mask bit 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Interrupt generation mask bit 0" "Not masked,Masked" rgroup.long 0x30++0x07 line.long 0x00 "PSW,Schedule Status" bitfld.long 0x00 13.--15. " NCP ,Gives the next pending channel priority" "No running channel,Active channel priority,?..." bitfld.long 0x00 8.--12. " NCR ,Indicates the number of the next scheduled pending channel with the highest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " CCP ,Indicates the priority of the current active channel" "No running channel,Active channel priority,?..." bitfld.long 0x00 0.--3. " CCR ,The current channel register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EVTERRDBG,DMA Request Error Register" bitfld.long 0x04 31. " CHNERR[31] ,Set when a DMA request that triggers channel 31 is received and the EP[31] bit is already set" "No error,Error" bitfld.long 0x04 30. " [30] ,Set when a DMA request that triggers channel 30 is received and the EP[30] bit is already set" "No error,Error" bitfld.long 0x04 29. " [29] ,Set when a DMA request that triggers channel 29 is received and the EP[29] bit is already set" "No error,Error" bitfld.long 0x04 28. " [28] ,Set when a DMA request that triggers channel 28 is received and the EP[28] bit is already set" "No error,Error" textline " " bitfld.long 0x04 27. " [27] ,Set when a DMA request that triggers channel 27 is received and the EP[27] bit is already set" "No error,Error" bitfld.long 0x04 26. " [26] ,Set when a DMA request that triggers channel 26 is received and the EP[26] bit is already set" "No error,Error" bitfld.long 0x04 25. " [25] ,Set when a DMA request that triggers channel 25 is received and the EP[25] bit is already set" "No error,Error" bitfld.long 0x04 24. " [24] ,Set when a DMA request that triggers channel 24 is received and the EP[24] bit is already set" "No error,Error" textline " " bitfld.long 0x04 23. " [23] ,Set when a DMA request that triggers channel 23 is received and the EP[23] bit is already set" "No error,Error" bitfld.long 0x04 22. " [22] ,Set when a DMA request that triggers channel 22 is received and the EP[22] bit is already set" "No error,Error" bitfld.long 0x04 21. " [21] ,Set when a DMA request that triggers channel 21 is received and the EP[21] bit is already set" "No error,Error" bitfld.long 0x04 20. " [20] ,Set when a DMA request that triggers channel 20 is received and the EP[20] bit is already set" "No error,Error" textline " " bitfld.long 0x04 19. " [19] ,Set when a DMA request that triggers channel 19 is received and the EP[19] bit is already set" "No error,Error" bitfld.long 0x04 18. " [18] ,Set when a DMA request that triggers channel 18 is received and the EP[18] bit is already set" "No error,Error" bitfld.long 0x04 17. " [17] ,Set when a DMA request that triggers channel 17 is received and the EP[17] bit is already set" "No error,Error" bitfld.long 0x04 16. " [16] ,Set when a DMA request that triggers channel 16 is received and the EP[16] bit is already set" "No error,Error" textline " " bitfld.long 0x04 15. " [15] ,Set when a DMA request that triggers channel 15 is received and the EP[15] bit is already set" "No error,Error" bitfld.long 0x04 14. " [14] ,Set when a DMA request that triggers channel 14 is received and the EP[14] bit is already set" "No error,Error" bitfld.long 0x04 13. " [13] ,Set when a DMA request that triggers channel 13 is received and the EP[13] bit is already set" "No error,Error" bitfld.long 0x04 12. " [12] ,Set when a DMA request that triggers channel 12 is received and the EP[12] bit is already set" "No error,Error" textline " " bitfld.long 0x04 11. " [11] ,Set when a DMA request that triggers channel 11 is received and the EP[11] bit is already set" "No error,Error" bitfld.long 0x04 10. " [10] ,Set when a DMA request that triggers channel 10 is received and the EP[10] bit is already set" "No error,Error" bitfld.long 0x04 9. " [9] ,Set when a DMA request that triggers channel 9 is received and the EP[9] bit is already set" "No error,Error" bitfld.long 0x04 8. " [8] ,Set when a DMA request that triggers channel 8 is received and the EP[8] bit is already set" "No error,Error" textline " " bitfld.long 0x04 7. " [7] ,Set when a DMA request that triggers channel 7 is received and the EP[7] bit is already set" "No error,Error" bitfld.long 0x04 6. " [6] ,Set when a DMA request that triggers channel 6 is received and the EP[6] bit is already set" "No error,Error" bitfld.long 0x04 5. " [5] ,Set when a DMA request that triggers channel 5 is received and the EP[5] bit is already set" "No error,Error" bitfld.long 0x04 4. " [4] ,Set when a DMA request that triggers channel 4 is received and the EP[4] bit is already set" "No error,Error" textline " " bitfld.long 0x04 3. " [3] ,Set when a DMA request that triggers channel 3 is received and the EP[3] bit is already set" "No error,Error" bitfld.long 0x04 2. " [2] ,Set when a DMA request that triggers channel 2 is received and the EP[2] bit is already set" "No error,Error" bitfld.long 0x04 1. " [1] ,Set when a DMA request that triggers channel 1 is received and the EP[1] bit is already set" "No error,Error" bitfld.long 0x04 0. " [0] ,Set when a DMA request that triggers channel 0 is received and the EP[0] bit is already set" "No error,Error" group.long 0x38++0x03 line.long 0x00 "CONFIG,Configuration Register" bitfld.long 0x00 11. " RTDOBS ,Indicates if Real-Time debug pins are used" "Disabled,Enabled" bitfld.long 0x00 4. " ACR ,Selects the clock ratio between ARM platform DMA interfaces and the internal SDMA core clock" "2x core freq,Core freq" bitfld.long 0x00 0.--1. " CSM ,Context switch mode" "Static,Dynamic low power,Dynamic with no loop,Dynamic" if (((per.l(ad:0x30BD0000+0x3C))&0x01)==0x01) rgroup.long 0x3C++0x07 line.long 0x00 "SDMA_LOCK,SDMA LOCK" bitfld.long 0x00 1. " SRESET_LOCK_CLR ,Determines if the LOCK bit is cleared on a software reset triggered by writing to the RESET register" "Not cleared,Cleared" bitfld.long 0x00 0. " LOCK ,Restricts access to update SDMA script memory through ROM channel zero scripts and through the once interface under ARM platform control" "Disengaged,Enabled" line.long 0x04 "ONCE_ENB,Once Enable" bitfld.long 0x04 0. " ENB ,Enables the ARM platform to access the ONCE_* as any other SDMA control register" "Disabled,Enabled" else group.long 0x3C++0x07 line.long 0x00 "SDMA_LOCK,SDMA LOCK" bitfld.long 0x00 1. " SRESET_LOCK_CLR ,Determines if the LOCK bit is cleared on a software reset triggered by writing to the RESET register" "Not cleared,Cleared" bitfld.long 0x00 0. " LOCK ,Restricts access to update SDMA script memory through ROM channel zero scripts and through the once interface under ARM platform control" "Disengaged,Enabled" line.long 0x04 "ONCE_ENB,Once Enable" bitfld.long 0x04 0. " ENB ,Enables the ARM platform to access the ONCE_* as any other SDMA control register" "Disabled,Enabled" endif group.long 0x44++0x07 line.long 0x00 "ONCE_DATA,Once Data Register" line.long 0x04 "ONCE_INSTR,Once Instruction Register" hexmask.long.word 0x04 0.--15. 1. " INSTR ,Instruction register of the once JTAG controller" rgroup.long 0x4C++0x03 line.long 0x00 "ONCE_STAT,Once Status Register" bitfld.long 0x00 12.--15. " PST ,Processor status" "Program,Data,Change of flow,Change of flow in loop,Debug,Functional unit,Sleep,Save,Program in sleep,Data in sleep,Change of flow in sleep,Change flow in loop in sleep,Debug in sleep,Functional unit in sleep,Sleep after reset,Restore" bitfld.long 0x00 11. " RCV ,Write access to the real time buffer" "No write access,Write access" bitfld.long 0x00 10. " EDR ,SDMA has entered debug mode after an external debug request" "No,Yes" bitfld.long 0x00 9. " ODR ,SDMA has entered debug mode after a once debug request" "No,Yes" textline " " bitfld.long 0x00 8. " SWB ,SDMA has entered debug mode after a software breakpoint" "No,Yes" bitfld.long 0x00 7. " MST ,Once is controlled from the ARM platform peripheral interface" "JTAG,ARM" bitfld.long 0x00 0.--2. " ECDR ,Event cell debug request" "1 matched addra_cond,1 matched addrb_cond,1 matched data_cond,?..." group.long 0x50++0x03 line.long 0x00 "ONCE_CMD,Once Command Register" bitfld.long 0x00 0.--3. " CMD ,CMD" "Rstatus,Dmov,Exec_once,Run_core,Exec_core,Debug_rqst,Rbuffer,?..." if ((per.l(ad:0x30BD0000+0x3C)&0x01)==0x01) rgroup.long 0x58++0x07 line.long 0x00 "ILLINSTADDR,Illegal Instruction Trap Address Register" hexmask.long.word 0x00 0.--13. 0x01 " ILLINSTADDR ,Illegal instruction trap address" line.long 0x04 "CHN0ADDR,Channel 0 Boot Address Register" bitfld.long 0x04 14. " SMSZ ,Scratch memory size" "24 words per context,32 words per context" hexmask.long.word 0x04 0.--13. 0x01 " CHN0ADDR ,Channel 0 boot address" else group.long 0x58++0x07 line.long 0x00 "ILLINSTADDR,Illegal Instruction Trap Address Register" hexmask.long.word 0x00 0.--13. 0x01 " ILLINSTADDR ,Illegal instruction trap address" line.long 0x04 "CHN0ADDR,Channel 0 Boot Address Register" bitfld.long 0x04 14. " SMSZ ,Scratch memory size" "24 words per context,32 words per context" hexmask.long.word 0x04 0.--13. 0x01 " CHN0ADDR ,Channel 0 boot address" endif rgroup.long 0x60++0x07 line.long 0x00 "EVT_MIRROR,DMA Requests Register" bitfld.long 0x00 31. " EVENTS[31] ,Reflects the DMA requests received by the SDMA for events 31" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Reflects the DMA requests received by the SDMA for events 30" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Reflects the DMA requests received by the SDMA for events 29" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Reflects the DMA requests received by the SDMA for events 28" "Not pending,Pending" textline " " bitfld.long 0x00 27. " [27] ,Reflects the DMA requests received by the SDMA for events 27" "Not pending,Pending" bitfld.long 0x00 26. " [26] ,Reflects the DMA requests received by the SDMA for events 26" "Not pending,Pending" bitfld.long 0x00 25. " [25] ,Reflects the DMA requests received by the SDMA for events 25" "Not pending,Pending" bitfld.long 0x00 24. " [24] ,Reflects the DMA requests received by the SDMA for events 24" "Not pending,Pending" textline " " bitfld.long 0x00 23. " [23] ,Reflects the DMA requests received by the SDMA for events 23" "Not pending,Pending" bitfld.long 0x00 22. " [22] ,Reflects the DMA requests received by the SDMA for events 22" "Not pending,Pending" bitfld.long 0x00 21. " [21] ,Reflects the DMA requests received by the SDMA for events 21" "Not pending,Pending" bitfld.long 0x00 20. " [20] ,Reflects the DMA requests received by the SDMA for events 20" "Not pending,Pending" textline " " bitfld.long 0x00 19. " [19] ,Reflects the DMA requests received by the SDMA for events 19" "Not pending,Pending" bitfld.long 0x00 18. " [18] ,Reflects the DMA requests received by the SDMA for events 18" "Not pending,Pending" bitfld.long 0x00 17. " [17] ,Reflects the DMA requests received by the SDMA for events 17" "Not pending,Pending" bitfld.long 0x00 16. " [16] ,Reflects the DMA requests received by the SDMA for events 16" "Not pending,Pending" textline " " bitfld.long 0x00 15. " [15] ,Reflects the DMA requests received by the SDMA for events 15" "Not pending,Pending" bitfld.long 0x00 14. " [14] ,Reflects the DMA requests received by the SDMA for events 14" "Not pending,Pending" bitfld.long 0x00 13. " [13] ,Reflects the DMA requests received by the SDMA for events 13" "Not pending,Pending" bitfld.long 0x00 12. " [12] ,Reflects the DMA requests received by the SDMA for events 12" "Not pending,Pending" textline " " bitfld.long 0x00 11. " [11] ,Reflects the DMA requests received by the SDMA for events 11" "Not pending,Pending" bitfld.long 0x00 10. " [10] ,Reflects the DMA requests received by the SDMA for events 10" "Not pending,Pending" bitfld.long 0x00 9. " [9] ,Reflects the DMA requests received by the SDMA for events 9" "Not pending,Pending" bitfld.long 0x00 8. " [8] ,Reflects the DMA requests received by the SDMA for events 8" "Not pending,Pending" textline " " bitfld.long 0x00 7. " [7] ,Reflects the DMA requests received by the SDMA for events 7" "Not pending,Pending" bitfld.long 0x00 6. " [6] ,Reflects the DMA requests received by the SDMA for events 6" "Not pending,Pending" bitfld.long 0x00 5. " [5] ,Reflects the DMA requests received by the SDMA for events 5" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Reflects the DMA requests received by the SDMA for events 4" "Not pending,Pending" textline " " bitfld.long 0x00 3. " [3] ,Reflects the DMA requests received by the SDMA for events 3" "Not pending,Pending" bitfld.long 0x00 2. " [2] ,Reflects the DMA requests received by the SDMA for events 2" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Reflects the DMA requests received by the SDMA for events 1" "Not pending,Pending" bitfld.long 0x00 0. " [0] ,Reflects the DMA requests received by the SDMA for events 0" "Not pending,Pending" line.long 0x04 "EVT_MIRROR2,DMA Requests 2 Register" bitfld.long 0x04 15. " EVENTS[47] ,Reflects the DMA requests received by the SDMA for events 47" "Not pending,Pending" bitfld.long 0x04 14. " [46] ,Reflects the DMA requests received by the SDMA for events 46" "Not pending,Pending" bitfld.long 0x04 13. " [45] ,Reflects the DMA requests received by the SDMA for events 45" "Not pending,Pending" bitfld.long 0x04 12. " [44] ,Reflects the DMA requests received by the SDMA for events 44" "Not pending,Pending" textline " " bitfld.long 0x04 11. " [43] ,Reflects the DMA requests received by the SDMA for events 43" "Not pending,Pending" bitfld.long 0x04 10. " [42] ,Reflects the DMA requests received by the SDMA for events 42" "Not pending,Pending" bitfld.long 0x04 9. " [41] ,Reflects the DMA requests received by the SDMA for events 41" "Not pending,Pending" bitfld.long 0x04 8. " [40] ,Reflects the DMA requests received by the SDMA for events 40" "Not pending,Pending" textline " " bitfld.long 0x04 7. " [39] ,Reflects the DMA requests received by the SDMA for events 39" "Not pending,Pending" bitfld.long 0x04 6. " [38] ,Reflects the DMA requests received by the SDMA for events 38" "Not pending,Pending" bitfld.long 0x04 5. " [37] ,Reflects the DMA requests received by the SDMA for events 37" "Not pending,Pending" bitfld.long 0x04 4. " [36] ,Reflects the DMA requests received by the SDMA for events 36" "Not pending,Pending" textline " " bitfld.long 0x04 3. " [35] ,Reflects the DMA requests received by the SDMA for events 35" "Not pending,Pending" bitfld.long 0x04 2. " [34] ,Reflects the DMA requests received by the SDMA for events 34" "Not pending,Pending" bitfld.long 0x04 1. " [33] ,Reflects the DMA requests received by the SDMA for events 33" "Not pending,Pending" bitfld.long 0x04 0. " [32] ,Reflects the DMA requests received by the SDMA for events 32" "Not pending,Pending" group.long 0x70++0x07 line.long 0x00 "XTRIG_CONF1,Cross-Trigger Events Configuration Register 1" bitfld.long 0x00 30. " CNF3 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x00 24.--29. " NUM3 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22. " CNF2 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x00 16.--21. " NUM2 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 14. " CNF1 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x00 8.--13. " NUM2 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. " CNF0 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x00 0.--5. " NUM0 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "XTRIG_CONF2,Cross-Trigger Events Configuration Register 2" bitfld.long 0x04 30. " CNF7 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x04 24.--29. " NUM7 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 22. " CNF6 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x04 16.--21. " NUM6 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 14. " CNF5 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x04 8.--13. " NUM5 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 6. " CNF4 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x04 0.--5. " NUM4 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 15. tree "Channel Priority Registers" group.long 0x100++0x03 line.long 0x00 "SDMA_CHNPRI0,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI0 ,Contains the priority of channel number 0 " ",1,2,3,4,5,6,7" group.long 0x104++0x03 line.long 0x00 "SDMA_CHNPRI1,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI1 ,Contains the priority of channel number 1 " ",1,2,3,4,5,6,7" group.long 0x108++0x03 line.long 0x00 "SDMA_CHNPRI2,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI2 ,Contains the priority of channel number 2 " ",1,2,3,4,5,6,7" group.long 0x10C++0x03 line.long 0x00 "SDMA_CHNPRI3,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI3 ,Contains the priority of channel number 3 " ",1,2,3,4,5,6,7" group.long 0x110++0x03 line.long 0x00 "SDMA_CHNPRI4,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI4 ,Contains the priority of channel number 4 " ",1,2,3,4,5,6,7" group.long 0x114++0x03 line.long 0x00 "SDMA_CHNPRI5,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI5 ,Contains the priority of channel number 5 " ",1,2,3,4,5,6,7" group.long 0x118++0x03 line.long 0x00 "SDMA_CHNPRI6,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI6 ,Contains the priority of channel number 6 " ",1,2,3,4,5,6,7" group.long 0x11C++0x03 line.long 0x00 "SDMA_CHNPRI7,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI7 ,Contains the priority of channel number 7 " ",1,2,3,4,5,6,7" group.long 0x120++0x03 line.long 0x00 "SDMA_CHNPRI8,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI8 ,Contains the priority of channel number 8 " ",1,2,3,4,5,6,7" group.long 0x124++0x03 line.long 0x00 "SDMA_CHNPRI9,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI9 ,Contains the priority of channel number 9 " ",1,2,3,4,5,6,7" group.long 0x128++0x03 line.long 0x00 "SDMA_CHNPRI10,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI10 ,Contains the priority of channel number 10" ",1,2,3,4,5,6,7" group.long 0x12C++0x03 line.long 0x00 "SDMA_CHNPRI11,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI11 ,Contains the priority of channel number 11" ",1,2,3,4,5,6,7" group.long 0x130++0x03 line.long 0x00 "SDMA_CHNPRI12,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI12 ,Contains the priority of channel number 12" ",1,2,3,4,5,6,7" group.long 0x134++0x03 line.long 0x00 "SDMA_CHNPRI13,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI13 ,Contains the priority of channel number 13" ",1,2,3,4,5,6,7" group.long 0x138++0x03 line.long 0x00 "SDMA_CHNPRI14,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI14 ,Contains the priority of channel number 14" ",1,2,3,4,5,6,7" group.long 0x13C++0x03 line.long 0x00 "SDMA_CHNPRI15,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI15 ,Contains the priority of channel number 15" ",1,2,3,4,5,6,7" group.long 0x140++0x03 line.long 0x00 "SDMA_CHNPRI16,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI16 ,Contains the priority of channel number 16" ",1,2,3,4,5,6,7" group.long 0x144++0x03 line.long 0x00 "SDMA_CHNPRI17,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI17 ,Contains the priority of channel number 17" ",1,2,3,4,5,6,7" group.long 0x148++0x03 line.long 0x00 "SDMA_CHNPRI18,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI18 ,Contains the priority of channel number 18" ",1,2,3,4,5,6,7" group.long 0x14C++0x03 line.long 0x00 "SDMA_CHNPRI19,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI19 ,Contains the priority of channel number 19" ",1,2,3,4,5,6,7" group.long 0x150++0x03 line.long 0x00 "SDMA_CHNPRI20,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI20 ,Contains the priority of channel number 20" ",1,2,3,4,5,6,7" group.long 0x154++0x03 line.long 0x00 "SDMA_CHNPRI21,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI21 ,Contains the priority of channel number 21" ",1,2,3,4,5,6,7" group.long 0x158++0x03 line.long 0x00 "SDMA_CHNPRI22,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI22 ,Contains the priority of channel number 22" ",1,2,3,4,5,6,7" group.long 0x15C++0x03 line.long 0x00 "SDMA_CHNPRI23,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI23 ,Contains the priority of channel number 23" ",1,2,3,4,5,6,7" group.long 0x160++0x03 line.long 0x00 "SDMA_CHNPRI24,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI24 ,Contains the priority of channel number 24" ",1,2,3,4,5,6,7" group.long 0x164++0x03 line.long 0x00 "SDMA_CHNPRI25,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI25 ,Contains the priority of channel number 25" ",1,2,3,4,5,6,7" group.long 0x168++0x03 line.long 0x00 "SDMA_CHNPRI26,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI26 ,Contains the priority of channel number 26" ",1,2,3,4,5,6,7" group.long 0x16C++0x03 line.long 0x00 "SDMA_CHNPRI27,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI27 ,Contains the priority of channel number 27" ",1,2,3,4,5,6,7" group.long 0x170++0x03 line.long 0x00 "SDMA_CHNPRI28,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI28 ,Contains the priority of channel number 28" ",1,2,3,4,5,6,7" group.long 0x174++0x03 line.long 0x00 "SDMA_CHNPRI29,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI29 ,Contains the priority of channel number 29" ",1,2,3,4,5,6,7" group.long 0x178++0x03 line.long 0x00 "SDMA_CHNPRI30,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI30 ,Contains the priority of channel number 30" ",1,2,3,4,5,6,7" group.long 0x17C++0x03 line.long 0x00 "SDMA_CHNPRI31,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI31 ,Contains the priority of channel number 31" ",1,2,3,4,5,6,7" tree.end width 11. tree "Channel Enable RAM Registers" group.long 0x200++0x03 line.long 0x00 "CHNENBL0,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 0 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 0 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 0 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 0 is received" "Disabled,Enabled" textline " " group.long 0x204++0x03 line.long 0x00 "CHNENBL1,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 1 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 1 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 1 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 1 is received" "Disabled,Enabled" textline " " group.long 0x208++0x03 line.long 0x00 "CHNENBL2,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 2 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 2 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 2 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 2 is received" "Disabled,Enabled" textline " " group.long 0x20C++0x03 line.long 0x00 "CHNENBL3,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 3 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 3 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 3 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 3 is received" "Disabled,Enabled" textline " " group.long 0x210++0x03 line.long 0x00 "CHNENBL4,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 4 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 4 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 4 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 4 is received" "Disabled,Enabled" textline " " group.long 0x214++0x03 line.long 0x00 "CHNENBL5,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 5 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 5 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 5 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 5 is received" "Disabled,Enabled" textline " " group.long 0x218++0x03 line.long 0x00 "CHNENBL6,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 6 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 6 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 6 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 6 is received" "Disabled,Enabled" textline " " group.long 0x21C++0x03 line.long 0x00 "CHNENBL7,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 7 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 7 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 7 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 7 is received" "Disabled,Enabled" textline " " group.long 0x220++0x03 line.long 0x00 "CHNENBL8,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 8 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 8 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 8 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 8 is received" "Disabled,Enabled" textline " " group.long 0x224++0x03 line.long 0x00 "CHNENBL9,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 9 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 9 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 9 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 9 is received" "Disabled,Enabled" textline " " group.long 0x228++0x03 line.long 0x00 "CHNENBL10,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 10 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 10 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 10 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 10 is received" "Disabled,Enabled" textline " " group.long 0x22C++0x03 line.long 0x00 "CHNENBL11,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 11 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 11 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 11 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 11 is received" "Disabled,Enabled" textline " " group.long 0x230++0x03 line.long 0x00 "CHNENBL12,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 12 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 12 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 12 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 12 is received" "Disabled,Enabled" textline " " group.long 0x234++0x03 line.long 0x00 "CHNENBL13,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 13 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 13 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 13 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 13 is received" "Disabled,Enabled" textline " " group.long 0x238++0x03 line.long 0x00 "CHNENBL14,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 14 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 14 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 14 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 14 is received" "Disabled,Enabled" textline " " group.long 0x23C++0x03 line.long 0x00 "CHNENBL15,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 15 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 15 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 15 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 15 is received" "Disabled,Enabled" textline " " group.long 0x240++0x03 line.long 0x00 "CHNENBL16,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 16 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 16 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 16 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 16 is received" "Disabled,Enabled" textline " " group.long 0x244++0x03 line.long 0x00 "CHNENBL17,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 17 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 17 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 17 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 17 is received" "Disabled,Enabled" textline " " group.long 0x248++0x03 line.long 0x00 "CHNENBL18,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 18 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 18 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 18 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 18 is received" "Disabled,Enabled" textline " " group.long 0x24C++0x03 line.long 0x00 "CHNENBL19,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 19 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 19 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 19 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 19 is received" "Disabled,Enabled" textline " " group.long 0x250++0x03 line.long 0x00 "CHNENBL20,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 20 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 20 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 20 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 20 is received" "Disabled,Enabled" textline " " group.long 0x254++0x03 line.long 0x00 "CHNENBL21,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 21 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 21 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 21 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 21 is received" "Disabled,Enabled" textline " " group.long 0x258++0x03 line.long 0x00 "CHNENBL22,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 22 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 22 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 22 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 22 is received" "Disabled,Enabled" textline " " group.long 0x25C++0x03 line.long 0x00 "CHNENBL23,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 23 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 23 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 23 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 23 is received" "Disabled,Enabled" textline " " group.long 0x260++0x03 line.long 0x00 "CHNENBL24,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 24 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 24 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 24 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 24 is received" "Disabled,Enabled" textline " " group.long 0x264++0x03 line.long 0x00 "CHNENBL25,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 25 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 25 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 25 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 25 is received" "Disabled,Enabled" textline " " group.long 0x268++0x03 line.long 0x00 "CHNENBL26,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 26 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 26 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 26 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 26 is received" "Disabled,Enabled" textline " " group.long 0x26C++0x03 line.long 0x00 "CHNENBL27,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 27 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 27 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 27 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 27 is received" "Disabled,Enabled" textline " " group.long 0x270++0x03 line.long 0x00 "CHNENBL28,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 28 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 28 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 28 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 28 is received" "Disabled,Enabled" textline " " group.long 0x274++0x03 line.long 0x00 "CHNENBL29,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 29 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 29 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 29 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 29 is received" "Disabled,Enabled" textline " " group.long 0x278++0x03 line.long 0x00 "CHNENBL30,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 30 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 30 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 30 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 30 is received" "Disabled,Enabled" textline " " group.long 0x27C++0x03 line.long 0x00 "CHNENBL31,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 31 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 31 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 31 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 31 is received" "Disabled,Enabled" textline " " group.long 0x280++0x03 line.long 0x00 "CHNENBL32,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 32 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 32 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 32 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 32 is received" "Disabled,Enabled" textline " " group.long 0x284++0x03 line.long 0x00 "CHNENBL33,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 33 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 33 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 33 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 33 is received" "Disabled,Enabled" textline " " group.long 0x288++0x03 line.long 0x00 "CHNENBL34,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 34 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 34 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 34 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 34 is received" "Disabled,Enabled" textline " " group.long 0x28C++0x03 line.long 0x00 "CHNENBL35,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 35 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 35 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 35 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 35 is received" "Disabled,Enabled" textline " " group.long 0x290++0x03 line.long 0x00 "CHNENBL36,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 36 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 36 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 36 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 36 is received" "Disabled,Enabled" textline " " group.long 0x294++0x03 line.long 0x00 "CHNENBL37,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 37 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 37 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 37 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 37 is received" "Disabled,Enabled" textline " " group.long 0x298++0x03 line.long 0x00 "CHNENBL38,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 38 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 38 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 38 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 38 is received" "Disabled,Enabled" textline " " group.long 0x29C++0x03 line.long 0x00 "CHNENBL39,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 39 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 39 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 39 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 39 is received" "Disabled,Enabled" textline " " group.long 0x2A0++0x03 line.long 0x00 "CHNENBL40,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 40 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 40 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 40 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 40 is received" "Disabled,Enabled" textline " " group.long 0x2A4++0x03 line.long 0x00 "CHNENBL41,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 41 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 41 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 41 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 41 is received" "Disabled,Enabled" textline " " group.long 0x2A8++0x03 line.long 0x00 "CHNENBL42,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 42 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 42 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 42 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 42 is received" "Disabled,Enabled" textline " " group.long 0x2AC++0x03 line.long 0x00 "CHNENBL43,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 43 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 43 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 43 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 43 is received" "Disabled,Enabled" textline " " group.long 0x2B0++0x03 line.long 0x00 "CHNENBL44,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 44 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 44 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 44 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 44 is received" "Disabled,Enabled" textline " " group.long 0x2B4++0x03 line.long 0x00 "CHNENBL45,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 45 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 45 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 45 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 45 is received" "Disabled,Enabled" textline " " group.long 0x2B8++0x03 line.long 0x00 "CHNENBL46,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 46 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 46 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 46 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 46 is received" "Disabled,Enabled" textline " " group.long 0x2BC++0x03 line.long 0x00 "CHNENBL47,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 47 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 47 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 47 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 47 is received" "Disabled,Enabled" tree.end width 0x0B tree.end tree "SDMAARM2" base ad:0x302C0000 width 15. group.long 0x00++0x13 line.long 0x00 "MC0PTR,ARM Platform Channel 0 Pointer Register" line.long 0x04 "INTR,Channel Interrupts Register" eventfld.long 0x04 31. " HI[31] ,Channel interrupt 31" "No interrupt,Interrupt" eventfld.long 0x04 30. " [30] ,Channel interrupt 30" "No interrupt,Interrupt" eventfld.long 0x04 29. " [29] ,Channel interrupt 29" "No interrupt,Interrupt" eventfld.long 0x04 28. " [28] ,Channel interrupt 28" "No interrupt,Interrupt" textline " " eventfld.long 0x04 27. " [27] ,Channel interrupt 27" "No interrupt,Interrupt" eventfld.long 0x04 26. " [26] ,Channel interrupt 26" "No interrupt,Interrupt" eventfld.long 0x04 25. " [25] ,Channel interrupt 25" "No interrupt,Interrupt" eventfld.long 0x04 24. " [24] ,Channel interrupt 24" "No interrupt,Interrupt" textline " " eventfld.long 0x04 23. " [23] ,Channel interrupt 23" "No interrupt,Interrupt" eventfld.long 0x04 22. " [22] ,Channel interrupt 22" "No interrupt,Interrupt" eventfld.long 0x04 21. " [21] ,Channel interrupt 21" "No interrupt,Interrupt" eventfld.long 0x04 20. " [20] ,Channel interrupt 20" "No interrupt,Interrupt" textline " " eventfld.long 0x04 19. " [19] ,Channel interrupt 19" "No interrupt,Interrupt" eventfld.long 0x04 18. " [18] ,Channel interrupt 18" "No interrupt,Interrupt" eventfld.long 0x04 17. " [17] ,Channel interrupt 17" "No interrupt,Interrupt" eventfld.long 0x04 16. " [16] ,Channel interrupt 16" "No interrupt,Interrupt" textline " " eventfld.long 0x04 15. " [15] ,Channel interrupt 15" "No interrupt,Interrupt" eventfld.long 0x04 14. " [14] ,Channel interrupt 14" "No interrupt,Interrupt" eventfld.long 0x04 13. " [13] ,Channel interrupt 13" "No interrupt,Interrupt" eventfld.long 0x04 12. " [12] ,Channel interrupt 12" "No interrupt,Interrupt" textline " " eventfld.long 0x04 11. " [11] ,Channel interrupt 11" "No interrupt,Interrupt" eventfld.long 0x04 10. " [10] ,Channel interrupt 10" "No interrupt,Interrupt" eventfld.long 0x04 9. " [9] ,Channel interrupt 9" "No interrupt,Interrupt" eventfld.long 0x04 8. " [8] ,Channel interrupt 8" "No interrupt,Interrupt" textline " " eventfld.long 0x04 7. " [7] ,Channel interrupt 7" "No interrupt,Interrupt" eventfld.long 0x04 6. " [6] ,Channel interrupt 6" "No interrupt,Interrupt" eventfld.long 0x04 5. " [5] ,Channel interrupt 5" "No interrupt,Interrupt" eventfld.long 0x04 4. " [4] ,Channel interrupt 4" "No interrupt,Interrupt" textline " " eventfld.long 0x04 3. " [3] ,Channel interrupt 3" "No interrupt,Interrupt" eventfld.long 0x04 2. " [2] ,Channel interrupt 2" "No interrupt,Interrupt" eventfld.long 0x04 1. " [1] ,Channel interrupt 1" "No interrupt,Interrupt" eventfld.long 0x04 0. " [0] ,Channel interrupt 0" "No interrupt,Interrupt" line.long 0x08 "STOP_STAT,Channel Stop/channel Status Register" eventfld.long 0x08 31. " HE[31] ,Channel 31 stop/status" "No access,Access" eventfld.long 0x08 30. " [30] ,Channel 30 stop/status" "No access,Access" eventfld.long 0x08 29. " [29] ,Channel 29 stop/status" "No access,Access" eventfld.long 0x08 28. " [28] ,Channel 28 stop/status" "No access,Access" textline " " eventfld.long 0x08 27. " [27] ,Channel 27 stop/status" "No access,Access" eventfld.long 0x08 26. " [26] ,Channel 26 stop/status" "No access,Access" eventfld.long 0x08 25. " [25] ,Channel 25 stop/status" "No access,Access" eventfld.long 0x08 24. " [24] ,Channel 24 stop/status" "No access,Access" textline " " eventfld.long 0x08 23. " [23] ,Channel 23 stop/status" "No access,Access" eventfld.long 0x08 22. " [22] ,Channel 22 stop/status" "No access,Access" eventfld.long 0x08 21. " [21] ,Channel 21 stop/status" "No access,Access" eventfld.long 0x08 20. " [20] ,Channel 20 stop/status" "No access,Access" textline " " eventfld.long 0x08 19. " [19] ,Channel 19 stop/status" "No access,Access" eventfld.long 0x08 18. " [18] ,Channel 18 stop/status" "No access,Access" eventfld.long 0x08 17. " [17] ,Channel 17 stop/status" "No access,Access" eventfld.long 0x08 16. " [16] ,Channel 16 stop/status" "No access,Access" textline " " eventfld.long 0x08 15. " [15] ,Channel 15 stop/status" "No access,Access" eventfld.long 0x08 14. " [14] ,Channel 14 stop/status" "No access,Access" eventfld.long 0x08 13. " [13] ,Channel 13 stop/status" "No access,Access" eventfld.long 0x08 12. " [12] ,Channel 12 stop/status" "No access,Access" textline " " eventfld.long 0x08 11. " [11] ,Channel 11 stop/status" "No access,Access" eventfld.long 0x08 10. " [10] ,Channel 10 stop/status" "No access,Access" eventfld.long 0x08 9. " [9] ,Channel 9 stop/status" "No access,Access" eventfld.long 0x08 8. " [8] ,Channel 8 stop/status" "No access,Access" textline " " eventfld.long 0x08 7. " [7] ,Channel 7 stop/status" "No access,Access" eventfld.long 0x08 6. " [6] ,Channel 6 stop/status" "No access,Access" eventfld.long 0x08 5. " [5] ,Channel 5 stop/status" "No access,Access" eventfld.long 0x08 4. " [4] ,Channel 4 stop/status" "No access,Access" textline " " eventfld.long 0x08 3. " [3] ,Channel 3 stop/status" "No access,Access" eventfld.long 0x08 2. " [2] ,Channel 2 stop/status" "No access,Access" eventfld.long 0x08 1. " [1] ,Channel 1 stop/status" "No access,Access" eventfld.long 0x08 0. " [0] ,Channel 0 stop/status" "No access,Access" line.long 0x0C "HSTART,Channel Start Register" eventfld.long 0x0C 31. " HSTART[31] ,Channel 31 enable" "Disabled,Enabled" eventfld.long 0x0C 30. " [30] ,Channel 30 enable" "Disabled,Enabled" eventfld.long 0x0C 29. " [29] ,Channel 29 enable" "Disabled,Enabled" eventfld.long 0x0C 28. " [28] ,Channel 28 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 27. " [27] ,Channel 27 enable" "Disabled,Enabled" eventfld.long 0x0C 26. " [26] ,Channel 26 enable" "Disabled,Enabled" eventfld.long 0x0C 25. " [25] ,Channel 25 enable" "Disabled,Enabled" eventfld.long 0x0C 24. " [24] ,Channel 24 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 23. " [23] ,Channel 23 enable" "Disabled,Enabled" eventfld.long 0x0C 22. " [22] ,Channel 22 enable" "Disabled,Enabled" eventfld.long 0x0C 21. " [21] ,Channel 21 enable" "Disabled,Enabled" eventfld.long 0x0C 20. " [20] ,Channel 20 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 19. " [19] ,Channel 19 enable" "Disabled,Enabled" eventfld.long 0x0C 18. " [18] ,Channel 18 enable" "Disabled,Enabled" eventfld.long 0x0C 17. " [17] ,Channel 17 enable" "Disabled,Enabled" eventfld.long 0x0C 16. " [16] ,Channel 16 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 15. " [15] ,Channel 15 enable" "Disabled,Enabled" eventfld.long 0x0C 14. " [14] ,Channel 14 enable" "Disabled,Enabled" eventfld.long 0x0C 13. " [13] ,Channel 13 enable" "Disabled,Enabled" eventfld.long 0x0C 12. " [12] ,Channel 12 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 11. " [11] ,Channel 11 enable" "Disabled,Enabled" eventfld.long 0x0C 10. " [10] ,Channel 10 enable" "Disabled,Enabled" eventfld.long 0x0C 9. " [9] ,Channel 9 enable" "Disabled,Enabled" eventfld.long 0x0C 8. " [8] ,Channel 8 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 7. " [7] ,Channel 7 enable" "Disabled,Enabled" eventfld.long 0x0C 6. " [6] ,Channel 6 enable" "Disabled,Enabled" eventfld.long 0x0C 5. " [5] ,Channel 5 enable" "Disabled,Enabled" eventfld.long 0x0C 4. " [4] ,Channel 4 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 3. " [3] ,Channel 3 enable" "Disabled,Enabled" eventfld.long 0x0C 2. " [2] ,Channel 2 enable" "Disabled,Enabled" eventfld.long 0x0C 1. " [1] ,Channel 1 enable" "Disabled,Enabled" eventfld.long 0x0C 0. " [0] ,Channel 0 enable" "Disabled,Enabled" line.long 0x10 "EVTOVR,Channel Event Override Register" bitfld.long 0x10 31. " EO[31] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 30. " [30] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 29. " [29] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 28. " [28] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 27. " [27] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 26. " [26] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 25. " [25] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 24. " [24] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 23. " [23] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 22. " [22] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 21. " [21] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 20. " [20] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 19. " [19] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 18. " [18] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 17. " [17] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 16. " [16] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 15. " [15] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 14. " [14] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 13. " [13] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 12. " [12] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 11. " [11] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 10. " [10] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 9. " [9] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 8. " [8] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 7. " [7] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 6. " [6] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 5. " [5] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 4. " [4] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 3. " [3] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 2. " [2] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 1. " [1] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 0. " [0] ,DMA request ignored by SDMA" "Not ignored,Ignored" group.long 0x18++0x07 line.long 0x00 "HOSTOVR,Channel AP Override Register" bitfld.long 0x00 31. " HO[31] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 30. " [30] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 29. " [29] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 28. " [28] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 27. " [27] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 26. " [26] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 25. " [25] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 24. " [24] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 23. " [23] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 22. " [22] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 21. " [21] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 20. " [20] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 19. " [19] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 18. " [18] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 17. " [17] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 16. " [16] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 15. " [15] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 14. " [14] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 13. " [13] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 12. " [12] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 11. " [11] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 10. " [10] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 9. " [9] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 8. " [8] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 7. " [7] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 6. " [6] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 5. " [5] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 4. " [4] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 3. " [3] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 2. " [2] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 1. " [1] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 0. " [0] ,AP enable ignored by SDMA" "Not ignored,Ignored" line.long 0x04 "EVTPEND,Channel Event Pending Register" eventfld.long 0x04 31. " EP[31] ,Channel 31 event pending" "Not pending,Pending" eventfld.long 0x04 30. " [30] ,Channel 30 event pending" "Not pending,Pending" eventfld.long 0x04 29. " [29] ,Channel 29 event pending" "Not pending,Pending" eventfld.long 0x04 28. " [28] ,Channel 28 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 27. " [27] ,Channel 27 event pending" "Not pending,Pending" eventfld.long 0x04 26. " [26] ,Channel 26 event pending" "Not pending,Pending" eventfld.long 0x04 25. " [25] ,Channel 25 event pending" "Not pending,Pending" eventfld.long 0x04 24. " [24] ,Channel 24 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 23. " [23] ,Channel 23 event pending" "Not pending,Pending" eventfld.long 0x04 22. " [22] ,Channel 22 event pending" "Not pending,Pending" eventfld.long 0x04 21. " [21] ,Channel 21 event pending" "Not pending,Pending" eventfld.long 0x04 20. " [20] ,Channel 20 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 19. " [19] ,Channel 19 event pending" "Not pending,Pending" eventfld.long 0x04 18. " [18] ,Channel 18 event pending" "Not pending,Pending" eventfld.long 0x04 17. " [17] ,Channel 17 event pending" "Not pending,Pending" eventfld.long 0x04 16. " [16] ,Channel 16 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 15. " [15] ,Channel 15 event pending" "Not pending,Pending" eventfld.long 0x04 14. " [14] ,Channel 14 event pending" "Not pending,Pending" eventfld.long 0x04 13. " [13] ,Channel 13 event pending" "Not pending,Pending" eventfld.long 0x04 12. " [12] ,Channel 12 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 11. " [11] ,Channel 11 event pending" "Not pending,Pending" eventfld.long 0x04 10. " [10] ,Channel 10 event pending" "Not pending,Pending" eventfld.long 0x04 9. " [9] ,Channel 9 event pending" "Not pending,Pending" eventfld.long 0x04 8. " [8] ,Channel 8 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 7. " [7] ,Channel 7 event pending" "Not pending,Pending" eventfld.long 0x04 6. " [6] ,Channel 6 event pending" "Not pending,Pending" eventfld.long 0x04 5. " [5] ,Channel 5 event pending" "Not pending,Pending" eventfld.long 0x04 4. " [4] ,Channel 4 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 3. " [3] ,Channel 3 event pending" "Not pending,Pending" eventfld.long 0x04 2. " [2] ,Channel 2 event pending" "Not pending,Pending" eventfld.long 0x04 1. " [1] ,Channel 1 event pending" "Not pending,Pending" eventfld.long 0x04 0. " [0] ,Channel 0 event pending" "Not pending,Pending" rgroup.long 0x24++0x03 line.long 0x00 "RESET,Reset Register" bitfld.long 0x00 1. " RESCHED ,Forces the SDMA to reschedule as if a script had executed a done instruction" "Not forced,Forced" bitfld.long 0x00 0. " RESET ,Causes the SDMA to be held in a software reset" "No software reset,Software reset" hgroup.long 0x28++0x03 hide.long 0x00 "EVTERR,DMA Request Error Register" in group.long 0x2C++0x03 line.long 0x00 "INTRMASK,Channel ARM Platform Interrupt Mask Register" bitfld.long 0x00 31. " HIMASK[31] ,Interrupt generation mask bit 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Interrupt generation mask bit 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Interrupt generation mask bit 29" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Interrupt generation mask bit 28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Interrupt generation mask bit 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Interrupt generation mask bit 26" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Interrupt generation mask bit 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Interrupt generation mask bit 24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Interrupt generation mask bit 23" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Interrupt generation mask bit 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Interrupt generation mask bit 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Interrupt generation mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Interrupt generation mask bit 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Interrupt generation mask bit 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Interrupt generation mask bit 17" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Interrupt generation mask bit 16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Interrupt generation mask bit 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Interrupt generation mask bit 14" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Interrupt generation mask bit 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Interrupt generation mask bit 12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Interrupt generation mask bit 11" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Interrupt generation mask bit 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Interrupt generation mask bit 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Interrupt generation mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Interrupt generation mask bit 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Interrupt generation mask bit 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Interrupt generation mask bit 5" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Interrupt generation mask bit 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Interrupt generation mask bit 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Interrupt generation mask bit 2" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Interrupt generation mask bit 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Interrupt generation mask bit 0" "Not masked,Masked" rgroup.long 0x30++0x07 line.long 0x00 "PSW,Schedule Status" bitfld.long 0x00 13.--15. " NCP ,Gives the next pending channel priority" "No running channel,Active channel priority,?..." bitfld.long 0x00 8.--12. " NCR ,Indicates the number of the next scheduled pending channel with the highest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " CCP ,Indicates the priority of the current active channel" "No running channel,Active channel priority,?..." bitfld.long 0x00 0.--3. " CCR ,The current channel register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EVTERRDBG,DMA Request Error Register" bitfld.long 0x04 31. " CHNERR[31] ,Set when a DMA request that triggers channel 31 is received and the EP[31] bit is already set" "No error,Error" bitfld.long 0x04 30. " [30] ,Set when a DMA request that triggers channel 30 is received and the EP[30] bit is already set" "No error,Error" bitfld.long 0x04 29. " [29] ,Set when a DMA request that triggers channel 29 is received and the EP[29] bit is already set" "No error,Error" bitfld.long 0x04 28. " [28] ,Set when a DMA request that triggers channel 28 is received and the EP[28] bit is already set" "No error,Error" textline " " bitfld.long 0x04 27. " [27] ,Set when a DMA request that triggers channel 27 is received and the EP[27] bit is already set" "No error,Error" bitfld.long 0x04 26. " [26] ,Set when a DMA request that triggers channel 26 is received and the EP[26] bit is already set" "No error,Error" bitfld.long 0x04 25. " [25] ,Set when a DMA request that triggers channel 25 is received and the EP[25] bit is already set" "No error,Error" bitfld.long 0x04 24. " [24] ,Set when a DMA request that triggers channel 24 is received and the EP[24] bit is already set" "No error,Error" textline " " bitfld.long 0x04 23. " [23] ,Set when a DMA request that triggers channel 23 is received and the EP[23] bit is already set" "No error,Error" bitfld.long 0x04 22. " [22] ,Set when a DMA request that triggers channel 22 is received and the EP[22] bit is already set" "No error,Error" bitfld.long 0x04 21. " [21] ,Set when a DMA request that triggers channel 21 is received and the EP[21] bit is already set" "No error,Error" bitfld.long 0x04 20. " [20] ,Set when a DMA request that triggers channel 20 is received and the EP[20] bit is already set" "No error,Error" textline " " bitfld.long 0x04 19. " [19] ,Set when a DMA request that triggers channel 19 is received and the EP[19] bit is already set" "No error,Error" bitfld.long 0x04 18. " [18] ,Set when a DMA request that triggers channel 18 is received and the EP[18] bit is already set" "No error,Error" bitfld.long 0x04 17. " [17] ,Set when a DMA request that triggers channel 17 is received and the EP[17] bit is already set" "No error,Error" bitfld.long 0x04 16. " [16] ,Set when a DMA request that triggers channel 16 is received and the EP[16] bit is already set" "No error,Error" textline " " bitfld.long 0x04 15. " [15] ,Set when a DMA request that triggers channel 15 is received and the EP[15] bit is already set" "No error,Error" bitfld.long 0x04 14. " [14] ,Set when a DMA request that triggers channel 14 is received and the EP[14] bit is already set" "No error,Error" bitfld.long 0x04 13. " [13] ,Set when a DMA request that triggers channel 13 is received and the EP[13] bit is already set" "No error,Error" bitfld.long 0x04 12. " [12] ,Set when a DMA request that triggers channel 12 is received and the EP[12] bit is already set" "No error,Error" textline " " bitfld.long 0x04 11. " [11] ,Set when a DMA request that triggers channel 11 is received and the EP[11] bit is already set" "No error,Error" bitfld.long 0x04 10. " [10] ,Set when a DMA request that triggers channel 10 is received and the EP[10] bit is already set" "No error,Error" bitfld.long 0x04 9. " [9] ,Set when a DMA request that triggers channel 9 is received and the EP[9] bit is already set" "No error,Error" bitfld.long 0x04 8. " [8] ,Set when a DMA request that triggers channel 8 is received and the EP[8] bit is already set" "No error,Error" textline " " bitfld.long 0x04 7. " [7] ,Set when a DMA request that triggers channel 7 is received and the EP[7] bit is already set" "No error,Error" bitfld.long 0x04 6. " [6] ,Set when a DMA request that triggers channel 6 is received and the EP[6] bit is already set" "No error,Error" bitfld.long 0x04 5. " [5] ,Set when a DMA request that triggers channel 5 is received and the EP[5] bit is already set" "No error,Error" bitfld.long 0x04 4. " [4] ,Set when a DMA request that triggers channel 4 is received and the EP[4] bit is already set" "No error,Error" textline " " bitfld.long 0x04 3. " [3] ,Set when a DMA request that triggers channel 3 is received and the EP[3] bit is already set" "No error,Error" bitfld.long 0x04 2. " [2] ,Set when a DMA request that triggers channel 2 is received and the EP[2] bit is already set" "No error,Error" bitfld.long 0x04 1. " [1] ,Set when a DMA request that triggers channel 1 is received and the EP[1] bit is already set" "No error,Error" bitfld.long 0x04 0. " [0] ,Set when a DMA request that triggers channel 0 is received and the EP[0] bit is already set" "No error,Error" group.long 0x38++0x03 line.long 0x00 "CONFIG,Configuration Register" bitfld.long 0x00 11. " RTDOBS ,Indicates if Real-Time debug pins are used" "Disabled,Enabled" bitfld.long 0x00 4. " ACR ,Selects the clock ratio between ARM platform DMA interfaces and the internal SDMA core clock" "2x core freq,Core freq" bitfld.long 0x00 0.--1. " CSM ,Context switch mode" "Static,Dynamic low power,Dynamic with no loop,Dynamic" if (((per.l(ad:0x302C0000+0x3C))&0x01)==0x01) rgroup.long 0x3C++0x07 line.long 0x00 "SDMA_LOCK,SDMA LOCK" bitfld.long 0x00 1. " SRESET_LOCK_CLR ,Determines if the LOCK bit is cleared on a software reset triggered by writing to the RESET register" "Not cleared,Cleared" bitfld.long 0x00 0. " LOCK ,Restricts access to update SDMA script memory through ROM channel zero scripts and through the once interface under ARM platform control" "Disengaged,Enabled" line.long 0x04 "ONCE_ENB,Once Enable" bitfld.long 0x04 0. " ENB ,Enables the ARM platform to access the ONCE_* as any other SDMA control register" "Disabled,Enabled" else group.long 0x3C++0x07 line.long 0x00 "SDMA_LOCK,SDMA LOCK" bitfld.long 0x00 1. " SRESET_LOCK_CLR ,Determines if the LOCK bit is cleared on a software reset triggered by writing to the RESET register" "Not cleared,Cleared" bitfld.long 0x00 0. " LOCK ,Restricts access to update SDMA script memory through ROM channel zero scripts and through the once interface under ARM platform control" "Disengaged,Enabled" line.long 0x04 "ONCE_ENB,Once Enable" bitfld.long 0x04 0. " ENB ,Enables the ARM platform to access the ONCE_* as any other SDMA control register" "Disabled,Enabled" endif group.long 0x44++0x07 line.long 0x00 "ONCE_DATA,Once Data Register" line.long 0x04 "ONCE_INSTR,Once Instruction Register" hexmask.long.word 0x04 0.--15. 1. " INSTR ,Instruction register of the once JTAG controller" rgroup.long 0x4C++0x03 line.long 0x00 "ONCE_STAT,Once Status Register" bitfld.long 0x00 12.--15. " PST ,Processor status" "Program,Data,Change of flow,Change of flow in loop,Debug,Functional unit,Sleep,Save,Program in sleep,Data in sleep,Change of flow in sleep,Change flow in loop in sleep,Debug in sleep,Functional unit in sleep,Sleep after reset,Restore" bitfld.long 0x00 11. " RCV ,Write access to the real time buffer" "No write access,Write access" bitfld.long 0x00 10. " EDR ,SDMA has entered debug mode after an external debug request" "No,Yes" bitfld.long 0x00 9. " ODR ,SDMA has entered debug mode after a once debug request" "No,Yes" textline " " bitfld.long 0x00 8. " SWB ,SDMA has entered debug mode after a software breakpoint" "No,Yes" bitfld.long 0x00 7. " MST ,Once is controlled from the ARM platform peripheral interface" "JTAG,ARM" bitfld.long 0x00 0.--2. " ECDR ,Event cell debug request" "1 matched addra_cond,1 matched addrb_cond,1 matched data_cond,?..." group.long 0x50++0x03 line.long 0x00 "ONCE_CMD,Once Command Register" bitfld.long 0x00 0.--3. " CMD ,CMD" "Rstatus,Dmov,Exec_once,Run_core,Exec_core,Debug_rqst,Rbuffer,?..." if ((per.l(ad:0x302C0000+0x3C)&0x01)==0x01) rgroup.long 0x58++0x07 line.long 0x00 "ILLINSTADDR,Illegal Instruction Trap Address Register" hexmask.long.word 0x00 0.--13. 0x01 " ILLINSTADDR ,Illegal instruction trap address" line.long 0x04 "CHN0ADDR,Channel 0 Boot Address Register" bitfld.long 0x04 14. " SMSZ ,Scratch memory size" "24 words per context,32 words per context" hexmask.long.word 0x04 0.--13. 0x01 " CHN0ADDR ,Channel 0 boot address" else group.long 0x58++0x07 line.long 0x00 "ILLINSTADDR,Illegal Instruction Trap Address Register" hexmask.long.word 0x00 0.--13. 0x01 " ILLINSTADDR ,Illegal instruction trap address" line.long 0x04 "CHN0ADDR,Channel 0 Boot Address Register" bitfld.long 0x04 14. " SMSZ ,Scratch memory size" "24 words per context,32 words per context" hexmask.long.word 0x04 0.--13. 0x01 " CHN0ADDR ,Channel 0 boot address" endif rgroup.long 0x60++0x07 line.long 0x00 "EVT_MIRROR,DMA Requests Register" bitfld.long 0x00 31. " EVENTS[31] ,Reflects the DMA requests received by the SDMA for events 31" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Reflects the DMA requests received by the SDMA for events 30" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Reflects the DMA requests received by the SDMA for events 29" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Reflects the DMA requests received by the SDMA for events 28" "Not pending,Pending" textline " " bitfld.long 0x00 27. " [27] ,Reflects the DMA requests received by the SDMA for events 27" "Not pending,Pending" bitfld.long 0x00 26. " [26] ,Reflects the DMA requests received by the SDMA for events 26" "Not pending,Pending" bitfld.long 0x00 25. " [25] ,Reflects the DMA requests received by the SDMA for events 25" "Not pending,Pending" bitfld.long 0x00 24. " [24] ,Reflects the DMA requests received by the SDMA for events 24" "Not pending,Pending" textline " " bitfld.long 0x00 23. " [23] ,Reflects the DMA requests received by the SDMA for events 23" "Not pending,Pending" bitfld.long 0x00 22. " [22] ,Reflects the DMA requests received by the SDMA for events 22" "Not pending,Pending" bitfld.long 0x00 21. " [21] ,Reflects the DMA requests received by the SDMA for events 21" "Not pending,Pending" bitfld.long 0x00 20. " [20] ,Reflects the DMA requests received by the SDMA for events 20" "Not pending,Pending" textline " " bitfld.long 0x00 19. " [19] ,Reflects the DMA requests received by the SDMA for events 19" "Not pending,Pending" bitfld.long 0x00 18. " [18] ,Reflects the DMA requests received by the SDMA for events 18" "Not pending,Pending" bitfld.long 0x00 17. " [17] ,Reflects the DMA requests received by the SDMA for events 17" "Not pending,Pending" bitfld.long 0x00 16. " [16] ,Reflects the DMA requests received by the SDMA for events 16" "Not pending,Pending" textline " " bitfld.long 0x00 15. " [15] ,Reflects the DMA requests received by the SDMA for events 15" "Not pending,Pending" bitfld.long 0x00 14. " [14] ,Reflects the DMA requests received by the SDMA for events 14" "Not pending,Pending" bitfld.long 0x00 13. " [13] ,Reflects the DMA requests received by the SDMA for events 13" "Not pending,Pending" bitfld.long 0x00 12. " [12] ,Reflects the DMA requests received by the SDMA for events 12" "Not pending,Pending" textline " " bitfld.long 0x00 11. " [11] ,Reflects the DMA requests received by the SDMA for events 11" "Not pending,Pending" bitfld.long 0x00 10. " [10] ,Reflects the DMA requests received by the SDMA for events 10" "Not pending,Pending" bitfld.long 0x00 9. " [9] ,Reflects the DMA requests received by the SDMA for events 9" "Not pending,Pending" bitfld.long 0x00 8. " [8] ,Reflects the DMA requests received by the SDMA for events 8" "Not pending,Pending" textline " " bitfld.long 0x00 7. " [7] ,Reflects the DMA requests received by the SDMA for events 7" "Not pending,Pending" bitfld.long 0x00 6. " [6] ,Reflects the DMA requests received by the SDMA for events 6" "Not pending,Pending" bitfld.long 0x00 5. " [5] ,Reflects the DMA requests received by the SDMA for events 5" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Reflects the DMA requests received by the SDMA for events 4" "Not pending,Pending" textline " " bitfld.long 0x00 3. " [3] ,Reflects the DMA requests received by the SDMA for events 3" "Not pending,Pending" bitfld.long 0x00 2. " [2] ,Reflects the DMA requests received by the SDMA for events 2" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Reflects the DMA requests received by the SDMA for events 1" "Not pending,Pending" bitfld.long 0x00 0. " [0] ,Reflects the DMA requests received by the SDMA for events 0" "Not pending,Pending" line.long 0x04 "EVT_MIRROR2,DMA Requests 2 Register" bitfld.long 0x04 15. " EVENTS[47] ,Reflects the DMA requests received by the SDMA for events 47" "Not pending,Pending" bitfld.long 0x04 14. " [46] ,Reflects the DMA requests received by the SDMA for events 46" "Not pending,Pending" bitfld.long 0x04 13. " [45] ,Reflects the DMA requests received by the SDMA for events 45" "Not pending,Pending" bitfld.long 0x04 12. " [44] ,Reflects the DMA requests received by the SDMA for events 44" "Not pending,Pending" textline " " bitfld.long 0x04 11. " [43] ,Reflects the DMA requests received by the SDMA for events 43" "Not pending,Pending" bitfld.long 0x04 10. " [42] ,Reflects the DMA requests received by the SDMA for events 42" "Not pending,Pending" bitfld.long 0x04 9. " [41] ,Reflects the DMA requests received by the SDMA for events 41" "Not pending,Pending" bitfld.long 0x04 8. " [40] ,Reflects the DMA requests received by the SDMA for events 40" "Not pending,Pending" textline " " bitfld.long 0x04 7. " [39] ,Reflects the DMA requests received by the SDMA for events 39" "Not pending,Pending" bitfld.long 0x04 6. " [38] ,Reflects the DMA requests received by the SDMA for events 38" "Not pending,Pending" bitfld.long 0x04 5. " [37] ,Reflects the DMA requests received by the SDMA for events 37" "Not pending,Pending" bitfld.long 0x04 4. " [36] ,Reflects the DMA requests received by the SDMA for events 36" "Not pending,Pending" textline " " bitfld.long 0x04 3. " [35] ,Reflects the DMA requests received by the SDMA for events 35" "Not pending,Pending" bitfld.long 0x04 2. " [34] ,Reflects the DMA requests received by the SDMA for events 34" "Not pending,Pending" bitfld.long 0x04 1. " [33] ,Reflects the DMA requests received by the SDMA for events 33" "Not pending,Pending" bitfld.long 0x04 0. " [32] ,Reflects the DMA requests received by the SDMA for events 32" "Not pending,Pending" group.long 0x70++0x07 line.long 0x00 "XTRIG_CONF1,Cross-Trigger Events Configuration Register 1" bitfld.long 0x00 30. " CNF3 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x00 24.--29. " NUM3 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22. " CNF2 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x00 16.--21. " NUM2 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 14. " CNF1 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x00 8.--13. " NUM2 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. " CNF0 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x00 0.--5. " NUM0 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "XTRIG_CONF2,Cross-Trigger Events Configuration Register 2" bitfld.long 0x04 30. " CNF7 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x04 24.--29. " NUM7 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 22. " CNF6 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x04 16.--21. " NUM6 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 14. " CNF5 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x04 8.--13. " NUM5 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 6. " CNF4 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x04 0.--5. " NUM4 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 15. tree "Channel Priority Registers" group.long 0x100++0x03 line.long 0x00 "SDMA_CHNPRI0,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI0 ,Contains the priority of channel number 0 " ",1,2,3,4,5,6,7" group.long 0x104++0x03 line.long 0x00 "SDMA_CHNPRI1,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI1 ,Contains the priority of channel number 1 " ",1,2,3,4,5,6,7" group.long 0x108++0x03 line.long 0x00 "SDMA_CHNPRI2,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI2 ,Contains the priority of channel number 2 " ",1,2,3,4,5,6,7" group.long 0x10C++0x03 line.long 0x00 "SDMA_CHNPRI3,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI3 ,Contains the priority of channel number 3 " ",1,2,3,4,5,6,7" group.long 0x110++0x03 line.long 0x00 "SDMA_CHNPRI4,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI4 ,Contains the priority of channel number 4 " ",1,2,3,4,5,6,7" group.long 0x114++0x03 line.long 0x00 "SDMA_CHNPRI5,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI5 ,Contains the priority of channel number 5 " ",1,2,3,4,5,6,7" group.long 0x118++0x03 line.long 0x00 "SDMA_CHNPRI6,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI6 ,Contains the priority of channel number 6 " ",1,2,3,4,5,6,7" group.long 0x11C++0x03 line.long 0x00 "SDMA_CHNPRI7,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI7 ,Contains the priority of channel number 7 " ",1,2,3,4,5,6,7" group.long 0x120++0x03 line.long 0x00 "SDMA_CHNPRI8,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI8 ,Contains the priority of channel number 8 " ",1,2,3,4,5,6,7" group.long 0x124++0x03 line.long 0x00 "SDMA_CHNPRI9,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI9 ,Contains the priority of channel number 9 " ",1,2,3,4,5,6,7" group.long 0x128++0x03 line.long 0x00 "SDMA_CHNPRI10,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI10 ,Contains the priority of channel number 10" ",1,2,3,4,5,6,7" group.long 0x12C++0x03 line.long 0x00 "SDMA_CHNPRI11,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI11 ,Contains the priority of channel number 11" ",1,2,3,4,5,6,7" group.long 0x130++0x03 line.long 0x00 "SDMA_CHNPRI12,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI12 ,Contains the priority of channel number 12" ",1,2,3,4,5,6,7" group.long 0x134++0x03 line.long 0x00 "SDMA_CHNPRI13,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI13 ,Contains the priority of channel number 13" ",1,2,3,4,5,6,7" group.long 0x138++0x03 line.long 0x00 "SDMA_CHNPRI14,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI14 ,Contains the priority of channel number 14" ",1,2,3,4,5,6,7" group.long 0x13C++0x03 line.long 0x00 "SDMA_CHNPRI15,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI15 ,Contains the priority of channel number 15" ",1,2,3,4,5,6,7" group.long 0x140++0x03 line.long 0x00 "SDMA_CHNPRI16,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI16 ,Contains the priority of channel number 16" ",1,2,3,4,5,6,7" group.long 0x144++0x03 line.long 0x00 "SDMA_CHNPRI17,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI17 ,Contains the priority of channel number 17" ",1,2,3,4,5,6,7" group.long 0x148++0x03 line.long 0x00 "SDMA_CHNPRI18,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI18 ,Contains the priority of channel number 18" ",1,2,3,4,5,6,7" group.long 0x14C++0x03 line.long 0x00 "SDMA_CHNPRI19,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI19 ,Contains the priority of channel number 19" ",1,2,3,4,5,6,7" group.long 0x150++0x03 line.long 0x00 "SDMA_CHNPRI20,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI20 ,Contains the priority of channel number 20" ",1,2,3,4,5,6,7" group.long 0x154++0x03 line.long 0x00 "SDMA_CHNPRI21,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI21 ,Contains the priority of channel number 21" ",1,2,3,4,5,6,7" group.long 0x158++0x03 line.long 0x00 "SDMA_CHNPRI22,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI22 ,Contains the priority of channel number 22" ",1,2,3,4,5,6,7" group.long 0x15C++0x03 line.long 0x00 "SDMA_CHNPRI23,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI23 ,Contains the priority of channel number 23" ",1,2,3,4,5,6,7" group.long 0x160++0x03 line.long 0x00 "SDMA_CHNPRI24,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI24 ,Contains the priority of channel number 24" ",1,2,3,4,5,6,7" group.long 0x164++0x03 line.long 0x00 "SDMA_CHNPRI25,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI25 ,Contains the priority of channel number 25" ",1,2,3,4,5,6,7" group.long 0x168++0x03 line.long 0x00 "SDMA_CHNPRI26,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI26 ,Contains the priority of channel number 26" ",1,2,3,4,5,6,7" group.long 0x16C++0x03 line.long 0x00 "SDMA_CHNPRI27,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI27 ,Contains the priority of channel number 27" ",1,2,3,4,5,6,7" group.long 0x170++0x03 line.long 0x00 "SDMA_CHNPRI28,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI28 ,Contains the priority of channel number 28" ",1,2,3,4,5,6,7" group.long 0x174++0x03 line.long 0x00 "SDMA_CHNPRI29,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI29 ,Contains the priority of channel number 29" ",1,2,3,4,5,6,7" group.long 0x178++0x03 line.long 0x00 "SDMA_CHNPRI30,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI30 ,Contains the priority of channel number 30" ",1,2,3,4,5,6,7" group.long 0x17C++0x03 line.long 0x00 "SDMA_CHNPRI31,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI31 ,Contains the priority of channel number 31" ",1,2,3,4,5,6,7" tree.end width 11. tree "Channel Enable RAM Registers" group.long 0x200++0x03 line.long 0x00 "CHNENBL0,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 0 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 0 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 0 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 0 is received" "Disabled,Enabled" textline " " group.long 0x204++0x03 line.long 0x00 "CHNENBL1,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 1 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 1 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 1 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 1 is received" "Disabled,Enabled" textline " " group.long 0x208++0x03 line.long 0x00 "CHNENBL2,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 2 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 2 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 2 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 2 is received" "Disabled,Enabled" textline " " group.long 0x20C++0x03 line.long 0x00 "CHNENBL3,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 3 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 3 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 3 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 3 is received" "Disabled,Enabled" textline " " group.long 0x210++0x03 line.long 0x00 "CHNENBL4,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 4 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 4 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 4 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 4 is received" "Disabled,Enabled" textline " " group.long 0x214++0x03 line.long 0x00 "CHNENBL5,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 5 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 5 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 5 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 5 is received" "Disabled,Enabled" textline " " group.long 0x218++0x03 line.long 0x00 "CHNENBL6,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 6 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 6 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 6 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 6 is received" "Disabled,Enabled" textline " " group.long 0x21C++0x03 line.long 0x00 "CHNENBL7,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 7 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 7 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 7 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 7 is received" "Disabled,Enabled" textline " " group.long 0x220++0x03 line.long 0x00 "CHNENBL8,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 8 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 8 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 8 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 8 is received" "Disabled,Enabled" textline " " group.long 0x224++0x03 line.long 0x00 "CHNENBL9,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 9 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 9 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 9 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 9 is received" "Disabled,Enabled" textline " " group.long 0x228++0x03 line.long 0x00 "CHNENBL10,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 10 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 10 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 10 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 10 is received" "Disabled,Enabled" textline " " group.long 0x22C++0x03 line.long 0x00 "CHNENBL11,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 11 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 11 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 11 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 11 is received" "Disabled,Enabled" textline " " group.long 0x230++0x03 line.long 0x00 "CHNENBL12,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 12 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 12 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 12 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 12 is received" "Disabled,Enabled" textline " " group.long 0x234++0x03 line.long 0x00 "CHNENBL13,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 13 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 13 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 13 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 13 is received" "Disabled,Enabled" textline " " group.long 0x238++0x03 line.long 0x00 "CHNENBL14,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 14 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 14 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 14 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 14 is received" "Disabled,Enabled" textline " " group.long 0x23C++0x03 line.long 0x00 "CHNENBL15,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 15 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 15 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 15 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 15 is received" "Disabled,Enabled" textline " " group.long 0x240++0x03 line.long 0x00 "CHNENBL16,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 16 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 16 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 16 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 16 is received" "Disabled,Enabled" textline " " group.long 0x244++0x03 line.long 0x00 "CHNENBL17,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 17 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 17 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 17 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 17 is received" "Disabled,Enabled" textline " " group.long 0x248++0x03 line.long 0x00 "CHNENBL18,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 18 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 18 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 18 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 18 is received" "Disabled,Enabled" textline " " group.long 0x24C++0x03 line.long 0x00 "CHNENBL19,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 19 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 19 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 19 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 19 is received" "Disabled,Enabled" textline " " group.long 0x250++0x03 line.long 0x00 "CHNENBL20,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 20 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 20 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 20 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 20 is received" "Disabled,Enabled" textline " " group.long 0x254++0x03 line.long 0x00 "CHNENBL21,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 21 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 21 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 21 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 21 is received" "Disabled,Enabled" textline " " group.long 0x258++0x03 line.long 0x00 "CHNENBL22,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 22 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 22 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 22 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 22 is received" "Disabled,Enabled" textline " " group.long 0x25C++0x03 line.long 0x00 "CHNENBL23,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 23 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 23 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 23 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 23 is received" "Disabled,Enabled" textline " " group.long 0x260++0x03 line.long 0x00 "CHNENBL24,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 24 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 24 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 24 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 24 is received" "Disabled,Enabled" textline " " group.long 0x264++0x03 line.long 0x00 "CHNENBL25,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 25 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 25 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 25 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 25 is received" "Disabled,Enabled" textline " " group.long 0x268++0x03 line.long 0x00 "CHNENBL26,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 26 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 26 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 26 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 26 is received" "Disabled,Enabled" textline " " group.long 0x26C++0x03 line.long 0x00 "CHNENBL27,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 27 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 27 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 27 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 27 is received" "Disabled,Enabled" textline " " group.long 0x270++0x03 line.long 0x00 "CHNENBL28,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 28 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 28 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 28 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 28 is received" "Disabled,Enabled" textline " " group.long 0x274++0x03 line.long 0x00 "CHNENBL29,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 29 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 29 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 29 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 29 is received" "Disabled,Enabled" textline " " group.long 0x278++0x03 line.long 0x00 "CHNENBL30,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 30 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 30 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 30 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 30 is received" "Disabled,Enabled" textline " " group.long 0x27C++0x03 line.long 0x00 "CHNENBL31,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 31 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 31 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 31 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 31 is received" "Disabled,Enabled" textline " " group.long 0x280++0x03 line.long 0x00 "CHNENBL32,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 32 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 32 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 32 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 32 is received" "Disabled,Enabled" textline " " group.long 0x284++0x03 line.long 0x00 "CHNENBL33,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 33 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 33 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 33 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 33 is received" "Disabled,Enabled" textline " " group.long 0x288++0x03 line.long 0x00 "CHNENBL34,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 34 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 34 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 34 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 34 is received" "Disabled,Enabled" textline " " group.long 0x28C++0x03 line.long 0x00 "CHNENBL35,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 35 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 35 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 35 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 35 is received" "Disabled,Enabled" textline " " group.long 0x290++0x03 line.long 0x00 "CHNENBL36,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 36 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 36 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 36 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 36 is received" "Disabled,Enabled" textline " " group.long 0x294++0x03 line.long 0x00 "CHNENBL37,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 37 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 37 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 37 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 37 is received" "Disabled,Enabled" textline " " group.long 0x298++0x03 line.long 0x00 "CHNENBL38,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 38 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 38 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 38 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 38 is received" "Disabled,Enabled" textline " " group.long 0x29C++0x03 line.long 0x00 "CHNENBL39,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 39 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 39 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 39 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 39 is received" "Disabled,Enabled" textline " " group.long 0x2A0++0x03 line.long 0x00 "CHNENBL40,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 40 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 40 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 40 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 40 is received" "Disabled,Enabled" textline " " group.long 0x2A4++0x03 line.long 0x00 "CHNENBL41,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 41 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 41 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 41 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 41 is received" "Disabled,Enabled" textline " " group.long 0x2A8++0x03 line.long 0x00 "CHNENBL42,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 42 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 42 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 42 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 42 is received" "Disabled,Enabled" textline " " group.long 0x2AC++0x03 line.long 0x00 "CHNENBL43,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 43 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 43 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 43 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 43 is received" "Disabled,Enabled" textline " " group.long 0x2B0++0x03 line.long 0x00 "CHNENBL44,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 44 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 44 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 44 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 44 is received" "Disabled,Enabled" textline " " group.long 0x2B4++0x03 line.long 0x00 "CHNENBL45,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 45 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 45 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 45 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 45 is received" "Disabled,Enabled" textline " " group.long 0x2B8++0x03 line.long 0x00 "CHNENBL46,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 46 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 46 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 46 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 46 is received" "Disabled,Enabled" textline " " group.long 0x2BC++0x03 line.long 0x00 "CHNENBL47,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 47 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 47 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 47 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 47 is received" "Disabled,Enabled" tree.end width 0x0B tree.end tree.end tree.open "Chip IO and Pinmux" tree "IOMUXC (IOMUX Controller)" tree "IOMUXC_GPR" base ad:0x30340000 width 7. group.long 0x00++0x17 line.long 0x00 "GPR0,GPR0 General Purpose Register" bitfld.long 0x00 6. " DMAREQ_MUX_SEL6 ,Selects sources for SDMA_EVENT41" "GPT4,FTM2_8" bitfld.long 0x00 5. " DMAREQ_MUX_SEL5 ,Selects sources for SDMA_EVENT40" "GPT3,FTM1_7" bitfld.long 0x00 4. " DMAREQ_MUX_SEL4 ,Selects sources for SDMA_EVENT47" "ENET1,ENET2" textline " " bitfld.long 0x00 3. " DMAREQ_MUX_SEL3 ,Selects sources for SDMA_EVENT21" "I2C4,SIM2" bitfld.long 0x00 2. " DMAREQ_MUX_SEL2 ,Selects sources for SDMA_EVENT20" "I2C3,SIM1" bitfld.long 0x00 1. " DMAREQ_MUX_SEL1 ,Selects sources for SDMA_EVENT19" "I2C2,SIM1" textline " " bitfld.long 0x00 0. " DMAREQ_MUX_SEL0 ,Selects sources for SDMA_EVENT18" "I2C1,SIM1" line.long 0x04 "GPR1,GPR1 General Purpose Register" bitfld.long 0x04 28.--31. " DBG_ACK ,Debug acknowledge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " TZASC1_SECURE_BOOT_LOCK ,TZASC-1 secure boot lock" "Disabled,Enabled" bitfld.long 0x04 17. " ENET1_CLK_DIR ,ENET1_TX_CLK data direction control" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " ENET1_TX_CLK_SEL ,ENET1 reference clock mode select" "0,1" bitfld.long 0x04 12. " IRQ ,Interrupt signal" "No interrupt,Interrupt" line.long 0x08 "GPR2,GPR2 General Purpose Register" bitfld.long 0x08 5. " GPR_SAI6_EXT_MCLK_EN ,SAI6 External MCLK Enable" "Disabled,Enabled" bitfld.long 0x08 4. " GPR_SAI5_EXT_MCLK_EN ,SAI5 External MCLK Enable" "Disabled,Enabled" bitfld.long 0x08 3. " GPR_SAI4_EXT_MCLK_EN ,SAI4 External MCLK Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 2. " GPR_SAI3_EXT_MCLK_EN ,SAI3 External MCLK Enable" "Disabled,Enabled" bitfld.long 0x08 1. " GPR_SAI2_EXT_MCLK_EN ,SAI2 External MCLK Enable" "Disabled,Enabled" bitfld.long 0x08 0. " GPR_SAI1_EXT_MCLK_EN ,SAI1 External MCLK Enable" "Disabled,Enabled" line.long 0x0C "GPR3,GPR3 General Purpose Register" rbitfld.long 0x0C 23. " S_WADDR_PIPE_EN_PNDG ,State Retention On-chip RAM write address pipeline enable update is pending" "Not pending,Pending" rbitfld.long 0x0C 22. " S_WDATA_PIPE_EN_PNDG ,State Retention On-chip RAM write data pipeline enable update is pending" "Not pending,Pending" rbitfld.long 0x0C 21. " S_RADDR_PIPE_EN_PNDG ,State Retention On-chip RAM read address pipeline enable update is pending" "Not pending,Pending" textline " " rbitfld.long 0x0C 20. " S_RDATA_WITE_EN_PNDG ,State Retention On-chip RAM read data pipeline enable update is pending" "Not pending,Pending" rbitfld.long 0x0C 19. " WADDR_PIPE_EN_PNDG ,On-chip RAM write address pipeline enable update is pending" "Not pending,Pending" rbitfld.long 0x0C 18. " WDATA_PIPE_EN_PNDG ,On-chip RAM write data pipeline enable update is pending" "Not pending,Pending" textline " " rbitfld.long 0x0C 17. " RADDR_PIPE_EN_PNDG ,On-chip RAM read address pipeline enable update is pending" "Not pending,Pending" rbitfld.long 0x0C 16. " RDATA_WAIT_EN_PNDG ,On-chip RAM read data pipeline enable update is pending" "Not pending,Pending" bitfld.long 0x0C 7. " S_WADDR_PIPE_EN_EN ,State Retention On-chip RAM write address pipeline enable update is enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 6. " S_WDATA_PIPE_EN_EN ,State Retention On-chip RAM write data pipeline enable update is enable" "Disabled,Enabled" bitfld.long 0x0C 5. " S_RADDR_PIPE_EN_EN ,State Retention On-chip RAM read address pipeline enable update is enable" "Disabled,Enabled" bitfld.long 0x0C 4. " S_RDATA_WITE_EN_EN ,State Retention On-chip RAM read data pipeline enable update is enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 3. " WADDR_PIPE_EN_EN ,On-chip RAM write address pipeline enable update is enable" "Disabled,Enabled" bitfld.long 0x0C 2. " WDATA_PIPE_EN_EN ,On-chip RAM write data pipeline enable update is enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RADDR_PIPE_EN_EN ,On-chip RAM read address pipeline enable update is enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " RDATA_WAIT_EN_EN ,On-chip RAM read data pipeline enable update is enable" "Disabled,Enabled" line.long 0x10 "GPR4,GPR4 General Purpose Register" rbitfld.long 0x10 26. " SAI6_IPG_STOP_ACK ,SAI6 stop acknowledge" "Not asserted,Asserted" rbitfld.long 0x10 25. " SAI5_IPG_STOP_ACK ,SAI5 stop acknowledge" "Not asserted,Asserted" rbitfld.long 0x10 24. " SAI4_IPG_STOP_ACK ,SAI4 stop acknowledge" "Not asserted,Asserted" textline " " rbitfld.long 0x10 23. " SAI3_IPG_STOP_ACK ,SAI3 stop acknowledge" "Not asserted,Asserted" rbitfld.long 0x10 22. " SAI2_IPG_STOP_ACK ,SAI2 stop acknowledge" "Not asserted,Asserted" rbitfld.long 0x10 21. " SAI1_IPG_STOP_ACK ,SAI1 stop acknowledge" "Not asserted,Asserted" textline " " rbitfld.long 0x10 20. " SDMA2_IPG_STOP_ACK ,SDMA2 stop acknowledge" "Not asserted,Asserted" rbitfld.long 0x10 19. " ENET1_IPG_STOP_ACK ,ENET1 stop acknowledge" "Not asserted,Asserted" rbitfld.long 0x10 16. " SDMA1_IPG_STOP_ACK ,SDMA1 stop acknowledge" "Not asserted,Asserted" textline " " bitfld.long 0x10 4. " SDMA2_IPG_STOP ,SDMA2 stop request" "Not requested,Requested" bitfld.long 0x10 3. " ENET1_IPG_STOP ,ENET1 stop request" "Not requested,Requested" bitfld.long 0x10 2. " ENET1_IPD_REQ_TIMER_SEL1 ,ENET1 IPD_REQ Timer Select1" "Timer 3,Timer 1" textline " " bitfld.long 0x10 1. " ENET1_IPD_REQ_TIMER_SEL0 ,ENET1 IPD_REQ Timer Select0" "Timer 2,Timer 0" bitfld.long 0x10 0. " SDMA1_IPG_STOP ,SDMA1 stop request" "Off,On" line.long 0x14 "GPR5,GPR5 General Purpose Register" bitfld.long 0x14 20. " WDOG3_MASK ,WDOG3 timeout mask" "Not masked,Masked" bitfld.long 0x14 7. " WDOG2_MASK ,WDOG2 timeout mask" "Not masked,Masked" bitfld.long 0x14 6. " WDOG1_MASK ,WDOG1 timeout mask" "Not masked,Masked" textline " " bitfld.long 0x14 3. " HDMI_CEC_PD ,Connect to hdmi_cec_pd_pad" "Not connected,Connected" bitfld.long 0x14 2. " HDMI_DDC_SCL_PD ,Connect to hdmi_ddc_scl_pd_pad" "Not connected,Connected" bitfld.long 0x14 1. " HDMI_DDC_SDA_PD ,Connect to hdmi_ddc_sda_pd_pad" "Not connected,Connected" textline " " bitfld.long 0x14 0. " HDMI_HPD_PD ,Connect to hdmi_hpd_pd_pad" "Not connected,Connected" group.long 0x28++0x1F line.long 0x00 "GPR10,GPR10 General Purpose Register" bitfld.long 0x00 19. " EXC_ERR_RESP_EN_LOCK ,Lock bit for EXC_ERR_RESP_EN" "Unlocked,Locked" bitfld.long 0x00 18. " SEC_ERR_RESP_EN_LOCK ,Lock bit for SEC_ERR_RESP_EN" "Unlocked,Locked" bitfld.long 0x00 17. " TZASC_ID_SWAP_BYPASS_LOCK ,Lock bit for TZASC_ID_SWAP_BYPASS" "Unlocked,Locked" textline " " bitfld.long 0x00 16. " TZASC_EN_LOCK ,Lock bit for TZASC_EN" "Unlocked,Locked" bitfld.long 0x00 3. " EXC_ERR_RESP_EN ,Security exclusive access error response enable" "OK,ERR" bitfld.long 0x00 2. " SEC_ERR_RESP_EN ,Security error response enable" "OKAY,SLVERR" textline " " bitfld.long 0x00 1. " TZASC_ID_SWAP_BYPASS ,Connect to id_swap_bypass input on tzasc_id_wrap" "Not connected,Connected" bitfld.long 0x00 0. " TZASC_EN ,Connect to tzasc_en input on tzasc_id_wrap" "Not connected,Connected" line.long 0x04 "GPR11,GPR11 General Purpose Register" bitfld.long 0x04 27.--29. " OCRAM_S_TZ_ADDR_LOCK ,OCRAM S TZ ADDR lock bits" "0,1,2,3,4,5,6,7" bitfld.long 0x04 26. " OCRAM_S_TZ_EN_LOCK ,OCRAM_S_TZ_EN lock bit" "Unlocked,Locked" bitfld.long 0x04 17.--21. " OCRAM_TZ_ADDR_LOCK ,OCRAM TZ ADDR lock bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 16. " OCRAM_TZ_EN_LOCK ,OCRAM_TZ_EN lock bit" "Unlocked,Locked" bitfld.long 0x04 11.--13. " OCRAM_S_TZ_ADDR ,State retention OCRAM TrustZone (TZ) start address" "0,1,2,3,4,5,6,7" bitfld.long 0x04 10. " OCRAM_S_TZ_EN ,State Retention OCRAM TrustZone (TZ) enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1.--5. " OCRAM_TZ_ADDR ,OCRAM TrustZone (TZ) start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0. " OCRAM_TZ_EN ,OCRAM TrustZone (TZ) enable" "Disabled,Enabled" line.long 0x08 "GPR12,GPR12 General Purpose Register" bitfld.long 0x08 31. " PCIE_DIAG_BUS_SEL ,Control the source of the PCIE DIAG STATUS bus" "PCIe1,PCIE2" bitfld.long 0x08 29.--30. " PCIE2_CTRL_DIAG_CTRL_BUS ,PCI Express 2 Diagnostic Control Bus" "0,1,2,3" bitfld.long 0x08 25.--28. " PCIE2_CTRL_DIAG_STATUS_BUS_SELECT ,PCI Express Diagnostic Status Bus Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 21.--22. " PCIE1_CTRL_DIAG_CTRL_BUS ,PCI Express 1 Diagnostic Control Bus" "0,1,2,3" bitfld.long 0x08 17.--20. " PCIE1_CTRL_DIAG_STATUS_BUS_SELECT ,PCI Express Diagnostic Status Bus Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 12.--15. " PCIE1_CTRL_DEVICE_TYPE ,PCI express 1 device/port type" "PCIe,Legacy PCIe,,PCIe root complex,?..." textline " " bitfld.long 0x08 8.--11. " PCIE2_CTRL_DEVICE_TYPE ,PCI express 2 device/port type" "PCIe,Legacy PCIe,,PCIe root complex,?..." line.long 0x0C "GPR13,GPR13 General Purpose Register" bitfld.long 0x0C 14. " AWCACHE_PCIE2 ,PCIe AXI Master Port AWCACHE Override Value" "0,1" bitfld.long 0x0C 13. " ARCACHE_PCIE2 ,PCIe AXI Master Port ARCACHE Override Value" "0,1" bitfld.long 0x0C 12. " ARCACHE_LCDIF_EN ,LCDIF AXI master port ARCACHE override enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 11. " AWCACHE_PCIE1_EN ,PCIe AXI Master port AWCACHE override enable" "Disabled,Enabled" bitfld.long 0x0C 10. " ARCACHE_PCIE1_EN ,PCIE AXI master port ARCACHE override enable" "Disabled,Enabled" bitfld.long 0x0C 9. " AWCACHE_PCIE2_EN ,PCIe AXI master port AWCACHE override enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 8. " ARCACHE_PCIE2_EN ,PCIE AXI master port ARCACHE override enable" "Disabled,Enabled" bitfld.long 0x0C 6. " ARCACHE_LCDIF ,LCDIF AXI master port ARCACHE override value" "0,1" bitfld.long 0x0C 5. " AWCACHE_PCIE1 ,PCIE AXI master port ARCACHE override" "0,1" textline " " bitfld.long 0x0C 4. " ARCACHE_PCIE1 ,PCIe AXI Master Port ARCACHE Override Value" "0,1" bitfld.long 0x0C 3. " MIPI_MUX_INV ,MIPI MUX INV" "0,1" bitfld.long 0x0C 2. " MIPI_MUX_SEL ,MIPI MUX SEL" "0,1" textline " " bitfld.long 0x0C 1. " AWCACHE_USDHC ,USDHC 1-3 AXI master port ARCACHE override value" "0,1" bitfld.long 0x0C 0. " ARCACHE_USDHC ,USDHC 1-3 AXI master ARCACHE override value" "0,1" line.long 0x10 "GPR14,GPR14 General Purpose Register" bitfld.long 0x10 29.--31. " PCIE1_PHY_LOS_BIAS ,PCIE1 PHY LOS BIAS" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--28. " PCIE1_PHY_LOS_LEVEL ,PCIE1_PHY_LOS_LEVEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 21.--23. " PCIE1_PHY_RX0_EQ ,PCIE1 PHY RX0 EQ" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x10 16.--20. " PCIE1_PHY_TX0_TERM_OFFSET ,PCIE1_PHY_TX0_TERM_OFFSET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 13.--15. " PCIE1_PHY_TX_VBOOST_LVL ,PCIE1 PHY TX VBOOST level" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12. " PCIE1_VREG_BYPASS ,PCIE1_VREG_BYPASS" "0,1" textline " " bitfld.long 0x10 11. " PCIE1_CLKREQ_B_OVERRIDE ,PCIE1 CLKREQ B override" "Not override,Overridden" bitfld.long 0x10 10. " PCIE1_CLKREQ_B_OVERRIDE_EN ,PCIE1_CLKREQ_B_OVERRIDE_EN" "Disabled,Enabled" bitfld.long 0x10 9. " PCIE1_REF_USE_PAD ,PCIE1 REF USE pad" "0,1" textline " " bitfld.long 0x10 8. " PCIE1_APP_CLK_PM_EN ,PCIE1_APP_CLK_PM_EN" "Disabled,Enabled" line.long 0x14 "GPR15,GPR15 General Purpose Register" bitfld.long 0x14 26.--31. " PCIE1_PCS_TX_DEEMPH_GEN1 ,PPCIE1_PCS_TX_DEEMPH_GEN1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 20.--25. " PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB ,PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 14.--19. " PCIE1_PCS_TX_DEEMPH_GEN2_6DB ,PCIE1_PCS_TX_DEEMPH_GEN2_6DB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x14 7.--13. 1. " PCIE1_PCS_TX_SWING_FULL ,PCIE1_PCS_TX_SWING_FULL" hexmask.long.byte 0x14 0.--6. 1. " PCI1_PCS_TX_SWING_LOW ,PCI1 PCS TX SWING low" line.long 0x18 "GPR16,GPR16 General Purpose Register" bitfld.long 0x18 29.--31. " PCIE2_PHY_LOS_BIAS ,PCIE2_PHY_LOS_BIAS" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--28. " PCIE2_PHY_LOS_LEVEL ,PCIE2_PHY_LOS_LEVEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 21.--23. " PCIE2_PHY_RX0_EQ ,PCIE2_PHY_RX0_EQ" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x18 16.--20. " PCIE2_PHY_TX0_TERM_OFFSET ,PCIE2_PHY_TX0_TERM_OFFSET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 13.--15. " PCIE2_PHY_TX_VBOOST_LVL ,PCIE2_PHY_TX_VBOOST_LVL" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12. " PCIE2_VREG_BYPASS ,PCIE2_VREG_BYPASS" "Not bypassed,Bypassed" textline " " bitfld.long 0x18 11. " PCIE2_CLKREQ_B_OVERRIDE ,PCIE2_CLKREQ_B_OVERRIDE" "Not override,Overridden" bitfld.long 0x18 10. " PCIE2_CLKREQ_B_OVERRIDE_EN ,PCIE2_CLKREQ_B_OVERRIDE_EN" "Disabled,Enabled" bitfld.long 0x18 9. " PCIE2_REF_USE_PAD ,PCIE2_REF_USE_PAD" "0,1" textline " " bitfld.long 0x18 8. " PCIE2_APP_CLK_PM_EN ,PCIE2_APP_CLK_PM_EN" "Disabled,Enabled" line.long 0x1C "GPR17,GPR17 General Purpose Register" bitfld.long 0x1C 26.--31. " PCIE2_PCS_TX_DEEMPH_GEN1 ,PCIE2 PCS TX DEEMPH GEN1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 20.--25. " PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB ,PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 14.--19. " PCIE2_PCS_TX_DEEMPH_GEN2_6DB ,PCIE2_PCS_TX_DEEMPH_GEN2_6DB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x1C 7.--13. 1. " PCIE2_PCS_TX_SWING_FULL ,PCIE2_PCS_TX_SWING_FULL" hexmask.long.byte 0x1C 0.--6. 1. " PCI2_PCS_TX_SWING_LOW ,PCI2_PCS_TX_SWING_LOW" rgroup.long 0x4C++0x03 line.long 0x00 "GPR19,GPR19 General Purpose Register" rgroup.long 0x58++0x03 line.long 0x00 "GPR22,GPR22 General Purpose Register" bitfld.long 0x00 20.--23. " CPU_STANDBYWFE ,CPU STANDBYWFE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CPU_STANDBYWFI ,CPU_STANDBYWFI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5C++0x03 line.long 0x00 "GPR23,GPR23 General Purpose Register" bitfld.long 0x00 15. " DDSI_DPHY_TURNAROUND ,DDSI_DPHY_TURNAROUND" "0,1" bitfld.long 0x00 14. " DSI_TRIGGER_REQ ,DSI_TRIGGER_REQ" "Not requested,Requested" bitfld.long 0x00 12.--13. " DSI_TRIGGER_SEND ,DSI trigger send" "0,1,2,3" textline " " bitfld.long 0x00 7.--11. " DSI_TX_ULPS_ENABLE ,DSI_TX_ULPS_ENABLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " DSI_HSEL ,DSI HSEL" "0,1" bitfld.long 0x00 5. " DSI_NOCAL ,DSI_NOCAL" "0,1" textline " " bitfld.long 0x00 3.--4. " DSI_RCALT ,DSI RCALT" "0,1,2,3" bitfld.long 0x00 2. " DSI_RTERM_SEL ,DSI_RTERM_SEL" "0,1" bitfld.long 0x00 0.--1. " DSI_RX_RCAL ,DSI RX RCAL" "0,1,2,3" rgroup.long 0x60++0x27 line.long 0x00 "GPR24,GPR24 General Purpose Register" bitfld.long 0x00 21.--25. " DSI_ULPS_ACTIVE ,DSI_ULPS_ACTIVE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DSI_CALCOMPL ,DSI_CALCOMPL" "0,1" bitfld.long 0x00 18.--19. " DSI_CALOUT ,DSI CALOUT" "0,1,2,3" textline " " bitfld.long 0x00 17. " DSI_CRC_ERR ,DSI_CRC_ERR" "No error,Error" bitfld.long 0x00 16. " DSI_DPHY_DIRECTION ,DSI DPHY direction" "0,1" bitfld.long 0x00 15. " DSI_HOST_BTA_TIMEOUT ,DSI_HOST_BTA_TIMEOUT" "0,1" textline " " bitfld.long 0x00 14. " DSI_HS_TX_TMEOUT ,DSI HS TX TIMEOUT" "0,1" bitfld.long 0x00 13. " DSI_LP_RX_TIMEOUT ,DSI_LP_RX_TIMEOUT" "0,1" bitfld.long 0x00 12. " DSI_TRIGGER_ACK ,DSI trigger ACK" "0,1" textline " " bitfld.long 0x00 11. " DSI_HOST_UNDERRUN_ERR ,DSI_HOST_UNDERRUN_ERR" "No error,Error" bitfld.long 0x00 10. " DSI_ECC_ERR ,DSI ECC ERR" "0,1" bitfld.long 0x00 7.--9. " DSI_ECC_ERR_POS ,DSI_ECC_ERR_POS" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6. " DSI_ECC_ONE_BIT_ERR ,DSI ECC one bit ERR" "0,1" bitfld.long 0x00 1.--5. " DSI_ECC_ONE_BIT_ERR_POS ,DSI_ECC_ONE_BIT_ERR_POS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " DSI_TWO_BIT_ERR ,DSI_TWO_BIT_ERR" "No error,Error" line.long 0x04 "GPR25,GPR25 General Purpose Register" hexmask.long 0x04 0.--29. 1. " DSI_UI_STATUS3_RO ,DSI_UI_STATUS3_RO" line.long 0x08 "GPR26,GPR26 General Purpose Register" line.long 0x0C "GPR27,GPR27 General Purpose Register" line.long 0x10 "GPR28,GPR28 General Purpose Register" line.long 0x14 "GPR29,GPR29 General Purpose Register" line.long 0x18 "GPR30,GPR30 General Purpose Register" bitfld.long 0x18 20. " DSI_D0_LB_ACTIVE ,DSI D0 LB active" "not activated,Activated" hexmask.long.word 0x18 10.--19. 1. " DSI_D0_INT_LB_ERR_CNT ,DSI_D0_INT_LB_ERR_CNT" hexmask.long.word 0x18 0.--9. 1. " DSI_D0_INT_LB_BYTE_CNT ,DSI D0 INT LB byte CNT" line.long 0x1C "GPR31,GPR31 General Purpose Register" bitfld.long 0x1C 20. " DSI_D1_LB_ACTIVE ,DSI D1 LB active" "not activated,Activated" hexmask.long.word 0x1C 10.--19. 1. " DSI_D1_INT_LB_ERR_CNT ,DSI_D1_INT_LB_ERR_CNT" hexmask.long.word 0x1C 0.--9. 1. " DSI_D1_INT_LB_BYTE_CNT ,DSI D1 INT LB byte CNT" line.long 0x20 "GPR32,GPR32 General Purpose Register" bitfld.long 0x20 20. " DSI_D2_LB_ACTIVE ,DSI D2 LB active" "not activated,Activated" hexmask.long.word 0x20 10.--19. 1. " DSI_D2_INT_LB_ERR_CNT ,DSI_D2_INT_LB_ERR_CNT" hexmask.long.word 0x20 0.--9. 1. " DSI_D2_INT_LB_BYTE_CNT ,DSI D2 INT LB byte CNT" line.long 0x24 "GPR33,GPR33 General Purpose Register" bitfld.long 0x24 20. " DSI_D3_LB_ACTIVE ,DSI D3 LB active" "not activated,Activated" hexmask.long.word 0x24 10.--19. 1. " DSI_D3_INT_LB_ERR_CNT ,DSI_D3_INT_LB_ERR_CNT" hexmask.long.word 0x24 0.--9. 1. " DSI_D3_INT_LB_BYTE_CNT ,DSI D3 INT LB byte CNT" group.long 0x88++0x03 line.long 0x00 "GPR34,GPR34 General Purpose Register" bitfld.long 0x00 13. " CSI2_1_RX_ENABLE ,CSI2 1 RX enable" "Disabled,Enabled" bitfld.long 0x00 12. " CSI2_1_VID_INTFC_ENB ,CSI2_1_VID_INTFC_ENB" "Disabled,Enabled" bitfld.long 0x00 11. " CSI2_1_PD_RX ,CSI2 1 PD RX" "0,1" textline " " bitfld.long 0x00 10. " CSI2_1_HSEL ,CSI2_1_HSEL" "0,1" bitfld.long 0x00 9. " CSI2_1_AUTO_PD_EN ,CSI2 1 auto PD enable" "Disabled,Enabled" bitfld.long 0x00 8. " CSI2_1_CONT_CLK_MODE ,CSI2_1_CONT_CLK_MODE" "0,1" textline " " bitfld.long 0x00 2.--7. " CSI2_1_S_PRG_RXHS_SETTLE ,CSI2 1 SPRG RXHS settle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. " CSI2_1_RX_RCAL ,CSI2 1 RX RCAL" "0,1,2,3" rgroup.long 0x8C++0x17 line.long 0x00 "GPR35,GPR35 General Purpose Register" bitfld.long 0x00 24. " CSI2_1_ERR_SEND_LEVEL ,CSI2 1 ERR send level" "0,1" bitfld.long 0x00 23. " CSI2_1_ERR_FIFO_WR_OVFL ,CSI2_1_ERR_FIFO_WR_OVFL" "0,1" bitfld.long 0x00 18.--22. " CSI2_1_ULPS_ACTIVE ,CSI2 1 ILPS active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 17. " CSI2_1_CRC_ERR ,CSI2_1_CRC_ERR" "No error,Error" bitfld.long 0x00 16. " CSI2_1_RX_DPHY_RDY ,CSI2 1 RX DPHY RDY" "0,1" bitfld.long 0x00 11.--15. " CSI2_1_ULPS_MARK_ACTIVE ,CSI2_1_ULPS_MARK_ACTIVE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 10. " CSI2_1_ECC_ERR ,CSI2 1 ECC ERR" "0,1" bitfld.long 0x00 7.--9. " CSI2_1_ECC_ERR_POS ,CSI2_1_ECC_ERR_POS" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. " CSI2_1_ECC_OE_BIT_ERROR ,CSI2 1 ECC one bit error" "0,1" textline " " bitfld.long 0x00 1.--5. " CSI2_1_ECC_ONE_BIT_ERR_POS ,CSI2_1_ECC_ONE_BIT_ERR_POS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " CSI2_1_ECC_TWO_BIT_ERROR ,CSI2 1 ECC two bit error" "0,1" line.long 0x04 "GPR36,GPR36 General Purpose Register" line.long 0x08 "GPR37,GPR37 General Purpose Register" bitfld.long 0x08 20. " CSI2_1_DO_LB_ACTIVE ,CSI2 1 D0 LB active" "Not activated,Activated" hexmask.long.word 0x08 10.--19. 1. " CSI2_1_D0_INT_LB_ERR_CNT ,CSI2_1_D0_INT_LB_ERR_CNT" hexmask.long.word 0x08 0.--9. 1. " CSI2_1_D0_INT_LB_BYTE_CNT ,CSI2 1 D0 INT LB byte CNT" line.long 0x0C "GPR38,GPR38 General Purpose Register" bitfld.long 0x0C 20. " CSI2_1_D1_LB_ACTIVE ,CSI2 1 D1 LB active" "Not activated,Activated" hexmask.long.word 0x0C 10.--19. 1. " CSI2_1_D1_INT_LB_ERR_CNT ,CSI2_1_D1_INT_LB_ERR_CNT" hexmask.long.word 0x0C 0.--9. 1. " CSI2_1_D1_INT_LB_BYTE_CNT ,CSI2 1 D1 INT LB byte CNT" line.long 0x10 "GPR39,GPR39 General Purpose Register" bitfld.long 0x10 20. " CSI2_1_D2_LB_ACTIVE ,CSI2 1 D2 LB active" "Not activated,Activated" hexmask.long.word 0x10 10.--19. 1. " CSI2_1_D2_INT_LB_ERR_CNT ,CSI2_1_D2_INT_LB_ERR_CNT" hexmask.long.word 0x10 0.--9. 1. " CSI2_1_D2_INT_LB_BYTE_CNT ,CSI2 1 D2 INT LB byte CNT" line.long 0x14 "GPR40,GPR40 General Purpose Register" bitfld.long 0x14 20. " CSI2_1_D3_LB_ACTIVE ,CSI2 1 D3 LB active" "Not activated,Activated" hexmask.long.word 0x14 10.--19. 1. " CSI2_1_D3_INT_LB_ERR_CNT ,CSI2_1_D3_INT_LB_ERR_CNT" hexmask.long.word 0x14 0.--9. 1. " CSI2_1_D3_INT_LB_BYTE_CNT ,CSI2 1 D3 INT LB byte CNT" group.long 0xA4++0x03 line.long 0x00 "GPR41,GPR41 General Purpose Register" bitfld.long 0x00 13. " CSI2_2_RX_Enable ,CSI2 2 RX enable" "Disabled,Enabled" bitfld.long 0x00 12. " CSI2_2_VID_INTFC_ENB ,CSI2_2_VID_INTFC_ENB" "Disabled,Enabled" bitfld.long 0x00 11. " CSI2_2_PD_RX ,CSI2 2 PD RX" "0,1" textline " " bitfld.long 0x00 10. " CSI2_2_HSEL ,CSI2_2_HSEL" "0,1" bitfld.long 0x00 9. " CSI2_2_AUTO_PD_EN ,CSI2 2 auto PD enable" "Disabled,Enabled" bitfld.long 0x00 8. " CSI2_2_CONT_CLK_MODE ,CSI2_2_CONT_CLK_MODE" "0,1" textline " " bitfld.long 0x00 2.--7. " CSI2_2_S_PRG_RXHS_SETTLE ,CSI2 2 SPRG RXHS settle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. " CSI2_2_RX_RCAL ,CSI2_2_RX_RCAL" "0,1,3,4" rgroup.long 0xA8++0x17 line.long 0x00 "GPR42,GPR42 General Purpose Register" bitfld.long 0x00 24. " CSI2_2_ERR_SEND_LEVEL ,CSI2 2 ERR send level" "0,1" bitfld.long 0x00 23. " CSI2_2_ERR_FIFO_WR_OVFL ,CSI2_2_ERR_FIFO_WR_OVFL" "0,1" bitfld.long 0x00 18.--22. " CSI2_2_ULPS_ACTIVE ,CSI2 2 ILPS active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 17. " CSI2_2_CRC_ERR ,CSI2_2_CRC_ERR" "No error,Error" bitfld.long 0x00 16. " CSI2_2_RX_DPHY_RDY ,CSI2 2 RX DPHY RDY" "0,1" bitfld.long 0x00 11.--15. " CSI2_2_ULPS_MARK_ACTIVE ,CSI2_2_ULPS_MARK_ACTIVE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 10. " CSI2_2_ECC_ERR ,CSI2 2 ECC ERR" "0,1" bitfld.long 0x00 7.--9. " CSI2_2_ECC_ERR_POS ,CSI2_2_ECC_ERR_POS" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. " CSI2_2_ECC_OE_BIT_ERROR ,CSI2 2 ECC one bit error" "0,1" textline " " bitfld.long 0x00 1.--5. " CSI2_2_ECC_ONE_BIT_ERR_POS ,CSI2_2_ECC_ONE_BIT_ERR_POS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " CSI2_2_ECC_TWO_BIT_ERROR ,CSI2 2 ECC two bit error" "0,1" line.long 0x04 "GPR43,GPR43 General Purpose Register" line.long 0x08 "GPR44,GPR4 General Purpose Register" bitfld.long 0x08 20. " CSI2_2_DO_LB_ACTIVE ,CSI2 2 D0 LB active" "Not activated,Activated" hexmask.long.word 0x08 10.--19. 1. " CSI2_2_D0_INT_LB_ERR_CNT ,CSI2_2_D0_INT_LB_ERR_CNT" hexmask.long.word 0x08 0.--9. 1. " CSI2_2_D0_INT_LB_BYTE_CNT ,CSI2 2 D0 INT LB byte CNT" line.long 0x0C "GPR45,GPR45 General Purpose Register" bitfld.long 0x0C 20. " CSI2_2_D1_LB_ACTIVE ,CSI2 2 D1 LB active" "Not activated,Activated" hexmask.long.word 0x0C 10.--19. 1. " CSI2_2_D1_INT_LB_ERR_CNT ,CSI2_2_D1_INT_LB_ERR_CNT" hexmask.long.word 0x0C 0.--9. 1. " CSI2_2_D1_INT_LB_BYTE_CNT ,CSI2 2 D1 INT LB byte CNT" line.long 0x10 "GPR46,GPR46 General Purpose Register" bitfld.long 0x10 20. " CSI2_2_D2_LB_ACTIVE ,CSI2 2 D2 LB active" "Not activated,Activated" hexmask.long.word 0x10 10.--19. 1. " CSI2_2_D2_INT_LB_ERR_CNT ,CSI2_2_D2_INT_LB_ERR_CNT" hexmask.long.word 0x10 0.--9. 1. " CSI2_2_D2_INT_LB_BYTE_CNT ,CSI2 2 D2 INT LB byte CNT" line.long 0x14 "GPR47,GPR47 General Purpose Register" bitfld.long 0x14 20. " CSI2_2_D3_LB_ACTIVE ,CSI2 2 D3 LB active" "Not activated,Activated" hexmask.long.word 0x14 10.--19. 1. " CSI2_2_D3_INT_LB_ERR_CNT ,CSI2_2_D3_INT_LB_ERR_CNT" hexmask.long.word 0x14 0.--9. 1. " CSI2_2_D3_INT_LB_BYTE_CNT ,CSI2 2 D3 INT LB byte CNT" width 0x0B tree.end tree "IOMUXC" base ad:0x30330000 width 35. group.long 0x14++0x13 line.long 0x00 "SW_MUX_CTL_PAD_PMIC_STBY_REQ,SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register" bitfld.long 0x00 6. " SION ,Software Input On Field" "Disabled,Enabled" line.long 0x04 "SW_MUX_CTL_PAD_PMIC_ON_REQ,SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register" bitfld.long 0x04 6. " SION ,Software Input On Field" "Disabled,Enabled" line.long 0x08 "SW_MUX_CTL_PAD_ONOFF,SW_MUX_CTL_PAD_ONOFF SW MUX Control Register" bitfld.long 0x08 6. " SION ,Software Input On Field" "Disabled,Enabled" line.long 0x0C "SW_MUX_CTL_PAD_POR_B,SW_MUX_CTL_PAD_POR_B SW MUX Control Register" bitfld.long 0x0C 6. " SION ,Software Input On Field" "Disabled,Enabled" line.long 0x10 "SW_MUX_CTL_PAD_RTC_RESET_B,SW_MUX_CTL_PAD_RTC_RESET_B SW MUX Control Register" bitfld.long 0x10 6. " SION ,Software Input On Field" "Disabled,Enabled" group.long 0x28++0x1F line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO00,SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Control Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "BPIO1_IO00,ENET_PHY_REF_CLK_ROOT,,,,ANAMIX_REF_CLK_32K,CCM_EXT_CLK1,?..." line.long 0x04 "SW_MUX_CTL_PAD_GPIO1_IO01,SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Control Register" bitfld.long 0x04 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO01,PWM1_OUT,,,,ANAMIX_REF_CLK_24M,CCM_EXT_CLK2,?..." line.long 0x08 "SW_MUX_CTL_PAD_GPIO1_IO02,SW_MUX_CTL_PAD_GPIO1_IO10 SW MUX Control Register" bitfld.long 0x08 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO02,WDOG1_WDOG_B,,,,WDOG_ANY,?..." line.long 0x0C "SW_MUX_CTL_PAD_GPIO1_IO03,SW_MUX_CTL_PAD_GPIO1_IO11 SW MUX Control Register" bitfld.long 0x0C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x0C 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO03,USDHC1_VSELECT,,,,SDMA_EXT_EVENT0,?..." line.long 0x10 "SW_MUX_CTL_PAD_GPIO1_IO04,SW_MUX_CTL_PAD_GPIO1_IO12 SW MUX Control Register" bitfld.long 0x10 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x10 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO04,USDHC2_VSELECT,,,,SDMA1_EXT_EVENT1,?..." line.long 0x14 "SW_MUX_CTL_PAD_GPIO1_IO05,SW_MUX_CTL_PAD_GPIO1_IO13 SW MUX Control Register" bitfld.long 0x14 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x14 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO05,M4_NMI,,,,CCM_PMIC_READY,?..." line.long 0x18 "SW_MUX_CTL_PAD_GPIO1_IO06,SW_MUX_CTL_PAD_GPIO1_IO14 SW MUX Control Register" bitfld.long 0x18 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x18 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO06,ENET1_MDC,,,,USDHC1_CD_B,CCM_EXT_CLK3,?..." line.long 0x1C "SW_MUX_CTL_PAD_GPIO1_IO07,SW_MUX_CTL_PAD_GPIO1_IO15 SW MUX Control Register" bitfld.long 0x1C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO07,ENET1_MDIO,,,,USDHC1_WP,CCM_EXT_CLK4,?..." group.long 0x48++0x473 line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO08,SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Control Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "BPIO1_IO08,ENET1_1588_EVENT0_IN,,,,USDHC_RESET_B,?..." line.long 0x04 "SW_MUX_CTL_PAD_GPIO1_IO09,SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Control Register" bitfld.long 0x04 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO9,ENET1_1588_EVENT0_OUT,,,,SDMA2_EXT_EVENT0,?..." line.long 0x08 "SW_MUX_CTL_PAD_GPIO1_IO10,SW_MUX_CTL_PAD_GPIO1_IO10 SW MUX Control Register" bitfld.long 0x08 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO10,USB1_OTG_ID,?..." line.long 0x0C "SW_MUX_CTL_PAD_GPIO1_IO11,SW_MUX_CTL_PAD_GPIO1_IO11 SW MUX Control Register" bitfld.long 0x0C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x0C 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO11,USB2_OTG_ID,,,,CCM_PMIC_READY,?..." line.long 0x10 "SW_MUX_CTL_PAD_GPIO1_IO12,SW_MUX_CTL_PAD_GPIO1_IO12 SW MUX Control Register" bitfld.long 0x10 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x10 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO12,USB1_OTG_PWR,,,,SDMA_EXT_EVENT1,?..." line.long 0x14 "SW_MUX_CTL_PAD_GPIO1_IO13,SW_MUX_CTL_PAD_GPIO1_IO13 SW MUX Control Register" bitfld.long 0x14 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x14 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO13,USB1_OTG_OC,,,,PWM2_OUT,?..." line.long 0x18 "SW_MUX_CTL_PAD_GPIO1_IO14,SW_MUX_CTL_PAD_GPIO1_IO14 SW MUX Control Register" bitfld.long 0x18 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x18 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO14,USB2_OTG_PWR,,,,PWM3_OUT,CCM_CLKO1,?..." line.long 0x1C "SW_MUX_CTL_PAD_GPIO1_IO15,SW_MUX_CTL_PAD_GPIO1_IO15 SW MUX Control Register" bitfld.long 0x1C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO15,USB2_OTG_OC,,,,PWM4_OUT,CCM_CLKO2,?..." line.long 0x20 "SW_MUX_CTL_PAD_ENET_MDC,SW_MUX_CTL_PAD_ENET_MDC SW MUX Control Register" bitfld.long 0x20 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x20 0.--2. " MUX_MODE ,MUX mode select field" "ENET_MDC,,,,,GPIO1_IO16,?..." line.long 0x24 "SW_MUX_CTL_PAD_ENET_MDIO,SW_MUX_CTL_PAD_ENET_MDIO SW MUX Control Register" bitfld.long 0x24 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x24 0.--2. " MUX_MODE ,MUX mode select field" "ENET_MDIO,,,,,GPIO1_IO17,?..." line.long 0x28 "SW_MUX_CTL_PAD_ENET_TD3,SW_MUX_CTL_PAD_ENET_TD3 SW MUX Control Register" bitfld.long 0x28 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x28 0.--2. " MUX_MODE ,MUX mode select field" "ENET_RGMII_TD3,,,,,GPIO1_IO18,?..." line.long 0x2C "SW_MUX_CTL_PAD_ENET_TD2,SW_MUX_CTL_PAD_ENET_TD2 SW MUX Control Register" bitfld.long 0x2C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x2C 0.--2. " MUX_MODE ,MUX mode select field" "ENET_1_RGMII_TD2,ENET1_TX_CLK,,,,GPIO1_IO19,?..." line.long 0x30 "SW_MUX_CTL_PAD_ENET_TD1,SW_MUX_CTL_PAD_ENET_TD1 SW MUX Control Register" bitfld.long 0x30 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x30 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_TD1,,,,,GPIO1_IO20,?..." line.long 0x34 "SW_MUX_CTL_PAD_ENET_TD0,SW_MUX_CTL_PAD_ENET_TD0 SW MUX Control Register" bitfld.long 0x34 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x34 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_TD0,,,,,GPIO1_IO21,?..." line.long 0x38 "SW_MUX_CTL_PAD_ENET_TX_CTL,SW_MUX_CTL_PAD_ENET_TX_CTL SW MUX Control Register" bitfld.long 0x38 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x38 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_TX_CTL,,,,,GPIO1_IO22,?..." line.long 0x3C "SW_MUX_CTL_PAD_ENET_TXC,SW_MUX_CTL_PAD_ENET_TXC SW MUX Control Register" bitfld.long 0x3C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_TXC,ENET1_TX_ER,,,,GPIO1_IO23,?..." line.long 0x40 "SW_MUX_CTL_PAD_ENET_RX_CTL,SW_MUX_CTL_PAD_ENET_RX_CTL SW MUX Control Register" bitfld.long 0x40 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x40 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_RX_CTL,,,,,GPIO1_IO24,?..." line.long 0x44 "SW_MUX_CTL_PAD_ENET_RXC,SW_MUX_CTL_PAD_ENET_RXC SW MUX Control Register" bitfld.long 0x44 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x44 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_RXC,ENET1_RX_ER,,,,GPIO1_IO25,?..." line.long 0x48 "SW_MUX_CTL_PAD_ENET_RD0,SW_MUX_CTL_PAD_ENET_RD0 SW MUX Control Register" bitfld.long 0x48 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x48 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_RD0,,,,,GPIO1_IO26,?..." line.long 0x4C "SW_MUX_CTL_PAD_ENET_RD1,SW_MUX_CTL_PAD_ENET_RD1 SW MUX Control Register" bitfld.long 0x4C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x4C 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_RD1,,,,,GPIO1_IO27,?..." line.long 0x50 "SW_MUX_CTL_PAD_ENET_RD2,SW_MUX_CTL_PAD_ENET_RD2 SW MUX Control Register" bitfld.long 0x50 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x50 0.--2. " MUX_MODE ,MUX mode select field" "ENET_1_RGMII_RD2,,,,,GPIO1_IO28,?..." line.long 0x54 "SW_MUX_CTL_PAD_ENET_RD3,SW_MUX_CTL_PAD_ENET_RD3 SW MUX Control Register" bitfld.long 0x54 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x54 0.--2. " MUX_MODE ,MUX mode select field" "ENET_RGMII_RD3,,,,,GPIO1_IO29,?..." line.long 0x58 "SW_MUX_CTL_PAD_SD1_CLK,SW_MUX_CTL_PAD_SD1_CLK SW MUX Control Register" bitfld.long 0x58 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x58 0.--2. " MUX_MODE ,MUX mode select field" "USDHC_CLK,,,,,GPIO2_IO00,?..." line.long 0x5C "SW_MUX_CTL_PAD_SD1_CMD,SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register" bitfld.long 0x5C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x5C 0.--2. " MUX_MODE ,MUX mode select field" "USDHC_Cmd,,,,,GPIO2_IO01,?..." line.long 0x60 "SW_MUX_CTL_PAD_SD1_DATA0,SW_MUX_CTL_PAD_SD1_DATA0 SW MUX Control Register" bitfld.long 0x60 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x60 0.--2. " MUX_MODE ,MUX mode select field" "USDHC_DATA0,,,,,GPIO2_IO02,?..." line.long 0x64 "SW_MUX_CTL_PAD_SD1_DATA1,SW_MUX_CTL_PAD_SD1_DATA1 SW MUX Control Register" bitfld.long 0x64 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x64 0.--2. " MUX_MODE ,MUX mode select field" "USDHC_DATA1,,,,,GPIO2_IO03,?..." line.long 0x68 "SW_MUX_CTL_PAD_SD1_DATA2,SW_MUX_CTL_PAD_SD1_DATA2 SW MUX Control Register" bitfld.long 0x68 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x68 0.--2. " MUX_MODE ,MUX mode select field" "USDHC_DATA2,,,,,GPIO2_IO04,?..." line.long 0x6C "SW_MUX_CTL_PAD_SD1_DATA3,SW_MUX_CTL_PAD_SD1_DATA3 SW MUX Control Register" bitfld.long 0x6C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x6C 0.--2. " MUX_MODE ,MUX mode select field" "USDHC_DATA3,,,,,GPIO2_IO05,?..." line.long 0x70 "SW_MUX_CTL_PAD_SD1_DATA4,SW_MUX_CTL_PAD_SD1_DATA4 SW MUX Control Register" bitfld.long 0x70 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x70 0.--2. " MUX_MODE ,MUX mode select field" "USDHC_DATA4,,,,,GPIO2_IO06,?..." line.long 0x74 "SW_MUX_CTL_PAD_SD1_DATA5,SW_MUX_CTL_PAD_SD1_DATA5 SW MUX Control Register" bitfld.long 0x74 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x74 0.--2. " MUX_MODE ,MUX mode select field" "USDHC_DATA5,,,,,GPIO2_IO07,?..." line.long 0x78 "SW_MUX_CTL_PAD_SD1_DATA6,SW_MUX_CTL_PAD_SD1_DATA6 SW MUX Control Register" bitfld.long 0x78 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x78 0.--2. " MUX_MODE ,MUX mode select field" "USDHC_DATA6,,,,,GPIO2_IO08,?..." line.long 0x7C "SW_MUX_CTL_PAD_SD1_DATA7,SW_MUX_CTL_PAD_SD1_DATA7 SW MUX Control Register" bitfld.long 0x7C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x7C 0.--2. " MUX_MODE ,MUX mode select field" "USDHC_DATA7,,,,,GPIO2_IO09,?..." line.long 0x80 "SW_MUX_CTL_PAD_SD1_RESET_B,SW_MUX_CTL_PAD_SD1_RESET_B SW MUX Control Register" bitfld.long 0x80 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x80 0.--2. " MUX_MODE ,MUX mode select field" "USDHC1_RESET_B,,,,,GPIO2_IO10,?..." line.long 0x84 "SW_MUX_CTL_PAD_SD1_STROBE,SW_MUX_CTL_PAD_SD1_STROBE SW MUX Control Register" bitfld.long 0x84 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x84 0.--2. " MUX_MODE ,MUX mode select field" "USDHC1_STROBE,,,,,GPIO2_IO11,?..." line.long 0x88 "SW_MUX_CTL_PAD_SD2_CD_B,SW_MUX_CTL_PAD_SD2_CD_B SW MUX Control Register" bitfld.long 0x88 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x88 0.--2. " MUX_MODE ,MUX mode select field" "USDHC2_CD_B,,,,,GPIO2_IO12,?..." line.long 0x8C "SW_MUX_CTL_PAD_SD2_CLK,SW_MUX_CTL_PAD_SD2_CLK SW MUX Control Register" bitfld.long 0x8C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x8C 0.--2. " MUX_MODE ,MUX mode select field" "USDHC2_CLK,,,,,GPIO2_IO13,?..." line.long 0x90 "SW_MUX_CTL_PAD_SD2_CMD,SW_MUX_CTL_PAD_SD2_CMD SW MUX Control Register" bitfld.long 0x90 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x90 0.--2. " MUX_MODE ,MUX mode select field" "USDHC2_CMD,,,,,GPIO2_IO14,?..." line.long 0x94 "SW_MUX_CTL_PAD_SD2_DATA0,SW_MUX_CTL_PAD_SD2_DATA0 SW MUX Control Register" bitfld.long 0x94 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x94 0.--2. " MUX_MODE ,MUX mode select field" "USDHC2_DATA0,,,,,GPIO2_IO015,?..." line.long 0x98 "SW_MUX_CTL_PAD_SD2_DATA1,SW_MUX_CTL_PAD_SD2_DATA1 SW MUX Control Register" bitfld.long 0x98 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x98 0.--2. " MUX_MODE ,MUX mode select field" "USDHC2_DATA1,,,,,GPIO2_IO016,?..." line.long 0x9C "SW_MUX_CTL_PAD_SD2_DATA2,SW_MUX_CTL_PAD_SD2_DATA2 SW MUX Control Register" bitfld.long 0x9C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x9C 0.--2. " MUX_MODE ,MUX mode select field" "USDHC2_DATA2,,,,,GPIO2_IO017,?..." line.long 0xA0 "SW_MUX_CTL_PAD_SD2_DATA3,SW_MUX_CTL_PAD_SD2_DATA3 SW MUX Control Register" bitfld.long 0xA0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xA0 0.--2. " MUX_MODE ,MUX mode select field" "USDHC2_DATA3,,,,,GPIO2_IO018,?..." line.long 0xA4 "SW_MUX_CTL_PAD_SD2_RESET_B,SW_MUX_CTL_PAD_SD2_RESET_B SW MUX Control Register" bitfld.long 0xA4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xA4 0.--2. " MUX_MODE ,MUX mode select field" "USDHC2_RESET_B,,,,,GPIO2_IO19,?..." line.long 0xA8 "SW_MUX_CTL_PAD_SD2_WP,SW_MUX_CTL_PAD_SD2_WP SW MUX Control Register" bitfld.long 0xA8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xA8 0.--2. " MUX_MODE ,MUX mode select field" "USDHC2_WP,,,,,GPIO2_IO20,?..." line.long 0xAC "SW_MUX_CTL_PAD_NAND_ALE,SW_MUX_CTL_PAD_NAND_ALE SW MUX Control Register" bitfld.long 0xAC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xAC 0.--2. " MUX_MODE ,MUX mode select field" "RAWBABD_ALE,QSPI_A_SCLK,,,,GPIO3_IO00,?..." line.long 0xB0 "SW_MUX_CTL_PAD_NAND_CE0_B,SW_MUX_CTL_PAD_NAND_CE0_B SW MUX Control Register" bitfld.long 0xB0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xB0 0.--2. " MUX_MODE ,MUX mode select field" "RAWBABD_CE0_B,QSPI_A_SS0_B,,,,GPIO3_IO01,?..." line.long 0xB4 "SW_MUX_CTL_PAD_NAND_CE1_B,SW_MUX_CTL_PAD_NAND_CE1_B SW MUX Control Register" bitfld.long 0xB4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xB4 0.--2. " MUX_MODE ,MUX mode select field" "RAWBABD_CE1_B,QSPI_A_SS1_B,,,,GPIO3_IO02,?..." line.long 0xB8 "SW_MUX_CTL_PAD_NAND_CE2_B,SW_MUX_CTL_PAD_NAND_CE2_B SW MUX Control Register" bitfld.long 0xB8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xB8 0.--2. " MUX_MODE ,MUX mode select field" "RAWBABD_CE2_B,QSPI_B_SS0_B,,,,GPIO3_IO03,?..." line.long 0xBC "SW_MUX_CTL_PAD_NAND_CE3_B,SW_MUX_CTL_PAD_NAND_CE3_B SW MUX Control Register" bitfld.long 0xBC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xBC 0.--2. " MUX_MODE ,MUX mode select field" "RAWBABD_CE3_B,QSPI_B_SS1_B,,,,GPIO3_IO04,?..." line.long 0xC0 "SW_MUX_CTL_PAD_NAND_CLE,SW_MUX_CTL_PAD_NAND_CLE SW MUX Control Register" bitfld.long 0xC0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xC0 0.--2. " MUX_MODE ,MUX mode select field" "RAWBABD_CLE,QSPI_B_SCLK,,,,GPIO3_IO05,?..." line.long 0xC4 "SW_MUX_CTL_PAD_NAND_DATA0,SW_MUX_CTL_PAD_NAND_DATA0 SW MUX Control Register" bitfld.long 0xC4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xC4 0.--2. " MUX_MODE ,MUX mode select field" "RAWNAND_DATA0,QSPI_A_DATA0,,,,GPIO3_IO06,?..." line.long 0xC8 "SW_MUX_CTL_PAD_NAND_DATA1,SW_MUX_CTL_PAD_NAND_DATA1 SW MUX Control Register" bitfld.long 0xC8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xC8 0.--2. " MUX_MODE ,MUX mode select field" "RAWNAND_DATA1,QSPI_A_DATA1,,,,GPIO3_IO07,?..." line.long 0xCC "SW_MUX_CTL_PAD_NAND_DATA2,SW_MUX_CTL_PAD_NAND_DATA2 SW MUX Control Register" bitfld.long 0xCC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xCC 0.--2. " MUX_MODE ,MUX mode select field" "RAWNAND_DATA2,QSPI_A_DATA2,,,,GPIO3_IO08,?..." line.long 0xD0 "SW_MUX_CTL_PAD_NAND_DATA3,SW_MUX_CTL_PAD_NAND_DATA3 SW MUX Control Register" bitfld.long 0xD0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xD0 0.--2. " MUX_MODE ,MUX mode select field" "RAWNAND_DATA3,QSPI_A_DATA3,,,,GPIO3_IO09,?..." line.long 0xD4 "SW_MUX_CTL_PAD_NAND_DATA4,SW_MUX_CTL_PAD_NAND_DATA4 SW MUX Control Register" bitfld.long 0xD4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xD4 0.--2. " MUX_MODE ,MUX mode select field" "RAWNAND_DATA4,QSPI_B_DATA0,,,,GPIO3_IO10,?..." line.long 0xD8 "SW_MUX_CTL_PAD_NAND_DATA5,SW_MUX_CTL_PAD_NAND_DATA5 SW MUX Control Register" bitfld.long 0xD8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xD8 0.--2. " MUX_MODE ,MUX mode select field" "RAWNAND_DATA5,QSPI_B_DATA1,,,,GPIO3_IO11,?..." line.long 0xDC "SW_MUX_CTL_PAD_NAND_DATA6,SW_MUX_CTL_PAD_NAND_DATA6 SW MUX Control Register" bitfld.long 0xDC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xDC 0.--2. " MUX_MODE ,MUX mode select field" "RAWNAND_DATA6,QSPI_B_DATA2,,,,GPIO3_IO12,?..." line.long 0xE0 "SW_MUX_CTL_PAD_NAND_DATA7,SW_MUX_CTL_PAD_NAND_DATA7 SW MUX Control Register" bitfld.long 0xE0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xE0 0.--2. " MUX_MODE ,MUX mode select field" "RAWNAND_DATA7,QSPI_B_DATA3,,,,GPIO3_IO13,?..." line.long 0xE4 "SW_MUX_CTL_PAD_NAND_DQS,SW_MUX_CTL_PAD_NAND_DQS SW MUX Control Register" bitfld.long 0xE4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xE4 0.--2. " MUX_MODE ,MUX mode select field" "RAWNAND_DQS,QSPI_A_DQS,,,,GPIO3_IO14,?..." line.long 0xE8 "SW_MUX_CTL_PAD_NAND_RE_B,SW_MUX_CTL_PAD_NAND_RE_B SW MUX Control Register" bitfld.long 0xE8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xE8 0.--2. " MUX_MODE ,MUX mode select field" "RAWNAND_RE_B,QSPI_B_DQS,,,,GPIO3_IO15,?..." line.long 0xEC "SW_MUX_CTL_PAD_NAND_READY_B,SW_MUX_CTL_PAD_NAND_READY_B SW MUX Control Register" bitfld.long 0xEC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xEC 0.--2. " MUX_MODE ,MUX mode select field" "RAWNAND_RAEADY_B,,,,,GPIO3_IO16,?..." line.long 0xF0 "SW_MUX_CTL_PAD_NAND_WE_B,SW_MUX_CTL_PAD_NAND_WE_B SW MUX Control Register" bitfld.long 0xF0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xF0 0.--2. " MUX_MODE ,MUX mode select field" "RAWNAND_WE_B,,,,,GPIO3_IO17,?..." line.long 0xF4 "SW_MUX_CTL_PAD_NAND_WP_B,SW_MUX_CTL_PAD_NAND_WP_B SW MUX Control Register" bitfld.long 0xF4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xF4 0.--2. " MUX_MODE ,MUX mode select field" "RAWNAND_WP_B,,,,,GPIO3_IO18,?..." line.long 0xF8 "SW_MUX_CTL_PAD_SAI5_RXFS,SW_MUX_CTL_PAD_SAI5_RXFS SW MUX Control Register" bitfld.long 0xF8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xF8 0.--2. " MUX_MODE ,MUX mode select field" "SAI5_RX_SYNC,SAI1_TX_DATA0,,,,GPIO3_IO19,?..." line.long 0xFC "SW_MUX_CTL_PAD_SAI5_RXC,SW_MUX_CTL_PAD_SAI5_RXC SW MUX Control Register" bitfld.long 0xFC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xFC 0.--2. " MUX_MODE ,MUX mode select field" "SAI5_RX_BCLK,SAI1_TX_DATA1,,,,GPIO3_IO20,?..." line.long 0x100 "SW_MUX_CTL_PAD_SAI5_RXD0,SW_MUX_CTL_PAD_SAI5_RXD0 SW MUX Control Register" bitfld.long 0x100 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x100 0.--2. " MUX_MODE ,MUX mode select field" "SAI5_RX_DATA0,SAI1_TX_DATA2,,,,GPIO3_IO21,?..." line.long 0x104 "SW_MUX_CTL_PAD_SAI5_RXD1,SW_MUX_CTL_PAD_SAI5_RXD1 SW MUX Control Register" bitfld.long 0x104 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x104 0.--2. " MUX_MODE ,MUX mode select field" "SAI5_RX_DATA1,SAI1_TX_DATA3,ALT2_SAI1_TX_SYNC,ALT3_SAI5_TX_SYNC,,GPIO3_IO22,?..." line.long 0x108 "SW_MUX_CTL_PAD_SAI5_RXD2,SW_MUX_CTL_PAD_SAI5_RXD2 SW MUX Control Register" bitfld.long 0x108 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x108 0.--2. " MUX_MODE ,MUX mode select field" "SAI5_RX_DATA2,SAI1_TX_DATA4,SAI1_TX_SYNC,SAI5_TX_BCLK,,GPIO3_IO23,?..." line.long 0x10C "SW_MUX_CTL_PAD_SAI5_RXD3,SW_MUX_CTL_PAD_SAI5_RXD3 SW MUX Control Register" bitfld.long 0x10C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x10C 0.--2. " MUX_MODE ,MUX mode select field" "SAI5_RX_DATA3,SAI1_TX_DATA5,SAI1_TX_SYNC,SAI5_TX_DATA0,,GPIO3_IO24,?..." line.long 0x110 "SW_MUX_CTL_PAD_SAI5_MCLK,SW_MUX_CTL_PAD_SAI5_MCLK SW MUX Control Register" bitfld.long 0x110 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x110 0.--2. " MUX_MODE ,MUX mode select field" "SAI5_RX_MCLK,SAI1_TX_BCLK,SAI4_MCLK,,,GPIO3_IO25,?..." line.long 0x114 "SW_MUX_CTL_PAD_SAI1_RXFS,SW_MUX_CTL_PAD_SAI1_RXFS SW MUX Control Register" bitfld.long 0x114 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x114 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_SYNC,SAI5_RX_SYNC,,,CORESIGHT_TRACE_CLK,GPIO4_IO00,?..." line.long 0x118 "SW_MUX_CTL_PAD_SAI1_RXC,SW_MUX_CTL_PAD_SAI1_RXC SW MUX Control Register" bitfld.long 0x118 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x118 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_BCLK,SAI5_RX_BCLK,,,CORESIGHT_TRACE_CTL,GPIO4_IO01,?..." line.long 0x11C "SW_MUX_CTL_PAD_SAI1_RXD0,SW_MUX_CTL_PAD_SAI1_RXD0 SW MUX Control Register" bitfld.long 0x11C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x11C 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_DATA0,SAI5_RX_DATA0,,,CORESIGHT_TRACE0,GPIO4_IO02,SRC_BOOT_CFG0,?..." line.long 0x120 "SW_MUX_CTL_PAD_SAI1_RXD1,SW_MUX_CTL_PAD_SAI1_RXD1 SW MUX Control Register" bitfld.long 0x120 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x120 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_DATA1,SAI5_RX_DATA1,,,CORESIGHT_TRACE1,GPIO4_IO03,SRC_BOOT_CFG1,?..." line.long 0x124 "SW_MUX_CTL_PAD_SAI1_RXD2,SW_MUX_CTL_PAD_SAI1_RXD2 SW MUX Control Register" bitfld.long 0x124 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x124 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_DATA2,SAI5_RX_DATA2,,,CORESIGHT_TRACE2,GPIO4_IO04,SRC_BOOT_CFG2,?..." line.long 0x128 "SW_MUX_CTL_PAD_SAI1_RXD3,SW_MUX_CTL_PAD_SAI1_RXD3 SW MUX Control Register" bitfld.long 0x128 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x128 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_DATA3,SAI5_RX_DATA3,,,CORESIGHT_TRACE3,GPIO4_IO05,SRC_BOOT_CFG3,?..." line.long 0x12C "SW_MUX_CTL_PAD_SAI1_RXD4,SW_MUX_CTL_PAD_SAI1_RXD4 SW MUX Control Register" bitfld.long 0x12C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x12C 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_DATA4,ALT1_SAI6_TX_BCLK,ALT2_SAI6_RX_BCLK,,CORESIGHT_TRACE4,GPIO4_IO06,SRC_BOOT_CFG4,?..." line.long 0x130 "SW_MUX_CTL_PAD_SAI1_RXD5,SW_MUX_CTL_PAD_SAI1_RXD5 SW MUX Control Register" bitfld.long 0x130 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x130 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_DATA5,SAI6_TX_DATA0,SAI6_RX_DATA0,SAI1_RX_SYNC,CORESIGHT_TRACE5,GPIO4_IO07,SRC_BOOT_CFG5,?..." line.long 0x134 "SW_MUX_CTL_PAD_SAI1_RXD6,SW_MUX_CTL_PAD_SAI1_RXD6 SW MUX Control Register" bitfld.long 0x134 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x134 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_DATA6,SAI6_TX_SYNC,SAI6_RX_SYNC,,CORESIGHT_TRACE6,GPIO4_IO08,SRC_BOOT_CFG6,?..." line.long 0x138 "SW_MUX_CTL_PAD_SAI1_RXD7,SW_MUX_CTL_PAD_SAI1_RXD7 SW MUX Control Register" bitfld.long 0x138 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x138 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_DATA7,SAI6_MCLK,SAI1_TX_SYNC,ALT3_SAI1_TX_DATA4,CORESIGHT_TRACE7,GPIO4_IO09,SRC_BOOT_CFG7,?..." line.long 0x13C "SW_MUX_CTL_PAD_SAI1_TXFS,SW_MUX_CTL_PAD_SAI1_TXFS SW MUX Control Register" bitfld.long 0x13C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x13C 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_TX_SYNC,SAI5_TX_SYNC,,,CORESIGHT_EVENTO,GPIO4_IO10,?..." line.long 0x140 "SW_MUX_CTL_PAD_SAI1_TXC,SW_MUX_CTL_PAD_SAI1_TXC SW MUX Control Register" bitfld.long 0x140 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x140 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_TX_BCLK,SAI5_TX_BCLK,,,CORESIGHT_EVENTI,GPIO4_IO11,?..." line.long 0x144 "SW_MUX_CTL_PAD_SAI1_TXD0,SW_MUX_CTL_PAD_SAI1_TXD0 SW MUX Control Register" bitfld.long 0x144 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x144 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_TX_DATA0,SAI5_TX_DATA0,,,CORESIGHT_TRACE8,GPIO4_IO12,SRC_BOOT_CFG8,?..." line.long 0x148 "SW_MUX_CTL_PAD_SAI1_TXD1,SW_MUX_CTL_PAD_SAI1_TXD1 SW MUX Control Register" bitfld.long 0x148 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x148 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_TX_DATA1,SAI5_TX_DATA1,,,CORESIGHT_TRACE9,GPIO4_IO13,SRC_BOOT_CFG9,?..." line.long 0x14C "SW_MUX_CTL_PAD_SAI1_TXD2,SW_MUX_CTL_PAD_SAI1_TXD2 SW MUX Control Register" bitfld.long 0x14C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x14C 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_TX_DATA2,SAI5_TX_DATA2,,,CORESIGHT_TRACE10,GPIO4_IO14,SRC_BOOT_CFG10,?..." line.long 0x150 "SW_MUX_CTL_PAD_SAI1_TXD3,SW_MUX_CTL_PAD_SAI1_TXD3 SW MUX Control Register" bitfld.long 0x150 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x150 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_TX_DATA3,SAI5_TX_DATA3,,,CORESIGHT_TRACE11,GPIO4_IO15,SRC_BOOT_CFG11,?..." line.long 0x154 "SW_MUX_CTL_PAD_SAI1_TXD4,SW_MUX_CTL_PAD_SAI1_TXD4 SW MUX Control Register" bitfld.long 0x154 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x154 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_TX_DATA4,SAI5_RX_BCLK,ALT2_SAI6_TX_BCLK,,CORESIGHT_TRACE12,GPIO4_IO16,SRC_BOOT_CFG12,?..." line.long 0x158 "SW_MUX_CTL_PAD_SAI1_TXD5,SW_MUX_CTL_PAD_SAI1_TXD5 SW MUX Control Register" bitfld.long 0x158 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x158 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_DATA5,SAI6_TX_DATA0,SAI6_RX_DATA0,,CORESIGHT_TRACE513,GPIO4_IO17,SRC_BOOT_CFG13,?..." line.long 0x15C "SW_MUX_CTL_PAD_SAI1_TXD6,SW_MUX_CTL_PAD_SAI1_TXD6 SW MUX Control Register" bitfld.long 0x15C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x15C 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_DATA6,SAI6_RX_SYNC,SAI6_TX_SYNC,,CORESIGHT_TRACE14,GPIO4_IO18,SRC_BOOT_CFG14,?..." line.long 0x160 "SW_MUX_CTL_PAD_SAI1_TXD7,SW_MUX_CTL_PAD_SAI1_TXD7 SW MUX Control Register" bitfld.long 0x160 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x160 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_DATA7,SAI6_MCLK,,,CORESIGHT_TRACE15,GPIO4_IO19,SRC_BOOT_CFG15,?..." line.long 0x164 "SW_MUX_CTL_PAD_SAI1_MCLK,SW_MUX_CTL_PAD_SAI1_MCLK SW MUX Control Register" bitfld.long 0x164 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x164 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_MCLK,SAI5_MCLK,SAI1_TX_BCLK,,,GPIO4_IO20,?..." line.long 0x168 "SW_MUX_CTL_PAD_SAI2_RXFS,SW_MUX_CTL_PAD_SAI2_RXFS SW MUX Control Register" bitfld.long 0x168 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x168 0.--2. " MUX_MODE ,MUX mode select field" "SAI2_RX_SYNC,SAI5_TX_SYNC,,,,GPIO4_IO21,?..." line.long 0x16C "SW_MUX_CTL_PAD_SAI2_RXC,SW_MUX_CTL_PAD_SAI2_RXC SW MUX Control Register" bitfld.long 0x16C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x16C 0.--2. " MUX_MODE ,MUX mode select field" "SAI2_RX_BCLK,SAI5_TX_BCLK,,,,GPIO4_IO22,?..." line.long 0x170 "SW_MUX_CTL_PAD_SAI2_RXD0,SW_MUX_CTL_PAD_SAI2_RXD0 SW MUX Control Register" bitfld.long 0x170 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x170 0.--2. " MUX_MODE ,MUX mode select field" "SAI2_RX_DATA0,SAI5_TX_DATA0,,,,GPIO4_IO23,?..." line.long 0x174 "SW_MUX_CTL_PAD_SAI2_TXFS,SW_MUX_CTL_PAD_SAI2_TXFS SW MUX Control Register" bitfld.long 0x174 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x174 0.--2. " MUX_MODE ,MUX mode select field" "SAI2_TX_SYNC,SAI5_TX_DATA1,,,,GPIO4_IO24,?..." line.long 0x178 "SW_MUX_CTL_PAD_SAI2_TXC,SW_MUX_CTL_PAD_SAI2_TXC SW MUX Control Register" bitfld.long 0x178 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x178 0.--2. " MUX_MODE ,MUX mode select field" "SAI2_TX_BCLK,SAI5_TX_DATA2,,,,GPIO4_IO25,?..." line.long 0x17C "SW_MUX_CTL_PAD_SAI2_TXD0,SW_MUX_CTL_PAD_SAI2_TXD0 SW MUX Control Register" bitfld.long 0x17C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x17C 0.--2. " MUX_MODE ,MUX mode select field" "SAI2_TX_DATA0,SAI5_TX_DATA3,,,,GPIO4_IO26,?..." line.long 0x180 "SW_MUX_CTL_PAD_SAI2_MCLK,SW_MUX_CTL_PAD_SAI2_MCLK SW MUX Control Register" bitfld.long 0x180 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x180 0.--2. " MUX_MODE ,MUX mode select field" "SAI2_MCLK,SAI5_MCLK,,,,GPIO4_IO27,?..." line.long 0x184 "SW_MUX_CTL_PAD_SAI3_RXFS,SW_MUX_CTL_PAD_SAI3_RXFS SW MUX Control Register" bitfld.long 0x184 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x184 0.--2. " MUX_MODE ,MUX mode select field" "SAI3_RX_SYNC,GRP1_CAPTURE1,SAI5_RX_SYNC,,,GPIO4_IO28,?..." line.long 0x188 "SW_MUX_CTL_PAD_SAI3_RXC,SW_MUX_CTL_PAD_SAI3_RXC SW MUX Control Register" bitfld.long 0x188 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x188 0.--2. " MUX_MODE ,MUX mode select field" "SAI3_RX_BCLK,GPT1_CAPTURE2,SAI5_RX_BCLK,,,GPIO4_IO29,?..." line.long 0x18C "SW_MUX_CTL_PAD_SAI3_RXD,SW_MUX_CTL_PAD_SAI3_RXD SW MUX Control Register" bitfld.long 0x18C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x18C 0.--2. " MUX_MODE ,MUX mode select field" "SAI3_RX_DATA0,GRP1_COMPARE1,SAI5_RX_DATA0,,,GPIO4_IO30,?..." line.long 0x190 "SW_MUX_CTL_PAD_SAI3_TXFS,SW_MUX_CTL_PAD_SAI3_TXFS SW MUX Control Register" bitfld.long 0x190 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x190 0.--2. " MUX_MODE ,MUX mode select field" "SAI3_TX_SYNC,GPT1_CLK,SAI5_RX_DATA1,,,GPIO4_IO31,?..." line.long 0x194 "SW_MUX_CTL_PAD_SAI3_TXC,SW_MUX_CTL_PAD_SAI3_TXC SW MUX Control Register" bitfld.long 0x194 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x194 0.--2. " MUX_MODE ,MUX mode select field" "SAI3_TX_BCLK,GPT_COMPARE2,SAI5_RX_DATA2,,,GPIO5_IO00,?..." line.long 0x198 "SW_MUX_CTL_PAD_SAI3_TXD,SW_MUX_CTL_PAD_SAI3_TXD SW MUX Control Register" bitfld.long 0x198 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x198 0.--2. " MUX_MODE ,MUX mode select field" "SAI3_TX_DATA0,GPT_COMPARE3,SAI5_RX_DATA3,,,GPIO5_IO01,?..." line.long 0x19C "SW_MUX_CTL_PAD_SAI3_MCLK,SW_MUX_CTL_PAD_SAI3_MCLK SW MUX Control Register" bitfld.long 0x19C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x19C 0.--2. " MUX_MODE ,MUX mode select field" "SAI3_MCLK,PWM4_OUT,SAI5_MCLK,,,GPIO5_IO02,?..." line.long 0x1A0 "SW_MUX_CTL_PAD_SPDIF_TX,SW_MUX_CTL_PAD_SPDIF_TX SW MUX Control Register" bitfld.long 0x1A0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1A0 0.--2. " MUX_MODE ,MUX mode select field" "SPDIF_OUT,PWM3_OUT,,,,GPIO5_IO03,?..." line.long 0x1A4 "SW_MUX_CTL_PAD_SPDIF_RX,SW_MUX_CTL_PAD_SPDIF_RX SW MUX Control Register" bitfld.long 0x1A4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1A4 0.--2. " MUX_MODE ,MUX mode select field" "SPDIF_IN,PWM2_OUT,,,,GPIO5_IO04,?..." line.long 0x1A8 "SW_MUX_CTL_PAD_SPDIF_EXT_CLK,SW_MUX_CTL_PAD_SPDIF_EXT_CLK SW MUX Control Register" bitfld.long 0x1A8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1A8 0.--2. " MUX_MODE ,MUX mode select field" "SPDIF1_EXT_CLK,PWM1_OUT,,,,GPIO5_IO05,?..." line.long 0x1AC "SW_MUX_CTL_PAD_ECSPI1_SCLK,SW_MUX_CTL_PAD_ECSPI1_SCLK SW MUX Control Register" bitfld.long 0x1AC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1AC 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI1_SCLK,UART3_RX,,,,GPIO5_IO06,?..." line.long 0x1B0 "SW_MUX_CTL_PAD_ECSPI1_MOSI,SW_MUX_CTL_PAD_ECSPI1_MOSI SW MUX Control Register" bitfld.long 0x1B0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1B0 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI1_MOSI,UART3_TX,,,,GPIO5_IO07,?..." line.long 0x1B4 "SW_MUX_CTL_PAD_ECSPI1_MISO,SW_MUX_CTL_PAD_ECSPI1_MISO SW MUX Control Register" bitfld.long 0x1B4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1B4 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI1_MISO,UART3_CTS_B,,,,GPIO5_IO08,?..." line.long 0x1B8 "SW_MUX_CTL_PAD_ECSPI1_SS0,SW_MUX_CTL_PAD_ECSPI1_SS0 SW MUX Control Register" bitfld.long 0x1B8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1B8 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI1_SS0,UART3_RTS_B,,,,GPIO5_IO09,?..." line.long 0x1BC "SW_MUX_CTL_PAD_ECSPI2_SCLK,SW_MUX_CTL_PAD_ECSPI2_SCLK SW MUX Control Register" bitfld.long 0x1bc 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1BC 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI2_SCLK,UART4_RX,,,,GPIO5_IO10,?..." line.long 0x1C0 "SW_MUX_CTL_PAD_ECSPI2_MOSI,SW_MUX_CTL_PAD_ECSPI2_MOSI SW MUX Control Register" bitfld.long 0x1C0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C0 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI2_MOSI,UART4_TX,,,,GPIO5_IO11,?..." line.long 0x1C4 "SW_MUX_CTL_PAD_ECSPI2_MISO,SW_MUX_CTL_PAD_ECSPI2_MISO SW MUX Control Register" bitfld.long 0x1C4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C4 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI2_MISO,UART4_CTS_B,,,,GPIO5_IO12,?..." line.long 0x1C8 "SW_MUX_CTL_PAD_ECSPI2_SS0,SW_MUX_CTL_PAD_ECSPI2_SS0 SW MUX Control Register" bitfld.long 0x1C8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C8 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI2_SS0,UART4_RTS_B,,,,GPIO5_IO13,?..." line.long 0x1CC "SW_MUX_CTL_PAD_I2C1_SCL,SW_MUX_CTL_PAD_I2C1_SCL SW MUX Control Register" bitfld.long 0x1CC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1CC 0.--2. " MUX_MODE ,MUX mode select field" "I2C1_SCL,ENET1_MDC,,,,GPIO5_IO14,?..." line.long 0x1D0 "SW_MUX_CTL_PAD_I2C1_SDA,SW_MUX_CTL_PAD_I2C1_SDA SW MUX Control Register" bitfld.long 0x1D0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1D0 0.--2. " MUX_MODE ,MUX mode select field" "I2C1_SDA,ENET1_MDIO,,,,GPIO5_IO15,?..." line.long 0x1D4 "SW_MUX_CTL_PAD_I2C2_SCL,SW_MUX_CTL_PAD_I2C2_SCL SW MUX Control Register" bitfld.long 0x1D4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1D4 0.--2. " MUX_MODE ,MUX mode select field" "I2C2_SCL,ENET1_1588_EVENT1_IN,,,,GPIO5_IO16,?..." line.long 0x1D8 "SW_MUX_CTL_PAD_I2C2_SDA,SW_MUX_CTL_PAD_I3C2_SDA SW MUX Control Register" bitfld.long 0x1D8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1D8 0.--2. " MUX_MODE ,MUX mode select field" "I2C2_SDA,ENET1_1588_EVENT1_OUT,,,,GPIO5_IO17,?..." line.long 0x1DC "SW_MUX_CTL_PAD_I3C1_SCL,SW_MUX_CTL_PAD_I3C1_SCL SW MUX Control Register" bitfld.long 0x1DC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1DC 0.--2. " MUX_MODE ,MUX mode select field" "I2C3_SCL,PWM4_OUT,GPT2_CLK,,,GPIO5_IO18,?..." line.long 0x1E0 "SW_MUX_CTL_PAD_I3C1_SDA,SW_MUX_CTL_PAD_I3C1_SDA SW MUX Control Register" bitfld.long 0x1E0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1E0 0.--2. " MUX_MODE ,MUX mode select field" "I2C3_SDA,PWM3_OUT,GPT3_CLK,,,GPIO5_IO19,?..." line.long 0x1E4 "SW_MUX_CTL_PAD_I4C2_SCL,SW_MUX_CTL_PAD_I4C2_SCL SW MUX Control Register" bitfld.long 0x1E4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1E4 0.--2. " MUX_MODE ,MUX mode select field" "I2C4_SCL,PWM2_OUT,PCIE1_CLKREQ_B,,,GPIO5_IO20,?..." line.long 0x1E8 "SW_MUX_CTL_PAD_I4C2_SDA,SW_MUX_CTL_PAD_I4C2_SDA SW MUX Control Register" bitfld.long 0x1E8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1E8 0.--2. " MUX_MODE ,MUX mode select field" "I2C4_SDA,PWM_OUT,PCIE_CLKREQ_B,,,GPIO5_IO21,?..." line.long 0x1EC "SW_MUX_CTL_PAD_UART1_RXD,SW_MUX_CTL_PAD_UART1_RXD SW MUX Control Register" bitfld.long 0x1EC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1EC 0.--2. " MUX_MODE ,MUX mode select field" "UART1_RX,ECSPI3_SCLK,,,,GPIO5_IO22,?..." line.long 0x1F0 "SW_MUX_CTL_PAD_UART1_TXD,SW_MUX_CTL_PAD_UART1_TXD SW MUX Control Register" bitfld.long 0x1F0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1F0 0.--2. " MUX_MODE ,MUX mode select field" "UART1_TX,ECSPI3_MOSI,,,,GPIO5_IO23,?..." line.long 0x1F4 "SW_MUX_CTL_PAD_UART2_RXD,SW_MUX_CTL_PAD_UART2_RXD SW MUX Control Register" bitfld.long 0x1F4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1F4 0.--2. " MUX_MODE ,MUX mode select field" "UART2_RX,ECSPI_MISO,,,,GPIO5_IO24,?..." line.long 0x1F8 "SW_MUX_CTL_PAD_UART2_TXD,SW_MUX_CTL_PAD_UART2_TXD SW MUX Control Register" bitfld.long 0x1F8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1F8 0.--2. " MUX_MODE ,MUX mode select field" "UART1_TX,ECSPI_SS0,,,,GPIO5_IO25,?..." line.long 0x1FC "SW_MUX_CTL_PAD_UART3_RXD,SW_MUX_CTL_PAD_UART3_RXD SW MUX Control Register" bitfld.long 0x1FC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1FC 0.--2. " MUX_MODE ,MUX mode select field" "UART3_RX,UART1_CTS_B,,,,GPIO5_IO26,?..." line.long 0x200 "SW_MUX_CTL_PAD_UART3_TXD,SW_MUX_CTL_PAD_UART3_TXD SW MUX Control Register" bitfld.long 0x200 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x200 0.--2. " MUX_MODE ,MUX mode select field" "UART3_TX,UART1_RTS_B,,,,GPIO5_IO27,?..." line.long 0x204 "SW_MUX_CTL_PAD_UART4_RXD,SW_MUX_CTL_PAD_UART4_RXD SW MUX Control Register" bitfld.long 0x204 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x204 0.--2. " MUX_MODE ,MUX mode select field" "UART4_RX,UART2_CTS_B,PCIE1_CLKREQ_B,,,GPIO5_IO28,?..." line.long 0x208 "SW_MUX_CTL_PAD_UART4_TXD,SW_MUX_CTL_PAD_UART4_TXD SW MUX Control Register" bitfld.long 0x208 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x208 0.--2. " MUX_MODE ,MUX mode select field" "UART4_TX,UART2_RTS_B,PCIE2_CLKREQ_B,,,GPIO5_IO29,?..." line.long 0x20C "SW_MUX_CTL_PAD_TEST_MODE,SW_MUX_CTL_PAD_TEST_MODE SW MUX Control Register" bitfld.long 0x20C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x20C 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x20C 5. " ODE ,Open drain enable field" "Disabled,Enabled" line.long 0x210 "SW_MUX_CTL_PAD_BOOT_MODE0,SW_MUX_CTL_PAD_BOOT_MODE0 SW MUX Control Register" bitfld.long 0x210 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x210 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x210 5. " ODE ,Open drain enable field" "Disabled,Enabled" line.long 0x214 "SW_MUX_CTL_PAD_BOOT_MODE1,SW_MUX_CTL_PAD_BOOT_MODE1 SW MUX Control Register" bitfld.long 0x214 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x214 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x214 5. " ODE ,Open drain enable field" "Disabled,Enabled" line.long 0x218 "SW_MUX_CTL_PAD_JTAG_MOD,SW_MUX_CTL_PAD_JTAG_MOD SW MUX Control Register" bitfld.long 0x218 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x218 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x218 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x218 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x218 5. " ODE ,Open drain enable field" "Disabled,Enabled" line.long 0x21C "SW_MUX_CTL_PAD_JTAG_TRST_B,SW_MUX_CTL_PAD_JTAG_TRST_B SW MUX Control Register" bitfld.long 0x21C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x21C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x21C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x21C 5. " ODE ,Open drain enable field" "Disabled,Enabled" line.long 0x220 "SW_MUX_CTL_PAD_JTAG_TDI,SW_MUX_CTL_PAD_JTAG_TDI SW MUX Control Register" bitfld.long 0x220 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x220 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x220 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x220 5. " ODE ,Open drain enable field" "Disabled,Enabled" line.long 0x224 "SW_MUX_CTL_PAD_JTAG_TMS,SW_MUX_CTL_PAD_JTAG_TMS SW MUX Control Register" bitfld.long 0x224 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x224 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x224 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x224 5. " ODE ,Open drain enable field" "Disabled,Enabled" line.long 0x228 "SW_MUX_CTL_PAD_JTAG_TCK,SW_MUX_CTL_PAD_JTAG_TCK SW MUX Control Register" bitfld.long 0x228 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x228 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x228 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x228 5. " ODE ,Open drain enable field" "Disabled,Enabled" line.long 0x22C "SW_MUX_CTL_PAD_JTAG_TDO,SW_MUX_CTL_PAD_JTAG_TDO SW MUX Control Register" bitfld.long 0x22C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x22C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x22C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x22C 5. " ODE ,Open drain enable field" "Disabled,Enabled" line.long 0x230 "SW_MUX_CTL_PAD_RTC,SW_MUX_CTL_PAD_RTC SW MUX Control Register" bitfld.long 0x230 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x230 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x230 5. " ODE ,Open drain enable field" "Disabled,Enabled" line.long 0x234 "SW_MUX_CTL_PAD_PMIC_STBY_REQ,SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register" bitfld.long 0x234 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x234 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x234 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x234 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x234 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x234 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x238 "SW_MUX_CTL_PAD_PMIC_ON_REQ,SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register" bitfld.long 0x238 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x238 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x238 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x238 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x238 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x238 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x238 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x23C "SW_MUX_CTL_PAD_ONOFF,SW_MUX_CTL_PAD_ONOFF SW MUX Control Register" bitfld.long 0x23C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x23C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x23C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x23C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x23C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x23C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x240 "SW_MUX_CTL_PAD_POR_B,SW_MUX_CTL_PAD_POR_B SW MUX Control Register" bitfld.long 0x240 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x240 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x240 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x240 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x240 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x240 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x244 "SW_MUX_CTL_PAD_RTC_RESET_B,SW_MUX_CTL_PAD_RTC_RESET_B SW MUX Control Register" bitfld.long 0x244 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x244 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x244 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x244 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x244 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x244 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x248 "SW_MUX_CTL_PAD_GPIO1_IO00,SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register" bitfld.long 0x248 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x248 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x248 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x248 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x248 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x248 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x24C "SW_MUX_CTL_PAD_GPIO1_IO01,SW_MUX_CTL_PAD_GPIO1_IO01 SW MUX Control Register" bitfld.long 0x24C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x24C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x24C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x24C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x24C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x24C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x250 "SW_MUX_CTL_PAD_GPIO1_IO02,SW_MUX_CTL_PAD_GPIO1_IO02 SW MUX Control Register" bitfld.long 0x250 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x250 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x250 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x250 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x250 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x250 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x254 "SW_MUX_CTL_PAD_GPIO1_IO03,SW_MUX_CTL_PAD_GPIO1_IO03 SW MUX Control Register" bitfld.long 0x254 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x254 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x254 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x254 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x254 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x254 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x258 "SW_MUX_CTL_PAD_GPIO1_IO04,SW_MUX_CTL_PAD_GPIO1_IO04 SW MUX Control Register" bitfld.long 0x258 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x258 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x258 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x258 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x258 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x258 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x25C "SW_MUX_CTL_PAD_GPIO1_IO05,SW_MUX_CTL_PAD_GPIO1_IO05 SW MUX Control Register" bitfld.long 0x25C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x25C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x25C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x25C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x25C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x25C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x260 "SW_MUX_CTL_PAD_GPIO1_IO06,SW_MUX_CTL_PAD_GPIO1_IO06 SW MUX Control Register" bitfld.long 0x260 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x260 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x260 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x260 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x260 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x260 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x264 "SW_MUX_CTL_PAD_GPIO1_IO07,SW_MUX_CTL_PAD_GPIO1_IO07 SW MUX Control Register" bitfld.long 0x264 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x264 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x264 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x264 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x264 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x264 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x264 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x268 "SW_MUX_CTL_PAD_GPIO1_IO08,SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Control Register" bitfld.long 0x268 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x268 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x268 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x268 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x268 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x268 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x26C "SW_MUX_CTL_PAD_GPIO1_IO09,SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Control Register" bitfld.long 0x26C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x26C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x26C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x26C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x26C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x26C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x270 "SW_MUX_CTL_PAD_GPIO1_IO10,SW_MUX_CTL_PAD_GPIO1_IO10 SW MUX Control Register" bitfld.long 0x270 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x270 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x270 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x270 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x270 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x270 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x274 "SW_MUX_CTL_PAD_GPIO1_IO11,SW_MUX_CTL_PAD_GPIO1_IO11 SW MUX Control Register" bitfld.long 0x274 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x274 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x274 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x274 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x274 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x274 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x278 "SW_MUX_CTL_PAD_GPIO1_IO12,SW_MUX_CTL_PAD_GPIO1_IO12 SW MUX Control Register" bitfld.long 0x278 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x278 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x278 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x278 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x278 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x278 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x27C "SW_MUX_CTL_PAD_GPIO1_IO13,SW_MUX_CTL_PAD_GPIO1_IO13 SW MUX Control Register" bitfld.long 0x27C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x27C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x27C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x27C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x27C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x27C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x280 "SW_MUX_CTL_PAD_GPIO1_IO14,SW_MUX_CTL_PAD_GPIO1_IO14 SW MUX Control Register" bitfld.long 0x280 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x280 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x280 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x280 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x280 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x280 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x284 "SW_MUX_CTL_PAD_GPIO1_IO15,SW_MUX_CTL_PAD_GPIO1_IO15 SW MUX Control Register" bitfld.long 0x284 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x284 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x284 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x284 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x284 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x284 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x288 "SW_MUX_CTL_PAD_ENET_MDC,SW_MUX_CTL_PAD_ENET_MDC SW MUX Control Register" bitfld.long 0x288 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x288 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x288 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x288 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x288 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x288 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x28C "SW_MUX_CTL_PAD_ENET_MDIO,SW_MUX_CTL_PAD_ENET_MDIO SW MUX Control Register" bitfld.long 0x28C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x28C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x28C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x28C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x28C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x28C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x290 "SW_MUX_CTL_PAD_ENET_TD3,SW_MUX_CTL_PAD_ENET_TD3 SW MUX Control Register" bitfld.long 0x290 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x290 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x290 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x290 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x290 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x290 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x294 "SW_MUX_CTL_PAD_ENET_TD2,SW_MUX_CTL_PAD_ENET_TD2 SW MUX Control Register" bitfld.long 0x294 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x294 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x294 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x294 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x294 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x294 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x298 "SW_MUX_CTL_PAD_ENET_TD1,SW_MUX_CTL_PAD_ENET_TD1 SW MUX Control Register" bitfld.long 0x298 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x298 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x298 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x298 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x298 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x298 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x29C "SW_MUX_CTL_PAD_ENET_TD0,SW_MUX_CTL_PAD_ENET_TD0 SW MUX Control Register" bitfld.long 0x29C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x29C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x29C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x29C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x29C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x29C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2A0 "SW_MUX_CTL_PAD_ENET_TX_CTL,SW_MUX_CTL_PAD_ENET_TX_CTL SW MUX Control Register" bitfld.long 0x2A0 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x2A0 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2A0 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x2A0 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x2A0 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2A0 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x2A0 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2A4 "SW_MUX_CTL_PAD_ENET_TXC,SW_MUX_CTL_PAD_ENET_TXC SW MUX Control Register" bitfld.long 0x2A4 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2A4 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2A4 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2A4 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2A4 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2A4 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2A8 "SW_MUX_CTL_PAD_ENET_RX_CTL,SW_MUX_CTL_PAD_ENET_RX_CTL SW MUX Control Register" bitfld.long 0x2A8 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2A8 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2A8 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2A8 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2A8 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2A8 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2AC "SW_MUX_CTL_PAD_ENET_RXC,SW_MUX_CTL_PAD_ENET_RXC SW MUX Control Register" bitfld.long 0x2AC 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2AC 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2AC 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2AC 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2AC 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2AC 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2B0 "SW_MUX_CTL_PAD_ENET_RD0,SW_MUX_CTL_PAD_ENET_RD0 SW MUX Control Register" bitfld.long 0x2B0 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2B0 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2B0 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2B0 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2B0 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2B0 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2B4 "SW_MUX_CTL_PAD_ENET_RD1,SW_MUX_CTL_PAD_ENET_RD1 SW MUX Control Register" bitfld.long 0x2B4 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2B4 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2B4 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2B4 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2B4 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2B4 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2B8 "SW_MUX_CTL_PAD_ENET_RD2,SW_MUX_CTL_PAD_ENET_RD2 SW MUX Control Register" bitfld.long 0x2B8 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2B8 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2B8 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2B8 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2B8 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2B8 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2BC "SW_MUX_CTL_PAD_ENET_RD3,SW_MUX_CTL_PAD_ENET_RD3 SW MUX Control Register" bitfld.long 0x2BC 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2BC 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2BC 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2BC 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2BC 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2BC 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2C0 "SW_MUX_CTL_PAD_SD1_CLK,SW_MUX_CTL_PAD_SD1_CLK SW MUX Control Register" bitfld.long 0x2C0 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2C0 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2C0 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2C0 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2C0 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2C0 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2C4 "SW_MUX_CTL_PAD_SD1_CMD,SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register" bitfld.long 0x2C4 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2C4 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2C4 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2C4 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2C4 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2C4 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2C8 "SW_MUX_CTL_PAD_SD1_DATA0,SW_MUX_CTL_PAD_SD1_DATA0 SW MUX Control Register" bitfld.long 0x2C8 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2C8 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2C8 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2C8 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2C8 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2C8 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2CC "SW_MUX_CTL_PAD_SD1_DATA1,SW_MUX_CTL_PAD_SD1_DATA1 SW MUX Control Register" bitfld.long 0x2CC 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2CC 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2CC 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2CC 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2CC 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2CC 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2D0 "SW_MUX_CTL_PAD_SD1_DATA2,SW_MUX_CTL_PAD_SD1_DATA2 SW MUX Control Register" bitfld.long 0x2D0 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2D0 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2D0 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2D0 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2D0 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2D0 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2D4 "SW_MUX_CTL_PAD_SD1_DATA3,SW_MUX_CTL_PAD_SD1_DATA3 SW MUX Control Register" bitfld.long 0x2D4 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x2D4 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2D4 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x2D4 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x2D4 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2D4 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x2D4 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2D8 "SW_MUX_CTL_PAD_SD1_DATA4,SW_MUX_CTL_PAD_SD1_DATA4 SW MUX Control Register" bitfld.long 0x2D8 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2D8 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2D8 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2D8 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2D8 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2D8 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2DC "SW_MUX_CTL_PAD_SD1_DATA5,SW_MUX_CTL_PAD_SD1_DATA5 SW MUX Control Register" bitfld.long 0x2DC 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2DC 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2DC 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2DC 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2DC 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2DC 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2E0 "SW_MUX_CTL_PAD_SD1_DATA6,SW_MUX_CTL_PAD_SD1_DATA6 SW MUX Control Register" bitfld.long 0x2E0 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2E0 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2E0 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2E0 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2E0 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2E0 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2E4 "SW_MUX_CTL_PAD_SD1_DATA7,SW_MUX_CTL_PAD_SD1_DATA7 SW MUX Control Register" bitfld.long 0x2E4 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2E4 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2E4 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2E4 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2E4 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2E4 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2E8 "SW_MUX_CTL_PAD_SD1_RESET_B,SW_MUX_CTL_PAD_SD1_RESET_B SW MUX Control Register" bitfld.long 0x2E8 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2E8 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2E8 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2E8 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2E8 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2E8 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2EC "SW_MUX_CTL_PAD_SD1_STROBE,SW_MUX_CTL_PAD_SD1_STROBE SW MUX Control Register" bitfld.long 0x2EC 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2EC 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2EC 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2EC 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2EC 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2EC 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2F0 "SW_MUX_CTL_PAD_SD2_CD_B,SW_MUX_CTL_PAD_SD2_CD_B SW MUX Control Register" bitfld.long 0x2F0 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2F0 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2F0 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2F0 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2F0 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2F0 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2F4 "SW_MUX_CTL_PAD_SD2_CLK,SW_MUX_CTL_PAD_SD2_CLK SW MUX Control Register" bitfld.long 0x2F4 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2F4 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2F4 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2F4 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2F4 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2F4 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2F8 "SW_MUX_CTL_PAD_SD2_CMD,SW_MUX_CTL_PAD_SD2_CMD SW MUX Control Register" bitfld.long 0x2F8 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2F8 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x2F8 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x2F8 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2F8 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x2F8 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x2FC "SW_MUX_CTL_PAD_SD2_DATA0,SW_MUX_CTL_PAD_SD2_DATA0 SW MUX Control Register" bitfld.long 0x2FC 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x2FC 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x2FC 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x2FC 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x2FC 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x2FC 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x2FC 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x300 "SW_MUX_CTL_PAD_SD2_DATA1,SW_MUX_CTL_PAD_SD2_DATA1 SW MUX Control Register" bitfld.long 0x300 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x300 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x300 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x300 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x300 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x300 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x304 "SW_MUX_CTL_PAD_SD2_DATA2,SW_MUX_CTL_PAD_SD2_DATA2 SW MUX Control Register" bitfld.long 0x304 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x304 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x304 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x304 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x304 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x304 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x308 "SW_MUX_CTL_PAD_SD2_DATA3,SW_MUX_CTL_PAD_SD2_DATA3 SW MUX Control Register" bitfld.long 0x308 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x308 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x308 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x308 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x308 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x308 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x30C "SW_MUX_CTL_PAD_SD2_RESET_B,SW_MUX_CTL_PAD_SD2_RESET_B SW MUX Control Register" bitfld.long 0x30C 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x30C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x30C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x30C 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x30C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x30C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x30C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x310 "SW_MUX_CTL_PAD_SD2_WP,SW_MUX_CTL_PAD_SD2_WP SW MUX Control Register" bitfld.long 0x310 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x310 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x310 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x310 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x310 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x310 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x314 "SW_MUX_CTL_PAD_NAND_ALE,SW_MUX_CTL_PAD_NAND_ALE SW MUX Control Register" bitfld.long 0x314 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x314 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x314 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x314 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x314 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x314 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x318 "SW_MUX_CTL_PAD_NAND_CE0_B,SW_MUX_CTL_PAD_NAND_CE0_B SW MUX Control Register" bitfld.long 0x318 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x318 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x318 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x318 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x318 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x318 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x31C "SW_MUX_CTL_PAD_NAND_CE1_B,SW_MUX_CTL_PAD_NAND_CE0_B SW MUX Control Register" bitfld.long 0x31C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x31C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x31C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x31C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x31C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x31C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x320 "SW_MUX_CTL_PAD_NAND_CE2_B,SW_MUX_CTL_PAD_NAND_CE2_B SW MUX Control Register" bitfld.long 0x320 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x320 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x320 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x320 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x320 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x320 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x324 "SW_MUX_CTL_PAD_NAND_CE3_B,SW_MUX_CTL_PAD_NAND_CE3_B SW MUX Control Register" bitfld.long 0x324 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x324 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x324 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x324 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x324 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x324 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x328 "SW_MUX_CTL_PAD_NAND_CLE,SW_MUX_CTL_PAD_NAND_CLE SW MUX Control Register" bitfld.long 0x328 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x328 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x328 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x328 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x328 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x328 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x32C "SW_MUX_CTL_PAD_NAND_DATA00,SW_MUX_CTL_PAD_NAND_DATA00 SW MUX Control Register" bitfld.long 0x32C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x32C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x32C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x32C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x32C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x32C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x330 "SW_MUX_CTL_PAD_NAND_DATA01,SW_MUX_CTL_PAD_NAND_DATA01 SW MUX Control Register" bitfld.long 0x330 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x330 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x330 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x330 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x330 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x330 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x334 "SW_MUX_CTL_PAD_NAND_DATA02,SW_MUX_CTL_PAD_NAND_DATA01 SW MUX Control Register" bitfld.long 0x334 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x334 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x334 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x334 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x334 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x334 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x338 "SW_MUX_CTL_PAD_NAND_DATA03,SW_MUX_CTL_PAD_NAND_DATA01 SW MUX Control Register" bitfld.long 0x338 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x338 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x338 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x338 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x338 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x338 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x338 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x33C "SW_MUX_CTL_PAD_NAND_DATA04,SW_MUX_CTL_PAD_NAND_DATA04 SW MUX Control Register" bitfld.long 0x33C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x33C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x33C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x33C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x33C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x33C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x340 "SW_MUX_CTL_PAD_NAND_DATA05,SW_MUX_CTL_PAD_NAND_DATA05 SW MUX Control Register" bitfld.long 0x340 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x340 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x340 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x340 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x340 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x340 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x344 "SW_MUX_CTL_PAD_NAND_DATA06,SW_MUX_CTL_PAD_NAND_DATA06 SW MUX Control Register" bitfld.long 0x344 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x344 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x344 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x344 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x344 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x344 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x348 "SW_MUX_CTL_PAD_NAND_DATA07,SW_MUX_CTL_PAD_NAND_DATA07 SW MUX Control Register" bitfld.long 0x348 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x348 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x348 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x348 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x348 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x348 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x34C "SW_MUX_CTL_PAD_NAND_DQS,SW_MUX_CTL_PAD_NAND_DQS SW MUX Control Register" bitfld.long 0x34C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x34C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x34C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x34C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x34C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x34C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x350 "SW_MUX_CTL_PAD_NAND_RE_B,SW_MUX_CTL_PAD_NAND_RE_B SW MUX Control Register" bitfld.long 0x350 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x350 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x350 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x350 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x350 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x350 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x354 "SW_MUX_CTL_PAD_NAND_READY_B,SW_MUX_CTL_PAD_NAND_READY_B SW MUX Control Register" bitfld.long 0x354 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x354 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x354 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x354 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x354 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x354 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x358 "SW_MUX_CTL_PAD_NAND_WE_B,SW_MUX_CTL_PAD_NAND_WE_B SW MUX Control Register" bitfld.long 0x358 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x358 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x358 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x358 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x358 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x358 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x35C "SW_MUX_CTL_PAD_NAND_WP_B,SW_MUX_CTL_PAD_NAND_WE_B SW MUX Control Register" bitfld.long 0x35C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x35C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x35C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x35C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x35C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x35C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x360 "SW_MUX_CTL_PAD_SAI5_RXFS,SW_MUX_CTL_PAD_SAI5_RXFS SW MUX Control Register" bitfld.long 0x360 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x360 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x360 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x360 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x360 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x360 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x364 "SW_MUX_CTL_PAD_SAI5_RXC,SW_MUX_CTL_PAD_SAI5_RXC SW MUX Control Register" bitfld.long 0x364 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x364 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x364 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x364 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x364 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x364 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x368 "SW_MUX_CTL_PAD_SAI5_RXD0,SW_MUX_CTL_PAD_SAI5_RXD0 SW MUX Control Register" bitfld.long 0x368 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x368 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x368 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x368 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x368 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x368 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x36C "SW_MUX_CTL_PAD_SAI5_RXD1,SW_MUX_CTL_PAD_SAI5_RXD1 SW MUX Control Register" bitfld.long 0x36C 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x36C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x36C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x36C 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x36C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x36C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x36C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x370 "SW_MUX_CTL_PAD_SAI5_RXD2,SW_MUX_CTL_PAD_SAI5_RXD2 SW MUX Control Register" bitfld.long 0x370 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x370 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x370 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x370 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x370 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x370 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x374 "SW_MUX_CTL_PAD_SAI5_RXD3,SW_MUX_CTL_PAD_SAI5_RXD3 SW MUX Control Register" bitfld.long 0x374 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x374 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x374 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x374 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x374 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x374 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x378 "SW_MUX_CTL_PAD_SAI5_MCLK,SW_MUX_CTL_PAD_SAI5_MCLK SW MUX Control Register" bitfld.long 0x378 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x378 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x378 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x378 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x378 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x378 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x37C "SW_MUX_CTL_PAD_SAI1_RXFS,SW_MUX_CTL_PAD_SAI1_RXFS SW MUX Control Register" bitfld.long 0x37C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x37C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x37C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x37C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x37C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x37C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x380 "SW_MUX_CTL_PAD_SAI1_RXC,SW_MUX_CTL_PAD_SAI1_RXC SW MUX Control Register" bitfld.long 0x380 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x380 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x380 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x380 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x380 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x380 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x384 "SW_MUX_CTL_PAD_SAI1_RXD0,SW_MUX_CTL_PAD_SAI1_RXD0 SW MUX Control Register" bitfld.long 0x384 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x384 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x384 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x384 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x384 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x384 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x388 "SW_MUX_CTL_PAD_SAI1_RXD1,SW_MUX_CTL_PAD_SAI1_RXD1 SW MUX Control Register" bitfld.long 0x388 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x388 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x388 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x388 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x388 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x388 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x38C "SW_MUX_CTL_PAD_SAI1_RXD2,SW_MUX_CTL_PAD_SAI1_RXD2 SW MUX Control Register" bitfld.long 0x38C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x38C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x38C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x38C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x38C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x38C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x390 "SW_MUX_CTL_PAD_SAI1_RXD3,SW_MUX_CTL_PAD_SAI1_RXD3 SW MUX Control Register" bitfld.long 0x390 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x390 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x390 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x390 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x390 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x390 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x394 "SW_MUX_CTL_PAD_SAI1_RXD4,SW_MUX_CTL_PAD_SAI1_RXD4 SW MUX Control Register" bitfld.long 0x394 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x394 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x394 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x394 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x394 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x394 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x398 "SW_MUX_CTL_PAD_SAI1_RXD5,SW_MUX_CTL_PAD_SAI1_RXD5 SW MUX Control Register" bitfld.long 0x398 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x398 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x398 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x398 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x398 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x398 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x39C "SW_MUX_CTL_PAD_SAI1_RXD6,SW_MUX_CTL_PAD_SAI1_RXD6 SW MUX Control Register" bitfld.long 0x39C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x39C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x39C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x39C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x39C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x39C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3A0 "SW_MUX_CTL_PAD_SAI1_RXD7,SW_MUX_CTL_PAD_SAI1_RXD7 SW MUX Control Register" bitfld.long 0x3A0 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3A0 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3A0 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3A0 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3A0 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3A0 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3A4 "SW_MUX_CTL_PAD_SAI1_TXFS,SW_MUX_CTL_PAD_SAI1_TXFS SW MUX Control Register" bitfld.long 0x3A4 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x3A4 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3A4 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x3A4 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x3A4 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3A4 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x3A4 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3A8 "SW_MUX_CTL_PAD_SAI1_TXC,SW_MUX_CTL_PAD_SAI1_TXC SW MUX Control Register" bitfld.long 0x3A8 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3A8 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3A8 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3A8 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3A8 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3A8 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3AC "SW_MUX_CTL_PAD_SAI1_TXD0,SW_MUX_CTL_PAD_SAI1_TXD0 SW MUX Control Register" bitfld.long 0x3AC 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3AC 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3AC 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3AC 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3AC 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3AC 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3B0 "SW_MUX_CTL_PAD_SAI1_TXD1,SW_MUX_CTL_PAD_SAI1_TXD1 SW MUX Control Register" bitfld.long 0x3B0 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3B0 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3B0 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3B0 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3B0 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3B0 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3B4 "SW_MUX_CTL_PAD_SAI1_TXD2,SW_MUX_CTL_PAD_SAI1_TXD2 SW MUX Control Register" bitfld.long 0x3B4 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3B4 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3B4 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3B4 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3B4 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3B4 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3B8 "SW_MUX_CTL_PAD_SAI1_TXD3,SW_MUX_CTL_PAD_SAI1_TXD3 SW MUX Control Register" bitfld.long 0x3B8 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3B8 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3B8 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3B8 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3B8 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3B8 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3BC "SW_MUX_CTL_PAD_SAI1_TXD4,SW_MUX_CTL_PAD_SAI1_TXD4 SW MUX Control Register" bitfld.long 0x3BC 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3BC 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3BC 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3BC 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3BC 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3BC 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3C0 "SW_MUX_CTL_PAD_SAI1_TXD5,SW_MUX_CTL_PAD_SAI1_TXD5 SW MUX Control Register" bitfld.long 0x3C0 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3C0 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3C0 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3C0 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3C0 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3C0 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3C4 "SW_MUX_CTL_PAD_SAI1_TXD6,SW_MUX_CTL_PAD_SAI1_TXD6 SW MUX Control Register" bitfld.long 0x3C4 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3C4 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3C4 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3C4 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3C4 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3C4 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3C8 "SW_MUX_CTL_PAD_SAI1_TXD7,SW_MUX_CTL_PAD_SAI1_TXD7 SW MUX Control Register" bitfld.long 0x3C8 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3C8 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3C8 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3C8 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3C8 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3C8 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3CC "SW_MUX_CTL_PAD_SAI1_MCLK,SW_MUX_CTL_PAD_SAI1_MCLK SW MUX Control Register" bitfld.long 0x3CC 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3CC 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3CC 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3CC 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3CC 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3CC 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3D0 "SW_MUX_CTL_PAD_SAI2_RXFS,SW_MUX_CTL_PAD_SAI2_RXFS SW MUX Control Register" bitfld.long 0x3D0 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3D0 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3D0 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3D0 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3D0 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3D0 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3D4 "SW_MUX_CTL_PAD_SAI2_RXC,SW_MUX_CTL_PAD_SAI2_RXC SW MUX Control Register" bitfld.long 0x3D4 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3D4 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3D4 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3D4 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3D4 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3D4 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3D8 "SW_MUX_CTL_PAD_SAI2_RXD0,SW_MUX_CTL_PAD_SAI2_RXD0 SW MUX Control Register" bitfld.long 0x3D8 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3D8 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3D8 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3D8 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3D8 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3D8 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3DC "SW_MUX_CTL_PAD_SAI2_TXFS,SW_MUX_CTL_PAD_SAI2_TXFS SW MUX Control Register" bitfld.long 0x3DC 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x3DC 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3DC 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x3DC 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x3DC 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3DC 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x3DC 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3E0 "SW_MUX_CTL_PAD_SAI2_TXC,SW_MUX_CTL_PAD_SAI2_TXC SW MUX Control Register" bitfld.long 0x3E0 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3E0 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3E0 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3E0 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3E0 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3E0 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3E4 "SW_MUX_CTL_PAD_SAI2_TXD0,SW_MUX_CTL_PAD_SAI2_TXD0 SW MUX Control Register" bitfld.long 0x3E4 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3E4 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3E4 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3E4 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3E4 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3E4 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3E8 "SW_MUX_CTL_PAD_SAI2_MCLK,SW_MUX_CTL_PAD_SAI2_MCLK SW MUX Control Register" bitfld.long 0x3E8 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3E8 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3E8 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3E8 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3E8 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3E8 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3EC "SW_MUX_CTL_PAD_SAI3_RXFS,SW_MUX_CTL_PAD_SAI3_RXFS SW MUX Control Register" bitfld.long 0x3EC 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3EC 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3EC 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3EC 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3EC 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3EC 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3F0 "SW_MUX_CTL_PAD_SAI3_RXC,SW_MUX_CTL_PAD_SAI3_RXC SW MUX Control Register" bitfld.long 0x3F0 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3F0 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3F0 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3F0 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3F0 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3F0 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3F4 "SW_MUX_CTL_PAD_SAI3_RXD0,SW_MUX_CTL_PAD_SAI3_RXD0 SW MUX Control Register" bitfld.long 0x3F4 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3F4 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3F4 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3F4 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3F4 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3F4 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3F8 "SW_MUX_CTL_PAD_SAI3_TXFS,SW_MUX_CTL_PAD_SAI3_TXFS SW MUX Control Register" bitfld.long 0x3F8 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3F8 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x3F8 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x3F8 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3F8 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x3F8 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x3FC "SW_MUX_CTL_PAD_SAI3_TXC,SW_MUX_CTL_PAD_SAI3_TXC SW MUX Control Register" bitfld.long 0x3FC 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x3FC 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x3FC 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x3FC 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x3FC 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x3FC 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x3FC 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x400 "SW_MUX_CTL_PAD_SAI3_TXD0,SW_MUX_CTL_PAD_SAI3_TXD0 SW MUX Control Register" bitfld.long 0x400 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x400 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x400 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x400 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x400 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x400 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x404 "SW_MUX_CTL_PAD_SAI3_MCLK,SW_MUX_CTL_PAD_SAI3_MCLK SW MUX Control Register" bitfld.long 0x404 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x404 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x404 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x404 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x404 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x404 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x408 "SW_MUX_CTL_PAD_SPDIF_TX,SW_MUX_CTL_PAD_SPDIS_TX SW MUX Control Register" bitfld.long 0x408 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x408 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x408 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x408 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x408 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x408 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x40C "SW_MUX_CTL_PAD_SPDIF_RX,SW_MUX_CTL_PAD_SPDIF_RX SW MUX Control Register" bitfld.long 0x40C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x40C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x40C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x40C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x40C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x40C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x410 "SW_MUX_CTL_PAD_SPDIF_EXT_CLK,SW_MUX_CTL_PAD_SPDIF_EXT_CLK SW MUX Control Register" bitfld.long 0x410 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x410 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x410 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x410 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x410 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x410 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x414 "SW_MUX_CTL_PAD_ECSPI1_SCLK,SW_MUX_CTL_PAD_ECSPI1_SCLK SW MUX Control Register" bitfld.long 0x414 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x414 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x414 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x414 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x414 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x414 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x414 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x418 "SW_MUX_CTL_PAD_ECSPI1_MOSI,SW_MUX_CTL_PAD_ECSPI1_MOSI SW MUX Control Register" bitfld.long 0x418 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x418 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x418 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x418 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x418 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x418 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x41C "SW_MUX_CTL_PAD_ECSPI1_MISO,SW_MUX_CTL_PAD_ECSPI1_MISO SW MUX Control Register" bitfld.long 0x41C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x41C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x41C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x41C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x41C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x41C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x420 "SW_MUX_CTL_PAD_ECSPI1_SS0,SW_MUX_CTL_PAD_ECSPI1_SS0 SW MUX Control Register" bitfld.long 0x420 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x420 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x420 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x420 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x420 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x420 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x424 "SW_MUX_CTL_PAD_ECSPI2_SCLK,SW_MUX_CTL_PAD_ECSPI2_SCLK SW MUX Control Register" bitfld.long 0x424 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x424 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x424 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x424 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x424 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x424 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x424 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x428 "SW_MUX_CTL_PAD_ECSPI2_MOSI,SW_MUX_CTL_PAD_ECSPI2_MOSI SW MUX Control Register" bitfld.long 0x428 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x428 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x428 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x428 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x428 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x428 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x42C "SW_MUX_CTL_PAD_ECSPI2_MISO,SW_MUX_CTL_PAD_ECSPI2_MISO SW MUX Control Register" bitfld.long 0x42C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x42C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x42C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x42C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x42C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x42C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x430 "SW_MUX_CTL_PAD_ECSPI2_SS0,SW_MUX_CTL_PAD_ECSPI2_SS0 SW MUX Control Register" bitfld.long 0x430 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x430 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x430 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x430 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x430 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x430 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x434 "SW_MUX_CTL_PAD_I2C1_SCL,SW_MUX_CTL_PAD_I2C1_SCL SW MUX Control Register" bitfld.long 0x434 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x434 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x434 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x434 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x434 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x434 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x438 "SW_MUX_CTL_PAD_I2C1_SDA,SW_MUX_CTL_PAD_I2C1_SDA SW MUX Control Register" bitfld.long 0x438 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x438 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x438 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x438 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x438 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x438 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x43C "SW_MUX_CTL_PAD_I2C2_SCL,SW_MUX_CTL_PAD_I2C2_SCL SW MUX Control Register" bitfld.long 0x43C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x43C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x43C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x43C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x43C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x43C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x440 "SW_MUX_CTL_PAD_I2C2_SDA,SW_MUX_CTL_PAD_I2C2_SDA SW MUX Control Register" bitfld.long 0x440 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x440 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x440 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x440 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x440 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x440 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x444 "SW_MUX_CTL_PAD_I2C3_SCL,SW_MUX_CTL_PAD_I2C3_SCL SW MUX Control Register" bitfld.long 0x444 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x444 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x444 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x444 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x444 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x444 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x444 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x448 "SW_MUX_CTL_PAD_I2C3_SDA,SW_MUX_CTL_PAD_I2C3_SDA SW MUX Control Register" bitfld.long 0x448 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x448 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x448 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x448 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x448 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x448 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x44C "SW_MUX_CTL_PAD_I2C4_SCL,SW_MUX_CTL_PAD_I2C4_SCL SW MUX Control Register" bitfld.long 0x44C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x44C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x44C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x44C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x44C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x44C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x450 "SW_MUX_CTL_PAD_I2C4_SDA,SW_MUX_CTL_PAD_I2C4_SDA SW MUX Control Register" bitfld.long 0x450 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x450 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x450 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x450 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x450 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x450 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x454 "SW_MUX_CTL_PAD_UART1_RXD,SW_MUX_CTL_PAD_UART1_RXD SW MUX Control Register" bitfld.long 0x454 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x454 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x454 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x454 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x454 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x454 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x458 "SW_MUX_CTL_PAD_UART1_TXD,SW_MUX_CTL_PAD_UART1_TXD SW MUX Control Register" bitfld.long 0x458 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x458 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x458 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x458 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x458 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x458 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x45C "SW_MUX_CTL_PAD_UART2_RXD,SW_MUX_CTL_PAD_UART2_RXD SW MUX Control Register" bitfld.long 0x45C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x45C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x45C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x45C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x45C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x45C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x460 "SW_MUX_CTL_PAD_UART2_TXD,SW_MUX_CTL_PAD_UART2_TXD SW MUX Control Register" bitfld.long 0x460 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x460 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x460 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x460 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x460 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x460 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x464 "SW_MUX_CTL_PAD_UART3_RXD,SW_MUX_CTL_PAD_UART3_RXD SW MUX Control Register" bitfld.long 0x464 11.--13. " VSEL ,Voltage Select Field" "0_AUTO_DETECT,1_AUTO_DETECT,2_AUTO_DETECT,3_AUTO_DETECT,Manual_3p3V,Manual_2p5V,Manual_2p5V,Manual_1p2_1p8" bitfld.long 0x464 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x464 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" textline " " bitfld.long 0x464 6. " PUE ,Pull up enable field" "Disabled,Enabled" bitfld.long 0x464 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x464 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" textline " " bitfld.long 0x464 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x468 "SW_MUX_CTL_PAD_UART3_TXD,SW_MUX_CTL_PAD_UART3_TXD SW MUX Control Register" bitfld.long 0x468 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x468 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x468 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x468 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x468 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x468 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x46C "SW_MUX_CTL_PAD_UART4_RXD,SW_MUX_CTL_PAD_UART4_RXD SW MUX Control Register" bitfld.long 0x46C 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x46C 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x46C 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x46C 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x46C 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x46C 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" line.long 0x470 "SW_MUX_CTL_PAD_UART4_TXD,SW_MUX_CTL_PAD_UART4_TXD SW MUX Control Register" bitfld.long 0x470 8. " LVTTL ,Lvttl enable field" "Disabled,Enabled" bitfld.long 0x470 7. " HYS ,Schmitt trigger enable field" "Disabled,Enabled" bitfld.long 0x470 6. " PUE ,Pull up enable field" "Disabled,Enabled" textline " " bitfld.long 0x470 5. " ODE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x470 3.--4. " SRE ,Slow rate field" "Slow,Medium,Fast,MAX" bitfld.long 0x470 0.--2. " DSE ,Drive strength field" "HI_Z,255 OHM,105 OHM,75 OHM,85 OHM,65 OHM,45 OHM,40 OHM" group.long 0x4BC++0x77 line.long 0x00 "CCM_PMIV_READY_SELECT_INPUT,CCM_PMIV_READY_SELECT_INPUT DAISY Register" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "0,1" line.long 0x04 "ENET1_MDIO_SELECT_INPUT,ENET1_MDIO_SELECT_INPUT DAISY Register" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "0,1,2,3" line.long 0x08 "SAI1_RX_SYNC_SELECT_INPUT,SAI1_RX_SYNC_SELECT_INPUT DAISY Register" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "SAI1_RXFS_ALT0,SAI1_RXD5_ALT3" line.long 0x0C "SAI1_TX_BCLK_SELECT_INPUT,SAI1_TX_BCLK_SELECT_INPUT DAISY Register" bitfld.long 0x0C 0.--1. " DAISY ,Input Select (DAISY) Field" "SAI5_MCLK_ALT1,SAI1_TXC_ALT0,SAI1_MCLK_ALT2," line.long 0x10 "SAI1_TX_SYNC_SELECT_INPUT,SAI1_TX_SYNC_SELECT_INPUT DAISY Register" bitfld.long 0x10 0.--2. " DAISY ,Input Select (DAISY) Field" "SAI5_RXD1_ALT2,SAI1_RXD2_ALT2,SAI5_RXD3_ALT2,SAI1_TXFS_ALT0,SAI1_RXD7_ALT2,?..." line.long 0x14 "SAI5_RX_BCLK_SELECT_INPUT,SAI5_RX_BCLK_SELECT_INPUT DAISY Register" bitfld.long 0x14 0.--1. " DAISY ,Input Select (DAISY) Field" "0,1,2,3" line.long 0x18 "SAI5_RXD0_SELECT_INPUT,SAI5_RXD0_SELECT_INPUT DAISY Register" bitfld.long 0x18 0.--1. " DAISY ,Input Select (DAISY) Field" "0,1,2,3" line.long 0x1C "SAI5_RXD1_SELECT_INPUT,SAI5_RXD1_SELECT_INPUT DAISY Register" bitfld.long 0x1C 0.--1. " DAISY ,Input Select (DAISY) Field" "0,1,2,3" line.long 0x20 "SAI5_RXD2_SELECT_INPUT,SAI5_RXD2_SELECT_INPUT DAISY Register" bitfld.long 0x20 0.--1. " DAISY ,Input Select (DAISY) Field" "0,1,2,3" line.long 0x24 "SAI5_RXD3_SELECT_INPUT,SAI5_RXD3_SELECT_INPUT DAISY Register" bitfld.long 0x24 0.--1. " DAISY ,Input Select (DAISY) Field" "0,1,2,3" line.long 0x28 "SAI5_RX_SYNC_SELECT_INPUT,SAI5_RX_SYNC_SELECT_INPUT DAISY Register" bitfld.long 0x28 0.--1. " DAISY ,Input Select (DAISY) Field" "0,1,2,3" line.long 0x2C "SAI5_TX_BCLK_SELECT_INPUT,SAI5_TX_BCLK_SELECT_INPUT DAISY Register" bitfld.long 0x2C 0.--1. " DAISY ,Input Select (DAISY) Field" "SAI5_RXD2_ALT3,SAI1_TXC_ALT1,SAI2_RXC_ALT1," line.long 0x30 "SAI5_TX_SYNC_SELECT_INPUT,SAI5_TX_SYNC_SELECT_INPUT DAISY Register" bitfld.long 0x30 0.--1. " DAISY ,Input Select (DAISY) Field" "SAI5_RXD1_ALT3,SAI1_TXFS_ALT1,SAI2_RXFS_ALT1," line.long 0x34 "UART1_RTS_B_SELECT_INPUT,UART1_RXD_B_SELECT_INPUT DAISY Register" bitfld.long 0x34 0. " DAISY ,Input Select (DAISY) Field" "UART3_RXD_ALT1,UART3_TXD_ALT1" line.long 0x38 "UART1_RXD_B_SELECT_INPUT,UART1_RXD_B_SELECT_INPUT DAISY Register" bitfld.long 0x38 0. " DAISY ,Input Select (DAISY) Field" "UART1_RXD_ALT3,UART1_TXD_ALT3" line.long 0x3C "UART2_RTS_B_SELECT_INPUT,UART2_RXD_B_SELECT_INPUT DAISY Register" bitfld.long 0x3C 0. " DAISY ,Input Select (DAISY) Field" "UART4_RXD_ALT1,UART4_TXD_ALT1" line.long 0x40 "UART2_RXD_B_SELECT_INPUT,UART2_RXD_B_SELECT_INPUT DAISY Register" bitfld.long 0x40 0. " DAISY ,Input Select (DAISY) Field" "UART2_RXD_ALT1,UART2_TXD_ALT0" line.long 0x44 "UART3_RTS_B_SELECT_INPUT,UART3_RXD_B_SELECT_INPUT DAISY Register" bitfld.long 0x44 0. " DAISY ,Input Select (DAISY) Field" "ECSPI1_MISO_ALT1,ECSPI1_SS0_ALT1" line.long 0x48 "UART3_RXD_B_SELECT_INPUT,UART3_RXD_B_SELECT_INPUT DAISY Register" bitfld.long 0x48 0.--1. " DAISY ,Input Select (DAISY) Field" "ECSPI1_SCLK_ALT1,ECSPI_MOSI_ALT1,UART3_RXD_ALT0,UART3_TXD_ALT0" line.long 0x4C "UART4_RTS_B_SELECT_INPUT,UART4_RXD_B_SELECT_INPUT DAISY Register" bitfld.long 0x4C 0. " DAISY ,Input Select (DAISY) Field" "ECSPI2_MISO_ALT1,ECSPI2_SS0_ALT1" line.long 0x50 "UART4_RXD_B_SELECT_INPUT,UART4_RXD_B_SELECT_INPUT DAISY Register" bitfld.long 0x50 0.--1. " DAISY ,Input Select (DAISY) Field" "ECSPI2_SCLK_ALT1,ECSPI2_MOSI_ALT1,UART4_RXD_ALT0," line.long 0x54 "SAI6_RX_BCLK_SELECT_INPUT,SAI6_RX_BCLK_SELECT_INPUT DAISY Register" bitfld.long 0x54 0. " DAISY ,Input Select (DAISY) Field" "0,1" line.long 0x58 "SAI6_RXD0_SELECT_INPUT,SAI6_RXD0_SELECT_INPUT DAISY Register" bitfld.long 0x58 0. " DAISY ,Input Select (DAISY) Field" "0,1" line.long 0x5C "SAI6_RX_SYNC_SELECT_INPUT,SAI6_RX_SYNC_SELECT_INPUT DAISY Register" bitfld.long 0x5C 0. " DAISY ,Input Select (DAISY) Field" "0,1" line.long 0x60 "SAI6_TX_BCLK_SELECT_INPUT,SAI6_TX_BCLK_SELECT_INPUT DAISY Register" bitfld.long 0x60 0. " DAISY ,Input Select (DAISY) Field" "SAI1_RXD4_ALT1,SAI1_TXD4_ALT2" line.long 0x64 "SAI6_TX_SYNC_SELECT_INPUT,SAI6_TX_SYNC_SELECT_INPUT DAISY Register" bitfld.long 0x64 0. " DAISY ,Input Select (DAISY) Field" "SAI1_RXD6_ALT1,SAI1_TXD6_ALT2" line.long 0x68 "PCIE1_CLKREQ_B_SELECT_INPUT,PCIE1_CLKREQ_B_SELECT_INPUT DAISY Register" bitfld.long 0x68 0. " DAISY ,Input Select (DAISY) Field" "I2C4_SCL_ALT2,UART4_RXD_ALT2" line.long 0x6C "PCIE2_CLKREQ_B_SELECT_INPUT,PCIE2_CLKREQ_B_SELECT_INPUT DAISY Register" bitfld.long 0x6C 0. " DAISY ,Input Select (DAISY) Field" "I2C4_SDA_ALT2,UART4_TXD_ALT2" line.long 0x70 "SAI5_MCLK_SELECT_INPUT,SAI5_MCLK_SELECT_INPUT DAISY Register" bitfld.long 0x70 0.--1. " DAISY ,Input Select (DAISY) Field" "SAI5_MCLK_ALT0,SAI1_MCLK_ALT1,SAI2_MCLK_ALT1,SAI3_MCLK_ALT2" line.long 0x74 "SAI6_MCLK_SELECT_INPUT,SAI6_MCLK_SELECT_INPUT DAISY Register" bitfld.long 0x74 0. " DAISY ,Input Select (DAISY) Field" "SAI1_RXD7_ALT1,SAI1_TXD7_ALT1" width 0x0B tree.end tree.end tree.open "GPIO (General Purpose Input/Output)" tree "GPIO 1" base ad:0x30200000 width 10. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High" bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High" bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High" bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High" newline bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High" bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High" bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High" bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" newline bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" newline bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" newline bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" newline bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" newline bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" newline bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" newline bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 29. " GDIR29 ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " GDIR28 ,GPIO direction 28 bit" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,GPIO direction 26 bit" "Input,Output" newline bitfld.long 0x04 25. " GDIR25 ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,GPIO direction 24 bit" "Input,Output" bitfld.long 0x04 23. " GDIR23 ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,GPIO direction 22 bit" "Input,Output" newline bitfld.long 0x04 21. " GDIR21 ,GPIO direction 21 bit" "Input,Output" newline bitfld.long 0x04 20. " GDIR20 ,GPIO direction 20 bit" "Input,Output" bitfld.long 0x04 19. " GDIR19 ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,GPIO direction 17 bit" "Input,Output" newline bitfld.long 0x04 16. " GDIR16 ,GPIO direction 16 bit" "Input,Output" bitfld.long 0x04 15. " GDIR15 ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,GPIO direction 13 bit" "Input,Output" newline bitfld.long 0x04 12. " GDIR12 ,GPIO direction 12 bit" "Input,Output" bitfld.long 0x04 11. " GDIR11 ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,GPIO direction 9 bit" "Input,Output" newline bitfld.long 0x04 8. " GDIR8 ,GPIO direction 8 bit" "Input,Output" bitfld.long 0x04 7. " GDIR7 ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,GPIO direction 5 bit" "Input,Output" newline bitfld.long 0x04 4. " GDIR4 ,GPIO direction 4 bit" "Input,Output" bitfld.long 0x04 3. " GDIR3 ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,GPIO direction 1 bit" "Input,Output" newline bitfld.long 0x04 0. " GDIR0 ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 29. " PSR29 ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " PSR28 ,GPIO pad status bit 28" "Low,High" bitfld.long 0x00 27. " PSR27 ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " PSR26 ,GPIO pad status bit 26" "Low,High" newline bitfld.long 0x00 25. " PSR25 ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " PSR24 ,GPIO pad status bit 24" "Low,High" bitfld.long 0x00 23. " PSR23 ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " PSR22 ,GPIO pad status bit 22" "Low,High" newline bitfld.long 0x00 21. " PSR21 ,GPIO pad status bit 21" "Low,High" newline bitfld.long 0x00 20. " PSR20 ,GPIO pad status bit 20" "Low,High" bitfld.long 0x00 19. " PSR19 ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,GPIO pad status bit 17" "Low,High" newline bitfld.long 0x00 16. " PSR16 ,GPIO pad status bit 16" "Low,High" bitfld.long 0x00 15. " PSR15 ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " PSR13 ,GPIO pad status bit 13" "Low,High" newline bitfld.long 0x00 12. " PSR12 ,GPIO pad status bit 12" "Low,High" bitfld.long 0x00 11. " PSR11 ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " PSR10 ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,GPIO pad status bit 9" "Low,High" newline bitfld.long 0x00 8. " PSR8 ,GPIO pad status bit 8" "Low,High" bitfld.long 0x00 7. " PSR7 ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,GPIO pad status bit 5" "Low,High" newline bitfld.long 0x00 4. " PSR4 ,GPIO pad status bit 4" "Low,High" bitfld.long 0x00 3. " PSR3 ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " PSR1 ,GPIO pad status bit 1" "Low,High" newline bitfld.long 0x00 0. " PSR0 ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x03 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR15 ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 28.--29. " ICR14 ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 26.--27. " ICR13 ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 24.--25. " ICR12 ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 22.--23. " ICR11 ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 20.--21. " ICR10 ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 18.--19. " ICR9 ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 16.--17. " ICR8 ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 14.--15. " ICR7 ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 12.--13. " ICR6 ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 10.--11. " ICR5 ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 8.--9. " ICR4 ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 6.--7. " ICR3 ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 4.--5. " ICR2 ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 2.--3. " ICR1 ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 0.--1. " ICR0 ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low level,High level,Rising edge,Falling edge" group.long 0x10++0x03 line.long 0x00 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x00 26.--27. " ICR29 ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 24.--25. " ICR28 ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 22.--23. " ICR27 ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 20.--21. " ICR26 ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 18.--19. " ICR25 ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 16.--17. " ICR24 ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 14.--15. " ICR23 ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 12.--13. " ICR22 ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 10.--11. " ICR21 ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 8.--9. " ICR20 ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 6.--7. " ICR19 ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 4.--5. " ICR18 ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 2.--3. " ICR17 ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 0.--1. " ICR16 ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low level,High level,Rising edge,Falling edge" group.long 0x14++0x0B line.long 0x00 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x00 29. " IMR29 ,Interrupt 29 mask bit" "Masked,Not masked" bitfld.long 0x00 28. " IMR28 ,Interrupt 28 mask bit" "Masked,Not masked" bitfld.long 0x00 27. " IMR27 ,Interrupt 27 mask bit" "Masked,Not masked" bitfld.long 0x00 26. " IMR26 ,Interrupt 26 mask bit" "Masked,Not masked" newline bitfld.long 0x00 25. " IMR25 ,Interrupt 25 mask bit" "Masked,Not masked" bitfld.long 0x00 24. " IMR24 ,Interrupt 24 mask bit" "Masked,Not masked" bitfld.long 0x00 23. " IMR23 ,Interrupt 23 mask bit" "Masked,Not masked" bitfld.long 0x00 22. " IMR22 ,Interrupt 22 mask bit" "Masked,Not masked" newline bitfld.long 0x00 21. " IMR21 ,Interrupt 21 mask bit" "Masked,Not masked" newline bitfld.long 0x00 20. " IMR20 ,Interrupt 20 mask bit" "Masked,Not masked" bitfld.long 0x00 19. " IMR19 ,Interrupt 19 mask bit" "Masked,Not masked" bitfld.long 0x00 18. " IMR18 ,Interrupt 18 mask bit" "Masked,Not masked" bitfld.long 0x00 17. " IMR17 ,Interrupt 17 mask bit" "Masked,Not masked" newline bitfld.long 0x00 16. " IMR16 ,Interrupt 16 mask bit" "Masked,Not masked" bitfld.long 0x00 15. " IMR15 ,Interrupt 15 mask bit" "Masked,Not masked" bitfld.long 0x00 14. " IMR14 ,Interrupt 14 mask bit" "Masked,Not masked" bitfld.long 0x00 13. " IMR13 ,Interrupt 13 mask bit" "Masked,Not masked" newline bitfld.long 0x00 12. " IMR12 ,Interrupt 12 mask bit" "Masked,Not masked" bitfld.long 0x00 11. " IMR11 ,Interrupt 11 mask bit" "Masked,Not masked" bitfld.long 0x00 10. " IMR10 ,Interrupt 10 mask bit" "Masked,Not masked" bitfld.long 0x00 9. " IMR9 ,Interrupt 9 mask bit" "Masked,Not masked" newline bitfld.long 0x00 8. " IMR8 ,Interrupt 8 mask bit" "Masked,Not masked" bitfld.long 0x00 7. " IMR7 ,Interrupt 7 mask bit" "Masked,Not masked" bitfld.long 0x00 6. " IMR6 ,Interrupt 6 mask bit" "Masked,Not masked" bitfld.long 0x00 5. " IMR5 ,Interrupt 5 mask bit" "Masked,Not masked" newline bitfld.long 0x00 4. " IMR4 ,Interrupt 4 mask bit" "Masked,Not masked" bitfld.long 0x00 3. " IMR3 ,Interrupt 3 mask bit" "Masked,Not masked" bitfld.long 0x00 2. " IMR2 ,Interrupt 2 mask bit" "Masked,Not masked" bitfld.long 0x00 1. " IMR1 ,Interrupt 1 mask bit" "Masked,Not masked" newline bitfld.long 0x00 0. " IMR0 ,Interrupt 0 mask bit" "Masked,Not masked" line.long 0x04 "ISR,GPIO Interrupt Status Register" eventfld.long 0x04 29. " ISR29 ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x04 28. " ISR28 ,Interrupt 28 status bit" "No interrupt,Interrupt" eventfld.long 0x04 27. " ISR27 ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x04 26. " ISR26 ,Interrupt 26 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 25. " ISR25 ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x04 24. " ISR24 ,Interrupt 24 status bit" "No interrupt,Interrupt" eventfld.long 0x04 23. " ISR23 ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x04 22. " ISR22 ,Interrupt 22 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 21. " ISR21 ,Interrupt 21 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 20. " ISR20 ,Interrupt 20 status bit" "No interrupt,Interrupt" eventfld.long 0x04 19. " ISR19 ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x04 18. " ISR18 ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x04 17. " ISR17 ,Interrupt 17 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 16. " ISR16 ,Interrupt 16 status bit" "No interrupt,Interrupt" eventfld.long 0x04 15. " ISR15 ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x04 14. " ISR14 ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x04 13. " ISR13 ,Interrupt 13 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 12. " ISR12 ,Interrupt 12 status bit" "No interrupt,Interrupt" eventfld.long 0x04 11. " ISR11 ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x04 10. " ISR10 ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x04 9. " ISR9 ,Interrupt 9 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 8. " ISR8 ,Interrupt 8 status bit" "No interrupt,Interrupt" eventfld.long 0x04 7. " ISR7 ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x04 6. " ISR6 ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x04 5. " ISR5 ,Interrupt 5 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 4. " ISR4 ,Interrupt 4 status bit" "No interrupt,Interrupt" eventfld.long 0x04 3. " ISR3 ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x04 2. " ISR2 ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x04 1. " ISR1 ,Interrupt 1 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 0. " ISR0 ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x08 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x08 29. " GPIO_EDGE_SEL29 ,Edge select bit 29" "0,1" bitfld.long 0x08 28. " GPIO_EDGE_SEL28 ,Edge select bit 28" "0,1" bitfld.long 0x08 27. " GPIO_EDGE_SEL27 ,Edge select bit 27" "0,1" bitfld.long 0x08 26. " GPIO_EDGE_SEL26 ,Edge select bit 26" "0,1" newline bitfld.long 0x08 25. " GPIO_EDGE_SEL25 ,Edge select bit 25" "0,1" bitfld.long 0x08 24. " GPIO_EDGE_SEL24 ,Edge select bit 24" "0,1" bitfld.long 0x08 23. " GPIO_EDGE_SEL23 ,Edge select bit 23" "0,1" bitfld.long 0x08 22. " GPIO_EDGE_SEL22 ,Edge select bit 22" "0,1" newline bitfld.long 0x08 21. " GPIO_EDGE_SEL21 ,Edge select bit 21" "0,1" newline bitfld.long 0x08 20. " GPIO_EDGE_SEL20 ,Edge select bit 20" "0,1" bitfld.long 0x08 19. " GPIO_EDGE_SEL19 ,Edge select bit 19" "0,1" bitfld.long 0x08 18. " GPIO_EDGE_SEL18 ,Edge select bit 18" "0,1" bitfld.long 0x08 17. " GPIO_EDGE_SEL17 ,Edge select bit 17" "0,1" newline bitfld.long 0x08 16. " GPIO_EDGE_SEL16 ,Edge select bit 16" "0,1" bitfld.long 0x08 15. " GPIO_EDGE_SEL15 ,Edge select bit 15" "0,1" bitfld.long 0x08 14. " GPIO_EDGE_SEL14 ,Edge select bit 14" "0,1" bitfld.long 0x08 13. " GPIO_EDGE_SEL13 ,Edge select bit 13" "0,1" newline bitfld.long 0x08 12. " GPIO_EDGE_SEL12 ,Edge select bit 12" "0,1" bitfld.long 0x08 11. " GPIO_EDGE_SEL11 ,Edge select bit 11" "0,1" bitfld.long 0x08 10. " GPIO_EDGE_SEL10 ,Edge select bit 10" "0,1" bitfld.long 0x08 9. " GPIO_EDGE_SEL9 ,Edge select bit 9" "0,1" newline bitfld.long 0x08 8. " GPIO_EDGE_SEL8 ,Edge select bit 8" "0,1" bitfld.long 0x08 7. " GPIO_EDGE_SEL7 ,Edge select bit 7" "0,1" bitfld.long 0x08 6. " GPIO_EDGE_SEL6 ,Edge select bit 6" "0,1" bitfld.long 0x08 5. " GPIO_EDGE_SEL5 ,Edge select bit 5" "0,1" newline bitfld.long 0x08 4. " GPIO_EDGE_SEL4 ,Edge select bit 4" "0,1" bitfld.long 0x08 3. " GPIO_EDGE_SEL3 ,Edge select bit 3" "0,1" bitfld.long 0x08 2. " GPIO_EDGE_SEL2 ,Edge select bit 2" "0,1" bitfld.long 0x08 1. " GPIO_EDGE_SEL1 ,Edge select bit 1" "0,1" newline bitfld.long 0x08 0. " GPIO_EDGE_SEL0 ,Edge select bit 0" "0,1" width 0x0B tree.end tree "GPIO 2" base ad:0x30210000 width 10. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" newline bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" newline bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" newline bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" newline bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" newline bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 20. " GDIR20 ,GPIO direction 20 bit" "Input,Output" bitfld.long 0x04 19. " GDIR19 ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,GPIO direction 17 bit" "Input,Output" newline bitfld.long 0x04 16. " GDIR16 ,GPIO direction 16 bit" "Input,Output" bitfld.long 0x04 15. " GDIR15 ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,GPIO direction 13 bit" "Input,Output" newline bitfld.long 0x04 12. " GDIR12 ,GPIO direction 12 bit" "Input,Output" bitfld.long 0x04 11. " GDIR11 ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,GPIO direction 9 bit" "Input,Output" newline bitfld.long 0x04 8. " GDIR8 ,GPIO direction 8 bit" "Input,Output" bitfld.long 0x04 7. " GDIR7 ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,GPIO direction 5 bit" "Input,Output" newline bitfld.long 0x04 4. " GDIR4 ,GPIO direction 4 bit" "Input,Output" bitfld.long 0x04 3. " GDIR3 ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,GPIO direction 1 bit" "Input,Output" newline bitfld.long 0x04 0. " GDIR0 ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 20. " PSR20 ,GPIO pad status bit 20" "Low,High" bitfld.long 0x00 19. " PSR19 ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,GPIO pad status bit 17" "Low,High" newline bitfld.long 0x00 16. " PSR16 ,GPIO pad status bit 16" "Low,High" bitfld.long 0x00 15. " PSR15 ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " PSR13 ,GPIO pad status bit 13" "Low,High" newline bitfld.long 0x00 12. " PSR12 ,GPIO pad status bit 12" "Low,High" bitfld.long 0x00 11. " PSR11 ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " PSR10 ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,GPIO pad status bit 9" "Low,High" newline bitfld.long 0x00 8. " PSR8 ,GPIO pad status bit 8" "Low,High" bitfld.long 0x00 7. " PSR7 ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,GPIO pad status bit 5" "Low,High" newline bitfld.long 0x00 4. " PSR4 ,GPIO pad status bit 4" "Low,High" bitfld.long 0x00 3. " PSR3 ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " PSR1 ,GPIO pad status bit 1" "Low,High" newline bitfld.long 0x00 0. " PSR0 ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x03 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR15 ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 28.--29. " ICR14 ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 26.--27. " ICR13 ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 24.--25. " ICR12 ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 22.--23. " ICR11 ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 20.--21. " ICR10 ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 18.--19. " ICR9 ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 16.--17. " ICR8 ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 14.--15. " ICR7 ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 12.--13. " ICR6 ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 10.--11. " ICR5 ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 8.--9. " ICR4 ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 6.--7. " ICR3 ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 4.--5. " ICR2 ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 2.--3. " ICR1 ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 0.--1. " ICR0 ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low level,High level,Rising edge,Falling edge" group.long 0x10++0x03 line.long 0x00 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x00 8.--9. " ICR20 ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 6.--7. " ICR19 ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 4.--5. " ICR18 ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 2.--3. " ICR17 ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 0.--1. " ICR16 ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low level,High level,Rising edge,Falling edge" group.long 0x14++0x0B line.long 0x00 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x00 20. " IMR20 ,Interrupt 20 mask bit" "Masked,Not masked" bitfld.long 0x00 19. " IMR19 ,Interrupt 19 mask bit" "Masked,Not masked" bitfld.long 0x00 18. " IMR18 ,Interrupt 18 mask bit" "Masked,Not masked" bitfld.long 0x00 17. " IMR17 ,Interrupt 17 mask bit" "Masked,Not masked" newline bitfld.long 0x00 16. " IMR16 ,Interrupt 16 mask bit" "Masked,Not masked" bitfld.long 0x00 15. " IMR15 ,Interrupt 15 mask bit" "Masked,Not masked" bitfld.long 0x00 14. " IMR14 ,Interrupt 14 mask bit" "Masked,Not masked" bitfld.long 0x00 13. " IMR13 ,Interrupt 13 mask bit" "Masked,Not masked" newline bitfld.long 0x00 12. " IMR12 ,Interrupt 12 mask bit" "Masked,Not masked" bitfld.long 0x00 11. " IMR11 ,Interrupt 11 mask bit" "Masked,Not masked" bitfld.long 0x00 10. " IMR10 ,Interrupt 10 mask bit" "Masked,Not masked" bitfld.long 0x00 9. " IMR9 ,Interrupt 9 mask bit" "Masked,Not masked" newline bitfld.long 0x00 8. " IMR8 ,Interrupt 8 mask bit" "Masked,Not masked" bitfld.long 0x00 7. " IMR7 ,Interrupt 7 mask bit" "Masked,Not masked" bitfld.long 0x00 6. " IMR6 ,Interrupt 6 mask bit" "Masked,Not masked" bitfld.long 0x00 5. " IMR5 ,Interrupt 5 mask bit" "Masked,Not masked" newline bitfld.long 0x00 4. " IMR4 ,Interrupt 4 mask bit" "Masked,Not masked" bitfld.long 0x00 3. " IMR3 ,Interrupt 3 mask bit" "Masked,Not masked" bitfld.long 0x00 2. " IMR2 ,Interrupt 2 mask bit" "Masked,Not masked" bitfld.long 0x00 1. " IMR1 ,Interrupt 1 mask bit" "Masked,Not masked" newline bitfld.long 0x00 0. " IMR0 ,Interrupt 0 mask bit" "Masked,Not masked" line.long 0x04 "ISR,GPIO Interrupt Status Register" eventfld.long 0x04 20. " ISR20 ,Interrupt 20 status bit" "No interrupt,Interrupt" eventfld.long 0x04 19. " ISR19 ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x04 18. " ISR18 ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x04 17. " ISR17 ,Interrupt 17 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 16. " ISR16 ,Interrupt 16 status bit" "No interrupt,Interrupt" eventfld.long 0x04 15. " ISR15 ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x04 14. " ISR14 ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x04 13. " ISR13 ,Interrupt 13 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 12. " ISR12 ,Interrupt 12 status bit" "No interrupt,Interrupt" eventfld.long 0x04 11. " ISR11 ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x04 10. " ISR10 ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x04 9. " ISR9 ,Interrupt 9 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 8. " ISR8 ,Interrupt 8 status bit" "No interrupt,Interrupt" eventfld.long 0x04 7. " ISR7 ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x04 6. " ISR6 ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x04 5. " ISR5 ,Interrupt 5 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 4. " ISR4 ,Interrupt 4 status bit" "No interrupt,Interrupt" eventfld.long 0x04 3. " ISR3 ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x04 2. " ISR2 ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x04 1. " ISR1 ,Interrupt 1 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 0. " ISR0 ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x08 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x08 20. " GPIO_EDGE_SEL20 ,Edge select bit 20" "0,1" bitfld.long 0x08 19. " GPIO_EDGE_SEL19 ,Edge select bit 19" "0,1" bitfld.long 0x08 18. " GPIO_EDGE_SEL18 ,Edge select bit 18" "0,1" bitfld.long 0x08 17. " GPIO_EDGE_SEL17 ,Edge select bit 17" "0,1" newline bitfld.long 0x08 16. " GPIO_EDGE_SEL16 ,Edge select bit 16" "0,1" bitfld.long 0x08 15. " GPIO_EDGE_SEL15 ,Edge select bit 15" "0,1" bitfld.long 0x08 14. " GPIO_EDGE_SEL14 ,Edge select bit 14" "0,1" bitfld.long 0x08 13. " GPIO_EDGE_SEL13 ,Edge select bit 13" "0,1" newline bitfld.long 0x08 12. " GPIO_EDGE_SEL12 ,Edge select bit 12" "0,1" bitfld.long 0x08 11. " GPIO_EDGE_SEL11 ,Edge select bit 11" "0,1" bitfld.long 0x08 10. " GPIO_EDGE_SEL10 ,Edge select bit 10" "0,1" bitfld.long 0x08 9. " GPIO_EDGE_SEL9 ,Edge select bit 9" "0,1" newline bitfld.long 0x08 8. " GPIO_EDGE_SEL8 ,Edge select bit 8" "0,1" bitfld.long 0x08 7. " GPIO_EDGE_SEL7 ,Edge select bit 7" "0,1" bitfld.long 0x08 6. " GPIO_EDGE_SEL6 ,Edge select bit 6" "0,1" bitfld.long 0x08 5. " GPIO_EDGE_SEL5 ,Edge select bit 5" "0,1" newline bitfld.long 0x08 4. " GPIO_EDGE_SEL4 ,Edge select bit 4" "0,1" bitfld.long 0x08 3. " GPIO_EDGE_SEL3 ,Edge select bit 3" "0,1" bitfld.long 0x08 2. " GPIO_EDGE_SEL2 ,Edge select bit 2" "0,1" bitfld.long 0x08 1. " GPIO_EDGE_SEL1 ,Edge select bit 1" "0,1" newline bitfld.long 0x08 0. " GPIO_EDGE_SEL0 ,Edge select bit 0" "0,1" width 0x0B tree.end tree "GPIO 3" base ad:0x30220000 width 10. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High" bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High" bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High" bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" newline bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" newline bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" newline bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" newline bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" newline bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" newline bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" newline bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 25. " GDIR25 ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,GPIO direction 24 bit" "Input,Output" bitfld.long 0x04 23. " GDIR23 ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,GPIO direction 22 bit" "Input,Output" newline bitfld.long 0x04 21. " GDIR21 ,GPIO direction 21 bit" "Input,Output" newline bitfld.long 0x04 20. " GDIR20 ,GPIO direction 20 bit" "Input,Output" bitfld.long 0x04 19. " GDIR19 ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,GPIO direction 17 bit" "Input,Output" newline bitfld.long 0x04 16. " GDIR16 ,GPIO direction 16 bit" "Input,Output" bitfld.long 0x04 15. " GDIR15 ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,GPIO direction 13 bit" "Input,Output" newline bitfld.long 0x04 12. " GDIR12 ,GPIO direction 12 bit" "Input,Output" bitfld.long 0x04 11. " GDIR11 ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,GPIO direction 9 bit" "Input,Output" newline bitfld.long 0x04 8. " GDIR8 ,GPIO direction 8 bit" "Input,Output" bitfld.long 0x04 7. " GDIR7 ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,GPIO direction 5 bit" "Input,Output" newline bitfld.long 0x04 4. " GDIR4 ,GPIO direction 4 bit" "Input,Output" bitfld.long 0x04 3. " GDIR3 ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,GPIO direction 1 bit" "Input,Output" newline bitfld.long 0x04 0. " GDIR0 ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 25. " PSR25 ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " PSR24 ,GPIO pad status bit 24" "Low,High" bitfld.long 0x00 23. " PSR23 ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " PSR22 ,GPIO pad status bit 22" "Low,High" newline bitfld.long 0x00 21. " PSR21 ,GPIO pad status bit 21" "Low,High" newline bitfld.long 0x00 20. " PSR20 ,GPIO pad status bit 20" "Low,High" bitfld.long 0x00 19. " PSR19 ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,GPIO pad status bit 17" "Low,High" newline bitfld.long 0x00 16. " PSR16 ,GPIO pad status bit 16" "Low,High" bitfld.long 0x00 15. " PSR15 ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " PSR13 ,GPIO pad status bit 13" "Low,High" newline bitfld.long 0x00 12. " PSR12 ,GPIO pad status bit 12" "Low,High" bitfld.long 0x00 11. " PSR11 ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " PSR10 ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,GPIO pad status bit 9" "Low,High" newline bitfld.long 0x00 8. " PSR8 ,GPIO pad status bit 8" "Low,High" bitfld.long 0x00 7. " PSR7 ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,GPIO pad status bit 5" "Low,High" newline bitfld.long 0x00 4. " PSR4 ,GPIO pad status bit 4" "Low,High" bitfld.long 0x00 3. " PSR3 ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " PSR1 ,GPIO pad status bit 1" "Low,High" newline bitfld.long 0x00 0. " PSR0 ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x03 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR15 ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 28.--29. " ICR14 ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 26.--27. " ICR13 ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 24.--25. " ICR12 ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 22.--23. " ICR11 ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 20.--21. " ICR10 ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 18.--19. " ICR9 ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 16.--17. " ICR8 ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 14.--15. " ICR7 ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 12.--13. " ICR6 ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 10.--11. " ICR5 ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 8.--9. " ICR4 ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 6.--7. " ICR3 ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 4.--5. " ICR2 ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 2.--3. " ICR1 ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 0.--1. " ICR0 ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low level,High level,Rising edge,Falling edge" group.long 0x10++0x03 line.long 0x00 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x00 18.--19. " ICR25 ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 16.--17. " ICR24 ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 14.--15. " ICR23 ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 12.--13. " ICR22 ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 10.--11. " ICR21 ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 8.--9. " ICR20 ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 6.--7. " ICR19 ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 4.--5. " ICR18 ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 2.--3. " ICR17 ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 0.--1. " ICR16 ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low level,High level,Rising edge,Falling edge" group.long 0x14++0x0B line.long 0x00 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x00 25. " IMR25 ,Interrupt 25 mask bit" "Masked,Not masked" bitfld.long 0x00 24. " IMR24 ,Interrupt 24 mask bit" "Masked,Not masked" bitfld.long 0x00 23. " IMR23 ,Interrupt 23 mask bit" "Masked,Not masked" bitfld.long 0x00 22. " IMR22 ,Interrupt 22 mask bit" "Masked,Not masked" newline bitfld.long 0x00 21. " IMR21 ,Interrupt 21 mask bit" "Masked,Not masked" newline bitfld.long 0x00 20. " IMR20 ,Interrupt 20 mask bit" "Masked,Not masked" bitfld.long 0x00 19. " IMR19 ,Interrupt 19 mask bit" "Masked,Not masked" bitfld.long 0x00 18. " IMR18 ,Interrupt 18 mask bit" "Masked,Not masked" bitfld.long 0x00 17. " IMR17 ,Interrupt 17 mask bit" "Masked,Not masked" newline bitfld.long 0x00 16. " IMR16 ,Interrupt 16 mask bit" "Masked,Not masked" bitfld.long 0x00 15. " IMR15 ,Interrupt 15 mask bit" "Masked,Not masked" bitfld.long 0x00 14. " IMR14 ,Interrupt 14 mask bit" "Masked,Not masked" bitfld.long 0x00 13. " IMR13 ,Interrupt 13 mask bit" "Masked,Not masked" newline bitfld.long 0x00 12. " IMR12 ,Interrupt 12 mask bit" "Masked,Not masked" bitfld.long 0x00 11. " IMR11 ,Interrupt 11 mask bit" "Masked,Not masked" bitfld.long 0x00 10. " IMR10 ,Interrupt 10 mask bit" "Masked,Not masked" bitfld.long 0x00 9. " IMR9 ,Interrupt 9 mask bit" "Masked,Not masked" newline bitfld.long 0x00 8. " IMR8 ,Interrupt 8 mask bit" "Masked,Not masked" bitfld.long 0x00 7. " IMR7 ,Interrupt 7 mask bit" "Masked,Not masked" bitfld.long 0x00 6. " IMR6 ,Interrupt 6 mask bit" "Masked,Not masked" bitfld.long 0x00 5. " IMR5 ,Interrupt 5 mask bit" "Masked,Not masked" newline bitfld.long 0x00 4. " IMR4 ,Interrupt 4 mask bit" "Masked,Not masked" bitfld.long 0x00 3. " IMR3 ,Interrupt 3 mask bit" "Masked,Not masked" bitfld.long 0x00 2. " IMR2 ,Interrupt 2 mask bit" "Masked,Not masked" bitfld.long 0x00 1. " IMR1 ,Interrupt 1 mask bit" "Masked,Not masked" newline bitfld.long 0x00 0. " IMR0 ,Interrupt 0 mask bit" "Masked,Not masked" line.long 0x04 "ISR,GPIO Interrupt Status Register" eventfld.long 0x04 25. " ISR25 ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x04 24. " ISR24 ,Interrupt 24 status bit" "No interrupt,Interrupt" eventfld.long 0x04 23. " ISR23 ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x04 22. " ISR22 ,Interrupt 22 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 21. " ISR21 ,Interrupt 21 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 20. " ISR20 ,Interrupt 20 status bit" "No interrupt,Interrupt" eventfld.long 0x04 19. " ISR19 ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x04 18. " ISR18 ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x04 17. " ISR17 ,Interrupt 17 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 16. " ISR16 ,Interrupt 16 status bit" "No interrupt,Interrupt" eventfld.long 0x04 15. " ISR15 ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x04 14. " ISR14 ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x04 13. " ISR13 ,Interrupt 13 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 12. " ISR12 ,Interrupt 12 status bit" "No interrupt,Interrupt" eventfld.long 0x04 11. " ISR11 ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x04 10. " ISR10 ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x04 9. " ISR9 ,Interrupt 9 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 8. " ISR8 ,Interrupt 8 status bit" "No interrupt,Interrupt" eventfld.long 0x04 7. " ISR7 ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x04 6. " ISR6 ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x04 5. " ISR5 ,Interrupt 5 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 4. " ISR4 ,Interrupt 4 status bit" "No interrupt,Interrupt" eventfld.long 0x04 3. " ISR3 ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x04 2. " ISR2 ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x04 1. " ISR1 ,Interrupt 1 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 0. " ISR0 ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x08 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x08 25. " GPIO_EDGE_SEL25 ,Edge select bit 25" "0,1" bitfld.long 0x08 24. " GPIO_EDGE_SEL24 ,Edge select bit 24" "0,1" bitfld.long 0x08 23. " GPIO_EDGE_SEL23 ,Edge select bit 23" "0,1" bitfld.long 0x08 22. " GPIO_EDGE_SEL22 ,Edge select bit 22" "0,1" newline bitfld.long 0x08 21. " GPIO_EDGE_SEL21 ,Edge select bit 21" "0,1" newline bitfld.long 0x08 20. " GPIO_EDGE_SEL20 ,Edge select bit 20" "0,1" bitfld.long 0x08 19. " GPIO_EDGE_SEL19 ,Edge select bit 19" "0,1" bitfld.long 0x08 18. " GPIO_EDGE_SEL18 ,Edge select bit 18" "0,1" bitfld.long 0x08 17. " GPIO_EDGE_SEL17 ,Edge select bit 17" "0,1" newline bitfld.long 0x08 16. " GPIO_EDGE_SEL16 ,Edge select bit 16" "0,1" bitfld.long 0x08 15. " GPIO_EDGE_SEL15 ,Edge select bit 15" "0,1" bitfld.long 0x08 14. " GPIO_EDGE_SEL14 ,Edge select bit 14" "0,1" bitfld.long 0x08 13. " GPIO_EDGE_SEL13 ,Edge select bit 13" "0,1" newline bitfld.long 0x08 12. " GPIO_EDGE_SEL12 ,Edge select bit 12" "0,1" bitfld.long 0x08 11. " GPIO_EDGE_SEL11 ,Edge select bit 11" "0,1" bitfld.long 0x08 10. " GPIO_EDGE_SEL10 ,Edge select bit 10" "0,1" bitfld.long 0x08 9. " GPIO_EDGE_SEL9 ,Edge select bit 9" "0,1" newline bitfld.long 0x08 8. " GPIO_EDGE_SEL8 ,Edge select bit 8" "0,1" bitfld.long 0x08 7. " GPIO_EDGE_SEL7 ,Edge select bit 7" "0,1" bitfld.long 0x08 6. " GPIO_EDGE_SEL6 ,Edge select bit 6" "0,1" bitfld.long 0x08 5. " GPIO_EDGE_SEL5 ,Edge select bit 5" "0,1" newline bitfld.long 0x08 4. " GPIO_EDGE_SEL4 ,Edge select bit 4" "0,1" bitfld.long 0x08 3. " GPIO_EDGE_SEL3 ,Edge select bit 3" "0,1" bitfld.long 0x08 2. " GPIO_EDGE_SEL2 ,Edge select bit 2" "0,1" bitfld.long 0x08 1. " GPIO_EDGE_SEL1 ,Edge select bit 1" "0,1" newline bitfld.long 0x08 0. " GPIO_EDGE_SEL0 ,Edge select bit 0" "0,1" width 0x0B tree.end tree "GPIO 4" base ad:0x30230000 width 10. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High" bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High" newline bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High" bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High" bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High" bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High" newline bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High" bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High" bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High" bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" newline bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" newline bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" newline bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" newline bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" newline bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" newline bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" newline bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR31 ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,GPIO direction 30 bit" "Input,Output" newline bitfld.long 0x04 29. " GDIR29 ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " GDIR28 ,GPIO direction 28 bit" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,GPIO direction 26 bit" "Input,Output" newline bitfld.long 0x04 25. " GDIR25 ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,GPIO direction 24 bit" "Input,Output" bitfld.long 0x04 23. " GDIR23 ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,GPIO direction 22 bit" "Input,Output" newline bitfld.long 0x04 21. " GDIR21 ,GPIO direction 21 bit" "Input,Output" newline bitfld.long 0x04 20. " GDIR20 ,GPIO direction 20 bit" "Input,Output" bitfld.long 0x04 19. " GDIR19 ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,GPIO direction 17 bit" "Input,Output" newline bitfld.long 0x04 16. " GDIR16 ,GPIO direction 16 bit" "Input,Output" bitfld.long 0x04 15. " GDIR15 ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,GPIO direction 13 bit" "Input,Output" newline bitfld.long 0x04 12. " GDIR12 ,GPIO direction 12 bit" "Input,Output" bitfld.long 0x04 11. " GDIR11 ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,GPIO direction 9 bit" "Input,Output" newline bitfld.long 0x04 8. " GDIR8 ,GPIO direction 8 bit" "Input,Output" bitfld.long 0x04 7. " GDIR7 ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,GPIO direction 5 bit" "Input,Output" newline bitfld.long 0x04 4. " GDIR4 ,GPIO direction 4 bit" "Input,Output" bitfld.long 0x04 3. " GDIR3 ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,GPIO direction 1 bit" "Input,Output" newline bitfld.long 0x04 0. " GDIR0 ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR31 ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " PSR30 ,GPIO pad status bit 30" "Low,High" newline bitfld.long 0x00 29. " PSR29 ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " PSR28 ,GPIO pad status bit 28" "Low,High" bitfld.long 0x00 27. " PSR27 ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " PSR26 ,GPIO pad status bit 26" "Low,High" newline bitfld.long 0x00 25. " PSR25 ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " PSR24 ,GPIO pad status bit 24" "Low,High" bitfld.long 0x00 23. " PSR23 ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " PSR22 ,GPIO pad status bit 22" "Low,High" newline bitfld.long 0x00 21. " PSR21 ,GPIO pad status bit 21" "Low,High" newline bitfld.long 0x00 20. " PSR20 ,GPIO pad status bit 20" "Low,High" bitfld.long 0x00 19. " PSR19 ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,GPIO pad status bit 17" "Low,High" newline bitfld.long 0x00 16. " PSR16 ,GPIO pad status bit 16" "Low,High" bitfld.long 0x00 15. " PSR15 ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " PSR13 ,GPIO pad status bit 13" "Low,High" newline bitfld.long 0x00 12. " PSR12 ,GPIO pad status bit 12" "Low,High" bitfld.long 0x00 11. " PSR11 ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " PSR10 ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,GPIO pad status bit 9" "Low,High" newline bitfld.long 0x00 8. " PSR8 ,GPIO pad status bit 8" "Low,High" bitfld.long 0x00 7. " PSR7 ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,GPIO pad status bit 5" "Low,High" newline bitfld.long 0x00 4. " PSR4 ,GPIO pad status bit 4" "Low,High" bitfld.long 0x00 3. " PSR3 ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " PSR1 ,GPIO pad status bit 1" "Low,High" newline bitfld.long 0x00 0. " PSR0 ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x03 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR15 ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 28.--29. " ICR14 ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 26.--27. " ICR13 ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 24.--25. " ICR12 ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 22.--23. " ICR11 ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 20.--21. " ICR10 ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 18.--19. " ICR9 ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 16.--17. " ICR8 ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 14.--15. " ICR7 ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 12.--13. " ICR6 ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 10.--11. " ICR5 ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 8.--9. " ICR4 ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 6.--7. " ICR3 ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 4.--5. " ICR2 ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 2.--3. " ICR1 ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 0.--1. " ICR0 ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low level,High level,Rising edge,Falling edge" group.long 0x10++0x03 line.long 0x00 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x00 30.--31. " ICR31 ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 28.--29. " ICR30 ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 26.--27. " ICR29 ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 24.--25. " ICR28 ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 22.--23. " ICR27 ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 20.--21. " ICR26 ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 18.--19. " ICR25 ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 16.--17. " ICR24 ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 14.--15. " ICR23 ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 12.--13. " ICR22 ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 10.--11. " ICR21 ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 8.--9. " ICR20 ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 6.--7. " ICR19 ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 4.--5. " ICR18 ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 2.--3. " ICR17 ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 0.--1. " ICR16 ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low level,High level,Rising edge,Falling edge" group.long 0x14++0x0B line.long 0x00 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x00 31. " IMR31 ,Interrupt 31 mask bit" "Masked,Not masked" bitfld.long 0x00 30. " IMR30 ,Interrupt 30 mask bit" "Masked,Not masked" newline bitfld.long 0x00 29. " IMR29 ,Interrupt 29 mask bit" "Masked,Not masked" bitfld.long 0x00 28. " IMR28 ,Interrupt 28 mask bit" "Masked,Not masked" bitfld.long 0x00 27. " IMR27 ,Interrupt 27 mask bit" "Masked,Not masked" bitfld.long 0x00 26. " IMR26 ,Interrupt 26 mask bit" "Masked,Not masked" newline bitfld.long 0x00 25. " IMR25 ,Interrupt 25 mask bit" "Masked,Not masked" bitfld.long 0x00 24. " IMR24 ,Interrupt 24 mask bit" "Masked,Not masked" bitfld.long 0x00 23. " IMR23 ,Interrupt 23 mask bit" "Masked,Not masked" bitfld.long 0x00 22. " IMR22 ,Interrupt 22 mask bit" "Masked,Not masked" newline bitfld.long 0x00 21. " IMR21 ,Interrupt 21 mask bit" "Masked,Not masked" newline bitfld.long 0x00 20. " IMR20 ,Interrupt 20 mask bit" "Masked,Not masked" bitfld.long 0x00 19. " IMR19 ,Interrupt 19 mask bit" "Masked,Not masked" bitfld.long 0x00 18. " IMR18 ,Interrupt 18 mask bit" "Masked,Not masked" bitfld.long 0x00 17. " IMR17 ,Interrupt 17 mask bit" "Masked,Not masked" newline bitfld.long 0x00 16. " IMR16 ,Interrupt 16 mask bit" "Masked,Not masked" bitfld.long 0x00 15. " IMR15 ,Interrupt 15 mask bit" "Masked,Not masked" bitfld.long 0x00 14. " IMR14 ,Interrupt 14 mask bit" "Masked,Not masked" bitfld.long 0x00 13. " IMR13 ,Interrupt 13 mask bit" "Masked,Not masked" newline bitfld.long 0x00 12. " IMR12 ,Interrupt 12 mask bit" "Masked,Not masked" bitfld.long 0x00 11. " IMR11 ,Interrupt 11 mask bit" "Masked,Not masked" bitfld.long 0x00 10. " IMR10 ,Interrupt 10 mask bit" "Masked,Not masked" bitfld.long 0x00 9. " IMR9 ,Interrupt 9 mask bit" "Masked,Not masked" newline bitfld.long 0x00 8. " IMR8 ,Interrupt 8 mask bit" "Masked,Not masked" bitfld.long 0x00 7. " IMR7 ,Interrupt 7 mask bit" "Masked,Not masked" bitfld.long 0x00 6. " IMR6 ,Interrupt 6 mask bit" "Masked,Not masked" bitfld.long 0x00 5. " IMR5 ,Interrupt 5 mask bit" "Masked,Not masked" newline bitfld.long 0x00 4. " IMR4 ,Interrupt 4 mask bit" "Masked,Not masked" bitfld.long 0x00 3. " IMR3 ,Interrupt 3 mask bit" "Masked,Not masked" bitfld.long 0x00 2. " IMR2 ,Interrupt 2 mask bit" "Masked,Not masked" bitfld.long 0x00 1. " IMR1 ,Interrupt 1 mask bit" "Masked,Not masked" newline bitfld.long 0x00 0. " IMR0 ,Interrupt 0 mask bit" "Masked,Not masked" line.long 0x04 "ISR,GPIO Interrupt Status Register" eventfld.long 0x04 31. " ISR31 ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x04 30. " ISR30 ,Interrupt 30 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 29. " ISR29 ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x04 28. " ISR28 ,Interrupt 28 status bit" "No interrupt,Interrupt" eventfld.long 0x04 27. " ISR27 ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x04 26. " ISR26 ,Interrupt 26 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 25. " ISR25 ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x04 24. " ISR24 ,Interrupt 24 status bit" "No interrupt,Interrupt" eventfld.long 0x04 23. " ISR23 ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x04 22. " ISR22 ,Interrupt 22 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 21. " ISR21 ,Interrupt 21 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 20. " ISR20 ,Interrupt 20 status bit" "No interrupt,Interrupt" eventfld.long 0x04 19. " ISR19 ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x04 18. " ISR18 ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x04 17. " ISR17 ,Interrupt 17 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 16. " ISR16 ,Interrupt 16 status bit" "No interrupt,Interrupt" eventfld.long 0x04 15. " ISR15 ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x04 14. " ISR14 ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x04 13. " ISR13 ,Interrupt 13 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 12. " ISR12 ,Interrupt 12 status bit" "No interrupt,Interrupt" eventfld.long 0x04 11. " ISR11 ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x04 10. " ISR10 ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x04 9. " ISR9 ,Interrupt 9 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 8. " ISR8 ,Interrupt 8 status bit" "No interrupt,Interrupt" eventfld.long 0x04 7. " ISR7 ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x04 6. " ISR6 ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x04 5. " ISR5 ,Interrupt 5 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 4. " ISR4 ,Interrupt 4 status bit" "No interrupt,Interrupt" eventfld.long 0x04 3. " ISR3 ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x04 2. " ISR2 ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x04 1. " ISR1 ,Interrupt 1 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 0. " ISR0 ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x08 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x08 31. " GPIO_EDGE_SEL31 ,Edge select bit 31" "0,1" bitfld.long 0x08 30. " GPIO_EDGE_SEL30 ,Edge select bit 30" "0,1" newline bitfld.long 0x08 29. " GPIO_EDGE_SEL29 ,Edge select bit 29" "0,1" bitfld.long 0x08 28. " GPIO_EDGE_SEL28 ,Edge select bit 28" "0,1" bitfld.long 0x08 27. " GPIO_EDGE_SEL27 ,Edge select bit 27" "0,1" bitfld.long 0x08 26. " GPIO_EDGE_SEL26 ,Edge select bit 26" "0,1" newline bitfld.long 0x08 25. " GPIO_EDGE_SEL25 ,Edge select bit 25" "0,1" bitfld.long 0x08 24. " GPIO_EDGE_SEL24 ,Edge select bit 24" "0,1" bitfld.long 0x08 23. " GPIO_EDGE_SEL23 ,Edge select bit 23" "0,1" bitfld.long 0x08 22. " GPIO_EDGE_SEL22 ,Edge select bit 22" "0,1" newline bitfld.long 0x08 21. " GPIO_EDGE_SEL21 ,Edge select bit 21" "0,1" newline bitfld.long 0x08 20. " GPIO_EDGE_SEL20 ,Edge select bit 20" "0,1" bitfld.long 0x08 19. " GPIO_EDGE_SEL19 ,Edge select bit 19" "0,1" bitfld.long 0x08 18. " GPIO_EDGE_SEL18 ,Edge select bit 18" "0,1" bitfld.long 0x08 17. " GPIO_EDGE_SEL17 ,Edge select bit 17" "0,1" newline bitfld.long 0x08 16. " GPIO_EDGE_SEL16 ,Edge select bit 16" "0,1" bitfld.long 0x08 15. " GPIO_EDGE_SEL15 ,Edge select bit 15" "0,1" bitfld.long 0x08 14. " GPIO_EDGE_SEL14 ,Edge select bit 14" "0,1" bitfld.long 0x08 13. " GPIO_EDGE_SEL13 ,Edge select bit 13" "0,1" newline bitfld.long 0x08 12. " GPIO_EDGE_SEL12 ,Edge select bit 12" "0,1" bitfld.long 0x08 11. " GPIO_EDGE_SEL11 ,Edge select bit 11" "0,1" bitfld.long 0x08 10. " GPIO_EDGE_SEL10 ,Edge select bit 10" "0,1" bitfld.long 0x08 9. " GPIO_EDGE_SEL9 ,Edge select bit 9" "0,1" newline bitfld.long 0x08 8. " GPIO_EDGE_SEL8 ,Edge select bit 8" "0,1" bitfld.long 0x08 7. " GPIO_EDGE_SEL7 ,Edge select bit 7" "0,1" bitfld.long 0x08 6. " GPIO_EDGE_SEL6 ,Edge select bit 6" "0,1" bitfld.long 0x08 5. " GPIO_EDGE_SEL5 ,Edge select bit 5" "0,1" newline bitfld.long 0x08 4. " GPIO_EDGE_SEL4 ,Edge select bit 4" "0,1" bitfld.long 0x08 3. " GPIO_EDGE_SEL3 ,Edge select bit 3" "0,1" bitfld.long 0x08 2. " GPIO_EDGE_SEL2 ,Edge select bit 2" "0,1" bitfld.long 0x08 1. " GPIO_EDGE_SEL1 ,Edge select bit 1" "0,1" newline bitfld.long 0x08 0. " GPIO_EDGE_SEL0 ,Edge select bit 0" "0,1" width 0x0B tree.end tree "GPIO 5" base ad:0x30240000 width 10. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High" bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High" bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High" bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High" newline bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High" bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High" bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High" bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" newline bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" newline bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" newline bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" newline bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" newline bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" newline bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" newline bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 29. " GDIR29 ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " GDIR28 ,GPIO direction 28 bit" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,GPIO direction 26 bit" "Input,Output" newline bitfld.long 0x04 25. " GDIR25 ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,GPIO direction 24 bit" "Input,Output" bitfld.long 0x04 23. " GDIR23 ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,GPIO direction 22 bit" "Input,Output" newline bitfld.long 0x04 21. " GDIR21 ,GPIO direction 21 bit" "Input,Output" newline bitfld.long 0x04 20. " GDIR20 ,GPIO direction 20 bit" "Input,Output" bitfld.long 0x04 19. " GDIR19 ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,GPIO direction 17 bit" "Input,Output" newline bitfld.long 0x04 16. " GDIR16 ,GPIO direction 16 bit" "Input,Output" bitfld.long 0x04 15. " GDIR15 ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,GPIO direction 13 bit" "Input,Output" newline bitfld.long 0x04 12. " GDIR12 ,GPIO direction 12 bit" "Input,Output" bitfld.long 0x04 11. " GDIR11 ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,GPIO direction 9 bit" "Input,Output" newline bitfld.long 0x04 8. " GDIR8 ,GPIO direction 8 bit" "Input,Output" bitfld.long 0x04 7. " GDIR7 ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,GPIO direction 5 bit" "Input,Output" newline bitfld.long 0x04 4. " GDIR4 ,GPIO direction 4 bit" "Input,Output" bitfld.long 0x04 3. " GDIR3 ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,GPIO direction 1 bit" "Input,Output" newline bitfld.long 0x04 0. " GDIR0 ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 29. " PSR29 ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " PSR28 ,GPIO pad status bit 28" "Low,High" bitfld.long 0x00 27. " PSR27 ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " PSR26 ,GPIO pad status bit 26" "Low,High" newline bitfld.long 0x00 25. " PSR25 ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " PSR24 ,GPIO pad status bit 24" "Low,High" bitfld.long 0x00 23. " PSR23 ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " PSR22 ,GPIO pad status bit 22" "Low,High" newline bitfld.long 0x00 21. " PSR21 ,GPIO pad status bit 21" "Low,High" newline bitfld.long 0x00 20. " PSR20 ,GPIO pad status bit 20" "Low,High" bitfld.long 0x00 19. " PSR19 ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,GPIO pad status bit 17" "Low,High" newline bitfld.long 0x00 16. " PSR16 ,GPIO pad status bit 16" "Low,High" bitfld.long 0x00 15. " PSR15 ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " PSR13 ,GPIO pad status bit 13" "Low,High" newline bitfld.long 0x00 12. " PSR12 ,GPIO pad status bit 12" "Low,High" bitfld.long 0x00 11. " PSR11 ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " PSR10 ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,GPIO pad status bit 9" "Low,High" newline bitfld.long 0x00 8. " PSR8 ,GPIO pad status bit 8" "Low,High" bitfld.long 0x00 7. " PSR7 ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,GPIO pad status bit 5" "Low,High" newline bitfld.long 0x00 4. " PSR4 ,GPIO pad status bit 4" "Low,High" bitfld.long 0x00 3. " PSR3 ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " PSR1 ,GPIO pad status bit 1" "Low,High" newline bitfld.long 0x00 0. " PSR0 ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x03 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR15 ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 28.--29. " ICR14 ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 26.--27. " ICR13 ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 24.--25. " ICR12 ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 22.--23. " ICR11 ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 20.--21. " ICR10 ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 18.--19. " ICR9 ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 16.--17. " ICR8 ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 14.--15. " ICR7 ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 12.--13. " ICR6 ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 10.--11. " ICR5 ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 8.--9. " ICR4 ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 6.--7. " ICR3 ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 4.--5. " ICR2 ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 2.--3. " ICR1 ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 0.--1. " ICR0 ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low level,High level,Rising edge,Falling edge" group.long 0x10++0x03 line.long 0x00 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x00 26.--27. " ICR29 ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 24.--25. " ICR28 ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 22.--23. " ICR27 ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 20.--21. " ICR26 ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 18.--19. " ICR25 ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 16.--17. " ICR24 ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 14.--15. " ICR23 ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 12.--13. " ICR22 ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 10.--11. " ICR21 ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 8.--9. " ICR20 ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 6.--7. " ICR19 ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 4.--5. " ICR18 ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x00 2.--3. " ICR17 ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low level,High level,Rising edge,Falling edge" newline bitfld.long 0x00 0.--1. " ICR16 ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low level,High level,Rising edge,Falling edge" group.long 0x14++0x0B line.long 0x00 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x00 29. " IMR29 ,Interrupt 29 mask bit" "Masked,Not masked" bitfld.long 0x00 28. " IMR28 ,Interrupt 28 mask bit" "Masked,Not masked" bitfld.long 0x00 27. " IMR27 ,Interrupt 27 mask bit" "Masked,Not masked" bitfld.long 0x00 26. " IMR26 ,Interrupt 26 mask bit" "Masked,Not masked" newline bitfld.long 0x00 25. " IMR25 ,Interrupt 25 mask bit" "Masked,Not masked" bitfld.long 0x00 24. " IMR24 ,Interrupt 24 mask bit" "Masked,Not masked" bitfld.long 0x00 23. " IMR23 ,Interrupt 23 mask bit" "Masked,Not masked" bitfld.long 0x00 22. " IMR22 ,Interrupt 22 mask bit" "Masked,Not masked" newline bitfld.long 0x00 21. " IMR21 ,Interrupt 21 mask bit" "Masked,Not masked" newline bitfld.long 0x00 20. " IMR20 ,Interrupt 20 mask bit" "Masked,Not masked" bitfld.long 0x00 19. " IMR19 ,Interrupt 19 mask bit" "Masked,Not masked" bitfld.long 0x00 18. " IMR18 ,Interrupt 18 mask bit" "Masked,Not masked" bitfld.long 0x00 17. " IMR17 ,Interrupt 17 mask bit" "Masked,Not masked" newline bitfld.long 0x00 16. " IMR16 ,Interrupt 16 mask bit" "Masked,Not masked" bitfld.long 0x00 15. " IMR15 ,Interrupt 15 mask bit" "Masked,Not masked" bitfld.long 0x00 14. " IMR14 ,Interrupt 14 mask bit" "Masked,Not masked" bitfld.long 0x00 13. " IMR13 ,Interrupt 13 mask bit" "Masked,Not masked" newline bitfld.long 0x00 12. " IMR12 ,Interrupt 12 mask bit" "Masked,Not masked" bitfld.long 0x00 11. " IMR11 ,Interrupt 11 mask bit" "Masked,Not masked" bitfld.long 0x00 10. " IMR10 ,Interrupt 10 mask bit" "Masked,Not masked" bitfld.long 0x00 9. " IMR9 ,Interrupt 9 mask bit" "Masked,Not masked" newline bitfld.long 0x00 8. " IMR8 ,Interrupt 8 mask bit" "Masked,Not masked" bitfld.long 0x00 7. " IMR7 ,Interrupt 7 mask bit" "Masked,Not masked" bitfld.long 0x00 6. " IMR6 ,Interrupt 6 mask bit" "Masked,Not masked" bitfld.long 0x00 5. " IMR5 ,Interrupt 5 mask bit" "Masked,Not masked" newline bitfld.long 0x00 4. " IMR4 ,Interrupt 4 mask bit" "Masked,Not masked" bitfld.long 0x00 3. " IMR3 ,Interrupt 3 mask bit" "Masked,Not masked" bitfld.long 0x00 2. " IMR2 ,Interrupt 2 mask bit" "Masked,Not masked" bitfld.long 0x00 1. " IMR1 ,Interrupt 1 mask bit" "Masked,Not masked" newline bitfld.long 0x00 0. " IMR0 ,Interrupt 0 mask bit" "Masked,Not masked" line.long 0x04 "ISR,GPIO Interrupt Status Register" eventfld.long 0x04 29. " ISR29 ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x04 28. " ISR28 ,Interrupt 28 status bit" "No interrupt,Interrupt" eventfld.long 0x04 27. " ISR27 ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x04 26. " ISR26 ,Interrupt 26 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 25. " ISR25 ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x04 24. " ISR24 ,Interrupt 24 status bit" "No interrupt,Interrupt" eventfld.long 0x04 23. " ISR23 ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x04 22. " ISR22 ,Interrupt 22 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 21. " ISR21 ,Interrupt 21 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 20. " ISR20 ,Interrupt 20 status bit" "No interrupt,Interrupt" eventfld.long 0x04 19. " ISR19 ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x04 18. " ISR18 ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x04 17. " ISR17 ,Interrupt 17 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 16. " ISR16 ,Interrupt 16 status bit" "No interrupt,Interrupt" eventfld.long 0x04 15. " ISR15 ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x04 14. " ISR14 ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x04 13. " ISR13 ,Interrupt 13 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 12. " ISR12 ,Interrupt 12 status bit" "No interrupt,Interrupt" eventfld.long 0x04 11. " ISR11 ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x04 10. " ISR10 ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x04 9. " ISR9 ,Interrupt 9 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 8. " ISR8 ,Interrupt 8 status bit" "No interrupt,Interrupt" eventfld.long 0x04 7. " ISR7 ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x04 6. " ISR6 ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x04 5. " ISR5 ,Interrupt 5 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 4. " ISR4 ,Interrupt 4 status bit" "No interrupt,Interrupt" eventfld.long 0x04 3. " ISR3 ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x04 2. " ISR2 ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x04 1. " ISR1 ,Interrupt 1 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 0. " ISR0 ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x08 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x08 29. " GPIO_EDGE_SEL29 ,Edge select bit 29" "0,1" bitfld.long 0x08 28. " GPIO_EDGE_SEL28 ,Edge select bit 28" "0,1" bitfld.long 0x08 27. " GPIO_EDGE_SEL27 ,Edge select bit 27" "0,1" bitfld.long 0x08 26. " GPIO_EDGE_SEL26 ,Edge select bit 26" "0,1" newline bitfld.long 0x08 25. " GPIO_EDGE_SEL25 ,Edge select bit 25" "0,1" bitfld.long 0x08 24. " GPIO_EDGE_SEL24 ,Edge select bit 24" "0,1" bitfld.long 0x08 23. " GPIO_EDGE_SEL23 ,Edge select bit 23" "0,1" bitfld.long 0x08 22. " GPIO_EDGE_SEL22 ,Edge select bit 22" "0,1" newline bitfld.long 0x08 21. " GPIO_EDGE_SEL21 ,Edge select bit 21" "0,1" newline bitfld.long 0x08 20. " GPIO_EDGE_SEL20 ,Edge select bit 20" "0,1" bitfld.long 0x08 19. " GPIO_EDGE_SEL19 ,Edge select bit 19" "0,1" bitfld.long 0x08 18. " GPIO_EDGE_SEL18 ,Edge select bit 18" "0,1" bitfld.long 0x08 17. " GPIO_EDGE_SEL17 ,Edge select bit 17" "0,1" newline bitfld.long 0x08 16. " GPIO_EDGE_SEL16 ,Edge select bit 16" "0,1" bitfld.long 0x08 15. " GPIO_EDGE_SEL15 ,Edge select bit 15" "0,1" bitfld.long 0x08 14. " GPIO_EDGE_SEL14 ,Edge select bit 14" "0,1" bitfld.long 0x08 13. " GPIO_EDGE_SEL13 ,Edge select bit 13" "0,1" newline bitfld.long 0x08 12. " GPIO_EDGE_SEL12 ,Edge select bit 12" "0,1" bitfld.long 0x08 11. " GPIO_EDGE_SEL11 ,Edge select bit 11" "0,1" bitfld.long 0x08 10. " GPIO_EDGE_SEL10 ,Edge select bit 10" "0,1" bitfld.long 0x08 9. " GPIO_EDGE_SEL9 ,Edge select bit 9" "0,1" newline bitfld.long 0x08 8. " GPIO_EDGE_SEL8 ,Edge select bit 8" "0,1" bitfld.long 0x08 7. " GPIO_EDGE_SEL7 ,Edge select bit 7" "0,1" bitfld.long 0x08 6. " GPIO_EDGE_SEL6 ,Edge select bit 6" "0,1" bitfld.long 0x08 5. " GPIO_EDGE_SEL5 ,Edge select bit 5" "0,1" newline bitfld.long 0x08 4. " GPIO_EDGE_SEL4 ,Edge select bit 4" "0,1" bitfld.long 0x08 3. " GPIO_EDGE_SEL3 ,Edge select bit 3" "0,1" bitfld.long 0x08 2. " GPIO_EDGE_SEL2 ,Edge select bit 2" "0,1" bitfld.long 0x08 1. " GPIO_EDGE_SEL1 ,Edge select bit 1" "0,1" newline bitfld.long 0x08 0. " GPIO_EDGE_SEL0 ,Edge select bit 0" "0,1" width 0x0B tree.end tree.end tree.end tree.open "External Memory" tree "DDRC (DDR Controller)" base ad:0x3DC00000 width 18. if (((per.l(ad:0x3DC00000+0xC4))&0x1)==0x1) group.long 0x00++0x03 line.long 0x00 "MSTR,Master Register 0" bitfld.long 0x00 30.--31. " DEVICE_CONFIG ,Configuration of the device" "x4,x8,x16,x32" bitfld.long 0x00 29. " FREQUENCY_MODE ,Frequency mode" "Original,Shadow" textline " " bitfld.long 0x00 24.--25. " ACTIVE_RANKS ,Active ranks" "One,Two,?..." bitfld.long 0x00 22. " FREQUENCY_RATIO ,Frequency ratio" "1:2,1:1" textline " " bitfld.long 0x00 16.--19. " BURST_RDWR ,SDRAM burst length" "2,4,8,16,?..." bitfld.long 0x00 12.--13. " DATA_BUS_WIDTH ,Data bus width" "Full,Half,Quarter,?..." textline " " bitfld.long 0x00 11. " GEARDOWN_MODE ,Geardown mode" "0,1" bitfld.long 0x00 10. " EN_2T_TIMING_MODE ,Enable 2T timing mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " BURSTCHOP ,Burstchop" "Disabled,Enabled" bitfld.long 0x00 5. " LPDDR4 ,Select LPDDR4 SDRAM" "LPDDR4,non-LPDDR4" textline " " bitfld.long 0x00 4. " DDR4 ,Select DDR4 SDRAM" "DDR4,non-DDR4" bitfld.long 0x00 3. " LPDDR3 ,Select LPDDR3 SDRAM" "LPDDR3,non-LPDDR3" textline " " bitfld.long 0x00 0. " DDR3 ,Select DDR3 SDRAM" "DDR3,non-DDR3" else group.long 0x00++0x03 line.long 0x00 "MSTR,Master Register 0" bitfld.long 0x00 30.--31. " DEVICE_CONFIG ,Configuration of the device" "x4,x8,x16,x32" bitfld.long 0x00 29. " FREQUENCY_MODE ,Frequency mode" "Original,Shadow" textline " " bitfld.long 0x00 24.--25. " ACTIVE_RANKS ,Active ranks" "One,Two,?..." bitfld.long 0x00 22. " FREQUENCY_RATIO ,Frequency ratio" "1:2,1:1" textline " " bitfld.long 0x00 16.--19. " BURST_RDWR ,SDRAM burst length" "2,4,8,16,?..." bitfld.long 0x00 15. " DLL_OFF_MODE ,DLL off mode" "0,1" textline " " bitfld.long 0x00 12.--13. " DATA_BUS_WIDTH ,Data bus width" "Full,Half,Quarter,?..." bitfld.long 0x00 11. " GEARDOWN_MODE ,Geardown mode" "0,1" textline " " bitfld.long 0x00 10. " EN_2T_TIMING_MODE ,Enable 2T timing mode" "Disabled,Enabled" bitfld.long 0x00 9. " BURSTCHOP ,Burstchop" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " LPDDR4 ,Select LPDDR4 SDRAM" "non-LPDDR4,LPDDR4" bitfld.long 0x00 4. " DDR4 ,Select DDR4 SDRAM" "non-DDR4,DDR4" textline " " bitfld.long 0x00 3. " LPDDR3 ,Select LPDDR3 SDRAM" "non-LPDDR3,LPDDR3" bitfld.long 0x00 0. " DDR3 ,Select DDR3 SDRAM" "non-DDR3,DDR3" endif textline " " rgroup.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" bitfld.long 0x00 8.--9. " SELFREF_STATE ,Selfref state" "SDRAM,Self refresh 1,Self refresh power down,Self refresh" bitfld.long 0x00 4.--5. " SELFREF_TYPE ,Selfref type" "Not selref,,Not automatic selref,Automatic selref" textline " " bitfld.long 0x00 0.--2. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self refresh,Deep power-down,?..." if ((per.l(ad:0x3DC00000)&0x10)==0x10) group.long 0x10++0x07 line.long 0x00 "MRCTRL0,Mode Register Read/Write Control Register 0" bitfld.long 0x00 31. " MR_WR ,MR_WR" "0,1" bitfld.long 0x00 30. " PBA_MODE ,PBA mode" "DRAM,Buffer" textline " " bitfld.long 0x00 12.--15. " MR_ADDR ,Address of the mode register" "MR0,MR1,MR2,MR3,MR4,MR5,MR6,MR7,?..." bitfld.long 0x00 4.--5. " MR_RANK ,Rank of mode register" "0,1,2,3" textline " " bitfld.long 0x00 3. " SW_INIT_INT ,Software init int" "Not allowed,Allowed" bitfld.long 0x00 2. " PDA_EN ,PDA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MPR_EN ,MPR enable" "Disabled,Enabled" bitfld.long 0x00 0. " MR_TYPE ,Type of mode register" "Write,Read" line.long 0x04 "MRCTRL1,Mode Register Read/Write Control Register 1" hexmask.long.tbyte 0x04 0.--17. 0x01 " MR_DATA ,Data of mode register" else group.long 0x10++0x07 line.long 0x00 "MRCTRL0,Mode Register Read/Write Control Register 0" bitfld.long 0x00 31. " MR_WR ,MR_WR" "0,1" bitfld.long 0x00 30. " PBA_MODE ,PBA mode" "DRAM,Buffer" textline " " bitfld.long 0x00 12.--15. " MR_ADDR ,Address of the mode register" "MR0,MR1,MR2,MR3,MR4,MR5,MR6,MR7,?..." bitfld.long 0x00 4.--5. " MR_RANK ,Rank of mode register" "0,1,2,3" textline " " bitfld.long 0x00 3. " SW_INIT_INT ,Software init int" "Not allowed,Allowed" bitfld.long 0x00 2. " PDA_EN ,PDA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MR_TYPE ,Type of mode register" "Write,Read" line.long 0x04 "MRCTRL1,Mode Register Read/Write Control Register 1" hexmask.long.tbyte 0x04 0.--17. 0x01 " MR_DATA ,Data of mode register" endif rgroup.long 0x18++0x03 line.long 0x00 "MRSTAT,Mode Register Read/Write Status Register" bitfld.long 0x00 8. " PDA_DONE ,PDA done" "In progress,Completed" bitfld.long 0x00 0. " MR_WR_BUSY ,Busy write of mode register" "0,1" group.long 0x1C++0x0B line.long 0x00 "MRCTRL2,Mode Register Read/Write Control Register 2" line.long 0x04 "DERATEEN,Temperature Derate Enable Register" bitfld.long 0x04 8.--9. " RC_DERATE_VALUE ,RC derate value" "+1,+2,+3,+4" bitfld.long 0x04 4.--7. " DERATE_BYTE ,Derate byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 1. " DERATE_VALUE ,Derate value" "+1,+2" bitfld.long 0x04 0. " DERATE_ENABLE ,Derate enable" "Disabled,Enabled" line.long 0x08 "DERATEINT,Temperature Derate Interval Register" group.long 0x30++0x0B line.long 0x00 "PWRCTL,Low Power Control Register" bitfld.long 0x00 6. " STAY_IN_SELFREF ,Self refresh state" "Prohibited,Allowed" bitfld.long 0x00 5. " SELFREF_SW ,Software self refresh" "Exit,Entry" textline " " bitfld.long 0x00 4. " MPSM_EN ,MPSM enable" "Disabled,Enabled" bitfld.long 0x00 3. " EN_DFI_DRAM_CLK_DISABLE ,Enable the assertion of DFI_DRAM_CLK_DISABLE" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " DEEPPOWERDOWN_EN ,Deep power down enable" "Disabled,Enabled" bitfld.long 0x00 1. " POWERDOWN_EN ,Power down enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SELFREF_EN ,Self refresh enable" "Disabled,Enabled" line.long 0x04 "PWRTMG,Low Power Timing Register" hexmask.long.byte 0x04 16.--23. 1. " SELFREF_TO_X32 ,Self refresh to x32" hexmask.long.byte 0x04 8.--15. 1. " T_DPD_X4096 ,T_DPD_X4096" textline " " bitfld.long 0x04 0.--4. " POWERDOWN_TO_X32 ,Power down to x32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "HWLPCTL,Hardware Low Power Control Register" hexmask.long.word 0x08 16.--27. 1. " HW_LP_IDLE_X32 ,Hardware idle period" bitfld.long 0x08 1. " HW_LP_EXIT_IDLE_EN ,Hardware low power idle exit enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " HW_LP_EN ,Enable for Hardware Low Power Interface" "Disabled,Enabled" group.long 0x50++0x07 line.long 0x00 "RFSHCTL0,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Refresh margin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Refresh to x32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 4.--8. " REFRESH_BURST ,Refresh burst" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " PER_BANK_REFRESH ,Per bank refresh" "Per,All" line.long 0x04 "RFSHCTL1,Refresh Control Register 1" hexmask.long.word 0x04 16.--27. 1. " REFRESH_TIMER1_START_VALUE_X32 ,Refresh timer 1 start value x32" hexmask.long.word 0x04 0.--11. 1. " REFRESH_TIMER0_START_VALUE_X32 ,Refresh timer0 start value_x32" if (((per.l(ad:0x3DC00000))&0x10)==0x1) group.long 0x60++0x03 line.long 0x00 "RFSHCTL3,Refresh Control Register 3" bitfld.long 0x00 4.--6. " REFRESH_MODE ,Refresh mode" "Normal,Fixed 2x,Fixed 4x,,,Enable on the fly 2x,Enable on the fly 4x,?..." bitfld.long 0x00 1. " REFRESH_UPDATE_LEVEL ,Refresh update level" "0,1" textline " " bitfld.long 0x00 0. " DIS_AUTO_REFRESH ,Disable auto refresh" "No,Yes" else group.long 0x60++0x03 line.long 0x00 "RFSHCTL3,Refresh Control Register 3" bitfld.long 0x00 1. " REFRESH_UPDATE_LEVEL ,Refresh update level" "0,1" bitfld.long 0x00 0. " DIS_AUTO_REFRESH ,Disable auto refresh" "No,Yes" endif group.long 0x64++0x03 line.long 0x00 "RFSHTMG,Refresh Timing Register" hexmask.long.word 0x00 16.--27. 1. " T_RFC_NOM_X32 ,t_rfc_nom_x32" bitfld.long 0x00 15. " LPDDR3_TREFBW_EN ,LPDDR3 trefbw enable" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--9. 1. " T_RFC_MIN ,tRFC min" group.long 0xC0++0x07 line.long 0x00 "CRCPARCTL0,CRC Parity Control Register 0" bitfld.long 0x00 2. " DFI_ALERT_ERR_CNT_CLR ,DFI alert error count clear" "No clear,Clear" bitfld.long 0x00 1. " DFI_ALERT_ERR_INT_CLR ,Interrupt clear bit for DFI alert error" "No clear,Clear" textline " " bitfld.long 0x00 0. " DFI_ALERT_ERR_INT_EN ,Interrupt enable bit for DFI alert error" "Disabled,Enabled" line.long 0x04 "CRCPARCTL1,CRC Parity Control Register 1" bitfld.long 0x04 12. " CAPARITY_DISABLE_BEFORE_SR ,Caparity disable before sr" "No,Yes" bitfld.long 0x04 7. " CRC_INC_DM ,CRC Calculation setting register" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " CRC_ENABLE ,CRC enable Register" "Disabled,Enabled" bitfld.long 0x04 0. " PARITY_ENABLE ,C/A Parity enable register" "Disabled,Enabled" rgroup.long 0xCC++0x03 line.long 0x00 "CRCPARSTAT,CRC Parity Status Register" bitfld.long 0x00 16. " DFI_ALERT_ERR_INT ,DFI alert error interrupt" "Not interrupt,Interrupt" hexmask.long.word 0x00 0.--15. 1. " DFI_ALERT_ERR_CNT ,DFI alert error counter" group.long 0xD0++0x27 line.long 0x00 "INIT0,SDRAM Initialization Register 0" bitfld.long 0x00 30.--31. " SKIP_DRAM_INIT ,Skip SDRAM initialization" "Run after power-up,Skipped after power-up,Run after power-up,Skipped after power-up" hexmask.long.word 0x00 16.--25. 1. " POST_CKE_X1024 ,POST_CKE_X1024" textline " " hexmask.long.word 0x00 0.--11. 1. " PRE_CKE_X1024 ,PRE_CKE_X1024" line.long 0x04 "INIT1,SDRAM Initialization Register 1" hexmask.long.word 0x04 16.--24. 1. " DRAM_RSTN_X1024 ,DRAM_RSTN_X1024" bitfld.long 0x04 0.--4. " PRE_OCD_X32 ,PRE OCD x32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "INIT2,SDRAM Initialization Register 2" hexmask.long.byte 0x08 8.--15. 1. " IDLE_AFTER_RESET_X32 ,Idle time after the reset command" bitfld.long 0x08 0.--3. " MIN_STABLE_CLOCK_X1 ,Min stable clock x1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "INIT3,SDRAM Initialization Register 3" hexmask.long.word 0x0C 16.--31. 1. " MR ,Value to write to MR register" hexmask.long.word 0x0C 0.--15. 1. " EMR ,Value to write to EMR register" line.long 0x10 "INIT4,SDRAM Initialization Register 4" hexmask.long.word 0x10 16.--31. 1. " EMR2 ,Value to write to EMR2 register" hexmask.long.word 0x10 0.--15. 1. " EMR3 ,Value to write to EMR3 register" line.long 0x14 "INIT5,SDRAM Initialization Register 5" hexmask.long.byte 0x14 16.--23. 1. " DEV_ZQINIT_X32 ,ZQ initial calibration" hexmask.long.word 0x14 0.--9. 1. " MAX_AUTO_INIT_X1024 ,Maximum duration of the auto initialization" line.long 0x18 "INIT6,SDRAM Initialization Register 6" hexmask.long.word 0x18 16.--31. 1. " MR4 ,Value to write to MR4 register" hexmask.long.word 0x18 0.--15. 1. " MR5 ,Value to write to MR5 register" line.long 0x1C "INIT7,SDRAM Initialization Register 7" hexmask.long.word 0x1C 16.--31. 1. " MR6 ,Value to write to MR6 register" line.long 0x20 "DIMMCTL,DIMM Control Register" bitfld.long 0x20 6. " LRDIMM_BCOM_CMD_PROT ,LRDIMM_BCOM_CMD_PROT" "0,1" bitfld.long 0x20 5. " DIMM_DIS_BG_MIRRORING ,Disabling address mirroring for BG bits" "No,Yes" textline " " bitfld.long 0x20 4. " MRS_BG1_EN ,Enable for BG1 bit of MRS command" "Disabled,Enabled" bitfld.long 0x20 3. " MRS_A17_EN ,Enable for A17 bit of MRS command" "Disabled,Enabled" textline " " bitfld.long 0x20 2. " DIMM_OUTPUT_INV_EN ,Output inversion enable" "Disabled,Enabled" bitfld.long 0x20 1. " DIMM_ADDR_MIRR_EN ,Address mirroring enable" "Disabled,Enabled" textline " " bitfld.long 0x20 0. " DIMM_STAGGER_CS_EN ,Staggering enable for multi-rank accesses" "Disabled,Enabled" line.long 0x24 "RANKCTL,Rank Control Register" bitfld.long 0x24 8.--11. " DIFF_RANK_WR_GAP ,Diff rank write gap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x24 4.--7. " DIFF_RANK_RD_GAP ,Diff rank read gap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x24 0.--3. " MAX_RANK_RD ,Max read rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x3F line.long 0x00 "DRAMTMG0,SDRAM Timing Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR2PRE ,Write 2 precharge" bitfld.long 0x00 16.--21. " T_FAW ,tFAW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x00 8.--14. 1. " T_RAS_MAX ,tRAS max" bitfld.long 0x00 0.--5. " T_RAS_MIN ,tRAS min" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DRAMTMG1,SDRAM Timing Register 1" bitfld.long 0x04 16.--20. " T_XP ,tXP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--13. " RD2PRE ,tRTP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x04 0.--6. 1. " T_RC ,tRC" line.long 0x08 "DRAMTMG2,SDRAM Timing Register 2" bitfld.long 0x08 24.--29. " WRITE_LATENCY ,Write latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " READ_LATENCY ,Read latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x08 8.--13. " RD2WR ,Minimum time from read command to write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " WR2RD ,Minimum time from write command to read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "DRAMTMG3,SDRAM Timing Register 3" hexmask.long.word 0x0C 20.--29. 1. " T_MRW ,Time to wait after a mode register write or read" bitfld.long 0x0C 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0C 0.--9. 1. " T_MOD ,Cycles between loadmode command and following non-load mode command" line.long 0x10 "DRAMTMG4,SDRAM Timing Register 4" bitfld.long 0x10 24.--28. " T_RCD ,Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 16.--19. " T_CCD ,Minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 8.--11. " T_RRD ,Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--4. " T_RP ,Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "DRAMTMG5,SDRAM Timing Register 5" bitfld.long 0x14 24.--27. " T_CKSRX ,Time before self refresh exit that CK is maintained as a valid clock before issuing SRX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 16.--19. " T_CKSRE ,Time after self refresh down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x14 8.--13. " T_CKESR ,Minimum CKE low width for self refresh entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 0.--4. " T_CKE ,Minimum number of cycles of CKE HIGH / LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "DRAMTMG6,SDRAM Timing Register 6" bitfld.long 0x18 24.--27. " T_CKDPDE ,Time after Deep Power Down Entry that CK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 16.--19. " T_CKDPDX ,Time before Deep Power Down Exit that CK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x18 0.--3. " T_CKCSX ,Time before Clock Stop Exit that CK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "DRAMTMG7,SDRAM Timing Register 7" bitfld.long 0x1C 8.--11. " T_CKPDE ,Time after Power Down Entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " T_CKPDX ,Time before power down exit that CK is maintained as a valid clock before issuing PDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "DRAMTMG8,SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. " T_XS_FAST_X32 ,Exit Self Refresh to ZQCL, ZQCS and MRS" hexmask.long.byte 0x20 16.--22. 1. " T_XS_ABORT_X32 ,Exit Self Refresh to commands not requiring a locked DLL in self refresh abort" textline " " hexmask.long.byte 0x20 8.--14. 1. " T_XS_DLL_X32 ,Exit self refresh to commands requiring a locked DLL" hexmask.long.byte 0x20 0.--6. 1. " T_XS_X32 ,Exit self refresh to commands not requiring a locked DLL" line.long 0x24 "DRAMTMG9,SDRAM Timing Register 9" bitfld.long 0x24 30. " DDR4_WR_PREAMBLE ,DDR4 Write preamble mode" "1tCK,2tCK" bitfld.long 0x24 16.--18. " T_CCD_S ,This is the minimum time between two reads or two writes for different bank group" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x24 8.--11. " T_RRD_S ,Minimum time between activates from bank a to bank b for different bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x24 0.--5. " WR2RD_S ,Minimum time from write command to read command for different bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "DRAMTMG10,SDRAM Timing Register 10" bitfld.long 0x28 16.--20. " T_SYNC_GEAR ,Time sync gear" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 8.--12. " T_CMD_GEAR ,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x28 2.--3. " T_GEAR_SETUP ,Geardown setup time" ",1,2,3" bitfld.long 0x28 0.--1. " T_GEAR_HOLD ,Geardown hold time" ",1,2,3" line.long 0x2C "DRAMTMG11,SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. " POST_MPSM_GAP_X32 ,Minimum Exit MPSM to commands requiring a locked DLL" bitfld.long 0x2C 16.--20. " T_MPX_LH ,Minimum CS_n Low hold time to CKE rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x2C 8.--9. " T_MPX_S ,Minimum time CS setup time to CKE" "0,1,2,3" bitfld.long 0x2C 0.--4. " T_CKMPE ,Minimum valid clock requirement after MPSM entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "DRAMTMG12,SDRAM Timing Register 12" bitfld.long 0x30 16.--17. " T_CMDCKE ,Delay from valid command to CKE input LOW" "0,1,2,3" bitfld.long 0x30 8.--11. " T_CKEHCMD ,Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x30 0.--4. " T_MRD_PDA ,This is the mode register set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "DRAMTMG13,SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. " ODTLOFF ,tODTLoff" bitfld.long 0x34 16.--21. " T_CCD_MW ,Minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x34 0.--2. " T_PPD ,Minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7" line.long 0x38 "DRAMTMG14,SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. " T_XSR ,Exit self refresh to any command" line.long 0x3C "DRAMTMG15,SDRAM Timing Register 15" bitfld.long 0x3C 31. " EN_DFI_LP_T_STAB ,Enable DFI tSTAB" "Disabled,Enabled" hexmask.long.byte 0x3C 0.--7. 1. " T_STAB_X32 ,Stabilization time" group.long 0x180++0x0B line.long 0x00 "ZQCTL0,ZQ Control Register 0" bitfld.long 0x00 31. " DIS_AUTO_ZQ ,Disable Auto ZQCS/MPC" "No,Yes" bitfld.long 0x00 30. " DIS_SRX_ZQCL ,Disable ZQCL/MPC" "No,Yes" textline " " bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED ,ZQ resistor sharing" "Not shared,Shared" bitfld.long 0x00 28. " DIS_MPSMX_ZQCL ,Disable issuing of ZQCL command at Maximum Power Saving Mode exit" "No,Yes" textline " " hexmask.long.word 0x00 16.--26. 1. " T_ZQ_LONG_NOP ,T_ZQ_LONG_NOP" hexmask.long.word 0x00 0.--9. 1. " T_ZQ_SHORT_NOP ,T_ZQ_LONG_NOP" line.long 0x04 "ZQCTL1,ZQ Control Register 1" hexmask.long.word 0x04 20.--29. 1. " T_ZQ_RESET_NOP ,Number of cycles of NOP required after a ZQReset" hexmask.long.tbyte 0x04 0.--19. 1. " T_ZQ_SHORT_INTERVAL_X1024 ,Average interval to wait between automatically issuing ZQCS" line.long 0x08 "ZQCTL2,ZQ Control Register 2" bitfld.long 0x08 0. " ZQ_RESET ,ZQ Reset" "No reset,Reset" rgroup.long 0x18C++0x03 line.long 0x00 "ZQSTAT,ZQ Status Register" bitfld.long 0x00 0. " ZQ_RESET_BUSY ,ZQ reset busy" "SoC core initiate,In progress" group.long 0x190++0x1B line.long 0x00 "DFITMG0,DFI Timing Register 0" bitfld.long 0x00 24.--28. " DFI_T_CTRL_DELAY ,Specifies the number of DFI clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " DFI_RDDATA_USE_SDR ,DFI_RDDATA_USE_SDR" "HDR,SDR" textline " " hexmask.long.byte 0x00 16.--22. 1. " DFI_T_RDDATA_EN ,Time from the assertion of a read command on the DFI interface to the assertion of the DFI_RDDATA_EN signal" bitfld.long 0x00 15. " DFI_WRDATA_USE_SDR ,DFI_WRDATA_USE_SDR" "HDR,SDR" textline " " bitfld.long 0x00 8.--13. " DFI_TPHY_WRDATA ,Specifies the number of clock cycles between when DFI_WRDATA_EN is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DFI_TPHY_WRLAT ,Number of clocks from the write command to write data enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG1,DFI Timing Register 1" bitfld.long 0x04 28.--31. " DFI_T_CMD_LAT ,Specifies the number of DFI PHY clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24.--25. " DFI_T_PARIN_LAT ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted" "0,1,2,3" textline " " bitfld.long 0x04 16.--20. " DFI_T_WRDATA_DELAY ,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " DFI_T_DRAM_CLK_DISABLE ,DFI_T_DRAM_CLK_DISABLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 0.--4. " DFI_T_DRAM_CLK_ENABLE ,DFI_T_DRAM_CLK_ENABLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "DFILPCFG0,DFI Low Power Configuration Register 0" bitfld.long 0x08 24.--28. " DFI_TLP_RESP ,DFI_TLP_RESP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 12.--15. " DFI_LP_WAKEUP_SR ,DFI LP WAKEUP SR" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" textline " " bitfld.long 0x08 8. " DFI_LP_EN_SR ,Enables DFI low power interface handshaking during self refresh entry/exit" "Disabled,Enabled" bitfld.long 0x08 4.--7. " DFI_LP_WAKEUP_PD ,Value to drive on dfi_lp_wakeup signal when Power Down mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" textline " " bitfld.long 0x08 0. " DFI_LP_EN_PD ,Enables DFI low power interface handshaking during power down entry/exit" "Disabled,Enabled" line.long 0x0C "DFILPCFG1,DFI Low Power Configuration Register 1" bitfld.long 0x0C 4.--7. " DFI_LP_WAKEUP_MPSM ,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,655536,131072,262144,Unlimited" bitfld.long 0x0C 0. " DFI_LP_EN_MPSM ,Enables DFI low power interface handshaking during maximum power saving mode entry/exit" "Disabled,Enabled" line.long 0x10 "DFIUPD0,DFI Update Register 0" bitfld.long 0x10 31. " DIS_AUTO_CTRLUPD ,Disables the automatic dfi_ctrlupd_req generation by the DDRC" "No,Yes" bitfld.long 0x10 30. " DIS_AUTO_CTRLUPD_SRX ,Disables the automatic dfi_ctrlupd_req generation by the DDRC following a self-refresh exit" "No,Yes" textline " " bitfld.long 0x10 29. " CTRLUPD_PRE_SRX ,Selects dfi_ctrlupd_req requirements at SRX" "After SRX,Before SRX" hexmask.long.word 0x10 16.--25. 1. " DFI_T_CTRLUP_MAX ,Specifies the maximum number of clock cycles that the dfi_ctrlupd_req signal can assert" textline " " hexmask.long.word 0x10 0.--9. 1. " DFI_T_CTRLUP_MIN ,Specifies the minimum number of clock cycles that the dfi_ctrlupd_req signal must be asserted" line.long 0x14 "DFIUPD1,DFI Update Register 1" hexmask.long.byte 0x14 16.--23. 1. " DFI_T_CTRLUPD_INTERVAL_MIN_X1024 ,The minimum amount of time between DDRC initiated DFI update requests" hexmask.long.byte 0x14 0.--7. 1. " DFI_T_CTRLUPD_INTERVAL_MAX_X1024 ,The maximum amount of time between DDRC initiated DFI update requests" line.long 0x18 "DFIUPD2,DFI Update Register 2" bitfld.long 0x18 31. " DFI_PHYUPD_EN ,Enables the support for acknowledging PHY- initiated updates" "Disabled,Enabled" group.long 0x1B0++0x0B line.long 0x00 "DFIMISC,DFI Miscellaneous Control Register" bitfld.long 0x00 8.--12. " DFI_FREQUENCY ,Indicates the operating frequency of the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DFI_INIT_START ,PHY init start request signal" "Not started,Started" textline " " bitfld.long 0x00 4. " CTL_IDLE_EN ,Enables support of ctl_idle signal" "Disabled,Enabled" bitfld.long 0x00 2. " DFI_DATA_CS_POLARITY ,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals" "Low,High" textline " " bitfld.long 0x00 1. " PHY_DBI_MODE ,DBI implemented in DDRC or PHY" "DDRC,PHY" bitfld.long 0x00 0. " DFI_INIT_COMPLETE_EN ,PHY initialization complete enable signal" "Disabled,Enabled" line.long 0x04 "DFITMG2,DFI Timing Register 2" hexmask.long.byte 0x04 8.--14. 1. " DFI_TPHY_RDCSLAT ,Number of DFI PHY clock cycles between when a read command is sent" bitfld.long 0x04 0.--5. " DFI_TPHY_WRCSLAT ,Number of DFI PHY clock cycles between when a write command is sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DFITMG3,DFI Timing Register 3" bitfld.long 0x08 0.--4. " DFI_T_GEARDOWN_DELAY ,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1BC++0x03 line.long 0x00 "DFISTAT,DFI Status Register" bitfld.long 0x00 1. " DFI_LP_ACK ,Stores the value of the dfi_lp_ack input to the controller" "0,1" bitfld.long 0x00 0. " DFI_INIT_COMPLETE ,The status flag register which announces when the DFI initialization has been completed" "Not completed,Completed" group.long 0x1C0++0x03 line.long 0x00 "DBICTL,DM/DBI Control Register" bitfld.long 0x00 2. " RD_DBI_EN ,Read DBI enable signal in DDRC" "Disabled,Enabled" bitfld.long 0x00 1. " WR_DBI_EN ,Write DBI enable signal in DDRC" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DM_EN ,DM enable signal in DDRC" "Disabled,Enabled" group.long 0x200++0x2F line.long 0x00 "ADDRMAP0,Address Map Register 0" bitfld.long 0x00 0.--4. " ADDRMAP_CS_BIT0 ,Adress map CS B0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "ADDRMAP1,Address Map Register 1" bitfld.long 0x04 16.--20. " ADDRMAP_BANK_B2 ,Adress map bank B2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " ADDRMAP_BANK_B1 ,Adress map bank B1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 0.--4. " ADDRMAP_BANK_B0 ,Adress map bank B0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "ADDRMAP2,Address Map Register 2" bitfld.long 0x08 24.--27. " ADDRMAP_COL_B5 ,Adress map column B5" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x08 16.--19. " ADDRMAP_COL_B4 ,Adress map column B4" "0,1,2,3,4,5,6,7,,,,,,,,15" textline " " bitfld.long 0x08 8.--11. " ADDRMAP_COL_B3 ,Adress map column B3" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x08 0.--3. " ADDRMAP_COL_B2 ,Adress map column B2" "0,1,2,3,4,5,6,7,?..." line.long 0x0C "ADDRMAP3,Address Map Register 3" bitfld.long 0x0C 24.--27. " ADDRMAP_COL_B9 ,Adress map column B9" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x0C 16.--19. " ADDRMAP_COL_B8 ,Adress map column B8" "0,1,2,3,4,5,6,7,,,,,,,,15" textline " " bitfld.long 0x0C 8.--11. " ADDRMAP_COL_B7 ,Adress map column B7" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x0C 0.--3. " ADDRMAP_COL_B6 ,Adress map column B6" "0,1,2,3,4,5,6,7,,,,,,,,15" line.long 0x10 "ADDRMAP4,Address Map Register 4" bitfld.long 0x10 8.--11. " ADDRMAP_COL_B11 ,Adress map column B11" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x10 0.--3. " ADDRMAP_COL_B10 ,Adress map column B10" "0,1,2,3,4,5,6,7,,,,,,,,15" line.long 0x14 "ADDRMAP5,Address Map Register 5" bitfld.long 0x14 24.--27. " ADDRMAP_ROW_B11 ,Adress map row B11" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x14 16.--19. " ADDRMAP_ROW_B2_10 ,Adress map row B2 to 10" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" textline " " bitfld.long 0x14 8.--11. " ADDRMAP_ROW_B1 ,Adress map row B1" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x14 0.--3. " ADDRMAP_ROW_B0 ,Adress map row B0" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x18 "ADDRMAP6,Address Map Register 6" bitfld.long 0x18 31. " LPDDR3_6GB_12GB ,LPDDR3 SDRAM 6Gb or 12Gb" "Disabled,Enabled" bitfld.long 0x18 24.--27. " ADDRMAP_ROW_B15 ,Adress map row B15" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" textline " " bitfld.long 0x18 16.--19. " ADDRMAP_ROW_B14 ,Adress map row B14" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x18 8.--11. " ADDRMAP_ROW_B13 ,Adress map row B13" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" textline " " bitfld.long 0x18 0.--3. " ADDRMAP_ROW_B12 ,Adress map row B12" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" line.long 0x1C "ADDRMAP7,Address Map Register 7" bitfld.long 0x1C 8.--11. " ADDRMAP_ROW_B17 ,Adress map row B17" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x1C 0.--3. " ADDRMAP_ROW_B16 ,Adress map row B16" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" line.long 0x20 "ADDRMAP8,Address Map Register 8" bitfld.long 0x20 8.--13. " ADDRMAP_BG_B1 ,Adress map bank group B1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,63" bitfld.long 0x20 0.--4. " ADDRMAP_BG_B0 ,Adress map bank group B0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "ADDRMAP9,Address Map Register 9" bitfld.long 0x24 24.--27. " ADDRMAP_ROW_B5 ,Adress map row B5" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x24 16.--19. " ADDRMAP_ROW_B4 ,Adress map row B4" "0,1,2,3,4,5,6,7,8,9,10,11,?..." textline " " bitfld.long 0x24 8.--11. " ADDRMAP_ROW_B3 ,Adress map row B3" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x24 0.--3. " ADDRMAP_ROW_B2 ,Adress map row B2" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x28 "ADDRMAP10,Address Map Register 10" bitfld.long 0x28 24.--27. " ADDRMAP_ROW_B9 ,Adress map row B9" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x28 16.--19. " ADDRMAP_ROW_B8 ,Adress map row B8" "0,1,2,3,4,5,6,7,8,9,10,11,?..." textline " " bitfld.long 0x28 8.--11. " ADDRMAP_ROW_B7 ,Adress map row B7" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x28 0.--3. " ADDRMAP_ROW_B6 ,Adress map row B6" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x2C "ADDRMAP11,Address Map Register 11" bitfld.long 0x2C 0.--3. " ADDRMAP_ROW_B10 ,Adress map row B10" "0,1,2,3,4,5,6,7,8,9,10,11,?..." group.long 0x240++0x07 line.long 0x00 "ODTCFG,ODT configuration register" bitfld.long 0x00 24.--27. " WR_ODT_HOLD ,Write ODT hold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " WR_ODT_DELAY ,Write ODT delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--11. " RD_ODT_HOLD ,Read ODT hold" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--6. " RD_ODT_DELAY ,Read ODT delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "ODTMAP,ODT/Rank Map Register" bitfld.long 0x04 12.--13. " RANK1_RD_ODT ,Rank1 read ODT" "0,1,2,3" bitfld.long 0x04 8.--9. " RANK1_WR_ODT ,Rank1 write ODT" "0,1,2,3" textline " " bitfld.long 0x04 4.--5. " RANK0_RD_ODT ,Rank0 read ODT" "0,1,2,3" bitfld.long 0x04 0.--1. " RANK0_WR_ODT ,Rank0 write ODT" "0,1,2,3" group.long 0x250++0x03 line.long 0x00 "SCHED,Scheduler Control Register" hexmask.long.byte 0x00 24.--30. 1. " RDWR_IDLE_GAP ,RDWR_IDLE_GAP" bitfld.long 0x00 8.--12. " LPR_NUM_ENTRIES ,Number of entries in the low priority transaction store" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 2. " PAGECLOSE ,Provides a midway between open and close page policies" "Open page policy,Close page policy" bitfld.long 0x00 1. " PREFER_WRITE ,Bank selector prefers writes over reads" "0,1" textline " " bitfld.long 0x00 0. " FORCE_LOW_PRI_N ,Low priority for incoming transactions" "Not allowed,Allowed" if (((per.l(ad:0x3DC00000+0x250))&0x2)==0x1) group.long 0x254++0x03 line.long 0x00 "SCHED1,Scheduler Control Register 1" hexmask.long.byte 0x00 0.--7. 1. " PAGECLOSE_TIMER ,Pageclose timer" endif group.long 0x25C++0x03 line.long 0x00 "PERFHPR1,High Priority Read CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " HPR_XACT_RUN_LENGTH ,Number of transactions that are serviced once the HPR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " HPR_MAX_STARVE ,Number of DFI clocks that the HPR queue can be starved before it goes critical" group.long 0x264++0x03 line.long 0x00 "PERFLPR1,Low Priority Read CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " LPR_XACT_RUN_LENGTH ,Number of transactions that are serviced once the LPR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " LPR_MAX_STARVE ,Number of clocks that the LPR queue can be starved before it goes critical" group.long 0x26C++0x03 line.long 0x00 "PERFWR1,Write CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " W_XACT_RUN_LENGTH ,Number of transactions that are serviced once the WR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " W_MAX_STARVE ,Number of clocks that the WR queue can be starved before it goes critical" group.long 0x300++0x07 line.long 0x00 "DBG0,Debug Register 0" bitfld.long 0x00 4. " DIS_COLLISION_PAGE_OPT ,Auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 2. " DIS_ACT_BYPASS ,Disable bypass path for high priority read activates" "No,Yes" textline " " bitfld.long 0x00 1. " DIS_RD_BYPASS ,Disable bypass path for high priority read page hits" "No,Yes" bitfld.long 0x00 0. " DIS_WC ,Disable write combine" "No,Yes" line.long 0x04 "DBG1,Debug Register 1" bitfld.long 0x04 1. " DIS_HIF ,HIF disable" "No,Yes" bitfld.long 0x04 0. " DIS_DQ ,De-queue from the CAM disable" "No,Yes" rgroup.long 0x308++0x13 line.long 0x00 "DBGCAM,CAM Debug Register" bitfld.long 0x00 31. " DBG_STALL_RD ,Stall for read channel" "Not stalled,Stalled" bitfld.long 0x00 30. " DBG_STALL_WR ,Stall for write channel" "Not stalled,Stalled" textline " " bitfld.long 0x00 29. " WR_DATA_PIPELINE_EMPTY ,Indicates that the write data pipeline on the DFI interface is empty" "Not empty,Empty" bitfld.long 0x00 28. " RD_DATA_PIPELINE_EMPTY ,Indicates that the read data pipeline on the DFI interface is empty" "Not empty,Empty" textline " " bitfld.long 0x00 26. " DBG_WR_Q_EMPTY ,Indicates that all the write command queues and write data buffers inside DDRC are empty" "Not empty,Empty" bitfld.long 0x00 25. " DBG_RD_Q_EMPTY ,Indicates that all the read command queues and read data buffers inside DDRC are empty" "Not empty,Empty" textline " " bitfld.long 0x00 24. " DBG_STALL ,Stall" "Not stalled,Stalled" bitfld.long 0x00 16.--21. " DBG_W_Q_DEPTH ,Write queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 8.--13. " DBG_LPR_Q_DEPTH ,Low priority read queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DBG_HPR_Q_DEPTH ,High priority read queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x30C++0x03 line.long 0x00 "DBGCMD,Command Debug Register" bitfld.long 0x00 5. " CTRLUPD ,Indicates to the DDRC to issue a dfi_ctrlupd_req to the PHY" "Not issued,Issued" bitfld.long 0x00 4. " ZQ_CALIB_SHORT ,Indicates to the DDRC to issue a ZQCS command to the SDRAM" "No calibration,ZQ calibration" textline " " bitfld.long 0x00 1. " RANK1_REFRESH ,Indicates to the DDRC to issue a refresh to rank 1" "No refresh,Refresh" bitfld.long 0x00 0. " RANK0_REFRESH ,Indicates to the DDRC to issue a refresh to rank 0" "No refresh,Refresh" rgroup.long 0x310++0x03 line.long 0x00 "DBGSTAT,Status Debug Register" bitfld.long 0x00 5. " CTRLUPD_BUSY ,Ctrlupd operation busy" "Not busy,Busy" bitfld.long 0x00 4. " ZQ_CALIB_SHORT_BUSY ,ZQCS operation busy" "Not busy,Busy" textline " " bitfld.long 0x00 1. " RANK1_REFRESH_BUSY ,Rank1_refresh operation busy" "Not busy,Busy" bitfld.long 0x00 0. " RANK0_REFRESH_BUSY ,Rank0_refresh operation busy" "Not busy,Busy" group.long 0x320++0x03 line.long 0x00 "SWCTL,Software Register Programming Control Enable" bitfld.long 0x00 0. " SW_DONE ,Enable quasi dynamic register programming outside reset" "Disabled,Enabled" rgroup.long 0x324++0x03 line.long 0x00 "SWSTAT,Software Register Programming Control Status" bitfld.long 0x00 0. " SW_DONE_ACK ,Register programming done" "No,Yes" group.long 0x36C++0x03 line.long 0x00 "POISONCFG,AXI Poison Configuration Register" bitfld.long 0x00 24. " RD_POISON_INTR_CLR ,Interrupt clear for read transaction poisoning" "Not cleared,Cleared" bitfld.long 0x00 20. " RD_POISON_INTR_EN ,Enables interrupts for read transaction poisoning" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RD_POISON_SLVERR_EN ,Enables SLVERR response for read transaction poisoning" "Disabled,Enabled" bitfld.long 0x00 8. " WR_POISON_INTR_CLR ,Interrupt clear for write transaction poisoning" "Not cleared,Cleared" textline " " bitfld.long 0x00 4. " WR_POISON_INTR_EN ,Enables interrupts for write transaction poisoning" "Enabled,Disabled" bitfld.long 0x00 0. " WR_POISON_SLVERR_E ,Enables SLVERR response for write transaction poisoning" "Enabled,Disabled" rgroup.long 0x370++0x03 line.long 0x00 "POISONSTAT,AXI Poison Status Register" bitfld.long 0x00 16. " RD_POISON_INTR_0 ,Read transaction poisoning error interrupt for port 0" "No interrupt,Interrupt" bitfld.long 0x00 0. " WR_POISON_INTR_0 ,Write transaction poisoning error interrupt for port 0" "No interrupt,Interrupt" rgroup.long 0x3FC++0x03 line.long 0x00 "POISONSTAT,Port Status Register" bitfld.long 0x00 16. " WR_PORT_BUSY_0 ,Indicates if there are outstanding writes for AXI port 0" "Not busy,Busy" bitfld.long 0x00 0. " RD_PORT_BUSY_0 ,Indicates if there are outstanding reads for AXI port 0" "Not busy,Busy" group.long 0x400++0x0B line.long 0x00 "PCCFG,Port Common Configuration Register" bitfld.long 0x00 8. " BL_EXP_MODE ,Burst length expansion mode" "0,1" bitfld.long 0x00 4. " PAGEMATCH_LIMIT ,Page match four limit" "No limit,Limit" textline " " bitfld.long 0x00 0. " GO2CRITICAL_EN ,Sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals" "Disabled,Enabled" line.long 0x04 "PCFGR_0,Port 0 Configuration Read Register" bitfld.long 0x04 16. " RDWR_ORDERED_EN ,Enable ordered read/writes" "Disabled,Enabled" bitfld.long 0x04 14. " RD_PORT_PAGEMATCH_EN ,Enables the Page Match feature" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " RD_PORT_PAGEMATCH_EN ,Enables the AXI urgent sideband signal" "Disabled,Enabled" bitfld.long 0x04 12. " RD_PORT_AGING_EN ,Enables aging function for the read channel of the port" "Disabled,Enabled" textline " " hexmask.long.word 0x04 0.--9. 1. " RD_PORT_PRIORITY ,Determines the initial load value of read aging counters" line.long 0x08 "PCFGW_0,Port n Configuration Write Register" bitfld.long 0x08 14. " WR_PORT_PAGEMATCH_EN ,Enables the Page Match feature" "Enabled,Disabled" bitfld.long 0x08 13. " WR_PORT_URGENT_EN ,Enables the AXI urgent sideband signal" "Enabled,Disabled" textline " " bitfld.long 0x08 12. " WR_PORT_AGING_EN ,Enables aging function for the write channel of the port" "Enabled,Disabled" hexmask.long.word 0x08 0.--9. 1. " WR_PORT_PRIORITY ,Determines the initial load value of write aging counters" group.long 0x490++0x13 line.long 0x00 "PCTRL_0,Port 0 Control Register" bitfld.long 0x00 0. " PORT_EN ,Enables AXI port n" "Disabled,Enabled" line.long 0x04 "PCFGQOS0_0,Port 0 Read QoS Configuration Register 0" bitfld.long 0x04 20.--21. " RQOS_MAP_REGION1 ,Indicates the traffic class of region 1" "LPR,VPR,HPR,?..." bitfld.long 0x04 16.--17. " RQOS_MAP_REGION0 ,This bitfield indicates the traffic class of region 0" "LPR,VPR,HPR,?..." textline " " bitfld.long 0x04 0.--3. " RQOS_MAP_LEVEL1 ,Separation level1 indicating the end of region0 mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..." line.long 0x08 "PCFGQOS1_0,Port n Read QoS Configuration Register 1" hexmask.long.word 0x08 16.--26. 1. " RQOS_MAP_TIMEOUTR ,Specifies the timeout value for transactions mapped to the red address queue" hexmask.long.word 0x08 0.--10. 1. " RQOS_MAP_TIMEOUTB ,Specifies the timeout value for transactions mapped to the blue address queue" line.long 0x0C "PCFGWQOS0_0,Port n Write QoS Configuration Register 0" bitfld.long 0x0C 20.--21. " WQOS_MAP_REGION1 ,This bitfield indicates the traffic class of region 1" "NPW,VPW,?..." bitfld.long 0x0C 16.--17. " WQOS_MAP_REGION0 ,This bitfield indicates the traffic class of region 0" "NPW,VPW,?..." textline " " bitfld.long 0x0C 0.--3. " WQOS_MAP_LEVEL ,Separation level indicating the end of region0 mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCFGWQOS1_0,Port n Write QoS Configuration Register 1" hexmask.long.word 0x10 0.--10. 1. " WQOS_MAP_TIMEOUT ,Specifies the timeout value for write transactions" group.long 0x2020++0x07 line.long 0x00 "DERATEEN_SHADOW,Temperature Derate Enable Register" bitfld.long 0x00 8.--9. " RC_DERATE_VALUE ,Derate value of tRC for LPDDR4" "+1,+2,+3,+4" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Derate value of tRC for LPDDR4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" bitfld.long 0x00 0. " DERATE_ENABLE ,Enables derating" "Disabled,Enabled" line.long 0x04 "DERATEINT_SHADOW,Temperature Derate Interval Register" group.long 0x2050++0x03 line.long 0x00 "RFSHCTL0_SHADOW,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " PER_BANK_REFRESH ,Per bank refresh" "Per bank,All bank" group.long 0x2064++0x03 line.long 0x00 "RFSHTMG_SHADOW,Refresh Timing Register" hexmask.long.word 0x00 16.--27. 1. " T_RFC_NOM_X32 ,Average time interval between refreshes per rank" bitfld.long 0x00 15. " LPDDR3_TREFBW_EN ,tREFBW parameter enabled" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--9. 1. " T_RFC_MIN ,Minimum time from refresh to refresh or activate" group.long 0x20DC++0x07 line.long 0x00 "INIT3_SHADOW,SDRAM Initialization Register 3" hexmask.long.word 0x00 16.--31. 1. " MR ,Value to write to MR register" hexmask.long.word 0x00 0.--15. 1. " EMR ,Value to write to EMR register" line.long 0x04 "INIT4_SHADOW,SDRAM Initialization Register 4" hexmask.long.word 0x04 16.--31. 1. " EMR2 ,Value to write to EMR2 register" hexmask.long.word 0x04 0.--15. 1. " EMR3 ,Value to write to EMR3 register" group.long 0x20E8++0x07 line.long 0x00 "INIT6_SHADOW,SDRAM Initialization Register 6" hexmask.long.word 0x00 16.--31. 1. " MR4 ,Value to write to MR4 register" hexmask.long.word 0x00 0.--15. 1. " MR5 ,Value to write to MR5 register" line.long 0x04 "INIT7_SHADOW,SDRAM Initialization Register 7" hexmask.long.word 0x04 16.--31. 1. " MR6 ,Value to write to MR6 register" group.long 0x2100++0x3F line.long 0x00 "DRAMTMG0_SHADOW,SDRAM Timing Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR2PRE ,Minimum time between write and precharge to same bank" bitfld.long 0x00 16.--21. " T_FAW ,T_FAW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x00 8.--15. 1. " T_RAS_MAX ,Maximum time between activate and precharge to same bank" bitfld.long 0x00 0.--5. " T_RAS_MIN ,Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DRAMTMG1_SHADOW,SDRAM Timing Register 1" bitfld.long 0x04 16.--20. " T_XP ,Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--13. " RD2PRE ,Minimum time from read to precharge of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x04 0.--6. 1. " T_RC ,Minimum time between activates to same bank" line.long 0x08 "DRAMTMG2_SHADOW,SDRAM Timing Register 2" bitfld.long 0x08 24.--29. " WRITE_LATENCY ,Set to WL time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " READ_LATENCY ,Set to RL time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x08 8.--13. " RD2WR ,Minimum time from read command to write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " WR2RD ,Minimum time from write command to read command for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "DRAMTMG3_SHADOW,SDRAM Timing Register 3" hexmask.long.word 0x0C 20.--29. 1. " T_MRW ,Time to wait after a mode register write or read (MRW or MRR)" bitfld.long 0x0C 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0C 0.--9. 1. " T_MOD ,Cycles between load mode command and following non-load mode command" line.long 0x10 "DRAMTMG4_SHADOW,SDRAM Timing Register 4" bitfld.long 0x10 24.--28. " T_RCD ,Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 16.--19. " T_CCD ,This is the minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 8.--11. " T_RRD ,Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--4. " T_RP ,Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "DRAMTMG5_SHADOW,SDRAM Timing Register 5" bitfld.long 0x14 24.--27. " T_CKSRX ,This is the time before self refresh exit that ck is maintained as a valid clock before issuing SRX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 16.--19. " T_CKSRE ,This is the time after self refresh down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x14 8.--13. " T_CKESR ,Minimum CKE low width for self refresh or self refresh power down entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 0.--4. " T_CKE ,Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "DRAMTMG6_SHADOW,SDRAM Timing Register 6" bitfld.long 0x18 24.--27. " T_CKDPDE ,This is the time after deep power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 16.--19. " T_CKDPDX ,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x18 0.--3. " T_CKCSX ,This is the time before clock stop exit that CK is maintained as a valid clock before issuing clock stop exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "DRAMTMG7_SHADOW,SDRAM Timing Register 7" bitfld.long 0x1C 8.--11. " T_CKPDE ,This is the time after Power Down Entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " T_CKPDX ,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "DRAMTMG8_SHADOW,SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. " T_XS_FAST_X32 ,T_XS_FAST_X32" hexmask.long.byte 0x20 16.--22. 1. " T_XS_ABORT_X32 ,T_XS_ABORT_X32" textline " " hexmask.long.byte 0x20 8.--14. 1. " T_XS_DLL_X32 ,T_XS_DLL_X32" hexmask.long.byte 0x20 0.--6. 1. " T_XS_X32 ,T_XS_X32" line.long 0x24 "DRAMTMG9_SHADOW,SDRAM Timing Register 9" bitfld.long 0x24 30. " DDR4_WR_PREAMBLE ,Write preamble mode" "1tCK,2tCK" bitfld.long 0x24 16.--18. " T_CCD_S , This is the minimum time between two reads or two writes for different bank group" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x24 8.--11. " T_RRD_S ,Minimum time between activates from bank a to bank b for different bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x24 0.--5. " WR2RD_S ,Minimum time from write command to read command for different bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "DRAMTMG10_SHADOW,SDRAM Timing Register 10" bitfld.long 0x28 16.--20. " T_SYNC_GEAR ,Indicates the time between MRS command and the sync pulse time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 8.--12. " T_CMD_GEAR ,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x28 2.--3. " T_GEAR_SETUP ,Geardown setup time" "0,1,2,3" bitfld.long 0x28 0.--1. " T_GEAR_HOLD ,Geardown hold time" "0,1,2,3" line.long 0x2C "DRAMTMG11_SHADOW,SDRAM Timing Register 11 " hexmask.long.byte 0x2C 24.--30. 1. " POST_MPSM_GAP_X32 ,This is the minimum Exit MPSM to commands requiring a locked DLL" bitfld.long 0x2C 16.--20. " POST_MPSM_GAP_X32 ,This is the minimum Exit MPSM to commands requiring a locked DLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x2C 8.--9. " T_MPX_S ,Minimum time CS setup time to CKE" "0,1,2,3" bitfld.long 0x2C 0.--4. " T_CKMPE ,Minimum valid clock requirement after MPSM entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "DRAMTMG12_SHADOW,SDRAM Timing Register 12" bitfld.long 0x30 16.--17. " T_CMDCKE ,Delay from valid command to CKE input LOW" "0,1,2,3" bitfld.long 0x30 8.--11. " T_CKEHCMD ,Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x30 0.--4. " T_MRD_PDA ,This is the Mode Register Set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "DRAMTMG13_SHADOW,SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. " ODTLOFF ,This is the latency from CAS-2 command to tODToff reference" bitfld.long 0x34 16.--21. " T_CCD_MW ,This is the minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x34 0.--2. " T_PPD ,This is the minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7" line.long 0x38 "DRAMTMG14_SHADOW,SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. " T_XSR ,Exit Self Refresh to any command" line.long 0x3C "DRAMTMG15_SHADOW,SDRAM Timing Register 15" bitfld.long 0x3C 31. " EN_DFI_LP_T_STAB ,Enables using tSTAB" "Disabled,Enabled" hexmask.long.byte 0x3C 0.--7. 1. " T_STAB_X32 ,Stabilization time" group.long 0x2180++0x03 line.long 0x00 "ZQCTL0_SHADOW,ZQ Control Register 0" bitfld.long 0x00 31. " DIS_AUTO_ZQ ,Disable DDRC generation of ZQCS/MPC command" "No,Yes" bitfld.long 0x00 30. " DIS_SRX_ZQCL ,Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/sr-powerdown exit" "No,Yes" textline " " bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED ,ZQ resistor is shared between ranks" "Not shared,Shared" bitfld.long 0x00 28. " DIS_MPSMX_ZQCL ,Disable issuing of ZQCL command at maximum power saving mode exit" "No,Yes" textline " " hexmask.long.word 0x00 16.--26. 1. " T_ZQ_LONG_NOP ,Number of DFI clock cycles of NOP required after a ZQCL/MPC command is issued to SDRAM" hexmask.long.word 0x00 0.--9. 1. " T_ZQ_SHORT_NOP ,Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM" group.long 0x2190++0x07 line.long 0x00 "DFITMG0_SHADOW,DFI Timing Register 0" bitfld.long 0x00 24.--28. " DFI_T_CTRL_DELAY ,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " DFI_RDDATA_USE_SDR ,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR(DFI PHY clock) values" "HDR,SDR" textline " " hexmask.long.byte 0x00 16.--22. 1. " DFI_T_RDDATA_EN ,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal" bitfld.long 0x00 15. " DFI_WRDATA_USE_SDR ,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values" "HDR,SDR" textline " " bitfld.long 0x00 8.--13. " DFI_TPHY_WRDATA ,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 0.--5. " DFI_TPHY_WRLAT ,Write latency number of clocks from the write command to write data enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG1_SHADOW,DFI Timing Register 1" bitfld.long 0x04 28.--31. " DFI_T_CMD_LAT ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven" "0,,,3,4,5,6,,8,?..." bitfld.long 0x04 24.--25. " DFI_T_PARIN_LAT ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven" "0,1,2,3" textline " " bitfld.long 0x04 16.--20. " DFI_T_WRDATA_DELAY ,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " DFI_T_DRAM_CLK_DISABLE ,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 0.--4. " DFI_T_DRAM_CLK_ENABLE ,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x21B4++0x07 line.long 0x00 "DFITMG2_SHADOW,DFI Timing Register 2" hexmask.long.byte 0x00 8.--14. 1. " DFI_TPHY_RDCSLAT ,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted" bitfld.long 0x00 0.--5. " DFI_TPHY_WRCSLAT ,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG3_SHADOW,DFI Timing Register 3" bitfld.long 0x04 0.--4. " DFI_T_GEARDOWN_DELAY ,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2240++0x03 line.long 0x00 "ODTCFG_SHADOW,ODT Configuration Register" bitfld.long 0x00 24.--27. " WR_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a write command" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " WR_ODT_DELAY ,The delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--11. " RD_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--6. " RD_ODT_DELAY ,The delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "APBH (AHB-to-APBH Bridge with DMA)" base ad:0x33000000 width 18. group.long 0x00++0x0F line.long 0x00 "CTRL0,AHB To APBH Bridge Control And Status Register 0" bitfld.long 0x00 31. " SFTRST ,Disables clocking with the APBH DMA and holds it in its reset state" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Gated on,Gated off" bitfld.long 0x00 29. " AHB_BURST8_EN ,Enables AHB 8-beat burst" "Disabled,Enabled" newline bitfld.long 0x00 28. " APB_BURST_EN ,Enables APB master do a continuous transfers when a device request a burst DMA" "Disabled,Enabled" bitfld.long 0x00 8. " CLKGATE_SSP ,Gates off the individual clocks to the SSP" "Gated on,Gated off" bitfld.long 0x00 7. " CLKGATE_NAND7 ,Gates off the individual clocks to the NAND7" "Gated on,Gated off" newline bitfld.long 0x00 6. " CLKGATE_NAND6 ,Gates off the individual clocks to the NAND6" "Gated on,Gated off" bitfld.long 0x00 5. " CLKGATE_NAND5 ,Gates off the individual clocks to the NAND5" "Gated on,Gated off" bitfld.long 0x00 4. " CLKGATE_NAND4 ,Gates off the individual clocks to the NAND4" "Gated on,Gated off" newline bitfld.long 0x00 3. " CLKGATE_NAND3 ,Gates off the individual clocks to the NAND3" "Gated on,Gated off" bitfld.long 0x00 2. " CLKGATE_NAND2 ,Gates off the individual clocks to the NAND2" "Gated on,Gated off" newline bitfld.long 0x00 1. " CLKGATE_NAND1 ,Gates off the individual clocks to the NAND1" "Gated on,Gated off" bitfld.long 0x00 0. " CLKGATE_NAND0 ,Gates off the individual clocks to the NAND0" "Gated on,Gated off" line.long 0x04 "CTRL0_SET,AHB To APBH Bridge Control And Status Set Register 0" bitfld.long 0x04 31. " SFTRST ,Disables clocking with the APBH DMA and holds it in its reset state" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" bitfld.long 0x04 29. " AHB_BURST8_EN ,Enables AHB 8-beat burst" "No effect,Set" newline bitfld.long 0x04 28. " APB_BURST_EN ,Enables APB master do a continuous transfers when a device request a burst DMA" "No effect,Set" bitfld.long 0x04 8. " CLKGATE_SSP ,Gates off the individual clocks to the SSP" "No effect,Set" bitfld.long 0x04 7. " CLKGATE_NAND7 ,Gates off the individual clocks to the NAND7" "No effect,Set" newline bitfld.long 0x04 6. " CLKGATE_NAND6 ,Gates off the individual clocks to the NAND6" "No effect,Set" bitfld.long 0x04 5. " CLKGATE_NAND5 ,Gates off the individual clocks to the NAND5" "No effect,Set" bitfld.long 0x04 4. " CLKGATE_NAND4 ,Gates off the individual clocks to the NAND4" "No effect,Set" newline bitfld.long 0x04 3. " CLKGATE_NAND3 ,Gates off the individual clocks to the NAND3" "No effect,Set" bitfld.long 0x04 2. " CLKGATE_NAND2 ,Gates off the individual clocks to the NAND2" "No effect,Set" newline bitfld.long 0x04 1. " CLKGATE_NAND1 ,Gates off the individual clocks to the NAND1" "No effect,Set" bitfld.long 0x04 0. " CLKGATE_NAND0 ,Gates off the individual clocks to the NAND0" "No effect,Set" line.long 0x08 "CTRL0_CLR,AHB To APBH Bridge Control And Status Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Disables clocking with the APBH DMA and holds it in its reset state" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" bitfld.long 0x08 29. " AHB_BURST8_EN ,Enables AHB 8-beat burst" "No effect,Clear" newline bitfld.long 0x08 28. " APB_BURST_EN ,Enables APB master do a continuous transfers when a device request a burst DMA" "No effect,Clear" bitfld.long 0x08 8. " CLKGATE_SSP ,Gates off the individual clocks to the SSP" "No effect,Clear" bitfld.long 0x08 7. " CLKGATE_NAND7 ,Gates off the individual clocks to the NAND7" "No effect,Clear" newline bitfld.long 0x08 6. " CLKGATE_NAND6 ,Gates off the individual clocks to the NAND6" "No effect,Clear" bitfld.long 0x08 5. " CLKGATE_NAND5 ,Gates off the individual clocks to the NAND5" "No effect,Clear" bitfld.long 0x08 4. " CLKGATE_NAND4 ,Gates off the individual clocks to the NAND4" "No effect,Clear" newline bitfld.long 0x08 3. " CLKGATE_NAND3 ,Gates off the individual clocks to the NAND3" "No effect,Clear" bitfld.long 0x08 2. " CLKGATE_NAND2 ,Gates off the individual clocks to the NAND2" "No effect,Clear" newline bitfld.long 0x08 1. " CLKGATE_NAND1 ,Gates off the individual clocks to the NAND1" "No effect,Clear" bitfld.long 0x08 0. " CLKGATE_NAND0 ,Gates off the individual clocks to the NAND0" "No effect,Clear" line.long 0x0C "CTRL0_TOG,AHB To APBH Bridge Control And Status Toggle Register 0" bitfld.long 0x0C 31. " SFTRST ,Disables clocking with the APBH DMA and holds it in its reset state" "No effect,Toggle" bitfld.long 0x0C 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Toggle" bitfld.long 0x0C 29. " AHB_BURST8_EN ,Enables AHB 8-beat burst" "No effect,Toggle" newline bitfld.long 0x0C 28. " APB_BURST_EN ,Enables APB master do a continuous transfers when a device request a burst DMA" "No effect,Toggle" bitfld.long 0x0C 8. " CLKGATE_SSP ,Gates off the individual clocks to the SSP" "No effect,Toggle" bitfld.long 0x0C 7. " CLKGATE_NAND7 ,Gates off the individual clocks to the NAND7" "No effect,Toggle" newline bitfld.long 0x0C 6. " CLKGATE_NAND6 ,Gates off the individual clocks to the NAND6" "No effect,Toggle" bitfld.long 0x0C 5. " CLKGATE_NAND5 ,Gates off the individual clocks to the NAND5" "No effect,Toggle" bitfld.long 0x0C 4. " CLKGATE_NAND4 ,Gates off the individual clocks to the NAND4" "No effect,Toggle" newline bitfld.long 0x0C 3. " CLKGATE_NAND3 ,Gates off the individual clocks to the NAND3" "No effect,Toggle" bitfld.long 0x0C 2. " CLKGATE_NAND2 ,Gates off the individual clocks to the NAND2" "No effect,Toggle" newline bitfld.long 0x0C 1. " CLKGATE_NAND1 ,Gates off the individual clocks to the NAND1" "No effect,Toggle" bitfld.long 0x0C 0. " CLKGATE_NAND0 ,Gates off the individual clocks to the NAND0" "No effect,Toggle" group.long 0x10++0x0F line.long 0x00 "CTRL1,AHB To APBH Bridge Control And Status Register 1" bitfld.long 0x00 31. " CH15_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 15" "Disabled,Enabled" bitfld.long 0x00 30. " CH14_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 14" "Disabled,Enabled" bitfld.long 0x00 29. " CH13_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 13" "Disabled,Enabled" newline bitfld.long 0x00 28. " CH12_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 12" "Disabled,Enabled" bitfld.long 0x00 27. " CH11_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 11" "Disabled,Enabled" bitfld.long 0x00 26. " CH10_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 10" "Disabled,Enabled" newline bitfld.long 0x00 25. " CH9_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 9" "Disabled,Enabled" bitfld.long 0x00 24. " CH8_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 8" "Disabled,Enabled" bitfld.long 0x00 23. " CH7_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 7" "Disabled,Enabled" newline bitfld.long 0x00 22. " CH6_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 6" "Disabled,Enabled" bitfld.long 0x00 21. " CH5_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 5" "Disabled,Enabled" bitfld.long 0x00 20. " CH4_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 4" "Disabled,Enabled" newline bitfld.long 0x00 19. " CH3_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 3" "Disabled,Enabled" bitfld.long 0x00 18. " CH2_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 2" "Disabled,Enabled" bitfld.long 0x00 17. " CH1_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 1" "Disabled,Enabled" newline bitfld.long 0x00 16. " CH0_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 0" "Disabled,Enabled" bitfld.long 0x00 15. " CH15_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " CH14_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No interrupt,Interrupt" bitfld.long 0x00 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No interrupt,Interrupt" line.long 0x04 "CTRL1_SET,AHB To APBH Bridge Control And Status Set Register 1" bitfld.long 0x04 31. " CH15_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 15" "No effect,Set" bitfld.long 0x04 30. " CH14_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 14" "No effect,Set" bitfld.long 0x04 29. " CH13_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 13" "No effect,Set" newline bitfld.long 0x04 28. " CH12_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 12" "No effect,Set" bitfld.long 0x04 27. " CH11_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 11" "No effect,Set" bitfld.long 0x04 26. " CH10_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 10" "No effect,Set" newline bitfld.long 0x04 25. " CH9_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 9" "No effect,Set" bitfld.long 0x04 24. " CH8_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 8" "No effect,Set" bitfld.long 0x04 23. " CH7_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 7" "No effect,Set" newline bitfld.long 0x04 22. " CH6_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 6" "No effect,Set" bitfld.long 0x04 21. " CH5_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 5" "No effect,Set" bitfld.long 0x04 20. " CH4_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 4" "No effect,Set" newline bitfld.long 0x04 19. " CH3_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 3" "No effect,Set" bitfld.long 0x04 18. " CH2_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 2" "No effect,Set" bitfld.long 0x04 17. " CH1_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 1" "No effect,Set" newline bitfld.long 0x04 16. " CH0_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 0" "No effect,Set" bitfld.long 0x04 15. " CH15_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 15" "No effect,Set" bitfld.long 0x04 14. " CH14_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 14" "No effect,Set" newline bitfld.long 0x04 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "No effect,Set" bitfld.long 0x04 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Set" bitfld.long 0x04 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "No effect,Set" newline bitfld.long 0x04 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "No effect,Set" bitfld.long 0x04 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "No effect,Set" bitfld.long 0x04 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "No effect,Set" newline bitfld.long 0x04 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No effect,Set" bitfld.long 0x04 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No effect,Set" bitfld.long 0x04 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No effect,Set" newline bitfld.long 0x04 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No effect,Set" bitfld.long 0x04 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No effect,Set" bitfld.long 0x04 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Set" newline bitfld.long 0x04 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No effect,Set" bitfld.long 0x04 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No effect,Set" line.long 0x08 "CTRL1_CLR,AHB To APBH Bridge Control And Status Clear Register 1" bitfld.long 0x08 31. " CH15_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 15" "No effect,Clear" bitfld.long 0x08 30. " CH14_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 14" "No effect,Clear" bitfld.long 0x08 29. " CH13_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 13" "No effect,Clear" newline bitfld.long 0x08 28. " CH12_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 12" "No effect,Clear" bitfld.long 0x08 27. " CH11_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 11" "No effect,Clear" bitfld.long 0x08 26. " CH10_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 10" "No effect,Clear" newline bitfld.long 0x08 25. " CH9_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 9" "No effect,Clear" bitfld.long 0x08 24. " CH8_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 8" "No effect,Clear" bitfld.long 0x08 23. " CH7_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 7" "No effect,Clear" newline bitfld.long 0x08 22. " CH6_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 6" "No effect,Clear" bitfld.long 0x08 21. " CH5_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 5" "No effect,Clear" bitfld.long 0x08 20. " CH4_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 4" "No effect,Clear" newline bitfld.long 0x08 19. " CH3_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 3" "No effect,Clear" bitfld.long 0x08 18. " CH2_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 2" "No effect,Clear" bitfld.long 0x08 17. " CH1_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 1" "No effect,Clear" newline bitfld.long 0x08 16. " CH0_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 0" "No effect,Clear" bitfld.long 0x08 15. " CH15_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 15" "No effect,Clear" bitfld.long 0x08 14. " CH14_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 14" "No effect,Clear" newline bitfld.long 0x08 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "No effect,Clear" bitfld.long 0x08 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Clear" bitfld.long 0x08 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "No effect,Clear" newline bitfld.long 0x08 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "No effect,Clear" bitfld.long 0x08 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "No effect,Clear" bitfld.long 0x08 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "No effect,Clear" newline bitfld.long 0x08 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No effect,Clear" bitfld.long 0x08 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No effect,Clear" bitfld.long 0x08 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No effect,Clear" newline bitfld.long 0x08 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No effect,Clear" bitfld.long 0x08 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No effect,Clear" bitfld.long 0x08 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Clear" newline bitfld.long 0x08 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No effect,Clear" bitfld.long 0x08 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No effect,Clear" line.long 0x0C "CTRL1_TOG,AHB To APBH Bridge Control And Status Toggle Register 1" bitfld.long 0x0C 31. " CH15_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 15" "No effect,Toggle" bitfld.long 0x0C 30. " CH14_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 14" "No effect,Toggle" bitfld.long 0x0C 29. " CH13_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 13" "No effect,Toggle" newline bitfld.long 0x0C 28. " CH12_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 12" "No effect,Toggle" bitfld.long 0x0C 27. " CH11_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 11" "No effect,Toggle" bitfld.long 0x0C 26. " CH10_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 10" "No effect,Toggle" newline bitfld.long 0x0C 25. " CH9_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 9" "No effect,Toggle" bitfld.long 0x0C 24. " CH8_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 8" "No effect,Toggle" bitfld.long 0x0C 23. " CH7_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 7" "No effect,Toggle" newline bitfld.long 0x0C 22. " CH6_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 6" "No effect,Toggle" bitfld.long 0x0C 21. " CH5_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 5" "No effect,Toggle" bitfld.long 0x0C 20. " CH4_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 4" "No effect,Toggle" newline bitfld.long 0x0C 19. " CH3_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 3" "No effect,Toggle" bitfld.long 0x0C 18. " CH2_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 2" "No effect,Toggle" bitfld.long 0x0C 17. " CH1_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 1" "No effect,Toggle" newline bitfld.long 0x0C 16. " CH0_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 0" "No effect,Toggle" bitfld.long 0x0C 15. " CH15_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 15" "No effect,Toggle" bitfld.long 0x0C 14. " CH14_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 14" "No effect,Toggle" newline bitfld.long 0x0C 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "No effect,Toggle" bitfld.long 0x0C 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Toggle" bitfld.long 0x0C 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "No effect,Toggle" newline bitfld.long 0x0C 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "No effect,Toggle" bitfld.long 0x0C 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "No effect,Toggle" bitfld.long 0x0C 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "No effect,Toggle" newline bitfld.long 0x0C 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No effect,Toggle" bitfld.long 0x0C 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No effect,Toggle" bitfld.long 0x0C 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No effect,Toggle" newline bitfld.long 0x0C 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No effect,Toggle" bitfld.long 0x0C 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No effect,Toggle" bitfld.long 0x0C 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Toggle" newline bitfld.long 0x0C 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No effect,Toggle" bitfld.long 0x0C 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No effect,Toggle" group.long 0x20++0x0F line.long 0x00 "CTRL2,AHB To APBH Bridge Control And Status Register 2" rbitfld.long 0x00 31. " CH15_ERROR_STATUS ,Error status bit for APBH DMA channel 15" "Early termination,AHB bus error" rbitfld.long 0x00 30. " CH14_ERROR_STATUS ,Error status bit for APBH DMA channel 14" "Early termination,AHB bus error" rbitfld.long 0x00 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA channel 13" "Early termination,AHB bus error" newline rbitfld.long 0x00 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA channel 12" "Early termination,AHB bus error" rbitfld.long 0x00 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA channel 11" "Early termination,AHB bus error" rbitfld.long 0x00 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA channel 10" "Early termination,AHB bus error" newline rbitfld.long 0x00 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA channel 9" "Early termination,AHB bus error" rbitfld.long 0x00 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA channel 8" "Early termination,AHB bus error" rbitfld.long 0x00 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA channel 7" "Early termination,AHB bus error" newline rbitfld.long 0x00 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA channel 6" "Early termination,AHB bus error" rbitfld.long 0x00 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA channel 5" "Early termination,AHB bus error" rbitfld.long 0x00 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA channel 4" "Early termination,AHB bus error" newline rbitfld.long 0x00 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA channel 3" "Early termination,AHB bus error" rbitfld.long 0x00 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA channel 2" "Early termination,AHB bus error" rbitfld.long 0x00 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA channel 1" "Early termination,AHB bus error" newline rbitfld.long 0x00 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA channel 0" "Early termination,AHB bus error" bitfld.long 0x00 15. " CH15_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " CH14_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 4" "No interrupt,Interrupt" bitfld.long 0x00 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 0" "No interrupt,Interrupt" line.long 0x04 "CTRL2_SET,AHB To APBH Bridge Control And Status Set Register 2" rbitfld.long 0x04 31. " CH15_ERROR_STATUS ,Error status bit for APBH DMA channel 15" "No effect,Set" rbitfld.long 0x04 30. " CH14_ERROR_STATUS ,Error status bit for APBH DMA channel 14" "No effect,Set" rbitfld.long 0x04 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA channel 13" "No effect,Set" newline rbitfld.long 0x04 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA channel 12" "No effect,Set" rbitfld.long 0x04 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA channel 11" "No effect,Set" rbitfld.long 0x04 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA channel 10" "No effect,Set" newline rbitfld.long 0x04 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA channel 9" "No effect,Set" rbitfld.long 0x04 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA channel 8" "No effect,Set" rbitfld.long 0x04 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA channel 7" "No effect,Set" newline rbitfld.long 0x04 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA channel 6" "No effect,Set" rbitfld.long 0x04 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA channel 5" "No effect,Set" rbitfld.long 0x04 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA channel 4" "No effect,Set" newline rbitfld.long 0x04 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA channel 3" "No effect,Set" rbitfld.long 0x04 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA channel 2" "No effect,Set" rbitfld.long 0x04 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA channel 1" "No effect,Set" newline rbitfld.long 0x04 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA channel 0" "No effect,Set" bitfld.long 0x04 15. " CH15_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 15" "No effect,Set" bitfld.long 0x04 14. " CH14_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 14" "No effect,Set" newline bitfld.long 0x04 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 13" "No effect,Set" bitfld.long 0x04 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 12" "No effect,Set" bitfld.long 0x04 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 11" "No effect,Set" newline bitfld.long 0x04 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 10" "No effect,Set" bitfld.long 0x04 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 9" "No effect,Set" bitfld.long 0x04 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 8" "No effect,Set" newline bitfld.long 0x04 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 7" "No effect,Set" bitfld.long 0x04 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 6" "No effect,Set" bitfld.long 0x04 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 5" "No effect,Set" newline bitfld.long 0x04 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 4" "No effect,Set" bitfld.long 0x04 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 3" "No effect,Set" bitfld.long 0x04 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 2" "No effect,Set" newline bitfld.long 0x04 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 1" "No effect,Set" bitfld.long 0x04 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 0" "No effect,Set" line.long 0x08 "CTRL2_CLR,AHB To APBH Bridge Control And Status Clear Register 2" rbitfld.long 0x08 31. " CH15_ERROR_STATUS ,Error status bit for APBH DMA channel 15" "No effect,Clear" rbitfld.long 0x08 30. " CH14_ERROR_STATUS ,Error status bit for APBH DMA channel 14" "No effect,Clear" rbitfld.long 0x08 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA channel 13" "No effect,Clear" newline rbitfld.long 0x08 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA channel 12" "No effect,Clear" rbitfld.long 0x08 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA channel 11" "No effect,Clear" rbitfld.long 0x08 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA channel 10" "No effect,Clear" newline rbitfld.long 0x08 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA channel 9" "No effect,Clear" rbitfld.long 0x08 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA channel 8" "No effect,Clear" rbitfld.long 0x08 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA channel 7" "No effect,Clear" newline rbitfld.long 0x08 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA channel 6" "No effect,Clear" rbitfld.long 0x08 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA channel 5" "No effect,Clear" rbitfld.long 0x08 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA channel 4" "No effect,Clear" newline rbitfld.long 0x08 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA channel 3" "No effect,Clear" rbitfld.long 0x08 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA channel 2" "No effect,Clear" rbitfld.long 0x08 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA channel 1" "No effect,Clear" newline rbitfld.long 0x08 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA channel 0" "No effect,Clear" bitfld.long 0x08 15. " CH15_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 15" "No effect,Clear" bitfld.long 0x08 14. " CH14_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 14" "No effect,Clear" newline bitfld.long 0x08 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 13" "No effect,Clear" bitfld.long 0x08 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 12" "No effect,Clear" bitfld.long 0x08 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 11" "No effect,Clear" newline bitfld.long 0x08 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 10" "No effect,Clear" bitfld.long 0x08 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 9" "No effect,Clear" bitfld.long 0x08 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 8" "No effect,Clear" newline bitfld.long 0x08 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 7" "No effect,Clear" bitfld.long 0x08 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 6" "No effect,Clear" bitfld.long 0x08 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 5" "No effect,Clear" newline bitfld.long 0x08 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 4" "No effect,Clear" bitfld.long 0x08 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 3" "No effect,Clear" bitfld.long 0x08 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 2" "No effect,Clear" newline bitfld.long 0x08 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 1" "No effect,Clear" bitfld.long 0x08 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 0" "No effect,Clear" line.long 0x0C "CTRL2_TOG,AHB To APBH Bridge Control And Status Register 2" rbitfld.long 0x0C 31. " CH15_ERROR_STATUS ,Error status bit for APBH DMA channel 15" "No effect,Toggle" rbitfld.long 0x0C 30. " CH14_ERROR_STATUS ,Error status bit for APBH DMA channel 14" "No effect,Toggle" rbitfld.long 0x0C 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA channel 13" "No effect,Toggle" newline rbitfld.long 0x0C 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA channel 12" "No effect,Toggle" rbitfld.long 0x0C 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA channel 11" "No effect,Toggle" rbitfld.long 0x0C 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA channel 10" "No effect,Toggle" newline rbitfld.long 0x0C 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA channel 9" "No effect,Toggle" rbitfld.long 0x0C 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA channel 8" "No effect,Toggle" rbitfld.long 0x0C 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA channel 7" "No effect,Toggle" newline rbitfld.long 0x0C 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA channel 6" "No effect,Toggle" rbitfld.long 0x0C 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA channel 5" "No effect,Toggle" rbitfld.long 0x0C 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA channel 4" "No effect,Toggle" newline rbitfld.long 0x0C 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA channel 3" "No effect,Toggle" rbitfld.long 0x0C 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA channel 2" "No effect,Toggle" rbitfld.long 0x0C 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA channel 1" "No effect,Toggle" newline rbitfld.long 0x0C 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA channel 0" "No effect,Toggle" bitfld.long 0x0C 15. " CH15_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 15" "No effect,Toggle" bitfld.long 0x0C 14. " CH14_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 14" "No effect,Toggle" newline bitfld.long 0x0C 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 13" "No effect,Toggle" bitfld.long 0x0C 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 12" "No effect,Toggle" bitfld.long 0x0C 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 11" "No effect,Toggle" newline bitfld.long 0x0C 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 10" "No effect,Toggle" bitfld.long 0x0C 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 9" "No effect,Toggle" bitfld.long 0x0C 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 8" "No effect,Toggle" newline bitfld.long 0x0C 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 7" "No effect,Toggle" bitfld.long 0x0C 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 6" "No effect,Toggle" bitfld.long 0x0C 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 5" "No effect,Toggle" newline bitfld.long 0x0C 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 4" "No effect,Toggle" bitfld.long 0x0C 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 3" "No effect,Toggle" bitfld.long 0x0C 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 2" "No effect,Toggle" newline bitfld.long 0x0C 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 1" "No effect,Toggle" bitfld.long 0x0C 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 0" "No effect,Toggle" group.long 0x30++0x0F line.long 0x00 "CHANNEL_CTRL,AHB To APBH Bridge Channel Register" bitfld.long 0x00 24. " RESET_SSP ,Causes the DMA controller to take the SSP through its reset state" "No reset,Reset" bitfld.long 0x00 23. " RESET_NAND7 ,Causes the DMA controller to take the NAND7 through its reset state" "No reset,Reset" bitfld.long 0x00 22. " RESET_NAND6 ,Causes the DMA controller to take the NAND6 through its reset state" "No reset,Reset" newline bitfld.long 0x00 21. " RESET_NAND5 ,Causes the DMA controller to take the NAND5 through its reset state" "No reset,Reset" bitfld.long 0x00 20. " RESET_NAND4 ,Causes the DMA controller to take the NAND4 through its reset state" "No reset,Reset" bitfld.long 0x00 19. " RESET_NAND3 ,Causes the DMA controller to take the NAND3 through its reset state" "No reset,Reset" newline bitfld.long 0x00 18. " RESET_NAND2 ,Causes the DMA controller to take the NAND2 through its reset state" "No reset,Reset" bitfld.long 0x00 17. " RESET_NAND1 ,Causes the DMA controller to take the NAND1 through its reset state" "No reset,Reset" bitfld.long 0x00 16. " RESET_NAND0 ,Causes the DMA controller to take the NAND0 through its reset state" "No reset,Reset" newline bitfld.long 0x00 8. " FREEZE_SSP ,Freezes the SSP" "Not frozen,Frozen" bitfld.long 0x00 7. " FREEZE_NAND7 ,Freezes the NSND7" "Not frozen,Frozen" bitfld.long 0x00 6. " FREEZE_NAND6 ,Freezes the NSND6" "Not frozen,Frozen" newline bitfld.long 0x00 5. " FREEZE_NAND5 ,Freezes the NSND5" "Not frozen,Frozen" bitfld.long 0x00 4. " FREEZE_NAND4 ,Freezes the NSND4" "Not frozen,Frozen" bitfld.long 0x00 3. " FREEZE_NAND3 ,Freezes the NSND3" "Not frozen,Frozen" newline bitfld.long 0x00 2. " FREEZE_NAND2 ,Freezes the NSND2" "Not frozen,Frozen" bitfld.long 0x00 1. " FREEZE_NAND1 ,Freezes the NSND1" "Not frozen,Frozen" bitfld.long 0x00 0. " FREEZE_NAND0 ,Freezes the NSND0" "Not frozen,Frozen" line.long 0x04 "CHANNEL_CTRL_SET,AHB To APBH Bridge Channel Set Register" bitfld.long 0x04 24. " RESET_SSP ,Causes the DMA controller to take the SSP through its reset state" "No effect,Set" bitfld.long 0x04 23. " RESET_NAND7 ,Causes the DMA controller to take the NAND7 through its reset state" "No effect,Set" bitfld.long 0x04 22. " RESET_NAND6 ,Causes the DMA controller to take the NAND6 through its reset state" "No effect,Set" newline bitfld.long 0x04 21. " RESET_NAND5 ,Causes the DMA controller to take the NAND5 through its reset state" "No effect,Set" bitfld.long 0x04 20. " RESET_NAND4 ,Causes the DMA controller to take the NAND4 through its reset state" "No effect,Set" bitfld.long 0x04 19. " RESET_NAND3 ,Causes the DMA controller to take the NAND3 through its reset state" "No effect,Set" newline bitfld.long 0x04 18. " RESET_NAND2 ,Causes the DMA controller to take the NAND2 through its reset state" "No effect,Set" bitfld.long 0x04 17. " RESET_NAND1 ,Causes the DMA controller to take the NAND1 through its reset state" "No effect,Set" bitfld.long 0x04 16. " RESET_NAND0 ,Causes the DMA controller to take the NAND0 through its reset state" "No effect,Set" newline bitfld.long 0x04 8. " FREEZE_SSP ,Freezes the SSP" "No effect,Set" bitfld.long 0x04 7. " FREEZE_NAND7 ,Freezes the NSND7" "No effect,Set" bitfld.long 0x04 6. " FREEZE_NAND6 ,Freezes the NSND6" "No effect,Set" newline bitfld.long 0x04 5. " FREEZE_NAND5 ,Freezes the NSND5" "No effect,Set" bitfld.long 0x04 4. " FREEZE_NAND4 ,Freezes the NSND4" "No effect,Set" bitfld.long 0x04 3. " FREEZE_NAND3 ,Freezes the NSND3" "No effect,Set" newline bitfld.long 0x04 2. " FREEZE_NAND2 ,Freezes the NSND2" "No effect,Set" bitfld.long 0x04 1. " FREEZE_NAND1 ,Freezes the NSND1" "No effect,Set" bitfld.long 0x04 0. " FREEZE_NAND0 ,Freezes the NSND0" "No effect,Set" line.long 0x08 "CHANNEL_CTRL_CLR,AHB To APBH Bridge Channel Clear Register" bitfld.long 0x08 24. " RESET_SSP ,Causes the DMA controller to take the SSP through its reset state" "No effect,Clear" bitfld.long 0x08 23. " RESET_NAND7 ,Causes the DMA controller to take the NAND7 through its reset state" "No effect,Clear" bitfld.long 0x08 22. " RESET_NAND6 ,Causes the DMA controller to take the NAND6 through its reset state" "No effect,Clear" newline bitfld.long 0x08 21. " RESET_NAND5 ,Causes the DMA controller to take the NAND5 through its reset state" "No effect,Clear" bitfld.long 0x08 20. " RESET_NAND4 ,Causes the DMA controller to take the NAND4 through its reset state" "No effect,Clear" bitfld.long 0x08 19. " RESET_NAND3 ,Causes the DMA controller to take the NAND3 through its reset state" "No effect,Clear" newline bitfld.long 0x08 18. " RESET_NAND2 ,Causes the DMA controller to take the NAND2 through its reset state" "No effect,Clear" bitfld.long 0x08 17. " RESET_NAND1 ,Causes the DMA controller to take the NAND1 through its reset state" "No effect,Clear" bitfld.long 0x08 16. " RESET_NAND0 ,Causes the DMA controller to take the NAND0 through its reset state" "No effect,Clear" newline bitfld.long 0x08 8. " FREEZE_SSP ,Freezes the SSP" "No effect,Clear" bitfld.long 0x08 7. " FREEZE_NAND7 ,Freezes the NSND7" "No effect,Clear" bitfld.long 0x08 6. " FREEZE_NAND6 ,Freezes the NSND6" "No effect,Clear" newline bitfld.long 0x08 5. " FREEZE_NAND5 ,Freezes the NSND5" "No effect,Clear" bitfld.long 0x08 4. " FREEZE_NAND4 ,Freezes the NSND4" "No effect,Clear" bitfld.long 0x08 3. " FREEZE_NAND3 ,Freezes the NSND3" "No effect,Clear" newline bitfld.long 0x08 2. " FREEZE_NAND2 ,Freezes the NSND2" "No effect,Clear" bitfld.long 0x08 1. " FREEZE_NAND1 ,Freezes the NSND1" "No effect,Clear" bitfld.long 0x08 0. " FREEZE_NAND0 ,Freezes the NSND0" "No effect,Clear" line.long 0x0C "CHANNEL_CTRL_TOG,AHB To APBH Bridge Channel Toggle Register" bitfld.long 0x0C 24. " RESET_SSP ,Causes the DMA controller to take the SSP through its reset state" "No effect,Toggle" bitfld.long 0x0C 23. " RESET_NAND7 ,Causes the DMA controller to take the NAND7 through its reset state" "No effect,Toggle" bitfld.long 0x0C 22. " RESET_NAND6 ,Causes the DMA controller to take the NAND6 through its reset state" "No effect,Toggle" newline bitfld.long 0x0C 21. " RESET_NAND5 ,Causes the DMA controller to take the NAND5 through its reset state" "No effect,Toggle" bitfld.long 0x0C 20. " RESET_NAND4 ,Causes the DMA controller to take the NAND4 through its reset state" "No effect,Toggle" bitfld.long 0x0C 19. " RESET_NAND3 ,Causes the DMA controller to take the NAND3 through its reset state" "No effect,Toggle" newline bitfld.long 0x0C 18. " RESET_NAND2 ,Causes the DMA controller to take the NAND2 through its reset state" "No effect,Toggle" bitfld.long 0x0C 17. " RESET_NAND1 ,Causes the DMA controller to take the NAND1 through its reset state" "No effect,Toggle" bitfld.long 0x0C 16. " RESET_NAND0 ,Causes the DMA controller to take the NAND0 through its reset state" "No effect,Toggle" newline bitfld.long 0x0C 8. " FREEZE_SSP ,Freezes the SSP" "No effect,Toggle" bitfld.long 0x0C 7. " FREEZE_NAND7 ,Freezes the NSND7" "No effect,Toggle" bitfld.long 0x0C 6. " FREEZE_NAND6 ,Freezes the NSND6" "No effect,Toggle" newline bitfld.long 0x0C 5. " FREEZE_NAND5 ,Freezes the NSND5" "No effect,Toggle" bitfld.long 0x0C 4. " FREEZE_NAND4 ,Freezes the NSND4" "No effect,Toggle" bitfld.long 0x0C 3. " FREEZE_NAND3 ,Freezes the NSND3" "No effect,Toggle" newline bitfld.long 0x0C 2. " FREEZE_NAND2 ,Freezes the NSND2" "No effect,Toggle" bitfld.long 0x0C 1. " FREEZE_NAND1 ,Freezes the NSND1" "No effect,Toggle" bitfld.long 0x0C 0. " FREEZE_NAND0 ,Freezes the NSND0" "No effect,Toggle" group.long 0x50++0x03 line.long 0x00 "DMA_BURST_SIZE,AHB To APBH DMA Burst Size" bitfld.long 0x00 16.--17. " CH8 ,DMA burst size for SSP" "BURST0,BURST4,BURST8,?..." bitfld.long 0x00 14.--15. " CH7 ,DMA burst size for GPMI channel 7" ",BURST4,?..." bitfld.long 0x00 12.--13. " CH6 ,DMA burst size for GPMI channel 6" ",BURST4,?..." newline bitfld.long 0x00 10.--11. " CH5 ,DMA burst size for GPMI channel 5" ",BURST4,?..." bitfld.long 0x00 8.--9. " CH4 ,DMA burst size for GPMI channel 4" ",BURST4,?..." bitfld.long 0x00 6.--7. " CH3 ,DMA burst size for GPMI channel 3" ",BURST4,?..." newline bitfld.long 0x00 4.--5. " CH2 ,DMA burst size for GPMI channel 2" ",BURST4,?..." bitfld.long 0x00 2.--3. " CH1 ,DMA burst size for GPMI channel 1" ",BURST4,?..." bitfld.long 0x00 0.--1. " CH0 ,DMA burst size for GPMI channel 0" ",BURST4,?..." group.long 0x60++0x03 line.long 0x00 "DEBUG,AHB To APBH DMA Debug Register" bitfld.long 0x00 0. " GPMI_ONE_FIFO ,DMA FIFO sharing" "Own,Shared" newline rgroup.long 0x100++0x03 line.long 0x00 "CH0_CURCMDAR,APBH DMA Channel 0 Current Command Address Register" group.long (0x100+0x10)++0x03 line.long 0x00 "CH0_NXTCMDAR,APBH DMA Channel 0 Next Command Address Register" rgroup.long (0x100+0x20)++0x03 line.long 0x00 "CH0_CMD,APBH DMA Channel 0 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x100+0x30)++0x03 line.long 0x00 "CH0_BAR,APBH DMA Channel 0 Buffer Address Register" group.long (0x100+0x40)++0x03 line.long 0x00 "CH0_SEMA,APBH DMA Channel 0 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x100+0x50)++0x03 line.long 0x00 "CH0_DEBUG1,AHB To APBH DMA Channel 0 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x100+0x60)++0x03 line.long 0x00 "CH0_DEBUG2,AHB To APBH DMA Channel 0 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x170++0x03 line.long 0x00 "CH1_CURCMDAR,APBH DMA Channel 1 Current Command Address Register" group.long (0x170+0x10)++0x03 line.long 0x00 "CH1_NXTCMDAR,APBH DMA Channel 1 Next Command Address Register" rgroup.long (0x170+0x20)++0x03 line.long 0x00 "CH1_CMD,APBH DMA Channel 1 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x170+0x30)++0x03 line.long 0x00 "CH1_BAR,APBH DMA Channel 1 Buffer Address Register" group.long (0x170+0x40)++0x03 line.long 0x00 "CH1_SEMA,APBH DMA Channel 1 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x170+0x50)++0x03 line.long 0x00 "CH1_DEBUG1,AHB To APBH DMA Channel 1 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x170+0x60)++0x03 line.long 0x00 "CH1_DEBUG2,AHB To APBH DMA Channel 1 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x1E0++0x03 line.long 0x00 "CH2_CURCMDAR,APBH DMA Channel 2 Current Command Address Register" group.long (0x1E0+0x10)++0x03 line.long 0x00 "CH2_NXTCMDAR,APBH DMA Channel 2 Next Command Address Register" rgroup.long (0x1E0+0x20)++0x03 line.long 0x00 "CH2_CMD,APBH DMA Channel 2 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x1E0+0x30)++0x03 line.long 0x00 "CH2_BAR,APBH DMA Channel 2 Buffer Address Register" group.long (0x1E0+0x40)++0x03 line.long 0x00 "CH2_SEMA,APBH DMA Channel 2 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x1E0+0x50)++0x03 line.long 0x00 "CH2_DEBUG1,AHB To APBH DMA Channel 2 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x1E0+0x60)++0x03 line.long 0x00 "CH2_DEBUG2,AHB To APBH DMA Channel 2 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x250++0x03 line.long 0x00 "CH3_CURCMDAR,APBH DMA Channel 3 Current Command Address Register" group.long (0x250+0x10)++0x03 line.long 0x00 "CH3_NXTCMDAR,APBH DMA Channel 3 Next Command Address Register" rgroup.long (0x250+0x20)++0x03 line.long 0x00 "CH3_CMD,APBH DMA Channel 3 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x250+0x30)++0x03 line.long 0x00 "CH3_BAR,APBH DMA Channel 3 Buffer Address Register" group.long (0x250+0x40)++0x03 line.long 0x00 "CH3_SEMA,APBH DMA Channel 3 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x250+0x50)++0x03 line.long 0x00 "CH3_DEBUG1,AHB To APBH DMA Channel 3 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x250+0x60)++0x03 line.long 0x00 "CH3_DEBUG2,AHB To APBH DMA Channel 3 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x2C0++0x03 line.long 0x00 "CH4_CURCMDAR,APBH DMA Channel 4 Current Command Address Register" group.long (0x2C0+0x10)++0x03 line.long 0x00 "CH4_NXTCMDAR,APBH DMA Channel 4 Next Command Address Register" rgroup.long (0x2C0+0x20)++0x03 line.long 0x00 "CH4_CMD,APBH DMA Channel 4 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x2C0+0x30)++0x03 line.long 0x00 "CH4_BAR,APBH DMA Channel 4 Buffer Address Register" group.long (0x2C0+0x40)++0x03 line.long 0x00 "CH4_SEMA,APBH DMA Channel 4 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x2C0+0x50)++0x03 line.long 0x00 "CH4_DEBUG1,AHB To APBH DMA Channel 4 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x2C0+0x60)++0x03 line.long 0x00 "CH4_DEBUG2,AHB To APBH DMA Channel 4 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x330++0x03 line.long 0x00 "CH5_CURCMDAR,APBH DMA Channel 5 Current Command Address Register" group.long (0x330+0x10)++0x03 line.long 0x00 "CH5_NXTCMDAR,APBH DMA Channel 5 Next Command Address Register" rgroup.long (0x330+0x20)++0x03 line.long 0x00 "CH5_CMD,APBH DMA Channel 5 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x330+0x30)++0x03 line.long 0x00 "CH5_BAR,APBH DMA Channel 5 Buffer Address Register" group.long (0x330+0x40)++0x03 line.long 0x00 "CH5_SEMA,APBH DMA Channel 5 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x330+0x50)++0x03 line.long 0x00 "CH5_DEBUG1,AHB To APBH DMA Channel 5 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x330+0x60)++0x03 line.long 0x00 "CH5_DEBUG2,AHB To APBH DMA Channel 5 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x3A0++0x03 line.long 0x00 "CH6_CURCMDAR,APBH DMA Channel 6 Current Command Address Register" group.long (0x3A0+0x10)++0x03 line.long 0x00 "CH6_NXTCMDAR,APBH DMA Channel 6 Next Command Address Register" rgroup.long (0x3A0+0x20)++0x03 line.long 0x00 "CH6_CMD,APBH DMA Channel 6 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x3A0+0x30)++0x03 line.long 0x00 "CH6_BAR,APBH DMA Channel 6 Buffer Address Register" group.long (0x3A0+0x40)++0x03 line.long 0x00 "CH6_SEMA,APBH DMA Channel 6 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x3A0+0x50)++0x03 line.long 0x00 "CH6_DEBUG1,AHB To APBH DMA Channel 6 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x3A0+0x60)++0x03 line.long 0x00 "CH6_DEBUG2,AHB To APBH DMA Channel 6 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x410++0x03 line.long 0x00 "CH7_CURCMDAR,APBH DMA Channel 7 Current Command Address Register" group.long (0x410+0x10)++0x03 line.long 0x00 "CH7_NXTCMDAR,APBH DMA Channel 7 Next Command Address Register" rgroup.long (0x410+0x20)++0x03 line.long 0x00 "CH7_CMD,APBH DMA Channel 7 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x410+0x30)++0x03 line.long 0x00 "CH7_BAR,APBH DMA Channel 7 Buffer Address Register" group.long (0x410+0x40)++0x03 line.long 0x00 "CH7_SEMA,APBH DMA Channel 7 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x410+0x50)++0x03 line.long 0x00 "CH7_DEBUG1,AHB To APBH DMA Channel 7 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x410+0x60)++0x03 line.long 0x00 "CH7_DEBUG2,AHB To APBH DMA Channel 7 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x480++0x03 line.long 0x00 "CH8_CURCMDAR,APBH DMA Channel 8 Current Command Address Register" group.long (0x480+0x10)++0x03 line.long 0x00 "CH8_NXTCMDAR,APBH DMA Channel 8 Next Command Address Register" rgroup.long (0x480+0x20)++0x03 line.long 0x00 "CH8_CMD,APBH DMA Channel 8 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x480+0x30)++0x03 line.long 0x00 "CH8_BAR,APBH DMA Channel 8 Buffer Address Register" group.long (0x480+0x40)++0x03 line.long 0x00 "CH8_SEMA,APBH DMA Channel 8 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x480+0x50)++0x03 line.long 0x00 "CH8_DEBUG1,AHB To APBH DMA Channel 8 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x480+0x60)++0x03 line.long 0x00 "CH8_DEBUG2,AHB To APBH DMA Channel 8 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x4F0++0x03 line.long 0x00 "CH9_CURCMDAR,APBH DMA Channel 9 Current Command Address Register" group.long (0x4F0+0x10)++0x03 line.long 0x00 "CH9_NXTCMDAR,APBH DMA Channel 9 Next Command Address Register" rgroup.long (0x4F0+0x20)++0x03 line.long 0x00 "CH9_CMD,APBH DMA Channel 9 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x4F0+0x30)++0x03 line.long 0x00 "CH9_BAR,APBH DMA Channel 9 Buffer Address Register" group.long (0x4F0+0x40)++0x03 line.long 0x00 "CH9_SEMA,APBH DMA Channel 9 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x4F0+0x50)++0x03 line.long 0x00 "CH9_DEBUG1,AHB To APBH DMA Channel 9 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x4F0+0x60)++0x03 line.long 0x00 "CH9_DEBUG2,AHB To APBH DMA Channel 9 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x560++0x03 line.long 0x00 "CH10_CURCMDAR,APBH DMA Channel 10 Current Command Address Register" group.long (0x560+0x10)++0x03 line.long 0x00 "CH10_NXTCMDAR,APBH DMA Channel 10 Next Command Address Register" rgroup.long (0x560+0x20)++0x03 line.long 0x00 "CH10_CMD,APBH DMA Channel 10 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x560+0x30)++0x03 line.long 0x00 "CH10_BAR,APBH DMA Channel 10 Buffer Address Register" group.long (0x560+0x40)++0x03 line.long 0x00 "CH10_SEMA,APBH DMA Channel 10 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x560+0x50)++0x03 line.long 0x00 "CH10_DEBUG1,AHB To APBH DMA Channel 10 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x560+0x60)++0x03 line.long 0x00 "CH10_DEBUG2,AHB To APBH DMA Channel 10 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x5D0++0x03 line.long 0x00 "CH11_CURCMDAR,APBH DMA Channel 11 Current Command Address Register" group.long (0x5D0+0x10)++0x03 line.long 0x00 "CH11_NXTCMDAR,APBH DMA Channel 11 Next Command Address Register" rgroup.long (0x5D0+0x20)++0x03 line.long 0x00 "CH11_CMD,APBH DMA Channel 11 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x5D0+0x30)++0x03 line.long 0x00 "CH11_BAR,APBH DMA Channel 11 Buffer Address Register" group.long (0x5D0+0x40)++0x03 line.long 0x00 "CH11_SEMA,APBH DMA Channel 11 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x5D0+0x50)++0x03 line.long 0x00 "CH11_DEBUG1,AHB To APBH DMA Channel 11 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x5D0+0x60)++0x03 line.long 0x00 "CH11_DEBUG2,AHB To APBH DMA Channel 11 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x640++0x03 line.long 0x00 "CH12_CURCMDAR,APBH DMA Channel 12 Current Command Address Register" group.long (0x640+0x10)++0x03 line.long 0x00 "CH12_NXTCMDAR,APBH DMA Channel 12 Next Command Address Register" rgroup.long (0x640+0x20)++0x03 line.long 0x00 "CH12_CMD,APBH DMA Channel 12 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x640+0x30)++0x03 line.long 0x00 "CH12_BAR,APBH DMA Channel 12 Buffer Address Register" group.long (0x640+0x40)++0x03 line.long 0x00 "CH12_SEMA,APBH DMA Channel 12 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x640+0x50)++0x03 line.long 0x00 "CH12_DEBUG1,AHB To APBH DMA Channel 12 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x640+0x60)++0x03 line.long 0x00 "CH12_DEBUG2,AHB To APBH DMA Channel 12 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x6B0++0x03 line.long 0x00 "CH13_CURCMDAR,APBH DMA Channel 13 Current Command Address Register" group.long (0x6B0+0x10)++0x03 line.long 0x00 "CH13_NXTCMDAR,APBH DMA Channel 13 Next Command Address Register" rgroup.long (0x6B0+0x20)++0x03 line.long 0x00 "CH13_CMD,APBH DMA Channel 13 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x6B0+0x30)++0x03 line.long 0x00 "CH13_BAR,APBH DMA Channel 13 Buffer Address Register" group.long (0x6B0+0x40)++0x03 line.long 0x00 "CH13_SEMA,APBH DMA Channel 13 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x6B0+0x50)++0x03 line.long 0x00 "CH13_DEBUG1,AHB To APBH DMA Channel 13 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x6B0+0x60)++0x03 line.long 0x00 "CH13_DEBUG2,AHB To APBH DMA Channel 13 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x720++0x03 line.long 0x00 "CH14_CURCMDAR,APBH DMA Channel 14 Current Command Address Register" group.long (0x720+0x10)++0x03 line.long 0x00 "CH14_NXTCMDAR,APBH DMA Channel 14 Next Command Address Register" rgroup.long (0x720+0x20)++0x03 line.long 0x00 "CH14_CMD,APBH DMA Channel 14 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x720+0x30)++0x03 line.long 0x00 "CH14_BAR,APBH DMA Channel 14 Buffer Address Register" group.long (0x720+0x40)++0x03 line.long 0x00 "CH14_SEMA,APBH DMA Channel 14 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x720+0x50)++0x03 line.long 0x00 "CH14_DEBUG1,AHB To APBH DMA Channel 14 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x720+0x60)++0x03 line.long 0x00 "CH14_DEBUG2,AHB To APBH DMA Channel 14 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x790++0x03 line.long 0x00 "CH15_CURCMDAR,APBH DMA Channel 15 Current Command Address Register" group.long (0x790+0x10)++0x03 line.long 0x00 "CH15_NXTCMDAR,APBH DMA Channel 15 Next Command Address Register" rgroup.long (0x790+0x20)++0x03 line.long 0x00 "CH15_CMD,APBH DMA Channel 15 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x790+0x30)++0x03 line.long 0x00 "CH15_BAR,APBH DMA Channel 15 Buffer Address Register" group.long (0x790+0x40)++0x03 line.long 0x00 "CH15_SEMA,APBH DMA Channel 15 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x790+0x50)++0x03 line.long 0x00 "CH15_DEBUG1,AHB To APBH DMA Channel 15 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x790+0x60)++0x03 line.long 0x00 "CH15_DEBUG2,AHB To APBH DMA Channel 15 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" group.long 0x800++0x03 line.long 0x00 "VERSION,APBH Bridge Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Reflects the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Reflects the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Reflects the stepping of the RTL version" width 0x0B tree.end tree "BCH (62BIT Correcting ECC Accelrator)" base ad:0x33004000 width 20. group.long 0x00++0x0F line.long 0x00 "CTRL,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x00 31. " SFTRST ,Disables clocking with the BCH and hold it in its reset state" "RUN,RESET" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "RUN,NO_CLKS" bitfld.long 0x00 22. " DEBUGSYNDROME ,Enables write of computed syndromes to memory on BCH decode operations" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " M2M_LAYOUT ,Selects the flash page format for memory-to-memory operations" "0,1,2,3" bitfld.long 0x00 17. " M2M_ENCODE ,Selects encode or decode mode for memory-to-memory operations" "Decoded,Encoded" bitfld.long 0x00 16. " M2M_ENABLE ,Memory-to-memory operation enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "Disabled,Enabled" bitfld.long 0x00 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "Disabled,Enabled" bitfld.long 0x00 3. " BM_ERROR_IRQ ,AHB bus interface error interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " DEBUG_STALL_IRQ ,DEBUG STALL interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 0. " COMPLETE_IRQ ,Indicates the state of the external interrupt line" "No interrupt,Interrupt" line.long 0x04 "CTRL_SET,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x04 31. " SFTRST ,Disables clocking with the BCH and hold it in its reset state" "RUN,RESET" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "RUN,NO_CLKS" bitfld.long 0x04 22. " DEBUGSYNDROME ,Enables write of computed syndromes to memory on BCH decode operations" "Disabled,Enabled" newline bitfld.long 0x04 18.--19. " M2M_LAYOUT ,Selects the flash page format for memory-to-memory operations" "0,1,2,3" bitfld.long 0x04 17. " M2M_ENCODE ,Selects encode or decode mode for memory-to-memory operations" "Decoded,Encoded" bitfld.long 0x04 16. " M2M_ENABLE ,Memory-to-memory operation enable" "Disabled,Enabled" newline bitfld.long 0x04 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "Disabled,Enabled" bitfld.long 0x04 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "Disabled,Enabled" bitfld.long 0x04 3. " BM_ERROR_IRQ ,AHB bus interface error interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x04 2. " DEBUG_STALL_IRQ ,DEBUG STALL interrupt status" "No interrupt,Interrupt" bitfld.long 0x04 0. " COMPLETE_IRQ ,Indicates the state of the external interrupt line" "No interrupt,Interrupt" line.long 0x08 "CTRL_CLR,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x08 31. " SFTRST ,Disables clocking with the BCH and hold it in its reset state" "RUN,RESET" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "RUN,NO_CLKS" bitfld.long 0x08 22. " DEBUGSYNDROME ,Enables write of computed syndromes to memory on BCH decode operations" "Disabled,Enabled" newline bitfld.long 0x08 18.--19. " M2M_LAYOUT ,Selects the flash page format for memory-to-memory operations" "0,1,2,3" bitfld.long 0x08 17. " M2M_ENCODE ,Selects encode or decode mode for memory-to-memory operations" "Decoded,Encoded" bitfld.long 0x08 16. " M2M_ENABLE ,Memory-to-memory operation enable" "Disabled,Enabled" newline bitfld.long 0x08 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "Disabled,Enabled" bitfld.long 0x08 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "Disabled,Enabled" bitfld.long 0x08 3. " BM_ERROR_IRQ ,AHB bus interface error interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x08 2. " DEBUG_STALL_IRQ ,DEBUG STALL interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 0. " COMPLETE_IRQ ,Indicates the state of the external interrupt line" "No interrupt,Interrupt" line.long 0x0C "CTRL_TOG,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x0C 31. " SFTRST ,Disables clocking with the BCH and hold it in its reset state" "RUN,RESET" bitfld.long 0x0C 30. " CLKGATE ,Gates off the clocks to the block" "RUN,NO_CLKS" bitfld.long 0x0C 22. " DEBUGSYNDROME ,Enables write of computed syndromes to memory on BCH decode operations" "Disabled,Enabled" newline bitfld.long 0x0C 18.--19. " M2M_LAYOUT ,Selects the flash page format for memory-to-memory operations" "0,1,2,3" bitfld.long 0x0C 17. " M2M_ENCODE ,Selects encode or decode mode for memory-to-memory operations" "Decoded,Encoded" bitfld.long 0x0C 16. " M2M_ENABLE ,Memory-to-memory operation enable" "Disabled,Enabled" newline bitfld.long 0x0C 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "Disabled,Enabled" bitfld.long 0x0C 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "Disabled,Enabled" bitfld.long 0x0C 3. " BM_ERROR_IRQ ,AHB bus interface error interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x0C 2. " DEBUG_STALL_IRQ ,DEBUG STALL interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 0. " COMPLETE_IRQ ,Indicates the state of the external interrupt line" "No interrupt,Interrupt" rgroup.long 0x10++0x0F line.long 0x00 "STATUS0,Hardware ECC Accelerator Status Register 0" hexmask.long.word 0x00 20.--31. 1. " HANDLE ,A part of the GPMI DMA PIO operation that started the transaction" bitfld.long 0x00 16.--19. " COMPLETED_CE ,Chip enable number corresponding to the NAND device from which this data came" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " STATUS_BLK0 ,Count of symbols in error during processing of first block of flash" newline bitfld.long 0x00 4. " ALLONES ,Indicates whether all data bits of this transaction are ONE" "No,Yes" bitfld.long 0x00 3. " CORRECTED ,Indicates whether at least one correctable error encountered during last processing cycle" "No,Yes" bitfld.long 0x00 2. " UNCORRECTABLE ,Indicates whether uncorrectable error encountered during last processing cycle" "No,Yes" line.long 0x04 "STATUS0_SET,Hardware ECC Accelerator Status Register 0" hexmask.long.word 0x04 20.--31. 1. " HANDLE ,A part of the GPMI DMA PIO operation that started the transaction" bitfld.long 0x04 16.--19. " COMPLETED_CE ,Chip enable number corresponding to the NAND device from which this data came" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 8.--15. 1. " STATUS_BLK0 ,Count of symbols in error during processing of first block of flash" newline bitfld.long 0x04 4. " ALLONES ,Indicates whether all data bits of this transaction are ONE" "No,Yes" bitfld.long 0x04 3. " CORRECTED ,Indicates whether at least one correctable error encountered during last processing cycle" "No,Yes" bitfld.long 0x04 2. " UNCORRECTABLE ,Indicates whether uncorrectable error encountered during last processing cycle" "No,Yes" line.long 0x08 "STATUS0_CLR,Hardware ECC Accelerator Status Register 0" hexmask.long.word 0x08 20.--31. 1. " HANDLE ,A part of the GPMI DMA PIO operation that started the transaction" bitfld.long 0x08 16.--19. " COMPLETED_CE ,Chip enable number corresponding to the NAND device from which this data came" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 8.--15. 1. " STATUS_BLK0 ,Count of symbols in error during processing of first block of flash" newline bitfld.long 0x08 4. " ALLONES ,Indicates whether all data bits of this transaction are ONE" "No,Yes" bitfld.long 0x08 3. " CORRECTED ,Indicates whether at least one correctable error encountered during last processing cycle" "No,Yes" bitfld.long 0x08 2. " UNCORRECTABLE ,Indicates whether uncorrectable error encountered during last processing cycle" "No,Yes" line.long 0x0C "STATUS0_TOG,Hardware ECC Accelerator Status Register 0" hexmask.long.word 0x0C 20.--31. 1. " HANDLE ,A part of the GPMI DMA PIO operation that started the transaction" bitfld.long 0x0C 16.--19. " COMPLETED_CE ,Chip enable number corresponding to the NAND device from which this data came" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0C 8.--15. 1. " STATUS_BLK0 ,Count of symbols in error during processing of first block of flash" newline bitfld.long 0x0C 4. " ALLONES ,Indicates whether all data bits of this transaction are ONE" "No,Yes" bitfld.long 0x0C 3. " CORRECTED ,Indicates whether at least one correctable error encountered during last processing cycle" "No,Yes" bitfld.long 0x0C 2. " UNCORRECTABLE ,Indicates whether uncorrectable error encountered during last processing cycle" "No,Yes" group.long 0x20++0x0F line.long 0x00 "MODE,Hardware ECC Accelerator Mode Register" hexmask.long.byte 0x00 0.--7. 1. " ERASE_THRESHOLD ,Indicates the maximum number of zero bits on a flash subpage for it to be considered erased" line.long 0x04 "MODE_SET,Hardware ECC Accelerator Mode Register" hexmask.long.byte 0x04 0.--7. 1. " ERASE_THRESHOLD ,Indicates the maximum number of zero bits on a flash subpage for it to be considered erased" line.long 0x08 "MODE_CLR,Hardware ECC Accelerator Mode Register" hexmask.long.byte 0x08 0.--7. 1. " ERASE_THRESHOLD ,Indicates the maximum number of zero bits on a flash subpage for it to be considered erased" line.long 0x0C "MODE_TOG,Hardware ECC Accelerator Mode Register" hexmask.long.byte 0x0C 0.--7. 1. " ERASE_THRESHOLD ,Indicates the maximum number of zero bits on a flash subpage for it to be considered erased" group.long 0x30++0x0F line.long 0x00 "ENCODEPTR,Hardware BCH ECC Loopback Encode Buffer Register" line.long 0x04 "ENCODEPTR_SET,Hardware BCH ECC Loopback Encode Buffer Register" line.long 0x08 "ENCODEPTR_CLR,Hardware BCH ECC Loopback Encode Buffer Register" line.long 0x0C "ENCODEPTR_TOG,Hardware BCH ECC Loopback Encode Buffer Register" group.long 0x40++0x0F line.long 0x00 "DATAPTR,Hardware BCH ECC Loopback Data Buffer Register" line.long 0x04 "DATAPTR_SET,Hardware BCH ECC Loopback Data Buffer Register" line.long 0x08 "DATAPTR_CLR,Hardware BCH ECC Loopback Data Buffer Register" line.long 0x0C "DATAPTR_TOG,Hardware BCH ECC Loopback Data Buffer Register" group.long 0x50++0x0F line.long 0x00 "METAPTR,Hardware BCH ECC Loopback Metadata Buffer Register" line.long 0x04 "METAPTR_SET,Hardware BCH ECC Loopback Metadata Buffer Register" line.long 0x08 "METAPTR_CLR,Hardware BCH ECC Loopback Metadata Buffer Register" line.long 0x0C "METAPTR_TOG,Hardware BCH ECC Loopback Metadata Buffer Register" group.long 0x70++0x0F line.long 0x00 "LAYOUTSELECT,Hardware ECC Accelerator Layout Select Register" bitfld.long 0x00 30.--31. " CS15_SELECT ,Selects which layout is used for chip select 15" "0,1,2,3" bitfld.long 0x00 28.--29. " CS14_SELECT ,Selects which layout is used for chip select 14" "0,1,2,3" bitfld.long 0x00 26.--27. " CS13_SELECT ,Selects which layout is used for chip select 13" "0,1,2,3" bitfld.long 0x00 24.--25. " CS12_SELECT ,Selects which layout is used for chip select 12" "0,1,2,3" newline bitfld.long 0x00 22.--23. " CS11_SELECT ,Selects which layout is used for chip select 11" "0,1,2,3" bitfld.long 0x00 20.--21. " CS10_SELECT ,Selects which layout is used for chip select 10" "0,1,2,3" bitfld.long 0x00 18.--19. " CS9_SELECT ,Selects which layout is used for chip select 9" "0,1,2,3" bitfld.long 0x00 16.--17. " CS8_SELECT ,Selects which layout is used for chip select 8" "0,1,2,3" newline bitfld.long 0x00 14.--15. " CS7_SELECT ,Selects which layout is used for chip select 7" "0,1,2,3" bitfld.long 0x00 12.--13. " CS6_SELECT ,Selects which layout is used for chip select 6" "0,1,2,3" bitfld.long 0x00 10.--11. " CS5_SELECT ,Selects which layout is used for chip select 5" "0,1,2,3" bitfld.long 0x00 8.--9. " CS4_SELECT ,Selects which layout is used for chip select 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. " CS3_SELECT ,Selects which layout is used for chip select 3" "0,1,2,3" bitfld.long 0x00 4.--5. " CS2_SELECT ,Selects which layout is used for chip select 2" "0,1,2,3" bitfld.long 0x00 2.--3. " CS1_SELECT ,Selects which layout is used for chip select 1" "0,1,2,3" bitfld.long 0x00 0.--1. " CS0_SELECT ,Selects which layout is used for chip select 0" "0,1,2,3" line.long 0x04 "LAYOUTSELECT_SET,Hardware ECC Accelerator Layout Select Register" bitfld.long 0x04 30.--31. " CS15_SELECT ,Selects which layout is used for chip select 15" "0,1,2,3" bitfld.long 0x04 28.--29. " CS14_SELECT ,Selects which layout is used for chip select 14" "0,1,2,3" bitfld.long 0x04 26.--27. " CS13_SELECT ,Selects which layout is used for chip select 13" "0,1,2,3" bitfld.long 0x04 24.--25. " CS12_SELECT ,Selects which layout is used for chip select 12" "0,1,2,3" newline bitfld.long 0x04 22.--23. " CS11_SELECT ,Selects which layout is used for chip select 11" "0,1,2,3" bitfld.long 0x04 20.--21. " CS10_SELECT ,Selects which layout is used for chip select 10" "0,1,2,3" bitfld.long 0x04 18.--19. " CS9_SELECT ,Selects which layout is used for chip select 9" "0,1,2,3" bitfld.long 0x04 16.--17. " CS8_SELECT ,Selects which layout is used for chip select 8" "0,1,2,3" newline bitfld.long 0x04 14.--15. " CS7_SELECT ,Selects which layout is used for chip select 7" "0,1,2,3" bitfld.long 0x04 12.--13. " CS6_SELECT ,Selects which layout is used for chip select 6" "0,1,2,3" bitfld.long 0x04 10.--11. " CS5_SELECT ,Selects which layout is used for chip select 5" "0,1,2,3" bitfld.long 0x04 8.--9. " CS4_SELECT ,Selects which layout is used for chip select 4" "0,1,2,3" newline bitfld.long 0x04 6.--7. " CS3_SELECT ,Selects which layout is used for chip select 3" "0,1,2,3" bitfld.long 0x04 4.--5. " CS2_SELECT ,Selects which layout is used for chip select 2" "0,1,2,3" bitfld.long 0x04 2.--3. " CS1_SELECT ,Selects which layout is used for chip select 1" "0,1,2,3" bitfld.long 0x04 0.--1. " CS0_SELECT ,Selects which layout is used for chip select 0" "0,1,2,3" line.long 0x08 "LAYOUTSELECT_CLR,Hardware ECC Accelerator Layout Select Register" bitfld.long 0x08 30.--31. " CS15_SELECT ,Selects which layout is used for chip select 15" "0,1,2,3" bitfld.long 0x08 28.--29. " CS14_SELECT ,Selects which layout is used for chip select 14" "0,1,2,3" bitfld.long 0x08 26.--27. " CS13_SELECT ,Selects which layout is used for chip select 13" "0,1,2,3" bitfld.long 0x08 24.--25. " CS12_SELECT ,Selects which layout is used for chip select 12" "0,1,2,3" newline bitfld.long 0x08 22.--23. " CS11_SELECT ,Selects which layout is used for chip select 11" "0,1,2,3" bitfld.long 0x08 20.--21. " CS10_SELECT ,Selects which layout is used for chip select 10" "0,1,2,3" bitfld.long 0x08 18.--19. " CS9_SELECT ,Selects which layout is used for chip select 9" "0,1,2,3" bitfld.long 0x08 16.--17. " CS8_SELECT ,Selects which layout is used for chip select 8" "0,1,2,3" newline bitfld.long 0x08 14.--15. " CS7_SELECT ,Selects which layout is used for chip select 7" "0,1,2,3" bitfld.long 0x08 12.--13. " CS6_SELECT ,Selects which layout is used for chip select 6" "0,1,2,3" bitfld.long 0x08 10.--11. " CS5_SELECT ,Selects which layout is used for chip select 5" "0,1,2,3" bitfld.long 0x08 8.--9. " CS4_SELECT ,Selects which layout is used for chip select 4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " CS3_SELECT ,Selects which layout is used for chip select 3" "0,1,2,3" bitfld.long 0x08 4.--5. " CS2_SELECT ,Selects which layout is used for chip select 2" "0,1,2,3" bitfld.long 0x08 2.--3. " CS1_SELECT ,Selects which layout is used for chip select 1" "0,1,2,3" bitfld.long 0x08 0.--1. " CS0_SELECT ,Selects which layout is used for chip select 0" "0,1,2,3" line.long 0x0C "LAYOUTSELECT_TOG,Hardware ECC Accelerator Layout Select Register" bitfld.long 0x0C 30.--31. " CS15_SELECT ,Selects which layout is used for chip select 15" "0,1,2,3" bitfld.long 0x0C 28.--29. " CS14_SELECT ,Selects which layout is used for chip select 14" "0,1,2,3" bitfld.long 0x0C 26.--27. " CS13_SELECT ,Selects which layout is used for chip select 13" "0,1,2,3" bitfld.long 0x0C 24.--25. " CS12_SELECT ,Selects which layout is used for chip select 12" "0,1,2,3" newline bitfld.long 0x0C 22.--23. " CS11_SELECT ,Selects which layout is used for chip select 11" "0,1,2,3" bitfld.long 0x0C 20.--21. " CS10_SELECT ,Selects which layout is used for chip select 10" "0,1,2,3" bitfld.long 0x0C 18.--19. " CS9_SELECT ,Selects which layout is used for chip select 9" "0,1,2,3" bitfld.long 0x0C 16.--17. " CS8_SELECT ,Selects which layout is used for chip select 8" "0,1,2,3" newline bitfld.long 0x0C 14.--15. " CS7_SELECT ,Selects which layout is used for chip select 7" "0,1,2,3" bitfld.long 0x0C 12.--13. " CS6_SELECT ,Selects which layout is used for chip select 6" "0,1,2,3" bitfld.long 0x0C 10.--11. " CS5_SELECT ,Selects which layout is used for chip select 5" "0,1,2,3" bitfld.long 0x0C 8.--9. " CS4_SELECT ,Selects which layout is used for chip select 4" "0,1,2,3" newline bitfld.long 0x0C 6.--7. " CS3_SELECT ,Selects which layout is used for chip select 3" "0,1,2,3" bitfld.long 0x0C 4.--5. " CS2_SELECT ,Selects which layout is used for chip select 2" "0,1,2,3" bitfld.long 0x0C 2.--3. " CS1_SELECT ,Selects which layout is used for chip select 1" "0,1,2,3" bitfld.long 0x0C 0.--1. " CS0_SELECT ,Selects which layout is used for chip select 0" "0,1,2,3" group.long 0x80++0x0F line.long 0x00 "FLASH0LAYOUT0,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x00 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH0LAYOUT0_SET,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x04 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x04 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x04 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH0LAYOUT0_CLR,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x08 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x08 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x08 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH0LAYOUT0_TOG,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x0C 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x0C 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" group.long 0x90++0x0F line.long 0x00 "FLASH0LAYOUT1,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x00 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH0LAYOUT1_SET,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x04 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x04 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH0LAYOUT1_CLR,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x08 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x08 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH0LAYOUT1_TOG,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x0C 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x0C 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" group.long 0xA0++0x0F line.long 0x00 "FLASH1LAYOUT0,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x00 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH1LAYOUT0_SET,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x04 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x04 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x04 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH1LAYOUT0_CLR,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x08 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x08 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x08 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH1LAYOUT0_TOG,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x0C 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x0C 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" group.long 0xB0++0x0F line.long 0x00 "FLASH1LAYOUT1,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x00 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH1LAYOUT1_SET,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x04 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x04 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH1LAYOUT1_CLR,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x08 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x08 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH1LAYOUT1_TOG,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x0C 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x0C 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" group.long 0xC0++0x0F line.long 0x00 "FLASH2LAYOUT0,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x00 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH2LAYOUT0_SET,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x04 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x04 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x04 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH2LAYOUT0_CLR,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x08 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x08 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x08 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH2LAYOUT0_TOG,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x0C 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x0C 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" group.long 0xD0++0x0F line.long 0x00 "FLASH2LAYOUT1,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x00 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH2LAYOUT1_SET,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x04 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x04 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH2LAYOUT1_CLR,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x08 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x08 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH2LAYOUT1_TOG,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x0C 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x0C 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" group.long 0xE0++0x0F line.long 0x00 "FLASH3LAYOUT0,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x00 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH3LAYOUT0_SET,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x04 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x04 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x04 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH3LAYOUT0_CLR,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x08 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x08 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x08 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH3LAYOUT0_TOG,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x0C 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x0C 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" group.long 0xF0++0x0F line.long 0x00 "FLASH3LAYOUT1,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x00 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH3LAYOUT1_SET,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x04 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x04 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH3LAYOUT1_CLR,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x08 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x08 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH3LAYOUT1_TOG,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x0C 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x0C 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" newline group.long 0x100++0x0F line.long 0x00 "DEBUG0,Hardware BCH ECC Debug Register0" hexmask.long.word 0x00 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,Shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled" bitfld.long 0x00 15. " KES_DEBUG_SHIFT_SYND ,Toggle to shift BCH_DEBUG0_KES_SYNDROME_SYMBOL into the syndrome register array" "0,1" bitfld.long 0x00 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "Data,Auxiliary" newline bitfld.long 0x00 13. " KES_DEBUG_MODE4K ,Input mode" "4K NAND pages,2K NAND pages" bitfld.long 0x00 12. " KES_DEBUG_KICK ,Toggle to make KES engine FSM start as if kick by the bus master" "0,1" bitfld.long 0x00 11. " KES_STANDALONE ,Bus master address generator's operation mode" "NORMAL,TEST_MODE" newline bitfld.long 0x00 10. " KES_DEBUG_STEP ,Toggle to make KES FSM skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block" "0,1" bitfld.long 0x00 9. " KES_DEBUG_STALL ,Indicates whether KES FSM proceeds to next block supplied by bus master or waits" "NORMAL,WAIT" bitfld.long 0x00 8. " BM_KES_TEST_BYPASS ,BM_KES_TEST_BYPASS" "NORMAL,TEST_MODE" newline bitfld.long 0x00 0.--5. " DEBUG_REG_SELECT ,Selects the internal register state view of KES engine or the chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DEBUG0_SET,Hardware BCH ECC Debug Register0" hexmask.long.word 0x04 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,Shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled" bitfld.long 0x04 15. " KES_DEBUG_SHIFT_SYND ,Toggle to shift BCH_DEBUG0_KES_SYNDROME_SYMBOL into the syndrome register array" "0,1" bitfld.long 0x04 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "Data,Auxiliary" newline bitfld.long 0x04 13. " KES_DEBUG_MODE4K ,Input mode" "4K NAND pages,2K NAND pages" bitfld.long 0x04 12. " KES_DEBUG_KICK ,KES_DEBUG_KICK" "0,1" bitfld.long 0x04 11. " KES_STANDALONE ,Bus master address generator's operation mode" "Normal,Test" newline bitfld.long 0x04 10. " KES_DEBUG_STEP ,KES_DEBUG_STEP" "0,1" bitfld.long 0x04 9. " KES_DEBUG_STALL ,Indicates whether KES FSM proceeds to next block supplied by bus master or waits" "NORMAL,WAIT" bitfld.long 0x04 8. " BM_KES_TEST_BYPASS ,BM_KES_TEST_BYPASS" "0,1" newline bitfld.long 0x04 0.--5. " DEBUG_REG_SELECT ,Selects the internal register state view of KES engine or the chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DEBUG0_CLR,Hardware BCH ECC Debug Register0" hexmask.long.word 0x08 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,Shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled" bitfld.long 0x08 15. " KES_DEBUG_SHIFT_SYND ,Toggle to shift BCH_DEBUG0_KES_SYNDROME_SYMBOL into the syndrome register array" "0,1" bitfld.long 0x08 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "Data,Auxiliary" newline bitfld.long 0x08 13. " KES_DEBUG_MODE4K ,Input mode" "4K NAND pages,2K NAND pages" bitfld.long 0x08 12. " KES_DEBUG_KICK ,KES_DEBUG_KICK" "0,1" bitfld.long 0x08 11. " KES_STANDALONE ,Bus master address generator's operation mode" "Normal,Test" newline bitfld.long 0x08 10. " KES_DEBUG_STEP ,KES_DEBUG_STEP" "0,1" bitfld.long 0x08 9. " KES_DEBUG_STALL ,Indicates whether KES FSM proceeds to next block supplied by bus master or waits" "NORMAL,WAIT" bitfld.long 0x08 8. " BM_KES_TEST_BYPASS ,BM_KES_TEST_BYPASS" "0,1" newline bitfld.long 0x08 0.--5. " DEBUG_REG_SELECT ,Selects the internal register state view of KES engine or the chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "DEBUG0_TOG,Hardware BCH ECC Debug Register0" hexmask.long.word 0x0C 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,Shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled" bitfld.long 0x0C 15. " KES_DEBUG_SHIFT_SYND ,Toggle to shift BCH_DEBUG0_KES_SYNDROME_SYMBOL into the syndrome register array" "0,1" bitfld.long 0x0C 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "Data,Auxiliary" newline bitfld.long 0x0C 13. " KES_DEBUG_MODE4K ,Input mode" "4K NAND pages,2K NAND pages" bitfld.long 0x0C 12. " KES_DEBUG_KICK ,KES_DEBUG_KICK" "0,1" bitfld.long 0x0C 11. " KES_STANDALONE ,Bus master address generator's operation mode" "Normal,Test" newline bitfld.long 0x0C 10. " KES_DEBUG_STEP ,KES_DEBUG_STEP" "0,1" bitfld.long 0x0C 9. " KES_DEBUG_STALL ,Indicates whether KES FSM proceeds to next block supplied by bus master or waits" "NORMAL,WAIT" bitfld.long 0x0C 8. " BM_KES_TEST_BYPASS ,BM_KES_TEST_BYPASS" "0,1" newline bitfld.long 0x0C 0.--5. " DEBUG_REG_SELECT ,Selects the internal register state view of KES engine or the chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x110++0x0F line.long 0x00 "DBGKESREAD,KES Debug Read Register" line.long 0x04 "DBGKESREAD_SET,KES Debug Read Register" line.long 0x08 "DBGKESREAD_CLR,KES Debug Read Register" line.long 0x0C "DBGKESREAD_TOG,KES Debug Read Register" sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")||cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4")) rgroup.long 0x110++0x0F line.long 0x00 "DBGCSFEREAD,Chien Search Debug Read Register" line.long 0x04 "DBGCSFEREAD_SET,Chien Search Debug Read Register" line.long 0x08 "DBGCSFEREAD_CLR,Chien Search Debug Read Register" line.long 0x0C "DBGCSFEREAD_TOG,Chien Search Debug Read Register" rgroup.long 0x130++0x0F line.long 0x00 "DBGSYNDGENREAD,Syndrome Generator Debug Read Register" line.long 0x04 "DBGSYNDGENREAD_SET,Syndrome Generator Debug Read Register" line.long 0x08 "DBGSYNDGENREAD_CLR,Syndrome Generator Debug Read Register" line.long 0x0C "DBGSYNDGENREAD_TOG,Syndrome Generator Debug Read Register" rgroup.long 0x140++0x0F line.long 0x00 "DBGAHBMREAD,Bus Master and ECC Controller Debug Read Register" line.long 0x04 "DBGAHBMREAD_SET,Bus Master and ECC Controller Debug Read Register" line.long 0x08 "DBGAHBMREAD_CLR,Bus Master and ECC Controller Debug Read Register" line.long 0x0C "DBGAHBMREAD_TOG,Bus Master and ECC Controller Debug Read Register" endif rgroup.long 0x150++0x0F line.long 0x00 "BLOCKNAME,Block Name Register" line.long 0x04 "BLOCKNAME_SET,Block Name Register" line.long 0x08 "BLOCKNAME_CLR,Block Name Register" line.long 0x0C "BLOCKNAME_TOG,Block Name Register" rgroup.long 0x160++0x0F line.long 0x00 "VERSION,BCH Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Indicates the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Indicates the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Reflects the stepping of the RTL version" line.long 0x04 "VERSION_SET,BCH Version Register" hexmask.long.byte 0x04 24.--31. 1. " MAJOR ,Indicates the MAJOR field of the RTL version" hexmask.long.byte 0x04 16.--23. 1. " MINOR ,Indicates the MINOR field of the RTL version" hexmask.long.word 0x04 0.--15. 1. " STEP ,Reflects the stepping of the RTL version" line.long 0x08 "VERSION_CLR,BCH Version Register" hexmask.long.byte 0x08 24.--31. 1. " MAJOR ,Indicates the MAJOR field of the RTL version" hexmask.long.byte 0x08 16.--23. 1. " MINOR ,Indicates the MINOR field of the RTL version" hexmask.long.word 0x08 0.--15. 1. " STEP ,Reflects the stepping of the RTL version" line.long 0x0C "VERSION_TOG,BCH Version Register" hexmask.long.byte 0x0C 24.--31. 1. " MAJOR ,Indicates the MAJOR field of the RTL version" hexmask.long.byte 0x0C 16.--23. 1. " MINOR ,Indicates the MINOR field of the RTL version" hexmask.long.word 0x0C 0.--15. 1. " STEP ,Reflects the stepping of the RTL version" group.long 0x170++0x0F line.long 0x00 "DEBUG1,Hardware BCH ECC Debug Register 1" bitfld.long 0x00 31. " DEBUG1_PREERASECHK ,Enables pre-erase check" "Disabled,Enabled" hexmask.long.word 0x00 0.--8. 1. " ERASED_ZERO_COUNT ,The zero counts on one page" line.long 0x04 "DEBUG1_SET,Hardware BCH ECC Debug Register 1" bitfld.long 0x04 31. " DEBUG1_PREERASECHK ,Enables pre-erase check" "Disabled,Enabled" hexmask.long.word 0x04 0.--8. 1. " ERASED_ZERO_COUNT ,The zero counts on one page" line.long 0x08 "DEBUG1_CLR,Hardware BCH ECC Debug Register 1" bitfld.long 0x08 31. " DEBUG1_PREERASECHK ,Enables pre-erase check" "Disabled,Enabled" hexmask.long.word 0x08 0.--8. 1. " ERASED_ZERO_COUNT ,The zero counts on one page" line.long 0x0C "DEBUG1_TOG,Hardware BCH ECC Debug Register 1" bitfld.long 0x0C 31. " DEBUG1_PREERASECHK ,Enables pre-erase check" "Disabled,Enabled" hexmask.long.word 0x0C 0.--8. 1. " ERASED_ZERO_COUNT ,The zero counts on one page" width 0x0B tree.end tree "GPMI (General Purpose Media Interface)" base ad:0x33002000 width 13. group.long 0x00++0x13 line.long 0x00 "CTRL0,GPMI Control Register 0" bitfld.long 0x00 31. " SFTRST ,Soft reset" "Run,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock gate" "RUN,NO_CLKS" bitfld.long 0x00 29. " RUN ,GPMI busy running" "Idle,Busy" newline bitfld.long 0x00 28. " DEV_IRQ_EN ,DEV IRQ enable" "Disabled,Enabled" bitfld.long 0x00 27. " LOCK_CS ,Chip select lock bit" "Disabled,Enabled" bitfld.long 0x00 26. " UDMA ,ATA-Ultra DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x00 23. " WORD_LENGTH ,Data bus mode" ",8-bit" bitfld.long 0x00 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 17.--19. " ADDRESS ,Address" "NAND data,NAND CLE,NAND ALE,?..." bitfld.long 0x00 16. " ADDRESS_INCREMENT ,Address increment" "Not incremented,Incremented" hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer for this command" line.long 0x04 "CTRL0_SET,GPMI Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Soft reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock gate" "No effect,Set" bitfld.long 0x04 29. " RUN ,GPMI busy running" "No effect,Set" newline bitfld.long 0x04 28. " DEV_IRQ_EN ,DEV IRQ enable" "No effect,Set" bitfld.long 0x04 27. " TIMEOUT_IRQ_EN ,Timeout interrupt enable" "No effect,Set" bitfld.long 0x04 26. " UDMA ,ATA-Ultra DMA enable" "No effect,Set" newline bitfld.long 0x04 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x04 23. " WORD_LENGTH ,Data bus mode" ",8-bit" bitfld.long 0x04 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 17.--19. " ADDRESS ,Address" "NAND data,NAND CLE,NAND ALE,?..." bitfld.long 0x04 16. " ADDRESS_INCREMENT ,Address increment" "No effect,Set" hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer for this command" line.long 0x08 "CTRL0_CLR,GPMI Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Soft reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Clock gate" "No effect,Clear" bitfld.long 0x08 29. " RUN ,GPMI busy running" "No effect,Clear" newline bitfld.long 0x08 28. " DEV_IRQ_EN ,DEV IRQ enable" "No effect,Clear" bitfld.long 0x08 27. " LOCK_CS ,Chip select lock bit" "No effect,Clear" bitfld.long 0x08 26. " UDMA ,ATA-Ultra DMA enable" "No effect,Clear" newline bitfld.long 0x08 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x08 23. " WORD_LENGTH ,Data bus mode" ",8-bit" bitfld.long 0x08 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 17.--19. " ADDRESS ,Address" "NAND data,NAND CLE,NAND ALE,?..." bitfld.long 0x08 16. " ADDRESS_INCREMENT ,Address increment" "No effect,Clear" hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer for this command" line.long 0x0C "CTRL0_TOG,GPMI Control Toggle Register 0" bitfld.long 0x0C 31. " SFTRST ,Soft reset" "No effect,Toggle" bitfld.long 0x0C 30. " CLKGATE ,Clock gate" "No effect,Toggle" bitfld.long 0x0C 29. " RUN ,GPMI busy running" "No effect,Toggle" newline bitfld.long 0x0C 28. " DEV_IRQ_EN ,DEV IRQ enable" "No effect,Toggle" bitfld.long 0x0C 27. " LOCK_CS ,Chip select lock bit" "No effect,Toggle" bitfld.long 0x0C 26. " UDMA ,ATA-Ultra DMA enable" "No effect,Toggle" newline bitfld.long 0x0C 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x0C 23. " WORD_LENGTH ,Data bus mode" ",8-bit" bitfld.long 0x0C 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 17.--19. " ADDRESS ,Address" "NAND data,NAND CLE,NAND ALE,?..." bitfld.long 0x0C 16. " ADDRESS_INCREMENT ,Address increment" "No effect,Toggle" hexmask.long.word 0x0C 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer for this command" line.long 0x10 "COMPARE,GPMI Compare Register Description" hexmask.long.word 0x10 16.--31. 1. " MASK ,16-bit mask which is applied after the read data is XORed with the REFERENCE bit field" hexmask.long.word 0x10 0.--15. 1. " REFERENCE ,16-bit value which is XORed with data read from the NAND device" group.long 0x20++0x13 line.long 0x00 "ECCCTRL,GPMI Integrated ECC Control Register" hexmask.long.word 0x00 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x00 13.--14. " ECC_CMD ,ECC command information" "DECODE,ENCODE,?..." newline bitfld.long 0x00 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "Disabled,Enabled" bitfld.long 0x00 11. " RANDOMIZER_ENABLE ,Enable randomizer function" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RANDOMIZER_TYPE ,Set randomizer type" "0,1,2,?..." hexmask.long.word 0x00 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x04 "ECCCTRL_SET,GPMI Integrated ECC Control Set Register" hexmask.long.word 0x04 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x04 13.--14. " ECC_CMD ,ECC command information" "DECODE,ENCODE,?..." newline bitfld.long 0x04 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Set" bitfld.long 0x04 11. " RANDOMIZER_ENABLE ,Enable randomizer function" "Disabled,Enabled" bitfld.long 0x04 9.--10. " RANDOMIZER_TYPE ,Set randomizer type" "0,1,2,?..." hexmask.long.word 0x04 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x08 "ECCCTRL_CLR,GPMI Integrated ECC Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x08 13.--14. " ECC_CMD ,ECC command information" "DECODE,ENCODE,?..." newline bitfld.long 0x08 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Clear" bitfld.long 0x08 11. " RANDOMIZER_ENABLE ,Enable randomizer function" "Disabled,Enabled" bitfld.long 0x08 9.--10. " RANDOMIZER_TYPE ,Set randomizer type" "0,1,2,?..." hexmask.long.word 0x08 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x0C "ECCCTRL_TOG,GPMI Integrated ECC Control Toggle Register" hexmask.long.word 0x0C 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x0C 13.--14. " ECC_CMD ,ECC command information" "DECODE,ENCODE,?..." newline bitfld.long 0x0C 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Toggle" bitfld.long 0x0C 11. " RANDOMIZER_ENABLE ,Enable randomizer function" "Disabled,Enabled" bitfld.long 0x0C 9.--10. " RANDOMIZER_TYPE ,Set randomizer type" "0,1,2,?..." hexmask.long.word 0x0C 0.--8. 1. " BUFFER_MASK ,ECC buffer information" newline line.long 0x10 "ECCCOUNT,GPMI Integrated ECC Transfer Count Register" hexmask.long.byte 0x10 16.--23. 1. " RANDOMIZER_PAGE ,Set NAND page number needed to be randomized" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of bytes to pass through ECC" group.long 0x40++0x03 line.long 0x00 "PAYLOAD,GPMI Payload Address Register" hexmask.long 0x00 2.--31. 0x04 " ADDRESS ,Pointer to an array of one or more 512 byte payload buffers" group.long 0x50++0x03 line.long 0x00 "AUXILIARY,GPMI Auxiliary Address Register" hexmask.long 0x00 2.--31. 0x04 " ADDRESS ,Pointer to ECC control structure and meta-data storage" group.long 0x60++0x13 line.long 0x00 "CTRL1,GPMI Control Register 1" bitfld.long 0x00 31. " DEV_CLK_STOP ,Device clock stop" "Not stopped,Stopped" bitfld.long 0x00 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "Not stopped,Stopped" bitfld.long 0x00 29. " WRITE_CLK_STOP ,Stop clock during data write" "Not stopped,Stopped" newline bitfld.long 0x00 28. " TOGGLE_MODE ,Samsung toggle mode enable" "Disabled,Enabled" bitfld.long 0x00 27. " GPMI_CLK_DIV2_EN ,GPMI CLK divider enable" "Disabled,Enabled" bitfld.long 0x00 26. " UPDATE_CS ,Force CS value update" "Not updated,Updated" newline bitfld.long 0x00 25. " SSYNCMODE ,Source synchronous mode 1 or asynchronous mode 0" "ASYNC,SSYNC" bitfld.long 0x00 24. " DECOUPLE_CS ,Decouple chip select from DMA channel" "Disabled,Enabled" bitfld.long 0x00 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "~2ns,~4ns,~6ns,No delay" newline bitfld.long 0x00 21. " TEST_TRIGGER ,Test trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for transfers in ATA mode only and for WAIT_FOR_READY commands in both ATA and NAND mode" "Disabled,Enabled" bitfld.long 0x00 19. " GANGED_RDYBUSY ,NAND RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "Not forced,Forced" newline bitfld.long 0x00 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" ",BCH" bitfld.long 0x00 17. " DLL_ENABLE ,GPMI DLL enable bit" "Disabled,Enabled" bitfld.long 0x00 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "Disabled,Enabled" newline bitfld.long 0x00 12.--15. " RDN_DELAY ,Delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " DMA2ECC_MODE ,DMA ECC mode. DMA write data to redirected to HWECC module (instead of NAND device) for encoding or decoding" "NAND device,HWECC module" bitfld.long 0x00 10. " DEV_IRQ ,ATA device interrupt received" "No interrupt,Interrupt" newline bitfld.long 0x00 9. " TIMEOUT_IRQ ,Interrupt timeout" "No interrupt,Interrupt" bitfld.long 0x00 8. " BURST_EN ,4-transfer burst on APB bus enable" "Disabled,Enabled" bitfld.long 0x00 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "Not aborted,Aborted" newline bitfld.long 0x00 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " DEV_RESET ,Device reset" "No reset,Reset" bitfld.long 0x00 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "Low,High" newline bitfld.long 0x00 1. " CAMERA_MODE ,CAMERA mode" "Disabled,Enabled" bitfld.long 0x00 0. " GPMI_MODE ,GPMI mode" "NAND,ATA" line.long 0x04 "CTRL1_SET,GPMI Control Set Register 1" bitfld.long 0x04 31. " DEV_CLK_STOP ,Device clock stop" "No effect,Set" bitfld.long 0x04 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "No effect,Set" bitfld.long 0x04 29. " WRITE_CLK_STOP ,Stop clock during data write" "No effect,Set" newline bitfld.long 0x04 28. " TOGGLE_MODE ,Samsung toggle mode enable" "No effect,Set" bitfld.long 0x04 27. " GPMI_CLK_DIV2_EN ,GPMI CLK divider enable" "No effect,Set" bitfld.long 0x04 26. " UPDATE_CS ,Force CS value update" "No effect,Set" newline bitfld.long 0x04 25. " SSYNCMODE ,Source synchronous mode 1 or asynchronous mode 0" "ASYNC,SSYNC" bitfld.long 0x04 24. " DECOUPLE_CS ,Decouple chip select from DMA channel" "No effect,Set" bitfld.long 0x04 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "~2ns,~4ns,~6ns,No delay" newline bitfld.long 0x04 21. " TEST_TRIGGER ,Test trigger enable" "Disabled,Enabled" bitfld.long 0x04 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for transfers in ATA mode only and for WAIT_FOR_READY commands in both ATA and NAND mode" "No effect,Set" bitfld.long 0x04 19. " GANGED_RDYBUSY ,NAND RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Set" newline bitfld.long 0x04 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Set" bitfld.long 0x04 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Set" bitfld.long 0x04 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Set" newline bitfld.long 0x04 12.--15. " RDN_DELAY ,Delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 11. " DMA2ECC_MODE ,DMA ECC mode. DMA write data to redirected to HWECC module (instead of NAND device) for encoding or decoding" "No effect,Set" bitfld.long 0x04 10. " DEV_IRQ ,ATA device interrupt received" "No effect,Set" newline bitfld.long 0x04 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Set" bitfld.long 0x04 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Set" bitfld.long 0x04 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "No effect,Set" newline bitfld.long 0x04 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. " DEV_RESET ,Device reset" "No effect,Set" bitfld.long 0x04 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Set" newline bitfld.long 0x04 1. " CAMERA_MODE ,CAMERA mode" "No effect,Set" bitfld.long 0x04 0. " GPMI_MODE ,GPMI mode" "No effect,Set" line.long 0x08 "CTRL1_CLR,GPMI Control Clear Register 1" bitfld.long 0x08 31. " DEV_CLK_STOP ,Device clock stop" "No effect,Clear" bitfld.long 0x08 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "No effect,Clear" bitfld.long 0x08 29. " WRITE_CLK_STOP ,Stop clock during data write" "No effect,Clear" newline bitfld.long 0x08 28. " TOGGLE_MODE ,Samsung toggle mode enable" "No effect,Clear" bitfld.long 0x08 27. " GPMI_CLK_DIV2_EN ,GPMI CLK divider enable" "No effect,Clear" bitfld.long 0x08 26. " UPDATE_CS ,Force CS value update" "No effect,Clear" newline bitfld.long 0x08 25. " SSYNCMODE ,Source synchronous mode 1 or asynchronous mode 0" "ASYNC,SSYNC" bitfld.long 0x08 24. " DECOUPLE_CS ,Decouple chip select from DMA channel" "No effect,Clear" bitfld.long 0x08 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "~2ns,~4ns,~6ns,No delay" newline bitfld.long 0x08 21. " TEST_TRIGGER ,Test trigger enable" "Disabled,Enabled" bitfld.long 0x08 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for transfers in ATA mode only and for WAIT_FOR_READY commands in both ATA and NAND mode" "No effect,Clear" bitfld.long 0x08 19. " GANGED_RDYBUSY ,NAND RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Clear" newline bitfld.long 0x08 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Clear" bitfld.long 0x08 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Clear" bitfld.long 0x08 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Clear" newline bitfld.long 0x08 12.--15. " RDN_DELAY ,Delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 11. " DMA2ECC_MODE ,DMA ECC mode. DMA write data to redirected to HWECC module (instead of NAND device) for encoding or decoding" "No effect,Clear" bitfld.long 0x08 10. " DEV_IRQ ,ATA device interrupt received" "No effect,Clear" newline bitfld.long 0x08 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Clear" bitfld.long 0x08 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Clear" bitfld.long 0x08 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "No effect,Clear" newline bitfld.long 0x08 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x08 3. " DEV_RESET ,Device reset" "No effect,Clear" bitfld.long 0x08 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Clear" newline bitfld.long 0x08 1. " CAMERA_MODE ,CAMERA mode" "No effect,Clear" bitfld.long 0x08 0. " GPMI_MODE ,GPMI mode" "No effect,Clear" line.long 0x0C "CTRL1_TOG,GPMI Control Toggle Register 1" bitfld.long 0x0C 31. " DEV_CLK_STOP ,Device clock stop" "No effect,Toggle" bitfld.long 0x0C 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "No effect,Toggle" bitfld.long 0x0C 29. " WRITE_CLK_STOP ,Stop clock during data write" "No effect,Toggle" newline bitfld.long 0x0C 28. " TOGGLE_MODE ,Samsung toggle mode enable" "No effect,Toggle" bitfld.long 0x0C 27. " GPMI_CLK_DIV2_EN ,GPMI CLK divider enable" "No effect,Toggle" bitfld.long 0x0C 26. " UPDATE_CS ,Force CS value update" "No effect,Toggle" newline bitfld.long 0x0C 25. " SSYNCMODE ,Source synchronous mode 1 or asynchronous mode 0" "ASYNC,SSYNC" bitfld.long 0x0C 24. " DECOUPLE_CS ,Decouple chip select from DMA channel" "No effect,Toggle" bitfld.long 0x0C 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "~2ns,~4ns,~6ns,No delay" newline bitfld.long 0x0C 21. " TEST_TRIGGER ,Test trigger enable" "Disabled,Enabled" bitfld.long 0x0C 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for transfers in ATA mode only and for WAIT_FOR_READY commands in both ATA and NAND mode" "No effect,Toggle" bitfld.long 0x0C 19. " GANGED_RDYBUSY ,NAND RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Toggle" newline bitfld.long 0x0C 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Toggle" bitfld.long 0x0C 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Toggle" bitfld.long 0x0C 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Toggle" newline bitfld.long 0x0C 12.--15. " RDN_DELAY ,Delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. " DMA2ECC_MODE ,DMA ECC mode. DMA write data to redirected to HWECC module (instead of NAND device) for encoding or decoding" "No effect,Toggle" bitfld.long 0x0C 10. " DEV_IRQ ,ATA device interrupt received" "No effect,Toggle" newline bitfld.long 0x0C 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Toggle" bitfld.long 0x0C 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Toggle" bitfld.long 0x0C 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "No effect,Toggle" newline bitfld.long 0x0C 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 3. " DEV_RESET ,Device reset" "No effect,Toggle" bitfld.long 0x0C 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Toggle" newline bitfld.long 0x0C 1. " CAMERA_MODE ,CAMERA mode" "No effect,Toggle" bitfld.long 0x0C 0. " GPMI_MODE ,GPMI mode" "No effect,Toggle" line.long 0x10 "TIMING0,GPMI Timing Register 0" hexmask.long.byte 0x10 16.--23. 1. " ADDRESS_SETUP ,Number of GPMICLK cycles that the CE/ADDR signals are active before a strobe is asserted" hexmask.long.byte 0x10 8.--15. 1. " DATA_HOLD ,Data bus hold time in GPMICLK cycles" hexmask.long.byte 0x10 0.--7. 1. " DATA_SETUP ,Data bus setup time in GPMICLK cycles" group.long 0x80++0x03 line.long 0x00 "TIMING1,GPMI Timing Register 1" hexmask.long.word 0x00 16.--31. 1. " DEVICE_BUSY_TIMEOUT ,Timeout waiting for NAND ready/busy or ATA IRQ" group.long 0x90++0x03 line.long 0x00 "TIMING2,GPMI Timing Register 2" bitfld.long 0x00 29.--31. " TRPSTH ,NAND timing control delay between CEn_B high and RE_B high" "8,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " TCR ,NAND timing control delay between CEn_B low and RE_B low" "1,2,3,4" bitfld.long 0x00 24.--26. " READ_LATENCY ,Read latency" "0,1,2,3,4,5,3,3" newline bitfld.long 0x00 16.--20. " CE_DELAY ,CE delay" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--15. " PREAMBLE_DELAY ,Pre-amble delay" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " POSTAMBLE_DELAY ,Post-amble delay" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " CMDADD_PAUSE ,Delay time from command/address pause to command/address resume in GPMICLK cycles" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DATA_PAUSE ,Delay time from data pause to data resume in GPMICLK cycles" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x03 line.long 0x00 "DATA,GPMI DMA Data Transfer Register" rgroup.long 0xB0++0x03 line.long 0x00 "STAT,GPMI Status Register" hexmask.long.byte 0x00 24.--31. 1. " READY_BUSY ,NAND ready_busy input pins" bitfld.long 0x00 23. " RDY_TIMEOUT[7] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" bitfld.long 0x00 22. " RDY_TIMEOUT[6] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" newline bitfld.long 0x00 21. " RDY_TIMEOUT[5] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" bitfld.long 0x00 20. " RDY_TIMEOUT[4] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" bitfld.long 0x00 19. " RDY_TIMEOUT[3] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" newline bitfld.long 0x00 18. " RDY_TIMEOUT[2] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" bitfld.long 0x00 17. " RDY_TIMEOUT[1] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" bitfld.long 0x00 16. " RDY_TIMEOUT[0] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" newline bitfld.long 0x00 15. " DEV7_ERROR ,Error condition on NAND device accessed by DMA channel 7" "No error,Error" bitfld.long 0x00 14. " DEV6_ERROR ,Error condition on NAND device accessed by DMA channel 6" "No error,Error" bitfld.long 0x00 13. " DEV5_ERROR ,Error condition on NAND device accessed by DMA channel 5" "No error,Error" newline bitfld.long 0x00 12. " DEV4_ERROR ,Error condition on NAND device accessed by DMA channel 4" "No error,Error" bitfld.long 0x00 11. " DEV3_ERROR ,Error condition on NAND device accessed by DMA channel 3" "No error,Error" bitfld.long 0x00 10. " DEV2_ERROR ,Error condition on NAND device accessed by DMA channel 2" "No error,Error" newline bitfld.long 0x00 9. " DEV1_ERROR ,Error condition on NAND device accessed by DMA channel 1" "No error,Error" bitfld.long 0x00 8. " DEV0_ERROR ,Error condition on NAND device accessed by DMA channel 0" "No error,Error" newline bitfld.long 0x00 4. " ATA_IRQ ,Status of ATA_IRQ input pin" "Low,High" bitfld.long 0x00 3. " INVALID_BUFFER_MASK ,ECC buffer mask validity" "Not invalid,Invalid" bitfld.long 0x00 2. " FIFO_EMPTY ,FIFO empty" "Not empty,Empty" newline bitfld.long 0x00 1. " FIFO_FULL ,FIFO full" "Not full,Full" bitfld.long 0x00 0. " PRESENT ,GPMI present" "Not present,Present" rgroup.long 0xC0++0x03 line.long 0x00 "DEBUG,GPMI Debug Information Register" bitfld.long 0x00 31. " WAIT_FOR_READY_END[7] ,WAIT_FOR_READY command end of channel 7" "Not occurred,Occurred" bitfld.long 0x00 30. " WAIT_FOR_READY_END[6] ,WAIT_FOR_READY command end of channel 6" "Not occurred,Occurred" bitfld.long 0x00 29. " WAIT_FOR_READY_END[5] ,WAIT_FOR_READY command end of channel 5" "Not occurred,Occurred" newline bitfld.long 0x00 28. " WAIT_FOR_READY_END[4] ,WAIT_FOR_READY command end of channel 4" "Not occurred,Occurred" bitfld.long 0x00 27. " WAIT_FOR_READY_END[3] ,WAIT_FOR_READY command end of channel 3" "Not occurred,Occurred" bitfld.long 0x00 26. " WAIT_FOR_READY_END[2] ,WAIT_FOR_READY command end of channel 2" "Not occurred,Occurred" newline bitfld.long 0x00 25. " WAIT_FOR_READY_END[1] ,WAIT_FOR_READY command end of channel 1" "Not occurred,Occurred" bitfld.long 0x00 24. " WAIT_FOR_READY_END[0] ,WAIT_FOR_READY command end of channel 0" "Not occurred,Occurred" bitfld.long 0x00 23. " DMA_SENSE[7] ,Indicates that a read and compare command failed or a timeout occurred for the channel 7" "Not occurred,Occurred" newline bitfld.long 0x00 22. " DMA_SENSE[6] ,Indicates that a read and compare command failed or a timeout occurred for the channel 6" "Not occurred,Occurred" bitfld.long 0x00 21. " DMA_SENSE[5] ,Indicates that a read and compare command failed or a timeout occurred for the channel 5" "Not occurred,Occurred" bitfld.long 0x00 20. " DMA_SENSE[4] ,Indicates that a read and compare command failed or a timeout occurred for the channel 4" "Not occurred,Occurred" newline bitfld.long 0x00 19. " DMA_SENSE[3] ,Indicates that a read and compare command failed or a timeout occurred for the channel 3" "Not occurred,Occurred" bitfld.long 0x00 18. " DMA_SENSE[2] ,Indicates that a read and compare command failed or a timeout occurred for the channel 2" "Not occurred,Occurred" bitfld.long 0x00 17. " DMA_SENSE[1] ,Indicates that a read and compare command failed or a timeout occurred for the channel 1" "Not occurred,Occurred" newline bitfld.long 0x00 16. " DMA_SENSE[0] ,Indicates that a read and compare command failed or a timeout occurred for the channel 0" "Not occurred,Occurred" bitfld.long 0x00 15. " DMAREQ[7] ,DMA request line for channel 7" "Not requested,Requested" bitfld.long 0x00 14. " DMAREQ[6] ,DMA request line for channel 6" "Not requested,Requested" newline bitfld.long 0x00 13. " DMAREQ[5] ,DMA request line for channel 5" "Not requested,Requested" bitfld.long 0x00 12. " DMAREQ[4] ,DMA request line for channel 4" "Not requested,Requested" bitfld.long 0x00 11. " DMAREQ[3] ,DMA request line for channel 3" "Not requested,Requested" newline bitfld.long 0x00 10. " DMAREQ[2] ,DMA request line for channel 2" "Not requested,Requested" bitfld.long 0x00 9. " DMAREQ[1] ,DMA request line for channel 1" "Not requested,Requested" bitfld.long 0x00 8. " DMAREQ[0] ,DMA request line for channel 0" "Not requested,Requested" newline bitfld.long 0x00 7. " CMD_END[7] ,Command end toggle to DMA channel 7" "Not finished,Finished" bitfld.long 0x00 6. " CMD_END[6] ,Command end toggle to DMA channel 6" "Not finished,Finished" bitfld.long 0x00 5. " CMD_END[5] ,Command end toggle to DMA channel 5" "Not finished,Finished" newline bitfld.long 0x00 4. " CMD_END[4] ,Command end toggle to DMA channel 4" "Not finished,Finished" bitfld.long 0x00 3. " CMD_END[3] ,Command end toggle to DMA channel 3" "Not finished,Finished" bitfld.long 0x00 2. " CMD_END[2] ,Command end toggle to DMA channel 2" "Not finished,Finished" newline bitfld.long 0x00 1. " CMD_END[1] ,Command end toggle to DMA channel 1" "Not finished,Finished" bitfld.long 0x00 0. " CMD_END[0] ,Command end toggle to DMA channel 0" "Not finished,Finished" rgroup.long 0xD0++0x03 line.long 0x00 "VERSION,GPMI Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" group.long 0xE0++0x03 line.long 0x00 "DEBUG2,GPMI Debug2 Information Register" rbitfld.long 0x00 24.--27. " UDMA_STATE ,UDMA state" "USM_IDLE,USM_DMARQ,USM_ACK,USM_FIFO_E,USM_WPAUSE,USM_TSTRB,USM_CAPTUR,USM_DATOUT,USM_CRC,USM_WAIT_R,USM_END,USM_WAIT_S,USM_RPAUSE,USM_RSTOP,USM_WTERM,USM_RTERM" rbitfld.long 0x00 23. " BUSY ,Asserted GPMI is busy" "Not busy,Busy" rbitfld.long 0x00 20.--22. " PIN_STATE ,Pin state" "PSM_IDLE,PSM_BYTCNT,PSM_ADDR,PSM_STALL,PSM_STROBE,PSM_ATARDY,PSM_DHOLD,PSM_DONE" newline rbitfld.long 0x00 16.--19. " MAIN_STATE ,Main state" "MSM_IDLE,MSM_BYTCNT,MSM_WAITFE,MSM_WAITFR,MSM_DMAREQ,MSM_DMAACK,MSM_WAITFF,MSM_LDFIFO,MSM_LDDMAR,MSM_RDCMP,MSM_DONE,?..." rbitfld.long 0x00 12.--15. " SYND2GPMI_BE ,Data byte enable input from BCH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 11. " GPMI2SYND_VALID ,Data handshake output to BCH" "Not valid,Valid" newline rbitfld.long 0x00 10. " GPMI2SYND_READY ,Data handshake output to BCH" "Not ready,Ready" rbitfld.long 0x00 9. " SYND2GPMI_VALID ,Data handshake input from BCH" "Not valid,Valid" rbitfld.long 0x00 8. " SYND2GPMI_READY ,Data handshake input from BCH" "Not ready,Ready" newline bitfld.long 0x00 7. " VIEW_DELAYED_RDN ,Feedback RDN to drive the GPMI_ADDR[0]" "No delay,Delay" rbitfld.long 0x00 6. " UPDATE_WINDOW ,DLL is busy generating the required delay" "No,Yes" rbitfld.long 0x00 0.--5. " RDN_TAP ,DLL tap calculated by the DLL controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0xF0++0x03 line.long 0x00 "DEBUG3,GPMI Debug3 Information Register Description" hexmask.long.word 0x00 16.--31. 1. " APB_WORD_CNTR ,Number of words remains to be transferred on the APB bus" hexmask.long.word 0x00 0.--15. 1. " DEV_WORD_CNTR ,Number of words remains to be transferred on the ATA/NAND bus" width 20. tree "GPMI Double Rate Read DLL Control&Status Register Description" group.long 0x100++0x03 line.long 0x00 "READ_DDR_DLL_CTRL,GPMI Double Rate Read DLL Control Register Description" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,Additional delay cycles to the DLL control loop" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Update interval of 256 GPMICLK cycles" hexmask.long.byte 0x00 10.--17. 1. " SLV_OVERRIDE_VAL ,Select 1 of 256 physical taps manually" bitfld.long 0x00 9. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 8. " REFCLK_ON ,Reference clock" "Off,On" newline bitfld.long 0x00 7. " GATE_UPDATE ,Forces the slave delay line is not updated" "No effect,Not updated" bitfld.long 0x00 3.--6. " SLV_DLY_TARGET ,The delay target for the read clock" "1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16,16/16" bitfld.long 0x00 2. " SLV_FORCE_UPD ,Forces the slave delay line to update" "No effect,Updated" bitfld.long 0x00 1. " RESET ,Reset on DLL" "No reset,Reset" bitfld.long 0x00 0. " ENABLE ,Enable the DLL and delay chain" "Disabled,Enabled" group.long 0x110++0x03 line.long 0x00 "WRITE_DDR_DLL_CTRL,GPMI Double Rate Write DLL Control Register Description" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,Additional delay cycles to the DLL control loop" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Update interval of 256 GPMICLK cycles" hexmask.long.byte 0x00 10.--17. 1. " SLV_OVERRIDE_VAL ,Select 1 of 256 physical taps manually" bitfld.long 0x00 9. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 8. " REFCLK_ON ,Reference clock" "Off,On" newline bitfld.long 0x00 7. " GATE_UPDATE ,Forces the slave delay line is not updated" "No effect,Not updated" bitfld.long 0x00 3.--6. " SLV_DLY_TARGET ,The delay target for the read clock" "1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16,16/16" bitfld.long 0x00 2. " SLV_FORCE_UPD ,Forces the slave delay line to update" "No effect,Updated" bitfld.long 0x00 1. " RESET ,Reset on DLL" "No reset,Reset" bitfld.long 0x00 0. " ENABLE ,Enable the DLL and delay chain" "Disabled,Enabled" rgroup.long 0x120++0x03 line.long 0x00 "READ_DDR_DLL_STS,GPMI Double Rate Read DLL Status Register Description" hexmask.long.byte 0x00 17.--24. 1. " REF_SEL ,Reference delay line select status" bitfld.long 0x00 16. " REF_LOCK ,Reference DLL lock status" "Not locked,Locked" hexmask.long.byte 0x00 1.--8. 1. " SLV_SEL ,Slave delay line select status" sif (cpuis("IMX8*")) bitfld.long 0x00 0. " SLV_LOCK ,Slave delay-line lock status" "Not locked,Locked" endif rgroup.long 0x130++0x03 line.long 0x00 "WRITE_DDR_DLL_STS,GPMI Double Rate Write DLL Status Register Description" hexmask.long.byte 0x00 17.--24. 1. " REF_SEL ,Reference delay line select status" bitfld.long 0x00 16. " REF_LOCK ,Reference DLL lock status" "Not locked,Locked" hexmask.long.byte 0x00 1.--8. 1. " SLV_SEL ,Slave delay line select status" bitfld.long 0x00 0. " SLV_LOCK ,Slave delay-line lock status" "Not locked,Locked" tree.end width 0x0B tree.end tree.end tree.open "Mass Storage" tree.open "ECSPI (Enhanced Configurable SPI)" tree "ECSPI 1" base ad:0x30820000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "RXDATA,Receive Data Register" in wgroup.long 0x04++0x03 line.long 0x00 "TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst length" bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select" "0,1,2,3" bitfld.long 0x00 16.--17. " DRCTL ,SPI data ready control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,?..." textline " " bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI pre divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI post divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" bitfld.long 0x00 7. " CHANNEL_MODE[3] ,Mode of each SPI channel 3" "Slave,Master" textline " " bitfld.long 0x00 6. " CHANNEL_MODE[2] ,Mode of each SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE[1] ,Mode of each SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE[0] ,Mode of each SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start mode control" "Normal,Automatic" bitfld.long 0x00 2. " XCH ,SPI exchange bit" "Idle,Exchanged/busy" bitfld.long 0x00 1. " HT ,Hardware trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,SPI module enable control" "Disabled,Enabled" if (((per.l(ad:0x30820000+0x08))&0xF0)==0x00) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SS for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SS for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SS for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SS for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x10) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x20) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x30) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x40) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x50) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x60) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x70) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x80) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x90) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0xA0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0xB0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0xC0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0xD0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0xE0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" else group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" endif textline " " group.long 0x10++0x07 line.long 0x00 "INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer completed interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO data request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO data request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO empty interrupt enable" "Disabled,Enabled" line.long 0x04 "DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA request enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA request enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,RX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO empty DMA request enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,TX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x30820000+0x14))&0x80000000)==0x00) group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" else group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD/DMA TAIL DMA" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" endif group.long 0x1C++0x07 line.long 0x00 "PERIODREG,Sample Period Control Register" bitfld.long 0x00 16.--21. " CSD_CTRL ,Chip select delay control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15. " CSRC ,Clock source control" "SPI clock,Low-Frequency Ref. Clock" hexmask.long.word 0x00 0.--14. 1. " SAMPLE_PERIOD ,Sample period control" line.long 0x04 "TESTREG,Test Control Register" bitfld.long 0x04 31. " LBC ,Loop back control" "Not connected,Connected" hexmask.long.byte 0x04 8.--14. 1. " RXCNT ,RXFIFO counter" hexmask.long.byte 0x04 0.--6. 1. " TXCNT ,TXFIFO counter" wgroup.long 0x40++0x03 line.long 0x00 "MSGDATA,Message Data Register" width 0x0B tree.end tree "ECSPI 2" base ad:0x30830000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "RXDATA,Receive Data Register" in wgroup.long 0x04++0x03 line.long 0x00 "TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst length" bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select" "0,1,2,3" bitfld.long 0x00 16.--17. " DRCTL ,SPI data ready control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,?..." textline " " bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI pre divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI post divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" bitfld.long 0x00 7. " CHANNEL_MODE[3] ,Mode of each SPI channel 3" "Slave,Master" textline " " bitfld.long 0x00 6. " CHANNEL_MODE[2] ,Mode of each SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE[1] ,Mode of each SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE[0] ,Mode of each SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start mode control" "Normal,Automatic" bitfld.long 0x00 2. " XCH ,SPI exchange bit" "Idle,Exchanged/busy" bitfld.long 0x00 1. " HT ,Hardware trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,SPI module enable control" "Disabled,Enabled" if (((per.l(ad:0x30830000+0x08))&0xF0)==0x00) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SS for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SS for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SS for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SS for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x10) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x20) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x30) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x40) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x50) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x60) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x70) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x80) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x90) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0xA0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0xB0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0xC0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0xD0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0xE0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" else group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" endif textline " " group.long 0x10++0x07 line.long 0x00 "INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer completed interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO data request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO data request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO empty interrupt enable" "Disabled,Enabled" line.long 0x04 "DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA request enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA request enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,RX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO empty DMA request enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,TX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x30830000+0x14))&0x80000000)==0x00) group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" else group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD/DMA TAIL DMA" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" endif group.long 0x1C++0x07 line.long 0x00 "PERIODREG,Sample Period Control Register" bitfld.long 0x00 16.--21. " CSD_CTRL ,Chip select delay control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15. " CSRC ,Clock source control" "SPI clock,Low-Frequency Ref. Clock" hexmask.long.word 0x00 0.--14. 1. " SAMPLE_PERIOD ,Sample period control" line.long 0x04 "TESTREG,Test Control Register" bitfld.long 0x04 31. " LBC ,Loop back control" "Not connected,Connected" hexmask.long.byte 0x04 8.--14. 1. " RXCNT ,RXFIFO counter" hexmask.long.byte 0x04 0.--6. 1. " TXCNT ,TXFIFO counter" wgroup.long 0x40++0x03 line.long 0x00 "MSGDATA,Message Data Register" width 0x0B tree.end tree "ECSPI 3" base ad:0x30840000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "RXDATA,Receive Data Register" in wgroup.long 0x04++0x03 line.long 0x00 "TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst length" bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select" "0,1,2,3" bitfld.long 0x00 16.--17. " DRCTL ,SPI data ready control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,?..." textline " " bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI pre divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI post divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" bitfld.long 0x00 7. " CHANNEL_MODE[3] ,Mode of each SPI channel 3" "Slave,Master" textline " " bitfld.long 0x00 6. " CHANNEL_MODE[2] ,Mode of each SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE[1] ,Mode of each SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE[0] ,Mode of each SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start mode control" "Normal,Automatic" bitfld.long 0x00 2. " XCH ,SPI exchange bit" "Idle,Exchanged/busy" bitfld.long 0x00 1. " HT ,Hardware trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,SPI module enable control" "Disabled,Enabled" if (((per.l(ad:0x30840000+0x08))&0xF0)==0x00) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SS for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SS for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SS for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SS for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x10) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x20) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x30) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x40) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x50) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x60) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x70) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x80) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x90) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0xA0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0xB0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0xC0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0xD0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0xE0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" else group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" endif textline " " group.long 0x10++0x07 line.long 0x00 "INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer completed interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO data request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO data request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO empty interrupt enable" "Disabled,Enabled" line.long 0x04 "DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA request enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA request enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,RX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO empty DMA request enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,TX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x30840000+0x14))&0x80000000)==0x00) group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" else group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD/DMA TAIL DMA" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" endif group.long 0x1C++0x07 line.long 0x00 "PERIODREG,Sample Period Control Register" bitfld.long 0x00 16.--21. " CSD_CTRL ,Chip select delay control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15. " CSRC ,Clock source control" "SPI clock,Low-Frequency Ref. Clock" hexmask.long.word 0x00 0.--14. 1. " SAMPLE_PERIOD ,Sample period control" line.long 0x04 "TESTREG,Test Control Register" bitfld.long 0x04 31. " LBC ,Loop back control" "Not connected,Connected" hexmask.long.byte 0x04 8.--14. 1. " RXCNT ,RXFIFO counter" hexmask.long.byte 0x04 0.--6. 1. " TXCNT ,TXFIFO counter" wgroup.long 0x40++0x03 line.long 0x00 "MSGDATA,Message Data Register" width 0x0B tree.end tree.end tree "QuadSPI (Quad Serial Peripheral Interface" base ad:0x30BB0000 width 9. sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if ((per.l(ad:0x30BB0000)&0x4000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial clock configuration" bitfld.long 0x00 17. " ISD3FA ,Idle Signal Drive IOFA[3] Flash A" "Disabled,Enabled" bitfld.long 0x00 16. " ISD2FA ,Idle Signal Drive IOFA[2] Flash A" "Disabled,Enabled" newline bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" newline bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" bitfld.long 0x00 5. " DQS_LAT_EN ,DQS latency enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial clock configuration" rbitfld.long 0x00 17. " ISD3FA ,Idle Signal Drive IOFA[3] Flash A" "Disabled,Enabled" rbitfld.long 0x00 16. " ISD2FA ,Idle Signal Drive IOFA[2] Flash A" "Disabled,Enabled" newline bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" newline bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" bitfld.long 0x00 5. " DQS_LAT_EN ,DQS latency enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" endif else if ((per.l(ad:0x30BB0000)&0x2000040)==0x2000040) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 26. " DQS_PHASE_EN ,Control of internal DQS output phase" "Disabled,Enabled" bitfld.long 0x00 25. " DQS_LOOPBACK_EN ,DQS loopback sampling enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" elif ((per.l(ad:0x30BB0000)&0x2000040)==0x40) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 25. " DQS_LOOPBACK_EN ,DQS loopback sampling enable" "Disabled,Enabled" bitfld.long 0x00 24. " DQS_LOOPBACK_FROM_PAD ,DQS_LOOPBACK_FROM_PAD" "0,1" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" elif ((per.l(ad:0x30BB0000)&0x2000040)==0x2000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 25. " DQS_LOOPBACK_EN ,DQS loopback sampling enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 25. " DQS_LOOPBACK_EN ,DQS loopback sampling enable" "Disabled,Enabled" bitfld.long 0x00 24. " DQS_LOOPBACK_FROM_PAD ,DQS_LOOPBACK_FROM_PAD" "0,1" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" endif endif if (((per.l(ad:0x30BB0000+0x15C))&0x02)==0x00) group.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" bitfld.long 0x00 24.--27. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" else bitfld.long 0x00 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" endif else rgroup.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" bitfld.long 0x00 24.--27. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" else bitfld.long 0x00 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" endif endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x30BB0000+0x15C)&0x06)==0x00)) if ((per.l(ad:0x30BB0000)&0x80)==0x00) group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" textfld " " bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "POSEDGE of internal ref clk,2x serial flash half clock,4x serial flash half clock,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if ((per.l(ad:0x30BB0000)&0x80)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" textfld " " bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "POSEDGE of internal ref clk,2x serial flash half clock,4x serial flash half clock,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif else if (((per.l(ad:0x30BB0000+0x15C)&0x06)==0x00)) group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "Quadspi's internal ref clock,2x serial flash half clock,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "Quadspi's internal ref clock,2x serial flash half clock,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif newline if (((per.l(ad:0x30BB0000+0x15C))&0x04)==0x00) group.long 0x10++0x13 line.long 0x00 "BUF0CR,Buffer0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High priority enable" "Disabled,Enabled" sif cpuis("IMX7ULP*") hexmask.long.byte 0x00 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x00 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x00 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer1 Configuration Register" sif cpuis("IMX7ULP*") hexmask.long.byte 0x04 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x04 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x04 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer2 Configuration Register" sif cpuis("IMX7ULP*") hexmask.long.byte 0x08 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x08 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer0 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" sif cpuis("IMX7ULP*") hexmask.long.byte 0x0C 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x0C 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer0 Configuration Register" sif cpuis("IMX7ULP*") bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x10 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) group.long 0x24++0x03 line.long 0x00 "SOCCR,SOC Configuration Register" hexmask.long.byte 0x00 16.--22. 1. " DQSDLY ,Delay chain tap selection (fine tuning) for QuadSPI DQS clock" newline bitfld.long 0x00 12. " DQSINVSEL ,DQS generation clock inverted" "Not inverted,Inverted" bitfld.long 0x00 10.--11. " DQSPHASE ,Phase shift for the internal DQS generation" "No shift,45 degree,90 degree,135 degree" newline bitfld.long 0x00 9. " DQSPADLPEN ,DQS external loopback enable" "Disabled,Enabled" bitfld.long 0x00 8. " DQSLPEN ,Internal DQS loopback enable" "Disabled,Enabled" endif group.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" else rgroup.long 0x10++0x13 line.long 0x00 "BUF0CR,Buffer0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High priority enable" "Disabled,Enabled" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x00 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x00 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x00 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer1 Configuration Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x04 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x04 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x04 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer2 Configuration Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x08 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x08 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer0 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x0C 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x0C 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer0 Configuration Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x10 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("IMX7ULP*") rgroup.long 0x24++0x03 line.long 0x00 "SOCCR,SOC Configuration Register" hexmask.long.byte 0x00 16.--22. 1. " DQSDLY ,Delay chain tap selection (fine tuning) for QuadSPI DQS clock" newline bitfld.long 0x00 12. " DQSINVSEL ,DQS generation clock inverted" "Not inverted,Inverted" bitfld.long 0x00 10.--11. " DQSPHASE ,Phase shift for the internal DQS generation" "No shift,45 degree,90 degree,135 degree" newline bitfld.long 0x00 9. " DQSPADLPEN ,DQS external loopback enable" "Disabled,Enabled" bitfld.long 0x00 8. " DQSLPEN ,Internal DQS loopback enable" "Disabled,Enabled" endif rgroup.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" endif if (((per.l(ad:0x30BB0000+0x15C))&0x02)==0x00) group.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" else rgroup.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x30BB0000+0x15C)&0x06)==0x00)) group.long 0x104++0x03 line.long 0x00 "SFACR,Serial Flash Address Configuration Register" bitfld.long 0x00 16. " WA ,Word addressable" "Byte addressable,Word addressable" bitfld.long 0x00 0.--3. " CAS ,Column address space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x104++0x03 line.long 0x00 "SFACR,Serial Flash Address Configuration Register" bitfld.long 0x00 16. " WA ,Word addressable" "Byte addressable,Word addressable" bitfld.long 0x00 0.--3. " CAS ,Column address space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0x30BB0000)&0x4000)==0x4000)) group.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 16.--18. " DDRSMP ,DDR sampling point" "0,1,2,3,4,5,6,7" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) newline bitfld.long 0x00 6. " FSDLY ,Full speed delay selection for SDR instructions" "1 cycle,2 cycles" newline bitfld.long 0x00 5. " FSPHS ,Full speed phase selection for SDR instruction" "Not inverted,Inverted" newline bitfld.long 0x00 2. " HSDLY ,Half speed delay selection for SDR instructions" "1 cycle,2 cycles" newline bitfld.long 0x00 1. " HSPHS ,Half speed phase selection for SDR instructions" "Not inverted,Inverted" newline bitfld.long 0x00 0. " HSENA ,Half speed serial flash clock enable" "Disabled,Enabled" else bitfld.long 0x00 5.--6. " SDRSMP ,SDR sampling point" "0,1,2,3" endif else rgroup.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 16.--18. " DDRSMP ,DDR sampling point" "0,1,2,3,4,5,6,7" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) newline bitfld.long 0x00 6. " FSDLY ,Full speed delay selection for SDR instructions" "1 cycle,2 cycles" newline bitfld.long 0x00 5. " FSPHS ,Full speed phase selection for SDR instruction" "Not inverted,Inverted" newline bitfld.long 0x00 2. " HSDLY ,Half speed delay selection for SDR instructions" "1 cycle,2 cycles" newline bitfld.long 0x00 1. " HSPHS ,Half speed phase selection for SDR instructions" "Not inverted,Inverted" newline bitfld.long 0x00 0. " HSENA ,Half speed serial flash clock enable" "Disabled,Enabled" else bitfld.long 0x00 5.--6. " SDRSMP ,SDR sampling point" "0,1,2,3" endif endif rgroup.long 0x10C++0x03 line.long 0x00 "RBSR,RX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " RDCTR ,Indicates how many entries of 4 bytes have been removed from the RX buffer" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--12. " RDBFL ,Indicates how many entries of 4 bytes are still available in the RX buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 8.--13. " RDBFL ,Indicates how many entries of 4 bytes are still available in the RX buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (((per.l(ad:0x30BB0000+0x15C))&0x02)==0x00) group.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,Access scheme for the RX buffer readout" "AHB bus,IP bus" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 0.--3. " WMRK ,Field determines when the readout action of the RX buffer is triggered" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes" else bitfld.long 0x00 0.--4. " WMRK ,Field determines when the readout action of the RX buffer is triggered" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes,128 bytes" endif else rgroup.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,Access scheme for the RX buffer readout" "AHB bus,IP bus" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 0.--3. " WMRK ,Field determines when the readout action of the RX buffer is triggered" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes" else bitfld.long 0x00 0.--4. " WMRK ,Field determines when the readout action of the RX buffer is triggered" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes,128 bytes" endif endif rgroup.long 0x150++0x03 line.long 0x00 "TBSR,TX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " TRCTR ,Field indicates how many entries of 4 bytes have been written into the TX buffer by host accesses" bitfld.long 0x00 8.--12. " TRBFL ,Number of entries of 4 bytes each available in the TX buffer for the quadspi module to transmit to the serial flash device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x30BB0000+0x15C))&0x8000000)==0x00) group.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" else rgroup.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) group.long 0x158++0x03 line.long 0x00 "TBCT,TX Buffer Control Register" bitfld.long 0x00 0.--3. " WMRK ,TX buffer watermark" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes" endif rgroup.long 0x15C++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 29.--31. " DLPSMP ,Data learning pattern sampling point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " TXFULL ,TX buffer full" "Not full,Full" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 26. " TXDMA ,TXFIFO fill via DMA is active" "Not active,Active" newline bitfld.long 0x00 25. " TXWA ,TX buffer watermark available" "Not available,Available" bitfld.long 0x00 24. " TXEDA ,TX buffer enough data available" "Not available,Available" else bitfld.long 0x00 24. " TXEDA ,TX buffer enough data available" "Not available,Available" endif newline bitfld.long 0x00 23. " RXDMA ,RX buffer read out via DMA" "Not active,Active" bitfld.long 0x00 19. " RXFULL ,RX buffer full" "Not full,Full" bitfld.long 0x00 16. " RXWE ,RX buffer watermark exceeded" "Not exceeded,Exceeded" newline bitfld.long 0x00 14. " AHB3FUL ,AHB 3 buffer full" "Not full,Full" bitfld.long 0x00 13. " AHB2FUL ,AHB 2 buffer full" "Not full,Full" bitfld.long 0x00 12. " AHB1FUL ,AHB 1 buffer full" "Not full,Full" bitfld.long 0x00 11. " AHB0FUL ,AHB 0 buffer full" "Not full,Full" newline bitfld.long 0x00 10. " AHB3NE ,AHB 3 buffer not empty" "No,Yes" bitfld.long 0x00 9. " AHB2NE ,AHB 2 buffer not empty" "No,Yes" bitfld.long 0x00 8. " AHB1NE ,AHB 1 buffer not empty" "No,Yes" bitfld.long 0x00 7. " AHB0NE ,AHB 0 buffer not empty" "No,Yes" newline bitfld.long 0x00 6. " AHBTRN ,AHB access transaction pending" "Not pending,Pending" bitfld.long 0x00 5. " AHBGNT ,AHB command priority granted" "Not granted,Granted" bitfld.long 0x00 2. " AHB_ACC ,AHB access" "Not AHB initiated,AHB initiated" newline bitfld.long 0x00 1. " IP_ACC ,IP access" "Not IP bus initiated,IP bus initiated" bitfld.long 0x00 0. " BUSY ,Indicates whether module is currently busy handling a transaction to an external flash device" "Not busy,Busy" group.long 0x160++0x07 line.long 0x00 "FR,Flag Register" eventfld.long 0x00 31. " DLPFF ,Data learning pattern failure" "Not occurred,Occurred" eventfld.long 0x00 27. " TBFF ,TX buffer fulfilment" "Full,Not full" eventfld.long 0x00 26. " TBUF ,TX buffer underrun" "Not occurred,Occurred" eventfld.long 0x00 23. " ILLINE ,Illegal instruction error" "Not occurred,Occurred" newline eventfld.long 0x00 17. " RBOF ,RX buffer overflow" "Not occurred,Occurred" eventfld.long 0x00 16. " RBDF ,RX buffer drain" "Not occurred,Occurred" eventfld.long 0x00 15. " ABSEF ,AHB sequence error" "Not occurred,Occurred" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) eventfld.long 0x00 14. " AITEF ,AHB illegal transaction error" "Not occurred,Occurred" newline eventfld.long 0x00 13. " AIBSEF ,AHB illegal burst size error" "Not occurred,Occurred" eventfld.long 0x00 12. " ABOF ,AHB buffer overflow" "Not occurred,Occurred" eventfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error" "Not occurred,Occurred" eventfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed" "Not occurred,Occurred" newline eventfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant" "Not occurred,Occurred" eventfld.long 0x00 0. " TFF ,IP command transaction finished" "Not occurred,Occurred" else eventfld.long 0x00 12. " ABOF ,AHB buffer overflow" "Not occurred,Occurred" newline eventfld.long 0x00 11. " IUEF ,IP command usage error" "Not occurred,Occurred" eventfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error" "Not occurred,Occurred" eventfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed" "Not occurred,Occurred" eventfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant" "Not occurred,Occurred" newline eventfld.long 0x00 0. " TFF ,IP command transaction finished" "Not occurred,Occurred" endif line.long 0x04 "RSER,Interrupt And DMA Request Select And Enable Register" bitfld.long 0x04 31. " DLPFIE ,Data learning pattern failure interrupt enable" "Disabled,Enabled" bitfld.long 0x04 27. " TBFIE ,TX buffer fill interrupt enable" "Disabled,Enabled" bitfld.long 0x04 26. " TBUIE ,TX buffer underrun interrupt enable" "Disabled,Enabled" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x04 25. " TBFDE ,TX buffer fill DMA enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " ILLINIE ,Illegal instruction error interrupt enable" "Disabled,Enabled" else bitfld.long 0x04 23. " ILLINIE ,Illegal instruction error interrupt enable" "Disabled,Enabled" endif newline bitfld.long 0x04 21. " RBDDE ,RX buffer drain DMA enable" "Disabled,Enabled" bitfld.long 0x04 17. " RBOIE ,RX buffer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x04 16. " RBDIE ,RX buffer drain interrupt enable" "Disabled,Enabled" bitfld.long 0x04 15. " ABSEIE ,AHB sequence error interrupt enable" "Disabled,Enabled" newline sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x04 14. " AITIE ,AHB illegal transaction interrupt enable" "Disabled,Enabled" bitfld.long 0x04 13. " AIBISIE ,AHB illegal burst size interrupt enable" "Disabled,Enabled" newline endif bitfld.long 0x04 12. " ABOIE ,AHB buffer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x04 11. " IUEIE ,AIP command usage error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 7. " IPAEIE ,IP command trigger during AHB access error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IPIEIE ,IP command trigger during IP access error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " IPGEIE ,IP command trigger during AHB grant error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " TFIE ,Transaction finished interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x30BB0000+0x168))&0x01)==0x01) rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 9.--14. " DATLFT ,Data left" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hexmask.long.byte 0x00 9.--15. 1. " DATLFT ,Data left" endif bitfld.long 0x00 6.--7. " SPDBUF ,Suspended buffer number" "0,1,2,3" newline bitfld.long 0x00 0. " SUSPND ,Sequence is in suspended state" "Not suspended,Suspended" else rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" newline bitfld.long 0x00 0. " SUSPND ,Sequence is in suspended state" "Not suspended,Suspended" endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) wgroup.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x00 8. " IPPTRC ,IP pointer clear" "No effect,Clear" bitfld.long 0x00 0. " BFPTRC ,Buffer pointer clear" "No effect,Clear" else group.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x00 8. " IPPTRC ,IP pointer clear" "No effect,Clear" bitfld.long 0x00 0. " BFPTRC ,Buffer pointer clear" "No effect,Clear" endif if (((per.l(ad:0x30BB0000+0x15C)&0x06)==0x00)) sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) group.long 0x180++0x07 line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" else group.long 0x180++0x0F line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" line.long 0x08 "SFB1AD,Serial Flash B1 Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial flash B1" line.long 0x0C "SFB2AD,Serial Flash B2 Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial flash B2" endif else sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) rgroup.long 0x180++0x07 line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" else rgroup.long 0x180++0x0F line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" line.long 0x08 "SFB1AD,Serial Flash B1 Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial flash B1" line.long 0x0C "SFB2AD,Serial Flash B2 Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial flash B2" endif endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x30BB0000+0x15C)&0x06)==0x00)) group.long 0x190++0x03 line.long 0x00 "DLPR,Data Learn Pattern Register" else rgroup.long 0x190++0x03 line.long 0x00 "DLPR,Data Learn Pattern Register" endif endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x0) group.long 0x200++0x03 line.long 0x00 "RBDR0,RX Buffer Data Register" else hgroup.long 0x200++0x03 hide.long 0x00 "RBDR0,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x100) group.long 0x204++0x03 line.long 0x00 "RBDR1,RX Buffer Data Register" else hgroup.long 0x204++0x03 hide.long 0x00 "RBDR1,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x200) group.long 0x208++0x03 line.long 0x00 "RBDR2,RX Buffer Data Register" else hgroup.long 0x208++0x03 hide.long 0x00 "RBDR2,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x300) group.long 0x20C++0x03 line.long 0x00 "RBDR3,RX Buffer Data Register" else hgroup.long 0x20C++0x03 hide.long 0x00 "RBDR3,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x400) group.long 0x210++0x03 line.long 0x00 "RBDR4,RX Buffer Data Register" else hgroup.long 0x210++0x03 hide.long 0x00 "RBDR4,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x500) group.long 0x214++0x03 line.long 0x00 "RBDR5,RX Buffer Data Register" else hgroup.long 0x214++0x03 hide.long 0x00 "RBDR5,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x600) group.long 0x218++0x03 line.long 0x00 "RBDR6,RX Buffer Data Register" else hgroup.long 0x218++0x03 hide.long 0x00 "RBDR6,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x700) group.long 0x21C++0x03 line.long 0x00 "RBDR7,RX Buffer Data Register" else hgroup.long 0x21C++0x03 hide.long 0x00 "RBDR7,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x800) group.long 0x220++0x03 line.long 0x00 "RBDR8,RX Buffer Data Register" else hgroup.long 0x220++0x03 hide.long 0x00 "RBDR8,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x900) group.long 0x224++0x03 line.long 0x00 "RBDR9,RX Buffer Data Register" else hgroup.long 0x224++0x03 hide.long 0x00 "RBDR9,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0xA00) group.long 0x228++0x03 line.long 0x00 "RBDR10,RX Buffer Data Register" else hgroup.long 0x228++0x03 hide.long 0x00 "RBDR10,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0xB00) group.long 0x22C++0x03 line.long 0x00 "RBDR11,RX Buffer Data Register" else hgroup.long 0x22C++0x03 hide.long 0x00 "RBDR11,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0xC00) group.long 0x230++0x03 line.long 0x00 "RBDR12,RX Buffer Data Register" else hgroup.long 0x230++0x03 hide.long 0x00 "RBDR12,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0xD00) group.long 0x234++0x03 line.long 0x00 "RBDR13,RX Buffer Data Register" else hgroup.long 0x234++0x03 hide.long 0x00 "RBDR13,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0xE00) group.long 0x238++0x03 line.long 0x00 "RBDR14,RX Buffer Data Register" else hgroup.long 0x238++0x03 hide.long 0x00 "RBDR14,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0xF00) group.long 0x23C++0x03 line.long 0x00 "RBDR15,RX Buffer Data Register" else hgroup.long 0x23C++0x03 hide.long 0x00 "RBDR15,RX Buffer Data Register" endif else group.long 0x200++0x03 line.long 0x00 "RBDR0,RX Buffer Data Register" group.long 0x204++0x03 line.long 0x00 "RBDR1,RX Buffer Data Register" group.long 0x208++0x03 line.long 0x00 "RBDR2,RX Buffer Data Register" group.long 0x20C++0x03 line.long 0x00 "RBDR3,RX Buffer Data Register" group.long 0x210++0x03 line.long 0x00 "RBDR4,RX Buffer Data Register" group.long 0x214++0x03 line.long 0x00 "RBDR5,RX Buffer Data Register" group.long 0x218++0x03 line.long 0x00 "RBDR6,RX Buffer Data Register" group.long 0x21C++0x03 line.long 0x00 "RBDR7,RX Buffer Data Register" group.long 0x220++0x03 line.long 0x00 "RBDR8,RX Buffer Data Register" group.long 0x224++0x03 line.long 0x00 "RBDR9,RX Buffer Data Register" group.long 0x228++0x03 line.long 0x00 "RBDR10,RX Buffer Data Register" group.long 0x22C++0x03 line.long 0x00 "RBDR11,RX Buffer Data Register" group.long 0x230++0x03 line.long 0x00 "RBDR12,RX Buffer Data Register" group.long 0x234++0x03 line.long 0x00 "RBDR13,RX Buffer Data Register" group.long 0x238++0x03 line.long 0x00 "RBDR14,RX Buffer Data Register" group.long 0x23C++0x03 line.long 0x00 "RBDR15,RX Buffer Data Register" group.long 0x240++0x03 line.long 0x00 "RBDR16,RX Buffer Data Register" group.long 0x244++0x03 line.long 0x00 "RBDR17,RX Buffer Data Register" group.long 0x248++0x03 line.long 0x00 "RBDR18,RX Buffer Data Register" group.long 0x24C++0x03 line.long 0x00 "RBDR19,RX Buffer Data Register" group.long 0x250++0x03 line.long 0x00 "RBDR20,RX Buffer Data Register" group.long 0x254++0x03 line.long 0x00 "RBDR21,RX Buffer Data Register" group.long 0x258++0x03 line.long 0x00 "RBDR22,RX Buffer Data Register" group.long 0x25C++0x03 line.long 0x00 "RBDR23,RX Buffer Data Register" group.long 0x260++0x03 line.long 0x00 "RBDR24,RX Buffer Data Register" group.long 0x264++0x03 line.long 0x00 "RBDR25,RX Buffer Data Register" group.long 0x268++0x03 line.long 0x00 "RBDR26,RX Buffer Data Register" group.long 0x26C++0x03 line.long 0x00 "RBDR27,RX Buffer Data Register" group.long 0x270++0x03 line.long 0x00 "RBDR28,RX Buffer Data Register" group.long 0x274++0x03 line.long 0x00 "RBDR29,RX Buffer Data Register" group.long 0x278++0x03 line.long 0x00 "RBDR30,RX Buffer Data Register" group.long 0x27C++0x03 line.long 0x00 "RBDR31,RX Buffer Data Register" endif group.long 0x300++0x07 line.long 0x00 "LUTKEY,LUT Key Register" line.long 0x04 "LCKCR,LUT Lock Configuration Register" bitfld.long 0x04 1. " UNLOCK ,LUT unlock" "No effect,Unlock" bitfld.long 0x04 0. " LOCK ,LUT lock" "No effect,Lock" width 7. tree "Look-up Tables" group.long 0x310++0x03 line.long 0x00 "LUT0,Look-up Table Register 0" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x314++0x03 line.long 0x00 "LUT1,Look-up Table Register 1" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x318++0x03 line.long 0x00 "LUT2,Look-up Table Register 2" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x31C++0x03 line.long 0x00 "LUT3,Look-up Table Register 3" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x320++0x03 line.long 0x00 "LUT4,Look-up Table Register 4" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x324++0x03 line.long 0x00 "LUT5,Look-up Table Register 5" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x328++0x03 line.long 0x00 "LUT6,Look-up Table Register 6" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x32C++0x03 line.long 0x00 "LUT7,Look-up Table Register 7" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x330++0x03 line.long 0x00 "LUT8,Look-up Table Register 8" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x334++0x03 line.long 0x00 "LUT9,Look-up Table Register 9" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x338++0x03 line.long 0x00 "LUT10,Look-up Table Register 10" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x33C++0x03 line.long 0x00 "LUT11,Look-up Table Register 11" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x340++0x03 line.long 0x00 "LUT12,Look-up Table Register 12" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x344++0x03 line.long 0x00 "LUT13,Look-up Table Register 13" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x348++0x03 line.long 0x00 "LUT14,Look-up Table Register 14" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x34C++0x03 line.long 0x00 "LUT15,Look-up Table Register 15" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x350++0x03 line.long 0x00 "LUT16,Look-up Table Register 16" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x354++0x03 line.long 0x00 "LUT17,Look-up Table Register 17" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x358++0x03 line.long 0x00 "LUT18,Look-up Table Register 18" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x35C++0x03 line.long 0x00 "LUT19,Look-up Table Register 19" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x360++0x03 line.long 0x00 "LUT20,Look-up Table Register 20" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x364++0x03 line.long 0x00 "LUT21,Look-up Table Register 21" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x368++0x03 line.long 0x00 "LUT22,Look-up Table Register 22" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x36C++0x03 line.long 0x00 "LUT23,Look-up Table Register 23" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x370++0x03 line.long 0x00 "LUT24,Look-up Table Register 24" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x374++0x03 line.long 0x00 "LUT25,Look-up Table Register 25" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x378++0x03 line.long 0x00 "LUT26,Look-up Table Register 26" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x37C++0x03 line.long 0x00 "LUT27,Look-up Table Register 27" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x380++0x03 line.long 0x00 "LUT28,Look-up Table Register 28" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x384++0x03 line.long 0x00 "LUT29,Look-up Table Register 29" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x388++0x03 line.long 0x00 "LUT30,Look-up Table Register 30" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x38C++0x03 line.long 0x00 "LUT31,Look-up Table Register 31" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x390++0x03 line.long 0x00 "LUT32,Look-up Table Register 32" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x394++0x03 line.long 0x00 "LUT33,Look-up Table Register 33" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x398++0x03 line.long 0x00 "LUT34,Look-up Table Register 34" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x39C++0x03 line.long 0x00 "LUT35,Look-up Table Register 35" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A0++0x03 line.long 0x00 "LUT36,Look-up Table Register 36" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A4++0x03 line.long 0x00 "LUT37,Look-up Table Register 37" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A8++0x03 line.long 0x00 "LUT38,Look-up Table Register 38" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3AC++0x03 line.long 0x00 "LUT39,Look-up Table Register 39" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B0++0x03 line.long 0x00 "LUT40,Look-up Table Register 40" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B4++0x03 line.long 0x00 "LUT41,Look-up Table Register 41" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B8++0x03 line.long 0x00 "LUT42,Look-up Table Register 42" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3BC++0x03 line.long 0x00 "LUT43,Look-up Table Register 43" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C0++0x03 line.long 0x00 "LUT44,Look-up Table Register 44" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C4++0x03 line.long 0x00 "LUT45,Look-up Table Register 45" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C8++0x03 line.long 0x00 "LUT46,Look-up Table Register 46" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3CC++0x03 line.long 0x00 "LUT47,Look-up Table Register 47" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D0++0x03 line.long 0x00 "LUT48,Look-up Table Register 48" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D4++0x03 line.long 0x00 "LUT49,Look-up Table Register 49" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D8++0x03 line.long 0x00 "LUT50,Look-up Table Register 50" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3DC++0x03 line.long 0x00 "LUT51,Look-up Table Register 51" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E0++0x03 line.long 0x00 "LUT52,Look-up Table Register 52" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E4++0x03 line.long 0x00 "LUT53,Look-up Table Register 53" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E8++0x03 line.long 0x00 "LUT54,Look-up Table Register 54" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3EC++0x03 line.long 0x00 "LUT55,Look-up Table Register 55" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F0++0x03 line.long 0x00 "LUT56,Look-up Table Register 56" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F4++0x03 line.long 0x00 "LUT57,Look-up Table Register 57" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F8++0x03 line.long 0x00 "LUT58,Look-up Table Register 58" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3FC++0x03 line.long 0x00 "LUT59,Look-up Table Register 59" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x400++0x03 line.long 0x00 "LUT60,Look-up Table Register 60" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x404++0x03 line.long 0x00 "LUT61,Look-up Table Register 61" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x408++0x03 line.long 0x00 "LUT62,Look-up Table Register 62" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x40C++0x03 line.long 0x00 "LUT63,Look-up Table Register 63" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" tree.end width 0x0B tree.end tree.open "uSDHC (Ultra Secured Digital Host Controller" tree "uSDHC1" base ad:0x30B40000 width 22. if ((((per.l(ad:0x30B40000+0x24))&0x04)==0x04)||(((per.l(ad:0x30B40000+0x30))&0x02)==0x02)) rgroup.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" endif else group.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" endif endif group.long 0x04++0x07 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" line.long 0x04 "CMD_ARG,Command Argument Register" if (((per.l(ad:0x30B40000+0x24))&0x80003)==0x80000) group.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" else rgroup.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" endif rgroup.long 0x10++0x03 line.long 0x00 "CMD_RSP0,Command Response Register 0" rgroup.long 0x14++0x03 line.long 0x00 "CMD_RSP1,Command Response Register 1" rgroup.long 0x18++0x03 line.long 0x00 "CMD_RSP2,Command Response Register 2" rgroup.long 0x1C++0x03 line.long 0x00 "CMD_RSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRES_STATE,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT[7] line 7 signal level" "Low,High" bitfld.long 0x00 30. " [6] ,DAT[6] line 6 signal level" "Low,High" bitfld.long 0x00 29. " [5] ,DAT[5] line 5 signal level" "Low,High" newline bitfld.long 0x00 28. " [4] ,DAT[4] line 4 signal level" "Low,High" bitfld.long 0x00 27. " [3] ,DAT[4] line 3 signal level" "Low,High" bitfld.long 0x00 26. " [2] ,DAT[2] line 2 signal level" "Low,High" newline bitfld.long 0x00 25. " [1] ,DAT[1] line 1 signal level" "Low,High" bitfld.long 0x00 24. " [0] ,DAT[0] line 0 signal level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "Low,High" newline bitfld.long 0x00 19. " WPSPL ,Write protect switch pin level" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card detect pin level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card inserted" "Reset/not inserted,Inserted" newline bitfld.long 0x00 15. " TSCD ,Tape select change done" "Not finished,Finished" bitfld.long 0x00 12. " RTR ,Re-Tuning request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "No,Yes" bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK gated off internally" "No,Yes" bitfld.long 0x00 5. " HCKOFF ,HCLK gated off internally" "No,Yes" newline bitfld.long 0x00 4. " IPGOFF ,IPG_CLK gated off internally" "No,Yes" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DATA)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" if (((per.l(ad:0x30B40000+0x28))&0x06)==0x02) group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" else group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" endif group.long 0x2C++0x0F line.long 0x00 "SYS_CTRL,System Control Register" bitfld.long 0x00 28. " RSTT ,Reset tuning" "No reset,Reset" bitfld.long 0x00 27. " INITA ,Initialization active" "Inactive,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" newline bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" bitfld.long 0x00 24. " RSTA ,Software reset for ALL" "No reset,Reset" bitfld.long 0x00 23. " IPP_RST_N ,Value output to CARD for hardware reset" "0,1" newline bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" bitfld.long 0x00 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x04 "INT_STATUS,Interrupt Status Register" eventfld.long 0x04 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x04 26. " TNE ,Tuning error" "No error,Error" eventfld.long 0x04 24. " AC12E ,Auto CMD12 error" "No error,Error" newline eventfld.long 0x04 22. " DEBE ,Data end bit error" "No error,Error" eventfld.long 0x04 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x04 20. " DTOE ,Data timeout error" "No error,Error" newline eventfld.long 0x04 19. " CIE ,Command index error" "No error,Error" eventfld.long 0x04 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x04 17. " CCE ,Command CRC error" "No error,Error" newline eventfld.long 0x04 16. " CTOE ,Command timeout error" "No error,Error" eventfld.long 0x04 14. " TP ,Tuning pass" "Not transferred,Transferred" eventfld.long 0x04 12. " RTE ,Re-Tuning event" "Not requested,Requested" newline eventfld.long 0x04 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x04 7. " CRM ,Card removal" "Not removed,Removed" eventfld.long 0x04 6. " CINS ,Card insertion" "Not inserted,Inserted" newline eventfld.long 0x04 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x04 4. " BWR ,Buffer write ready" "Not ready,Ready" eventfld.long 0x04 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" newline eventfld.long 0x04 2. " BGE ,Block gap event" "Not occurred,Occurred" eventfld.long 0x04 1. " TC ,Transfer complete" "Not completed,Completed" eventfld.long 0x04 0. " CC ,Command complete" "Not completed,Completed" line.long 0x08 "INT_STATUS_EN,Interrupt Status Enable Register" bitfld.long 0x08 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x08 26. " TNESEN ,Tuning error status enable" "Disabled,Enabled" bitfld.long 0x08 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" newline bitfld.long 0x08 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x08 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x08 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" bitfld.long 0x08 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" bitfld.long 0x08 14. " TPSEN ,Tuning pass status enable" "Disabled,Enabled" bitfld.long 0x08 12. " RTESEN ,Re-Tuning event status enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x08 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" bitfld.long 0x08 6. " CINSSEN ,Card insertion status enable" "Disabled,Enabled" newline bitfld.long 0x08 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x08 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" bitfld.long 0x08 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x08 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" bitfld.long 0x08 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x0C "INT_SIGNAL_EN,Interrupt Signal Enable Register" bitfld.long 0x0C 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 26. " TNEIEN ,Tuning error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 14. " TPIEN ,Tuning pass interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 12. " RTEIEN ,Re-Tuning event interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " CINTIEN ,Card interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " DINTIEN ,DMA interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" if ((per.l(ad:0x30B40000+0xCC)&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample clock select" "Fixed clock,Tuned clock" bitfld.long 0x00 22. " EXECUTE_TUNING ,Execute tuning" "Not started,Started" newline rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" newline bitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" endif group.long 0x40++0x0B line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" newline rbitfld.long 0x00 23. " SRS ,Suspend / resume support" "Not supported,Supported" rbitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" newline rbitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL ,Max block length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3,?..." newline bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use tuning for SDR50" "Not required,Required" bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time counter for retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" newline rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" line.long 0x04 "WTMK_LVL,Watermark Level Register" bitfld.long 0x04 24.--28. " WR_BRST_LEN ,Write burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x04 16.--23. 1. " WR_WML ,Write watermark level" bitfld.long 0x04 8.--12. " RD_BRST_LEN ,Read burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." newline hexmask.long.byte 0x04 0.--7. 1. " RD_WML ,Read watermark level" newline line.long 0x08 "MIX_CTRL,Mixer Control Register" bitfld.long 0x08 26. " HS400_MODE ,HS400 enable" "Disabled,Enabled" bitfld.long 0x08 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" newline bitfld.long 0x08 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" bitfld.long 0x08 23. " SMP_CLK_SEL ,Sample clock selection" "Fixed,Tuned" newline bitfld.long 0x08 22. " EXE_TUNE ,Execute tuning" "Not executed,Executed" newline bitfld.long 0x08 7. " AC23EN ,Auto CMD23 enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " NIBBLE_POS ,Nibble position" "Odd high->even high->odd low->even low,Odd high->odd low->even high->even low" bitfld.long 0x08 5. " MSBSEL ,Multi/single block select" "Single,Multiple" newline bitfld.long 0x08 4. " DTDSEL ,Data transfer direction select" "Write,Read" bitfld.long 0x08 3. " DDR_EN ,Dual data rate mode selection" "Disabled,Enabled" newline bitfld.long 0x08 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" bitfld.long 0x08 1. " BCEN ,Block count enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " DMAEN ,DMA enable" "Disabled,Enabled" newline wgroup.long 0x50++0x03 line.long 0x00 "FORCE_EVENT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force event card interrupt" "No interrupt,Interrupt" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No error,Error" bitfld.long 0x00 26. " FEVTTNE ,Force tuning error" "No error,Error" newline bitfld.long 0x00 24. " FEVTAC12E ,Force event auto command 12 error" "No error,Error" bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No error,Error" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No error,Error" newline bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No error,Error" bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No error,Error" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No error,Error" newline bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No error,Error" bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No error,Error" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by auto command 12 error" "No error,Error" newline bitfld.long 0x00 4. " FEVTAC12IE ,Force event auto command 12 index error" "No error,Error" bitfld.long 0x00 3. " FEVTAC12EBE ,Force event auto command 12 end bit error" "No error,Error" bitfld.long 0x00 2. " FEVTAC12CE ,Force event auto command 12 CRC error" "No error,Error" newline bitfld.long 0x00 1. " FEVTAC12TOE ,Force event auto command 12 time out error" "No error,Error" bitfld.long 0x00 0. " FEVTAC12NE ,Force event auto command 12 not executed" "No error,Error" rgroup.long 0x54++0x03 line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "ST_STOP,ST_FDS,ST_CADR,ST_TFR" if (((per.l(ad:0x30B40000+0x30))&0x02)==0x02) rgroup.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" else group.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" endif group.long 0x60++0x03 line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Slave delay line update interval" bitfld.long 0x00 16.--18. " SLV_DLY_TARGET1 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 9.--15. 1. " SLV_OVERRIDE_VAL ,Slave override value" bitfld.long 0x00 8. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " GATE_UPDATE ,The DLL update" "Automatically,No update" newline bitfld.long 0x00 3.--6. " SLV_DLY_TARGET0 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " SLV_FORCE_UPD ,DLL slave update" "No update,Updated" bitfld.long 0x00 1. " RESET ,DLL reset" "No reset,Reset" newline bitfld.long 0x00 0. " ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLL_STATUS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" newline bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if ((per.l(ad:0x30B40000+0x48)&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" textfld " " hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textfld " " hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x70++0x03 line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL Control" bitfld.long 0x00 28.--31. " STROBE_DLL_CTRL_REF_UPDATE_INT ,Strobe DLL control reference update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " STROBE_DLL_CTRL_SLV_UPDATE_INT ,Strobe DLL control slave update interval" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ,Strobe DLL control slave override value" newline bitfld.long 0x00 8. " STROBE_DLL_CTRL_SLV_OVERRIDE ,Strobe DLL control slave override enable" "Disabled,Enabled" bitfld.long 0x00 7. " STROBE_DLL_CTRL_GATE_UPDATE_1 ,Strobe DLL control gate update" "Automatically,No update" bitfld.long 0x00 6. " STROBE_DLL_CTRL_GATE_UPDATE_0 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 3.--5. " STROBE_DLL_CTRL_SLV_DLY_TARGET ,Strobe DLL control slave delay target" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. " STROBE_DLL_CTRL_SLV_FORCE_UPD ,Strobe DLL control slave force updated" "Not forced,Forced" bitfld.long 0x00 1. " STROBE_DLL_CTRL_RESET ,Strobe DLL control reset" "No reset,Reset" newline bitfld.long 0x00 0. " STROBE_DLL_CTRL_ENABLE ,Strobe DLL control enable" "Disabled,Enabled" rgroup.long 0x74++0x03 line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL Status" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_STS_REF_SEL ,Strobe DLL status reference select" hexmask.long.byte 0x00 2.--8. 1. " STROBE_DLL_STS_SLV_SEL ,Strobe DLL status slave select" bitfld.long 0x00 1. " STROBE_DLL_STS_REF_LOCK ,Strobe DLL status reference lock" "Not locked,Locked" newline bitfld.long 0x00 0. " STROBE_DLL_STS_SLV_LOCK ,Strobe DLL status slave lock" "Not locked,Locked" group.long 0xC0++0x0F line.long 0x00 "VEND_SPEC,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal state value" endif newline bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" endif newline bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Not forced,Forced" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending abort command" "Active,Inactive" bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" newline bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of dat3 pin when its used as card detection" "High,Low" endif newline bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage selection (Around: 3.0V,1.8V)" "High,Low" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) newline bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA request enable" "Disabled,Enabled" endif line.long 0x04 "MMC_BOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ACK mode select" "No ACK,ACK" newline sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,,,,,,,SDCLK x 2^28,SDCLK x 2^29" else bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" endif line.long 0x08 "VEND_SPEC2,Vendor Specific 2 Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x08 14. " BUS_RST ,BUS reset" "No reset,Reset" bitfld.long 0x08 13. " PART_DLL_DEBUG ,Debug for part dll" "No debug,Debug" bitfld.long 0x08 12. " ACMD23_ARGU2_EN ,Argument2 register enable for ACMD23" "Disabled,Enabled" newline endif bitfld.long 0x08 11. " HS400_RD_CLK_STOP_EN ,HS400 read clock stop enable" "Disabled,Enabled" bitfld.long 0x08 10. " HS400_WR_CLK_STOP_EN ,HS400 write clock stop enable" "Disabled,Enabled" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the card interrupt status bit" "No,Yes" newline bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0],Invalid" bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" newline bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Disable drive CMD_OE/DAT_OE at once after driving the end bit" "No,Yes" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for ncr changes/ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0C 24. " STD_TUNING_EN ,Standard tuning circuit and procedure enable" "Disabled,Enabled" bitfld.long 0x0C 20.--22. " TUNING_WINDOW ,Select data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " TUNING_STEP ,The increasing delay cell steps in tuning procedure" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,The MAX repeat CMD19 times in tuning procedure" hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start dealy cell point when send first CMD19 in tuning procedure" width 0x0B tree.end tree "uSDHC2" base ad:0x30B50000 width 22. if ((((per.l(ad:0x30B50000+0x24))&0x04)==0x04)||(((per.l(ad:0x30B50000+0x30))&0x02)==0x02)) rgroup.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" endif else group.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" endif endif group.long 0x04++0x07 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" line.long 0x04 "CMD_ARG,Command Argument Register" if (((per.l(ad:0x30B50000+0x24))&0x80003)==0x80000) group.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" else rgroup.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" endif rgroup.long 0x10++0x03 line.long 0x00 "CMD_RSP0,Command Response Register 0" rgroup.long 0x14++0x03 line.long 0x00 "CMD_RSP1,Command Response Register 1" rgroup.long 0x18++0x03 line.long 0x00 "CMD_RSP2,Command Response Register 2" rgroup.long 0x1C++0x03 line.long 0x00 "CMD_RSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRES_STATE,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT[7] line 7 signal level" "Low,High" bitfld.long 0x00 30. " [6] ,DAT[6] line 6 signal level" "Low,High" bitfld.long 0x00 29. " [5] ,DAT[5] line 5 signal level" "Low,High" newline bitfld.long 0x00 28. " [4] ,DAT[4] line 4 signal level" "Low,High" bitfld.long 0x00 27. " [3] ,DAT[4] line 3 signal level" "Low,High" bitfld.long 0x00 26. " [2] ,DAT[2] line 2 signal level" "Low,High" newline bitfld.long 0x00 25. " [1] ,DAT[1] line 1 signal level" "Low,High" bitfld.long 0x00 24. " [0] ,DAT[0] line 0 signal level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "Low,High" newline bitfld.long 0x00 19. " WPSPL ,Write protect switch pin level" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card detect pin level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card inserted" "Reset/not inserted,Inserted" newline bitfld.long 0x00 15. " TSCD ,Tape select change done" "Not finished,Finished" bitfld.long 0x00 12. " RTR ,Re-Tuning request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "No,Yes" bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK gated off internally" "No,Yes" bitfld.long 0x00 5. " HCKOFF ,HCLK gated off internally" "No,Yes" newline bitfld.long 0x00 4. " IPGOFF ,IPG_CLK gated off internally" "No,Yes" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DATA)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" if (((per.l(ad:0x30B50000+0x28))&0x06)==0x02) group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" else group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" endif group.long 0x2C++0x0F line.long 0x00 "SYS_CTRL,System Control Register" bitfld.long 0x00 28. " RSTT ,Reset tuning" "No reset,Reset" bitfld.long 0x00 27. " INITA ,Initialization active" "Inactive,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" newline bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" bitfld.long 0x00 24. " RSTA ,Software reset for ALL" "No reset,Reset" bitfld.long 0x00 23. " IPP_RST_N ,Value output to CARD for hardware reset" "0,1" newline bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" bitfld.long 0x00 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x04 "INT_STATUS,Interrupt Status Register" eventfld.long 0x04 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x04 26. " TNE ,Tuning error" "No error,Error" eventfld.long 0x04 24. " AC12E ,Auto CMD12 error" "No error,Error" newline eventfld.long 0x04 22. " DEBE ,Data end bit error" "No error,Error" eventfld.long 0x04 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x04 20. " DTOE ,Data timeout error" "No error,Error" newline eventfld.long 0x04 19. " CIE ,Command index error" "No error,Error" eventfld.long 0x04 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x04 17. " CCE ,Command CRC error" "No error,Error" newline eventfld.long 0x04 16. " CTOE ,Command timeout error" "No error,Error" eventfld.long 0x04 14. " TP ,Tuning pass" "Not transferred,Transferred" eventfld.long 0x04 12. " RTE ,Re-Tuning event" "Not requested,Requested" newline eventfld.long 0x04 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x04 7. " CRM ,Card removal" "Not removed,Removed" eventfld.long 0x04 6. " CINS ,Card insertion" "Not inserted,Inserted" newline eventfld.long 0x04 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x04 4. " BWR ,Buffer write ready" "Not ready,Ready" eventfld.long 0x04 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" newline eventfld.long 0x04 2. " BGE ,Block gap event" "Not occurred,Occurred" eventfld.long 0x04 1. " TC ,Transfer complete" "Not completed,Completed" eventfld.long 0x04 0. " CC ,Command complete" "Not completed,Completed" line.long 0x08 "INT_STATUS_EN,Interrupt Status Enable Register" bitfld.long 0x08 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x08 26. " TNESEN ,Tuning error status enable" "Disabled,Enabled" bitfld.long 0x08 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" newline bitfld.long 0x08 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x08 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x08 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" bitfld.long 0x08 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" bitfld.long 0x08 14. " TPSEN ,Tuning pass status enable" "Disabled,Enabled" bitfld.long 0x08 12. " RTESEN ,Re-Tuning event status enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x08 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" bitfld.long 0x08 6. " CINSSEN ,Card insertion status enable" "Disabled,Enabled" newline bitfld.long 0x08 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x08 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" bitfld.long 0x08 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x08 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" bitfld.long 0x08 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x0C "INT_SIGNAL_EN,Interrupt Signal Enable Register" bitfld.long 0x0C 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 26. " TNEIEN ,Tuning error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 14. " TPIEN ,Tuning pass interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 12. " RTEIEN ,Re-Tuning event interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " CINTIEN ,Card interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " DINTIEN ,DMA interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" if ((per.l(ad:0x30B50000+0xCC)&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample clock select" "Fixed clock,Tuned clock" bitfld.long 0x00 22. " EXECUTE_TUNING ,Execute tuning" "Not started,Started" newline rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" newline bitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" endif group.long 0x40++0x0B line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" newline rbitfld.long 0x00 23. " SRS ,Suspend / resume support" "Not supported,Supported" rbitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" newline rbitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL ,Max block length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3,?..." newline bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use tuning for SDR50" "Not required,Required" bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time counter for retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" newline rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" line.long 0x04 "WTMK_LVL,Watermark Level Register" bitfld.long 0x04 24.--28. " WR_BRST_LEN ,Write burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x04 16.--23. 1. " WR_WML ,Write watermark level" bitfld.long 0x04 8.--12. " RD_BRST_LEN ,Read burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." newline hexmask.long.byte 0x04 0.--7. 1. " RD_WML ,Read watermark level" newline line.long 0x08 "MIX_CTRL,Mixer Control Register" bitfld.long 0x08 26. " HS400_MODE ,HS400 enable" "Disabled,Enabled" bitfld.long 0x08 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" newline bitfld.long 0x08 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" bitfld.long 0x08 23. " SMP_CLK_SEL ,Sample clock selection" "Fixed,Tuned" newline bitfld.long 0x08 22. " EXE_TUNE ,Execute tuning" "Not executed,Executed" newline bitfld.long 0x08 7. " AC23EN ,Auto CMD23 enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " NIBBLE_POS ,Nibble position" "Odd high->even high->odd low->even low,Odd high->odd low->even high->even low" bitfld.long 0x08 5. " MSBSEL ,Multi/single block select" "Single,Multiple" newline bitfld.long 0x08 4. " DTDSEL ,Data transfer direction select" "Write,Read" bitfld.long 0x08 3. " DDR_EN ,Dual data rate mode selection" "Disabled,Enabled" newline bitfld.long 0x08 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" bitfld.long 0x08 1. " BCEN ,Block count enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " DMAEN ,DMA enable" "Disabled,Enabled" newline wgroup.long 0x50++0x03 line.long 0x00 "FORCE_EVENT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force event card interrupt" "No interrupt,Interrupt" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No error,Error" bitfld.long 0x00 26. " FEVTTNE ,Force tuning error" "No error,Error" newline bitfld.long 0x00 24. " FEVTAC12E ,Force event auto command 12 error" "No error,Error" bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No error,Error" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No error,Error" newline bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No error,Error" bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No error,Error" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No error,Error" newline bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No error,Error" bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No error,Error" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by auto command 12 error" "No error,Error" newline bitfld.long 0x00 4. " FEVTAC12IE ,Force event auto command 12 index error" "No error,Error" bitfld.long 0x00 3. " FEVTAC12EBE ,Force event auto command 12 end bit error" "No error,Error" bitfld.long 0x00 2. " FEVTAC12CE ,Force event auto command 12 CRC error" "No error,Error" newline bitfld.long 0x00 1. " FEVTAC12TOE ,Force event auto command 12 time out error" "No error,Error" bitfld.long 0x00 0. " FEVTAC12NE ,Force event auto command 12 not executed" "No error,Error" rgroup.long 0x54++0x03 line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "ST_STOP,ST_FDS,ST_CADR,ST_TFR" if (((per.l(ad:0x30B50000+0x30))&0x02)==0x02) rgroup.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" else group.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" endif group.long 0x60++0x03 line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Slave delay line update interval" bitfld.long 0x00 16.--18. " SLV_DLY_TARGET1 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 9.--15. 1. " SLV_OVERRIDE_VAL ,Slave override value" bitfld.long 0x00 8. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " GATE_UPDATE ,The DLL update" "Automatically,No update" newline bitfld.long 0x00 3.--6. " SLV_DLY_TARGET0 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " SLV_FORCE_UPD ,DLL slave update" "No update,Updated" bitfld.long 0x00 1. " RESET ,DLL reset" "No reset,Reset" newline bitfld.long 0x00 0. " ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLL_STATUS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" newline bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if ((per.l(ad:0x30B50000+0x48)&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" textfld " " hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textfld " " hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x70++0x03 line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL Control" bitfld.long 0x00 28.--31. " STROBE_DLL_CTRL_REF_UPDATE_INT ,Strobe DLL control reference update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " STROBE_DLL_CTRL_SLV_UPDATE_INT ,Strobe DLL control slave update interval" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ,Strobe DLL control slave override value" newline bitfld.long 0x00 8. " STROBE_DLL_CTRL_SLV_OVERRIDE ,Strobe DLL control slave override enable" "Disabled,Enabled" bitfld.long 0x00 7. " STROBE_DLL_CTRL_GATE_UPDATE_1 ,Strobe DLL control gate update" "Automatically,No update" bitfld.long 0x00 6. " STROBE_DLL_CTRL_GATE_UPDATE_0 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 3.--5. " STROBE_DLL_CTRL_SLV_DLY_TARGET ,Strobe DLL control slave delay target" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. " STROBE_DLL_CTRL_SLV_FORCE_UPD ,Strobe DLL control slave force updated" "Not forced,Forced" bitfld.long 0x00 1. " STROBE_DLL_CTRL_RESET ,Strobe DLL control reset" "No reset,Reset" newline bitfld.long 0x00 0. " STROBE_DLL_CTRL_ENABLE ,Strobe DLL control enable" "Disabled,Enabled" rgroup.long 0x74++0x03 line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL Status" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_STS_REF_SEL ,Strobe DLL status reference select" hexmask.long.byte 0x00 2.--8. 1. " STROBE_DLL_STS_SLV_SEL ,Strobe DLL status slave select" bitfld.long 0x00 1. " STROBE_DLL_STS_REF_LOCK ,Strobe DLL status reference lock" "Not locked,Locked" newline bitfld.long 0x00 0. " STROBE_DLL_STS_SLV_LOCK ,Strobe DLL status slave lock" "Not locked,Locked" group.long 0xC0++0x0F line.long 0x00 "VEND_SPEC,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal state value" endif newline bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" endif newline bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Not forced,Forced" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending abort command" "Active,Inactive" bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" newline bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of dat3 pin when its used as card detection" "High,Low" endif newline bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage selection (Around: 3.0V,1.8V)" "High,Low" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) newline bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA request enable" "Disabled,Enabled" endif line.long 0x04 "MMC_BOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ACK mode select" "No ACK,ACK" newline sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,,,,,,,SDCLK x 2^28,SDCLK x 2^29" else bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" endif line.long 0x08 "VEND_SPEC2,Vendor Specific 2 Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x08 14. " BUS_RST ,BUS reset" "No reset,Reset" bitfld.long 0x08 13. " PART_DLL_DEBUG ,Debug for part dll" "No debug,Debug" bitfld.long 0x08 12. " ACMD23_ARGU2_EN ,Argument2 register enable for ACMD23" "Disabled,Enabled" newline endif bitfld.long 0x08 11. " HS400_RD_CLK_STOP_EN ,HS400 read clock stop enable" "Disabled,Enabled" bitfld.long 0x08 10. " HS400_WR_CLK_STOP_EN ,HS400 write clock stop enable" "Disabled,Enabled" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the card interrupt status bit" "No,Yes" newline bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0],Invalid" bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" newline bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Disable drive CMD_OE/DAT_OE at once after driving the end bit" "No,Yes" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for ncr changes/ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0C 24. " STD_TUNING_EN ,Standard tuning circuit and procedure enable" "Disabled,Enabled" bitfld.long 0x0C 20.--22. " TUNING_WINDOW ,Select data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " TUNING_STEP ,The increasing delay cell steps in tuning procedure" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,The MAX repeat CMD19 times in tuning procedure" hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start dealy cell point when send first CMD19 in tuning procedure" width 0x0B tree.end tree.end tree.end tree.open "Connectivity" tree.open "USB3.0 (Universal Serial Bus Control 3.0)" tree "USB1" base ad:0x38100000 width 16. rgroup.long 0x00++0x1F line.long 0x00 "CAPLENGTH,Capability register length and HC interface version number" hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,HC interface version number" hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability register length" line.long 0x04 "HCSPARAMS1,Host controller structural parameters 1" hexmask.long.byte 0x04 24.--31. 1. " MAXPORTS ,Maximum number of ports set as 2" hexmask.long.word 0x04 8.--18. 1. " MAXINTRS ,Number of interrupters set as 1" textline " " hexmask.long.byte 0x04 0.--7. 1. " MAXSLOTS ,Number of device slots set as 127" line.long 0x08 "HCSPARAMS2,Host controller structural parameters 2" bitfld.long 0x08 27.--31. " MAXSCRATCHPADBUFS ,Max scratchpad buffers low set as 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 26. " SPR ,Scratchpad restore" "Not restored,Restored" textline " " bitfld.long 0x08 21.--25. " MAXSCRATCHPADBUFS ,Max scratchpad buffers high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. " ERSTMAX ,Event ring segment table max set as 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 0.--3. " IST ,Isochronous scheduling threshold set as 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "HCSPARAMS3,Host controller structural parameters 3" hexmask.long.word 0x0C 16.--31. 1. " U2_DEVIC_EXIT_LAT ,U2 device exit latency" hexmask.long.byte 0x0C 0.--7. 1. " U1_DEVIC_EXIT_LAT ,U1 device exit latency" line.long 0x10 "HCCPARAMS1, Host controller capability parameters 1" hexmask.long.word 0x10 16.--31. 0x01 " xECP ,xHCI extended capabilities pointer" bitfld.long 0x10 12.--15. " MAXPSASIZE ,Maximum primary stream array size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 11. " CFC ,Contiguous frame ID capability" "No capability,Capability" bitfld.long 0x10 10. " SEC ,Stopped EDLTA capability" "No capability,Capability" textline " " bitfld.long 0x10 9. " SPC ,Short packet capability" "No capability,Capability" bitfld.long 0x10 8. " PAE ,Parse all event data" "Not parsed,Parsed" textline " " bitfld.long 0x10 7. " NSS ,No secondary SID support" "Supported,Not supported" bitfld.long 0x10 6. " LTC ,Latency tolerance messaging capability" "No capability,Capability" textline " " bitfld.long 0x10 5. " LHRC ,Light HC reset capability" "No capability,Capability" bitfld.long 0x10 4. " PIND ,Port indicators" "0,1" textline " " bitfld.long 0x10 3. " PPC ,Port power control" "0,1" bitfld.long 0x10 2. " CSZ ,Context size" "0,1" textline " " bitfld.long 0x10 1. " BNC ,BW negotiation capability" "No capability,Capability" bitfld.long 0x10 0. " AC64 ,64_bit addressing capability" "No capability,Capability" line.long 0x14 "DBOFF,Doorbell offset" hexmask.long 0x14 2.--31. 0x04 " DOORBELL_ARRAY_OFFSET ,Doorbell array offset" line.long 0x18 "RTSOFF,Runtime register space offset" hexmask.long 0x18 5.--31. 0x20 " RUNTIME_REG_SPAC_OFFSET ,Runtime register space offset" line.long 0x1C "HCCPARAMS1,HOST controller capability parameters 2" bitfld.long 0x1C 5. " CIC ,Configuration information capability" "No capability,Capability" bitfld.long 0x1C 4. " LEC ,Large ESIT payload capability" "No capability,Capability" textline " " bitfld.long 0x1C 3. " CTC ,Compliance transition capability" "No capability,Capability" bitfld.long 0x1C 2. " FSC ,Force save context capability" "No capability,Capability" textline " " bitfld.long 0x1C 1. " CMC ,Configure endpoint command max exit latency too large capability" "No capability,Capability" bitfld.long 0x1C 0. " U3C ,U3 entry capability" "No capability,Capability" group.long 0xC100++0x07 line.long 0x00 "GSBUSCFG0,Global SoC bus configuration register 0" bitfld.long 0x00 28.--31. " DATRDREQINFO ,AXI-cache for data read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " DESRDREQINFO ,AXI-cache for description read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--23. " DATWRREQINFO ,AXI-cache for data write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " DESWRREQINFO ,AXI-cache for description write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " INCR256BRSTENA ,INCR256 burst enable" "Disabled,Enabled" bitfld.long 0x00 6. " INCR128BRSTENA ,INCR128 burst enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " INCR64BRSTENA ,INCR64 burst enable" "Disabled,Enabled" bitfld.long 0x00 4. " INCR32BRSTENA ,INCR32 burst enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INCR16BRSTENA ,INCR16 burst enable" "Disabled,Enabled" bitfld.long 0x00 2. " INCR8BRSTENA ,INCR8 burst enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " INCR4BRSTENA ,INCR4 burst enable" "Disabled,Enabled" bitfld.long 0x00 0. " INCRBRSTENA ,Undefined length INCR burst type enable" "Disabled,Enabled" line.long 0x04 "GSBUSCFG1,Global SoC bus configuration register 1" bitfld.long 0x04 12. " EN1KPAGE ,1K page boundary enable" "Disabled,Enabled" bitfld.long 0x04 8.--11. " PIPETRANSLIM ,AXI pipelined transfer request limit" "1 request,2 requests,3 requests,4 requests,5 requests,6 requests,7 requests,8 requests,9 requests,10 requests,11 requests,12 requests,13 requests,14 requests,15 requests,16 requests" if (((per.l(ad:0x38100000+0xC108))&0x20000000)==0x20000000) group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx threshold control register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBTXPKTCNT ,USB transmit packet count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 16.--23. 1. " USBMAXTXBUTSTSIZE ,USB maximum Tx burst size" else group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx threshold control register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 16.--23. 1. " USBMAXTXBUTSTSIZE ,USB maximum Tx burst size" endif if (((per.l(ad:0x38100000+0xC10C))&0x20000000)==0x20000000) group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx threshold control register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBRXPKTCNT ,USB receive packet count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 19.--23. " USBMAXRXBURSTSIZE ,USB maximum receive burst size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx threshold control register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" endif if (((per.l(ad:0x38100000+0xC118))&0x03)==0x00) if (((per.l(ad:0x38100000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global core control register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Enabled,Bypassed" textline " " bitfld.long 0x00 17. " BYPSSETADDR ,Bypass Set address in device mode" "No effect," bitfld.long 0x00 16. " U2RSTECN ,Connecting SS mode 3 more times if failed" "No,Yes" textline " " bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scaling down device view of a SoF/USOF/ITP duration" "1024 bytes,512 bytes,256 bytes,128 bytes" bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host mode,Device mode,Device OTG 2.0 device" textline " " bitfld.long 0x00 11. " CORESOFTRESET ,Core soft reset" "No reset,Reset" rbitfld.long 0x00 10. " SOFITSYNC ,Sofitsync" "0,1" textline " " bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus,Pipe,Pipe/2," bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" textline " " bitfld.long 0x00 2. " U2EXIT_LFPS ,Causing the device to exit from U2 state because the LFPS filter value is 248 ns" "0,1" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global core control register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Enabled,Bypassed" textline " " bitfld.long 0x00 17. " BYPSSETADDR ,Bypass Set address in device mode" "No effect," bitfld.long 0x00 16. " U2RSTECN ,Connecting SS mode 3 more times if failed" "No,Yes" textline " " bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scaling down device view of a SoF/USOF/ITP duration" "125 us,62.5 us,31.25 us,15.625 us" bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host mode,Device mode,Device OTG 2.0 device" textline " " bitfld.long 0x00 11. " CORESOFTRESET ,Core soft reset" "No reset,Reset" rbitfld.long 0x00 10. " SOFITSYNC ,Sofitsync" "0,1" textline " " bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus,Pipe,Pipe/2," bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" textline " " bitfld.long 0x00 2. " U2EXIT_LFPS ,Causing the device to exit from U2 state because the LFPS filter value is 248 ns" "0,1" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif else if (((per.l(ad:0x38100000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global core control register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Enabled,Bypassed" textline " " bitfld.long 0x00 17. " BYPSSETADDR ,Bypass Set address in device mode" "No effect," textline " " bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scaling down device view of a SoF/USOF/ITP duration" "1024 bytes,512 bytes,256 bytes,128 bytes" bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host mode,Device mode,Device OTG 2.0 device" textline " " bitfld.long 0x00 11. " CORESOFTRESET ,Core soft reset" "No reset,Reset" rbitfld.long 0x00 10. " SOFITSYNC ,Sofitsync" "0,1" textline " " bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus,Pipe,Pipe/2," bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" textline " " bitfld.long 0x00 2. " U2EXIT_LFPS ,Causing the device to exit from U2 state because the LFPS filter value is 248 ns" "0,1" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global core control register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Enabled,Bypassed" textline " " bitfld.long 0x00 17. " BYPSSETADDR ,Bypass Set address in device mode" "No effect," textline " " bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scaling down device view of a SoF/USOF/ITP duration" "125 us,62.5 us,31.25 us,15.625 us" bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host mode,Device mode,Device OTG 2.0 device" textline " " bitfld.long 0x00 11. " CORESOFTRESET ,Core soft reset" "No reset,Reset" rbitfld.long 0x00 10. " SOFITSYNC ,Sofitsync" "0,1" textline " " bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus,Pipe,Pipe/2," bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" textline " " bitfld.long 0x00 2. " U2EXIT_LFPS ,Causing the device to exit from U2 state because the LFPS filter value is 248 ns" "0,1" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif endif group.long 0xC118++0x03 line.long 0x00 "GSTS,Global status register" rbitfld.long 0x00 10. " OTG_IP ,OTG Interrupt pending" "No pending,Pending" rbitfld.long 0x00 7. " HOST_IP ,HOST Interrupt pending" "No pending,Pending" textline " " rbitfld.long 0x00 6. " DEVICE_IP ,DEVICE Interrupt pending" "No pending,Pending" bitfld.long 0x00 5. " CSRTIMEOUT ,CSR timeout" "0,1" textline " " bitfld.long 0x00 4. " BUSERRADDR ,Bus error address valid" "No valid,Valid" rbitfld.long 0x00 0.--1. " CURMOD ,Current mode of operation" "Device mode,Host mode,?..." if (((per.l(ad:0x38100000+0xC110))&0x400)==0x01) if (((per.l(ad:0x38100000+0xC118))&0x03)==0x01) if (((per.l(ad:0x38100000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 28. " TZ_IPAP_LINECHECK_DIS ,TZ IPGAP LINECKECK disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" textline " " bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" elif (((per.l(ad:0x38100000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,FILTER SE0 FS/LS EOP" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" textline " " bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" else group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" endif elif (((per.l(ad:0x38100000+0xC118))&0x03)==0x00) if (((per.l(ad:0x38100000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 28. " TZ_IPAP_LINECHECK_DIS ,TZ IPGAP LINECKECK disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,DEV_FORCE_20_CLK_FOR_30_CLK" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" elif (((per.l(ad:0x38100000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,FILTER SE0 FS/LS EOP" "Disabled,Enabled" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,DEV_FORCE_20_CLK_FOR_30_CLK" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" elif (((per.l(ad:0x38100000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" else group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,DEV_FORCE_20_CLK_FOR_30_CLK" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" textline " " bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" endif endif else if (((per.l(ad:0x38100000+0xC118))&0x03)==0x01) if (((per.l(ad:0x38100000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 28. " TZ_IPAP_LINECHECK_DIS ,TZ IPGAP LINECKECK disable" "No,Yes" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" elif (((per.l(ad:0x38100000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,FILTER SE0 FS/LS EOP" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" else group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" endif elif (((per.l(ad:0x38100000+0xC118))&0x03)==0x00) if (((per.l(ad:0x38100000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 28. " TZ_IPAP_LINECHECK_DIS ,TZ IPGAP LINECKECK disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,DEV_FORCE_20_CLK_FOR_30_CLK" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" textline " " bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" elif (((per.l(ad:0x38100000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,FILTER SE0 FS/LS EOP" "Disabled,Enabled" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,DEV_FORCE_20_CLK_FOR_30_CLK" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" textline " " bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" elif (((per.l(ad:0x38100000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" textline " " bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" else group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,DEV_FORCE_20_CLK_FOR_30_CLK" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" endif endif endif group.long 0xC128++0x03 line.long 0x00 "GUID,Global user ID register" if (((per.l(ad:0x38100000+0xC118))&0x03)==0x01) group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global user control register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Terms of nano seconds the period of ref_clk" bitfld.long 0x00 21. " NOEXTRDI ,No extra delay between SOF and the first pocket" "Waiting,No waiting" textline " " bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,SPRASE control transaction enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RESBWHSEPS ,Reserving 85% bandwidth for HS periodic EPs" "0,1" bitfld.long 0x00 15. " CMDEVADDR ,Compliance mode for device address" "Equal to Slot AD,Increment device address" textline " " bitfld.long 0x00 14. " USBHSSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote UX exit" "Not looking for LFPS overlap,Looking for LFPS overlap" textline " " bitfld.long 0x00 12. " EXTCAPSUPTEM ,External extended capability support enable" "Disabled,Enabled" bitfld.long 0x00 11. " INSERTEXTRFSBODI ,Insert extra delay between FS bulk OUT transaction" "Not inserted,Inserted" textline " " bitfld.long 0x00 9.--10. " DTCT ,Deice timeout coarse tuning" "STDT value used,500 us,1.5 us,6.5 us" hexmask.long.word 0x00 0.--8. 1. " DTFT ,Device timeout fine tuning" else group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global user control register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Terms of nano seconds the period of ref_clk" bitfld.long 0x00 21. " NOEXTRDI ,No extra delay between SOF and the first pocket" "Waiting,No waiting" textline " " bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,SPRASE control transaction enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " USBHSSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote UX exit" "Not looking for LFPS overlap,Looking for LFPS overlap" textline " " bitfld.long 0x00 12. " EXTCAPSUPTEM ,External extended capability support enable" "Disabled,Enabled" bitfld.long 0x00 11. " INSERTEXTRFSBODI ,Insert extra delay between FS bulk OUT transaction" "Not inserted,Inserted" textline " " bitfld.long 0x00 9.--10. " DTCT ,Deice timeout coarse tuning" "STDT value used,500 us,1.5 us,6.5 us" hexmask.long.word 0x00 0.--8. 1. " DTFT ,Device timeout fine tuning" endif rgroup.long 0xC130++0x07 line.long 0x00 "GBUSERRADDRLO,Global SoC bus error address register low" line.long 0x04 "GBUSERRADDRHI,Global SoC bus error address register high" group.long 0xC138++0x07 line.long 0x00 "GPRTBIMAPLO,Global SS port to bus instance mapping register - low" bitfld.long 0x00 0.--3. " BINUM1 ,SS USB instance number for port." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAPHI,Global SS port to bus instance mapping register - high" bitfld.long 0x04 0.--3. " BINUM9 ,SS USB instance number for port 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xC140++0x1F line.long 0x00 "GHWPARAMS0,Global hardware parameters register 0" hexmask.long.byte 0x00 24.--31. 1. " DWC_USB3_AWIDTH ,Master/Slave address bus width" hexmask.long.byte 0x00 16.--23. 1. " DWC_USB3_SDWIDTH ,Slave bus data bus width" textline " " hexmask.long.byte 0x00 8.--15. 1. " DWC_USB3_MDWIDTH ,Master bus data bus width" bitfld.long 0x00 6.--7. " DWC_USB3_SBUS_TYPE ,Slave bus interface type" "AHB,,," textline " " bitfld.long 0x00 3.--5. " DWC_USB3_MBUS_TYPE ,Master bus interface type" ",AXI,?..." bitfld.long 0x00 0.--2. " DWC_USB3_MODE ,Mode of operation" ",,DRD,?..." line.long 0x04 "GHWPARAMS1,Global hardware parameters register 1" bitfld.long 0x04 31. " DWC_USB3_EN_DBC ,Enables xHCI debug capability" "No,Yes" bitfld.long 0x04 30. " DWC_USB3_RM_OPT_FEATURES ,Removing optional features" "No,Yes" textline " " bitfld.long 0x04 28. " DWC_USB3_RAM_BUS_CLKS_SYNC ,RAM clock and the Bus clock are synchronous to each other" "No,Yes" bitfld.long 0x04 27. " DWC_USB3_MAC_BUS_CLKS_SYNC ,MAC clock and the Bus clock are synchronous to each other" "No,Yes" textline " " bitfld.long 0x04 26. " DWC_USB3_MAC_PHY_CLKS_SYNC ,MAC clock and the PHY clock are synchronous to each other" "No,Yes" bitfld.long 0x04 24.--25. " DWC_USB3_EN_PWROPT ,Power optimization mode" "No power optimization,Clock gating only,," textline " " bitfld.long 0x04 23. " DWC_USB3_SPRAM_TYP ,Synchronous static RAM type" "2-port RAM,Single-port RAM" bitfld.long 0x04 21.--22. " DWC_USB3_NUM_RAMS ,NUMBER of RAMS" "1,2,3," textline " " bitfld.long 0x04 15.--20. " DWC_USB3_DEVICE_NUM_INT ,Number of device mode event buffers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 12.--14. " DWC_USB3_ASPACEWIDTH ,the address space port width of the master and slave bus interfaces" "1,2,3,4,5,6,," textline " " bitfld.long 0x04 9.--11. " DWC_USB3_REQINFOWIDTH ,request/response info port width of the master and slave bus interfaces" ",,,4,5,6,," bitfld.long 0x04 6.--8. " DWC_USB3_DATAINFOWIDTH ,Data info port width of the master and slave bus interfaces" "1,2,3,4,5,6,," textline " " bitfld.long 0x04 3.--5. " DWC_USB3_BURSTINFOWIDTH ,Burst port width of the master and slave bus interfaces" "1,2,3,4,5,6,7,8" bitfld.long 0x04 0.--2. " DWC_USB3_IDWIDTH1 ,Master ID port width" ",,,4,5,6,7,8" line.long 0x08 "GHWPARAMS2,Global hardware parameters register 2" line.long 0x0C "GHWPARAMS3,Global hardware parameters register 3" hexmask.long.word 0x0C 23.--31. 1. " DWC_USB3_CACHE_TOTAL_XFER_RESOURCES ,Maximum number of transfer resources in the core" bitfld.long 0x0C 18.--22. " DWC_USB3_NUM_IN_EPS ,Number of device mode active IN endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0C 12.--17. " DWC_USB3_NUM_EPS ,Number of device mode endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 10. " DWC_USB3_VENDOR_CTL_INTERAFACE ,Enabling the UTMI+ PHY vendor control interface" "Disabled,Enabled" textline " " bitfld.long 0x0C 6.--7. " DWC_USB3_HSPHY_DWIDTH ,Enabling the UTMI+ PHY vendor control interface" ",,8/16 bits," bitfld.long 0x0C 2.--3. " DWC_USB3_HSPHY_INTERFACE ,high-speed PHY interface" "0,1,2,3" textline " " bitfld.long 0x0C 0.--1. " DWC_USB3_SSPHY_INTERFACE ,high-speed PHY interface" "0,1,2,3" line.long 0x10 "GHWPARAMS4,Global hardware parameters register 4" bitfld.long 0x10 28.--31. " DWC_USB3_BMU_LSP_DEPTH ,depth of the BMU-LSP status buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. " DWC_USB3_BMU_PTL_DEPTH ,depth of the BMU-LSP source/sink buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 23. " DWC_USB3_EN_ISOC_SUPT ,Enabling isochronous endpoint capability" "Disabled,Enabled" textline " " bitfld.long 0x10 17.--20. " DWC_USB3_NUM_SS_USB_INSTANCES ,Number of SuperSpeed USB bus instances" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 0.--5. " DWC_USB3_CACHE_TRBS_PER_TRANSFER ,Number of cached TRBs per transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "GHWPARAMS5,Global hardware parameters register 5" bitfld.long 0x14 22.--27. " DWC_USB3_DFQ_FIFO_DEPT_H ,Size of the BMU descriptor fetch request queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 16.--21. " DWC_USB3_DWQ_FIFO_DEPT_H ,Size of the BMU descriptor write queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x14 10.--15. " DWC_USB3_TXQ_FIFO_DEPT_H ,Size of the BMU TX request queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 4.--9. " DWC_USB3_RXQ_FIFO_DEPT_H ,Size of the BMU RX request queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x14 0.--3. " DWC_USB3_BMU_BUSGM_DEPTH ,Depth of the BMU-BUSGM source/sink buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "GHWPARAMS6,Global hardware parameters register 6" hexmask.long.word 0x18 16.--31. 1. " DWC_USB3_RAM0_DEPTH ,Depth of RAM0" bitfld.long 0x18 15. " BUSFLTRSSUPPORT ,Adding a filter for VBUS and ID related control inputs from the PHY" "No,Yes" textline " " bitfld.long 0x18 12. " ADPSUPPORT ,Internal ADP capability of the USB 3.0 core enabled" "Disabled,Enabled" bitfld.long 0x18 11. " HNPSUPPORT ,HNP support enabled" "Disabled,Enabled" textline " " bitfld.long 0x18 10. " SRPSUPPORT ,SRP support enabled" "Disabled,Enabled" bitfld.long 0x18 7. " DWC_USB3_EN_FPGA ,Hardware validation/driver development with an FPGA platform" "No,Yes" textline " " bitfld.long 0x18 6. " DWC_USB3_EN_DBG_PORTS ,FPGA hardware validation of the core" "No,Yes" bitfld.long 0x18 0.--5. " DWC_USB3_PSQ_FIFIO_DEPTH ,size of the BMU protocol status queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "GHWPARAMS7,Global hardware parameters register 7" hexmask.long.word 0x1C 16.--31. 1. " DWC_USB3_RAM2_DEPTH ,Total RAM2 depth" hexmask.long.word 0x1C 0.--15. 1. " DWC_USB3_RAM1_DEPTH ,Total RAM1 depth" group.long 0xC180++0x07 line.long 0x00 "GPRTBIMAP_HSLO,Global high-speed port to bus instance mapping register - low" bitfld.long 0x00 0.--3. " BINUM1 ,HS USB instance number for port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAP_HSHI,Global high-speed port to bus instance mapping register - high" bitfld.long 0x04 0.--3. " BINUM9 ,HS USB instance number for port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x38100000+0xC118))&0x03)==0x00) group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFG,Global USB2 PHY configuration register" bitfld.long 0x00 31. " PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,USB 2.0 PHY free-running PHY clock exists" "No existed,Existed" textline " " bitfld.long 0x00 22.--24. " LSTRD ,LS turnaround time" "2-bit times,2.5-bit times,3-bit times,3.5-bit times,4-bit times,4.5-bit times,5-bit times,5.5-bit times" bitfld.long 0x00 19.--21. " LSPID ,LS inter-packet time" "2-bit times,2.5-bit times,3-bit times,3.5-bit times,4-bit times,4.5-bit times,5-bit times,5.5-bit times" textline " " bitfld.long 0x00 8. " ENBLSLPM ,Enable utmi_sleep_n and utmi_l1_suspend_n" "Not transferred,Transfered" bitfld.long 0x00 6. " SUSPENDUSB20 ,Suspend USB2.0 HS/FS/LS PHY" "Not suspended,Suspended" textline " " bitfld.long 0x00 3. " PHYIF ,PHY interface" "8-bit interface,Interface" else group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFG,Global USB2 PHY configuration register" bitfld.long 0x00 31. " PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,USB 2.0 PHY free-running PHY clock exists" "No existed,Existed" textline " " textline " " bitfld.long 0x00 8. " ENBLSLPM ,Enable utmi_sleep_n and utmi_l1_suspend_n" "Not transferred,Transfered" bitfld.long 0x00 6. " SUSPENDUSB20 ,Suspend USB2.0 HS/FS/LS PHY" "Not suspended,Suspended" textline " " bitfld.long 0x00 3. " PHYIF ,PHY interface" "8-bit interface,Interface" endif group.long 0xC2C0++0x03 line.long 0x00 "GUSB3PIPECTL,Global USB 3.0 PIPE control register" bitfld.long 0x00 31. " PHYSOFTRST ,USB3 PHY soft reset" "No soft reset,Soft reset" bitfld.long 0x00 29. " U2SSINACTP3OK ,P3 OK for U2/SSImactive" "P2,P3" textline " " bitfld.long 0x00 28. " DISRXDETP3 ,Disabled receiver detection in P3" "Enabled,Disabled" bitfld.long 0x00 25. " U1U2EXITFAIL_TO_RECOV ,U1U2exitfail to recovery" "No recovery,Recovery" textline " " rbitfld.long 0x00 15.--16. " DATWIDTH ,PIPE data width" "32 bits,16 bits,8bits,?..." textline " " bitfld.long 0x00 6. " TX_SWING ,Tx swing" "0,1" bitfld.long 0x00 3.--5. " TX_MARGING ,Tx margin[2:0]" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1.--2. " TX_DE_EPPHASIS ,Tx deemphasis" "0,1,2,3" bitfld.long 0x00 0. " ELASTIC_BUFFER_MODE ,Elastic buffer mode" "0,1" group.long 0xC300++0x03 line.long 0x00 "GTXFIFOSIZ_0,Global transmit FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_N ,Transmit FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " TXFDEP_N ,TXFIFO depth" group.long 0xC310++0x03 line.long 0x00 "GTXFIFOSIZ_1,Global transmit FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_N ,Transmit FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " TXFDEP_N ,TXFIFO depth" group.long 0xC320++0x03 line.long 0x00 "GTXFIFOSIZ_2,Global transmit FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_N ,Transmit FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " TXFDEP_N ,TXFIFO depth" group.long 0xC330++0x03 line.long 0x00 "GTXFIFOSIZ_3,Global transmit FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_N ,Transmit FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " TXFDEP_N ,TXFIFO depth" group.long 0xC380++0x03 line.long 0x00 "GRXFIFOSIZ_0,Global receive FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " RXFSTADDR_N ,RXt FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " RXFDEP_N ,RXFIFO depth" group.long 0xC390++0x03 line.long 0x00 "GRXFIFOSIZ_1,Global receive FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " RXFSTADDR_N ,RXt FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " RXFDEP_N ,RXFIFO depth" group.long 0xC3A0++0x03 line.long 0x00 "GRXFIFOSIZ_2,Global receive FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " RXFSTADDR_N ,RXt FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " RXFDEP_N ,RXFIFO depth" group.long 0xC400++0x0F line.long 0x00 "GEVNTADRLO,Global event buffer address (low) register" line.long 0x04 "GEVNTADRHI,Global event buffer address (high) register" line.long 0x08 "GEVNTSIZ,Global event buffer size register" bitfld.long 0x08 31. " EVNTINTRPTMASK ,Event interrupt mask" "Not masked,Masked" hexmask.long.word 0x08 0.--15. 0x01 " EVENTSIZ ,Event buffer size in bytes" line.long 0x0C "GEVNTCOUNT,Global event buffer count register" hexmask.long.word 0x0C 0.--15. 1. " EVNTCOUNT ,Event count" group.long 0xC600++0x03 line.long 0x00 "GHWPARAMS8,Global hardware parameters register 8" group.long 0xC610++0x03 line.long 0x00 "GTXFIFOPRIDEV,Global device TXFIFO DMA priority register" bitfld.long 0x00 0.--3. " GTXFIFOPRIDEV ,Device TXFIFO priority" "Low,High,?..." group.long 0xC618++0x07 line.long 0x00 "GTXFIFOPRIHT,Global host TXFIFO DMA priority register" bitfld.long 0x00 0.--2. " GTXFIFOPRIHST ,Host TXFIFO priority" "Low,High,?..." line.long 0x04 "RXFIFOPRIHST,Global host RXFIFO DMA priority register" bitfld.long 0x04 0.--2. " GRXFIFOPRIHST ,Host RXFIFO priority" "Low,High,?..." group.long 0xC624++0x03 line.long 0x00 "GDMAHLRATIO,Global host FIFO DMA high-low priority ratio register" bitfld.long 0x00 8.--12. " HSTRXFIFO ,Host RXFIFO DMA high-low priority ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " HSTTXFIFO ,Host TXFIFO DMA high-low priority ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC630++0x03 line.long 0x00 "GFLADJ,Global frame length adjustment register" hexmask.long.word 0x00 8.--21. 1. " GFLADJ_REFCLK_FLADJ ,the frame length adjustment to be applied when SOF/ITP counter is running on theref_clk" bitfld.long 0x00 7. " GFLADJ_30MHZ_REG_SEL ,GFLADJ 30MHZ REG select" "32,value in GFLADJ[GFLADJ_30MHZ]" textline " " bitfld.long 0x00 0.--5. " GFLADJ_30MHZ ,GFLADJ 30MHZ REG select" "59488 HS bit times,59504 HS bit times,59520 HS bit times,59536 HS bit times,59552 HS bit times,59568 HS bit times,59584 HS bit times,59600 HS bit times,59616 HS bit times,59632 HS bit times,59648 HS bit times,59664 HS bit times,59680 HS bit times,59696 HS bit times,59712 HS bit times,59728 HS bit times,59744 HS bit times,59760 HS bit times,59776 HS bit times,59792 HS bit times,59808 HS bit times,59824 HS bit times,59840 HS bit times,59856 HS bit times,59872 HS bit times,59888 HS bit times,59904 HS bit times,59920 HS bit times,59936 HS bit times,59952 HS bit times,59968 HS bit times,59984 HS bit times,60000 HS bit times,60016 HS bit times,60032 HS bit times,60048 HS bit times,60064 HS bit times,60080 HS bit times,60096 HS bit times,60112 HS bit times,60128 HS bit times,60144 HS bit times,60160 HS bit times,60176 HS bit times,60192 HS bit times,60208 HS bit times,60224 HS bit times,60240 HS bit times,60256 HS bit times,60272 HS bit times,60288 HS bit times,60304 HS bit times,60320 HS bit times,60336 HS bit times,60352 HS bit times,60368 HS bit times,60384 HS bit times,60400 HS bit times,60416 HS bit times,60432 HS bit times,60448 HS bit times,60464 HS bit times,60480 HS bit times,60496" if (((per.l(ad:0x38100000+0xC118))&0x03)==0x01) group.long 0xC700++0x03 line.long 0x00 "DCFG,Device configuration register" bitfld.long 0x00 23. " IGMSTRMPP ,Ignore stream PP" "Not ignored,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capable" "Disabled,Enabled" textline " " bitfld.long 0x00 17.--21. " NUMP ,Number of receive buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 12.--16. " ITRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" textline " " bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High speed,Full speed,,,SuperSpeed,?..." else group.long 0xC700++0x03 line.long 0x00 "DCFG,Device configuration register" bitfld.long 0x00 23. " IGMSTRMPP ,Ignore stream PP" "Not ignored,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capable" "Disabled,Enabled" textline " " textline " " bitfld.long 0x00 12.--16. " ITRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" textline " " bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High speed,Full speed,,,SuperSpeed,?..." endif if (((per.l(ad:0x38100000+0xC700))&0x07)==0x04) group.long 0xC704++0x03 line.long 0x00 "DCTL,Device control register" bitfld.long 0x00 31. " RUN_STOP ,Run stop" "Stop,Run" bitfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" textline " " bitfld.long 0x00 24.--28. " HIRDTHRES ,HIRD threshold" "0,?..." bitfld.long 0x00 20.--23. " LPM_NYET_THRES ,LPM NYET response threshold handshake" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 17. " CRS ,Controller restore data" "No effect,Start restoring process" bitfld.long 0x00 16. " CRS ,Controller save data" "No effect,Start saving data" textline " " bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Not initiated,Initiated" bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Not initiated,Initiated" bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" "No action,,,,SS disbanded,Rx detect,SS Inactive,,Recovery,?..." bitfld.long 0x00 1.--4. " TSTCL ,Test control" "Test mode disabled,Test_J mode,Test_K mode,Test_SE0_NAK,Test Packet mode,Test force enable,SS Inactive,?..." else group.long 0xC704++0x03 line.long 0x00 "DCTL,Device control register" bitfld.long 0x00 31. " RUN_STOP ,Run stop" "Stop,Run" bitfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" textline " " bitfld.long 0x00 24.--28. " HIRDTHRES ,HIRD threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--23. " LPM_NYET_THRES ,LPM NYET response threshold handshake" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 17. " CRS ,Controller restore data" "No effect,Start restoring process" bitfld.long 0x00 16. " CRS ,Controller save data" "No effect,Start saving data" textline " " bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Not initiated,Initiated" bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Not initiated,Initiated" bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" "No action,,,,SS disbanded,Rx detect,SS Inactive,,Recovery,?..." bitfld.long 0x00 1.--4. " TSTCL ,Test control" "Test mode disabled,Test_J mode,Test_K mode,Test_SE0_NAK,Test Packet mode,Test force enable,SS Inactive,?..." endif group.long 0xC708++0x03 line.long 0x00 "DEVTEN,Device event enable register" bitfld.long 0x00 12. " VENDEVTSTRCVDEN ,Vendor device test LPM received rvent" "Not received,Received" bitfld.long 0x00 9. " ERRTICERREVTEN ,Erratic error event enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SOFTEVTEN ,Start of frame enable" "Disabled,Enabled" bitfld.long 0x00 6. " U3L2L1SUSPEN ,U3/L2-L1 suspend event enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " WKUPEVTEN ,Resume/Remote wakeup detected event enable" "Disabled,Enabled" bitfld.long 0x00 3. " ULSTCNGEN ,USB/Link state change event enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " CONNECTDONEEVTEN ,Connection done enable" "Disabled,Enabled" bitfld.long 0x00 1. " USBRSTEVTEN ,USB reset enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DISSCONNEVTEN ,Disconnect detected event enable" "Disabled,Enabled" if (((per.l(ad:0x38100000+0xC700))&0x07)==0x04) rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device status register" bitfld.long 0x00 25. " RSS ,Restore state status" "No during restore process,During restore process" bitfld.long 0x00 24. " SSS ,Save state status" "No during save process,During save process" textline " " bitfld.long 0x00 23. " COREIDLE ,Core idle" "No idle,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Run,Stopped" textline " " bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state" "U0,U1,U2,U3,SS_DIS,RX_DET,SS_INACT,POLL,RECOV,HRESET,CMPLY,LPBK,,,,Resume/reset" bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High speed (30 or 60 MHz),Full speed (30 or 60 MHz),Low speed (6 MHz),Full speed (48 MHz),SuperSpeed(125 or 250 MHz),?..." else rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device status register" bitfld.long 0x00 25. " RSS ,Restore state status" "No during restore process,During restore process" bitfld.long 0x00 24. " SSS ,Save state status" "No during save process,During save process" textline " " bitfld.long 0x00 23. " COREIDLE ,Core idle" "No idle,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Run,Stopped" textline " " bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state" "On state,,Sleep state,Suspended state,Disconnected state,?..." bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High speed (30 or 60 MHz),Full speed (30 or 60 MHz),Low speed (6 MHz),Full speed (48 MHz),SuperSpeed(125 or 250 MHz),?..." endif group.long 0xC710++0x03 line.long 0x00 "DGCMDPAR,Device generic command parameter register" if (((per.l(ad:0x38100000+0xC704))&0x80000000)==0x80000000) group.long 0xC714++0x03 line.long 0x00 "DGCMD,Device generic command register" rbitfld.long 0x00 12.--15. " CMDSTATUS ,Command status" "No error,Error,?..." bitfld.long 0x00 10. " CMDACT ,Command active" "Command executing disabled,Command executing enabled" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" hexmask.long.byte 0x00 0.--7. 1. " CMDTYP ,Command type" else group.long 0xC714++0x03 line.long 0x00 "DGCMD,Device generic command register" rbitfld.long 0x00 12.--15. " CMDSTATUS ,Command status" "No error,Error,?..." bitfld.long 0x00 10. " CMDACT ,Command active" "Command executing disabled,Command executing enabled" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,?..." hexmask.long.byte 0x00 0.--7. 1. " CMDTYP ,Command type" endif group.long 0xC720++0x03 line.long 0x00 "DALEPENA,Device active USB endpoint enable register" hexmask.long.byte 0x00 0.--7. 1. " USBACTEP ,USB active endpoints" group.long 0xC800++0x0B line.long 0x00 "DEPCMDPAR2_0,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_0,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_0,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38100000+0xC704))&0x80000000)==0x80000000) group.long (0xC800+0x0C)++0x03 line.long 0x00 "DEPCMD_0,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC800+0x0C)++0x03 line.long 0x00 "DEPCMD_0,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC810++0x0B line.long 0x00 "DEPCMDPAR2_1,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_1,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_1,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38100000+0xC704))&0x80000000)==0x80000000) group.long (0xC810+0x0C)++0x03 line.long 0x00 "DEPCMD_1,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC810+0x0C)++0x03 line.long 0x00 "DEPCMD_1,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC820++0x0B line.long 0x00 "DEPCMDPAR2_2,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_2,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_2,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38100000+0xC704))&0x80000000)==0x80000000) group.long (0xC820+0x0C)++0x03 line.long 0x00 "DEPCMD_2,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC820+0x0C)++0x03 line.long 0x00 "DEPCMD_2,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC830++0x0B line.long 0x00 "DEPCMDPAR2_3,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_3,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_3,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38100000+0xC704))&0x80000000)==0x80000000) group.long (0xC830+0x0C)++0x03 line.long 0x00 "DEPCMD_3,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC830+0x0C)++0x03 line.long 0x00 "DEPCMD_3,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC840++0x0B line.long 0x00 "DEPCMDPAR2_4,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_4,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_4,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38100000+0xC704))&0x80000000)==0x80000000) group.long (0xC840+0x0C)++0x03 line.long 0x00 "DEPCMD_4,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC840+0x0C)++0x03 line.long 0x00 "DEPCMD_4,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC850++0x0B line.long 0x00 "DEPCMDPAR2_5,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_5,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_5,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38100000+0xC704))&0x80000000)==0x80000000) group.long (0xC850+0x0C)++0x03 line.long 0x00 "DEPCMD_5,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC850+0x0C)++0x03 line.long 0x00 "DEPCMD_5,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC860++0x0B line.long 0x00 "DEPCMDPAR2_6,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_6,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_6,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38100000+0xC704))&0x80000000)==0x80000000) group.long (0xC860+0x0C)++0x03 line.long 0x00 "DEPCMD_6,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC860+0x0C)++0x03 line.long 0x00 "DEPCMD_6,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC870++0x0B line.long 0x00 "DEPCMDPAR2_7,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_7,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_7,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38100000+0xC704))&0x80000000)==0x80000000) group.long (0xC870+0x0C)++0x03 line.long 0x00 "DEPCMD_7,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC870+0x0C)++0x03 line.long 0x00 "DEPCMD_7,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xCC00++0x0F line.long 0x00 "OCFG,OTG configuration register" bitfld.long 0x00 5. " DISPRTPWRCUTOFF ,OTG disable port power cut off" "Disabled,Enabled" bitfld.long 0x00 3. " OTGSFTRSTMSK ,OTG soft reset mask" "Not masked,Masked" textline " " bitfld.long 0x00 1. " HNPCAP ,HNP capability" "Disabled,Enabled" bitfld.long 0x00 0. " SRPCAP ,SRP capability" "Disabled,Enabled" line.long 0x04 "OCTL,OTG control register" bitfld.long 0x04 6. " PERIMODE ,Peripheral mode" "Host,Peripheral" bitfld.long 0x04 5. " PRTPWRCTL ,Port power control" "Not initiated VBUS drive,Initiated VBUS drive" textline " " bitfld.long 0x04 4. " HNPREQ ,HNP request" "No HNP request,HNP request" bitfld.long 0x04 3. " SESREQ ,Session request" "No session request,Session request" textline " " bitfld.long 0x04 2. " TERMSELDLPULSE ,TermSel DLine pulsing selection" "Utmi_txvalid,Utmi_termsel" bitfld.long 0x04 1. " DEVSETHNPEN ,Device set HNP enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " HSTSETHNPEN ,Host set HNP enable" "Disabled,Enabled" line.long 0x08 "OEVT,OTG events register" rbitfld.long 0x08 31. " DEVICEMODE ,Device mode" "A-device,B-device" bitfld.long 0x08 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not occurred,Occurred" textline " " bitfld.long 0x08 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not occurred,Occurred" bitfld.long 0x08 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not occurred,Occurred" textline " " bitfld.long 0x08 21. " OTGADEVIDLEEVNT ,A-device A-IDLE event" "Not occurred," bitfld.long 0x08 20. " OTGADEVBHOSTENDEVNT ,A-device B-host event" "Not occurred," textline " " bitfld.long 0x08 19. " OTGADEVHOSTEVNT ,A-device host event" "Not occurred," bitfld.long 0x08 18. " OTGADEVHNPCHNGEVNT ,A-dev HNP change event" "Not occurred," textline " " bitfld.long 0x08 17. " OTGADEVSRPDETEVNT ,SRP detect event" "Not occurred," bitfld.long 0x08 16. " OTGADEVSESSENDDETEVNT ,Session end detected event" "Not occurred," textline " " bitfld.long 0x08 11. " OTGBDEVBHOSTENDEVNT ,B-device B-host event" "Not occurred,Occurred" bitfld.long 0x08 10. " OTGBDEVHNPCHNGEVNT ,B-dev HNP change event" "Not occurred,Occurred" textline " " bitfld.long 0x08 9. " OTGBDEVSESSVLDDETEVNT ,Session valid detected event" "Not occurred,Occurred" bitfld.long 0x08 8. " OTGBDEVVBUSCHNGEVNT ,VBUS change event" "Not occurred,Occurred" textline " " rbitfld.long 0x08 3. " BSESVLD ,B-Session valid" "Not valid,Valid" rbitfld.long 0x08 2. " HSTNEGSTS ,Host negotiation status" "Failure,Success" textline " " bitfld.long 0x08 0. " OEVTERROR ,Host negotiation status" "No error,Error" line.long 0x0C "OEVTEN,OTG events enable register" bitfld.long 0x0C 27. " OTGXHCIRUNSTPSETEVNTEN ,OTG host run stop set event enable" "Disabled,Enabled" bitfld.long 0x0C 26. " OTGDEVRUNSTPSETEVNTEN ,OTG device run stop set event enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 24. " OTGCONIDSTSCHNGEVNTEN ,Connector ID status change event enable" "Disabled,Enabled" bitfld.long 0x0C 23. " HRRCONFNOTIFEVNTEN ,HRRCONFNOTIF event enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 22. " HRRINITNOTIFEVNTEN ,HRRINITNOTIF event enable" "Disabled,Enabled" bitfld.long 0x0C 21. " OTGADEVIDLEEVNTEN ,A-device A-IDLE event" "Disabled,Enabled" textline " " bitfld.long 0x0C 20. " OTGADEVBHOSTENDEVNTEN ,A-device B-host end event enable" "Disabled,Enabled" bitfld.long 0x0C 19. " OTGADEVHOSTEVNTEN ,A-device host event" "Disabled,Enabled" textline " " bitfld.long 0x0C 18. " OTGADEVHNPCHNGEVNTEN ,A-Device HNP change event enable" "Disabled,Enabled" bitfld.long 0x0C 17. " OTGADEVSRPDETEVNTEN ,SRP detect event enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 16. " OTGADEVSESSENDDETEVNTEN ,Session end detected event enable" "Disabled,Enabled" bitfld.long 0x0C 11. " OTGBDEVBHOSTENDEVNTEN ,B-device B-host end event enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 10. " OTGBDEVHNPCHNGEVNTEN ,B-device HNP change event enable" "Disabled,Enabled" bitfld.long 0x0C 9. " OTGBDEVSESSVLDDETEVNTEN ,Session valid detected event enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 8. " OTGBDEVVBUSCHNGEVNTEN ,VBUS change event enable" "Disabled,Enabled" rgroup.long 0xCC10++0x03 line.long 0x00 "OSTS,OTG status register" bitfld.long 0x00 13. " DEVRUNSTP ,Deice run/stop status" "Stop,Run" bitfld.long 0x00 12. " XHCIRUNSTP ,OTG host run stop set event" "Stop,Run" textline " " bitfld.long 0x00 4. " PERIPHERALSTATE ,Core as peripheral or host" "Host,Peripheral" bitfld.long 0x00 2. " BSESVLD ,B-session valid" "Not valid,Valid" textline " " bitfld.long 0x00 1. " ASESVLD ,A-session valid" "Not valid,Valid" bitfld.long 0x00 0. " CONIDSTS ,Connector ID status" "A-device,B-device" group.long 0xCC20++0x0F line.long 0x00 "ADPCFG,ADP configuration register" bitfld.long 0x00 30.--31. " PRBPER ,Probe period" "775 ms,1550 ms,2275 ms,?..." bitfld.long 0x00 28.--29. " PRBDELTA ,Probe delta" "1 cycle,2 cycle,3 cycle,4 cycle" textline " " bitfld.long 0x00 26.--27. " PRBDSCHG ,Probe discharge" "4 ms,8 ms,16 ms,32 ms" line.long 0x04 "ADPCTL,ADP control register" bitfld.long 0x04 28. " ENAPRB ,Enable probe" "Disabled,Enabled" bitfld.long 0x04 27. " ENASNS ,Enable sense" "Disabled,Enabled" textline " " bitfld.long 0x04 26. " ADPEN ,ADP enable" "Suspend clock is gated,Sense/Probe operation is performed" bitfld.long 0x04 25. " ADPRES ,ADP reset" "No reset,Reset" textline " " rbitfld.long 0x04 24. " WB ,Write busy" "Completed,In progress" line.long 0x08 "ADPEVT,ADP event register" bitfld.long 0x08 28. " ADPPRBEVNT ,ADP probe event" "Not occurred,Occurred" bitfld.long 0x08 27. " ADPPRBEVNT ,ADP sense event" "Not occurred,Occurred" textline " " bitfld.long 0x08 26. " ADPTMOUTEVNT ,ADP timeout event" "Not occurred,Occurred" bitfld.long 0x08 25. " ADPRSTCMPLTEVNT ,ADP reset complete event" "Not occurred,Occurred" textline " " hexmask.long.word 0x08 0.--15. 1. " RTIM ,Ramp time" line.long 0x0C "ADPEVTEN,ADP event enable register" bitfld.long 0x0C 28. " ADPPRBEVNTEN ,ADP probe event enable" "Disabled,Enabled" bitfld.long 0x0C 27. " ADPPRBEVNTEN ,ADP sense event enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 26. " ADPTMOUTEVNTEN ,ADP timeout event enable" "Disabled,Enabled" bitfld.long 0x0C 25. " ADPRSTCMPLTEVNTEN ,ADP reset complete event enable" "Disabled,Enabled" width 0x0B tree.end tree "USB2" base ad:0x38200000 width 16. rgroup.long 0x00++0x1F line.long 0x00 "CAPLENGTH,Capability register length and HC interface version number" hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,HC interface version number" hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability register length" line.long 0x04 "HCSPARAMS1,Host controller structural parameters 1" hexmask.long.byte 0x04 24.--31. 1. " MAXPORTS ,Maximum number of ports set as 2" hexmask.long.word 0x04 8.--18. 1. " MAXINTRS ,Number of interrupters set as 1" textline " " hexmask.long.byte 0x04 0.--7. 1. " MAXSLOTS ,Number of device slots set as 127" line.long 0x08 "HCSPARAMS2,Host controller structural parameters 2" bitfld.long 0x08 27.--31. " MAXSCRATCHPADBUFS ,Max scratchpad buffers low set as 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 26. " SPR ,Scratchpad restore" "Not restored,Restored" textline " " bitfld.long 0x08 21.--25. " MAXSCRATCHPADBUFS ,Max scratchpad buffers high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. " ERSTMAX ,Event ring segment table max set as 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 0.--3. " IST ,Isochronous scheduling threshold set as 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "HCSPARAMS3,Host controller structural parameters 3" hexmask.long.word 0x0C 16.--31. 1. " U2_DEVIC_EXIT_LAT ,U2 device exit latency" hexmask.long.byte 0x0C 0.--7. 1. " U1_DEVIC_EXIT_LAT ,U1 device exit latency" line.long 0x10 "HCCPARAMS1, Host controller capability parameters 1" hexmask.long.word 0x10 16.--31. 0x01 " xECP ,xHCI extended capabilities pointer" bitfld.long 0x10 12.--15. " MAXPSASIZE ,Maximum primary stream array size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 11. " CFC ,Contiguous frame ID capability" "No capability,Capability" bitfld.long 0x10 10. " SEC ,Stopped EDLTA capability" "No capability,Capability" textline " " bitfld.long 0x10 9. " SPC ,Short packet capability" "No capability,Capability" bitfld.long 0x10 8. " PAE ,Parse all event data" "Not parsed,Parsed" textline " " bitfld.long 0x10 7. " NSS ,No secondary SID support" "Supported,Not supported" bitfld.long 0x10 6. " LTC ,Latency tolerance messaging capability" "No capability,Capability" textline " " bitfld.long 0x10 5. " LHRC ,Light HC reset capability" "No capability,Capability" bitfld.long 0x10 4. " PIND ,Port indicators" "0,1" textline " " bitfld.long 0x10 3. " PPC ,Port power control" "0,1" bitfld.long 0x10 2. " CSZ ,Context size" "0,1" textline " " bitfld.long 0x10 1. " BNC ,BW negotiation capability" "No capability,Capability" bitfld.long 0x10 0. " AC64 ,64_bit addressing capability" "No capability,Capability" line.long 0x14 "DBOFF,Doorbell offset" hexmask.long 0x14 2.--31. 0x04 " DOORBELL_ARRAY_OFFSET ,Doorbell array offset" line.long 0x18 "RTSOFF,Runtime register space offset" hexmask.long 0x18 5.--31. 0x20 " RUNTIME_REG_SPAC_OFFSET ,Runtime register space offset" line.long 0x1C "HCCPARAMS1,HOST controller capability parameters 2" bitfld.long 0x1C 5. " CIC ,Configuration information capability" "No capability,Capability" bitfld.long 0x1C 4. " LEC ,Large ESIT payload capability" "No capability,Capability" textline " " bitfld.long 0x1C 3. " CTC ,Compliance transition capability" "No capability,Capability" bitfld.long 0x1C 2. " FSC ,Force save context capability" "No capability,Capability" textline " " bitfld.long 0x1C 1. " CMC ,Configure endpoint command max exit latency too large capability" "No capability,Capability" bitfld.long 0x1C 0. " U3C ,U3 entry capability" "No capability,Capability" group.long 0xC100++0x07 line.long 0x00 "GSBUSCFG0,Global SoC bus configuration register 0" bitfld.long 0x00 28.--31. " DATRDREQINFO ,AXI-cache for data read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " DESRDREQINFO ,AXI-cache for description read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--23. " DATWRREQINFO ,AXI-cache for data write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " DESWRREQINFO ,AXI-cache for description write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " INCR256BRSTENA ,INCR256 burst enable" "Disabled,Enabled" bitfld.long 0x00 6. " INCR128BRSTENA ,INCR128 burst enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " INCR64BRSTENA ,INCR64 burst enable" "Disabled,Enabled" bitfld.long 0x00 4. " INCR32BRSTENA ,INCR32 burst enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INCR16BRSTENA ,INCR16 burst enable" "Disabled,Enabled" bitfld.long 0x00 2. " INCR8BRSTENA ,INCR8 burst enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " INCR4BRSTENA ,INCR4 burst enable" "Disabled,Enabled" bitfld.long 0x00 0. " INCRBRSTENA ,Undefined length INCR burst type enable" "Disabled,Enabled" line.long 0x04 "GSBUSCFG1,Global SoC bus configuration register 1" bitfld.long 0x04 12. " EN1KPAGE ,1K page boundary enable" "Disabled,Enabled" bitfld.long 0x04 8.--11. " PIPETRANSLIM ,AXI pipelined transfer request limit" "1 request,2 requests,3 requests,4 requests,5 requests,6 requests,7 requests,8 requests,9 requests,10 requests,11 requests,12 requests,13 requests,14 requests,15 requests,16 requests" if (((per.l(ad:0x38200000+0xC108))&0x20000000)==0x20000000) group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx threshold control register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBTXPKTCNT ,USB transmit packet count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 16.--23. 1. " USBMAXTXBUTSTSIZE ,USB maximum Tx burst size" else group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx threshold control register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 16.--23. 1. " USBMAXTXBUTSTSIZE ,USB maximum Tx burst size" endif if (((per.l(ad:0x38200000+0xC10C))&0x20000000)==0x20000000) group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx threshold control register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBRXPKTCNT ,USB receive packet count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 19.--23. " USBMAXRXBURSTSIZE ,USB maximum receive burst size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx threshold control register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" endif if (((per.l(ad:0x38200000+0xC118))&0x03)==0x00) if (((per.l(ad:0x38200000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global core control register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Enabled,Bypassed" textline " " bitfld.long 0x00 17. " BYPSSETADDR ,Bypass Set address in device mode" "No effect," bitfld.long 0x00 16. " U2RSTECN ,Connecting SS mode 3 more times if failed" "No,Yes" textline " " bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scaling down device view of a SoF/USOF/ITP duration" "1024 bytes,512 bytes,256 bytes,128 bytes" bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host mode,Device mode,Device OTG 2.0 device" textline " " bitfld.long 0x00 11. " CORESOFTRESET ,Core soft reset" "No reset,Reset" rbitfld.long 0x00 10. " SOFITSYNC ,Sofitsync" "0,1" textline " " bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus,Pipe,Pipe/2," bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" textline " " bitfld.long 0x00 2. " U2EXIT_LFPS ,Causing the device to exit from U2 state because the LFPS filter value is 248 ns" "0,1" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global core control register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Enabled,Bypassed" textline " " bitfld.long 0x00 17. " BYPSSETADDR ,Bypass Set address in device mode" "No effect," bitfld.long 0x00 16. " U2RSTECN ,Connecting SS mode 3 more times if failed" "No,Yes" textline " " bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scaling down device view of a SoF/USOF/ITP duration" "125 us,62.5 us,31.25 us,15.625 us" bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host mode,Device mode,Device OTG 2.0 device" textline " " bitfld.long 0x00 11. " CORESOFTRESET ,Core soft reset" "No reset,Reset" rbitfld.long 0x00 10. " SOFITSYNC ,Sofitsync" "0,1" textline " " bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus,Pipe,Pipe/2," bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" textline " " bitfld.long 0x00 2. " U2EXIT_LFPS ,Causing the device to exit from U2 state because the LFPS filter value is 248 ns" "0,1" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif else if (((per.l(ad:0x38200000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global core control register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Enabled,Bypassed" textline " " bitfld.long 0x00 17. " BYPSSETADDR ,Bypass Set address in device mode" "No effect," textline " " bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scaling down device view of a SoF/USOF/ITP duration" "1024 bytes,512 bytes,256 bytes,128 bytes" bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host mode,Device mode,Device OTG 2.0 device" textline " " bitfld.long 0x00 11. " CORESOFTRESET ,Core soft reset" "No reset,Reset" rbitfld.long 0x00 10. " SOFITSYNC ,Sofitsync" "0,1" textline " " bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus,Pipe,Pipe/2," bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" textline " " bitfld.long 0x00 2. " U2EXIT_LFPS ,Causing the device to exit from U2 state because the LFPS filter value is 248 ns" "0,1" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global core control register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Enabled,Bypassed" textline " " bitfld.long 0x00 17. " BYPSSETADDR ,Bypass Set address in device mode" "No effect," textline " " bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scaling down device view of a SoF/USOF/ITP duration" "125 us,62.5 us,31.25 us,15.625 us" bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host mode,Device mode,Device OTG 2.0 device" textline " " bitfld.long 0x00 11. " CORESOFTRESET ,Core soft reset" "No reset,Reset" rbitfld.long 0x00 10. " SOFITSYNC ,Sofitsync" "0,1" textline " " bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus,Pipe,Pipe/2," bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" textline " " bitfld.long 0x00 2. " U2EXIT_LFPS ,Causing the device to exit from U2 state because the LFPS filter value is 248 ns" "0,1" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif endif group.long 0xC118++0x03 line.long 0x00 "GSTS,Global status register" rbitfld.long 0x00 10. " OTG_IP ,OTG Interrupt pending" "No pending,Pending" rbitfld.long 0x00 7. " HOST_IP ,HOST Interrupt pending" "No pending,Pending" textline " " rbitfld.long 0x00 6. " DEVICE_IP ,DEVICE Interrupt pending" "No pending,Pending" bitfld.long 0x00 5. " CSRTIMEOUT ,CSR timeout" "0,1" textline " " bitfld.long 0x00 4. " BUSERRADDR ,Bus error address valid" "No valid,Valid" rbitfld.long 0x00 0.--1. " CURMOD ,Current mode of operation" "Device mode,Host mode,?..." if (((per.l(ad:0x38200000+0xC110))&0x400)==0x01) if (((per.l(ad:0x38200000+0xC118))&0x03)==0x01) if (((per.l(ad:0x38200000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 28. " TZ_IPAP_LINECHECK_DIS ,TZ IPGAP LINECKECK disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" textline " " bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" elif (((per.l(ad:0x38200000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,FILTER SE0 FS/LS EOP" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" textline " " bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" else group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" endif elif (((per.l(ad:0x38200000+0xC118))&0x03)==0x00) if (((per.l(ad:0x38200000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 28. " TZ_IPAP_LINECHECK_DIS ,TZ IPGAP LINECKECK disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,DEV_FORCE_20_CLK_FOR_30_CLK" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" elif (((per.l(ad:0x38200000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,FILTER SE0 FS/LS EOP" "Disabled,Enabled" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,DEV_FORCE_20_CLK_FOR_30_CLK" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" elif (((per.l(ad:0x38200000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" else group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,DEV_FORCE_20_CLK_FOR_30_CLK" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " P3_IN_U2 ,P3 in U2" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" textline " " bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" endif endif else if (((per.l(ad:0x38200000+0xC118))&0x03)==0x01) if (((per.l(ad:0x38200000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 28. " TZ_IPAP_LINECHECK_DIS ,TZ IPGAP LINECKECK disable" "No,Yes" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" elif (((per.l(ad:0x38200000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,FILTER SE0 FS/LS EOP" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" else group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" endif elif (((per.l(ad:0x38200000+0xC118))&0x03)==0x00) if (((per.l(ad:0x38200000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 28. " TZ_IPAP_LINECHECK_DIS ,TZ IPGAP LINECKECK disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,DEV_FORCE_20_CLK_FOR_30_CLK" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" textline " " bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" elif (((per.l(ad:0x38200000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,FILTER SE0 FS/LS EOP" "Disabled,Enabled" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,DEV_FORCE_20_CLK_FOR_30_CLK" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" textline " " bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" elif (((per.l(ad:0x38200000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" textline " " bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" textline " " bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" textline " " bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" else group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global user control register 1" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,DEV_TRB_OUT_SPR_IND" "Disabled,Enabled" bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,DEV_FORCE_20_CLK_FOR_30_CLK" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,DEV_L1_EXIT_BY_HW" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_AGP_ADD_ON ,IP GAP add on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK ,DEV LSP TAIL lock disable" "No,Yes" bitfld.long 0x00 19. " NAK_PRE_ENH_FS ,NAK performance enhancement for FS" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " NAK_PRE_ENH_HS ,NAK performance enhancement for HS" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Parkmode disable HS" "No,Yes" textline " " bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals to the PHY in the L1 state" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 SUSP THRLD for host" ",,,,,L1 suspend,L2 suspend,,,,,L1 sleep,,,,Normal working" textline " " bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,HOST parameter check disable" "No,Yes" textline " " bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overload L1 suspend COM" "Not overloaded,Overloaded" bitfld.long 0x00 0. " LOA_FILTER_EN ,LOA filter enable" "Disabled,Enabled" endif endif endif group.long 0xC128++0x03 line.long 0x00 "GUID,Global user ID register" if (((per.l(ad:0x38200000+0xC118))&0x03)==0x01) group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global user control register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Terms of nano seconds the period of ref_clk" bitfld.long 0x00 21. " NOEXTRDI ,No extra delay between SOF and the first pocket" "Waiting,No waiting" textline " " bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,SPRASE control transaction enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RESBWHSEPS ,Reserving 85% bandwidth for HS periodic EPs" "0,1" bitfld.long 0x00 15. " CMDEVADDR ,Compliance mode for device address" "Equal to Slot AD,Increment device address" textline " " bitfld.long 0x00 14. " USBHSSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote UX exit" "Not looking for LFPS overlap,Looking for LFPS overlap" textline " " bitfld.long 0x00 12. " EXTCAPSUPTEM ,External extended capability support enable" "Disabled,Enabled" bitfld.long 0x00 11. " INSERTEXTRFSBODI ,Insert extra delay between FS bulk OUT transaction" "Not inserted,Inserted" textline " " bitfld.long 0x00 9.--10. " DTCT ,Deice timeout coarse tuning" "STDT value used,500 us,1.5 us,6.5 us" hexmask.long.word 0x00 0.--8. 1. " DTFT ,Device timeout fine tuning" else group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global user control register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Terms of nano seconds the period of ref_clk" bitfld.long 0x00 21. " NOEXTRDI ,No extra delay between SOF and the first pocket" "Waiting,No waiting" textline " " bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,SPRASE control transaction enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " USBHSSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote UX exit" "Not looking for LFPS overlap,Looking for LFPS overlap" textline " " bitfld.long 0x00 12. " EXTCAPSUPTEM ,External extended capability support enable" "Disabled,Enabled" bitfld.long 0x00 11. " INSERTEXTRFSBODI ,Insert extra delay between FS bulk OUT transaction" "Not inserted,Inserted" textline " " bitfld.long 0x00 9.--10. " DTCT ,Deice timeout coarse tuning" "STDT value used,500 us,1.5 us,6.5 us" hexmask.long.word 0x00 0.--8. 1. " DTFT ,Device timeout fine tuning" endif rgroup.long 0xC130++0x07 line.long 0x00 "GBUSERRADDRLO,Global SoC bus error address register low" line.long 0x04 "GBUSERRADDRHI,Global SoC bus error address register high" group.long 0xC138++0x07 line.long 0x00 "GPRTBIMAPLO,Global SS port to bus instance mapping register - low" bitfld.long 0x00 0.--3. " BINUM1 ,SS USB instance number for port." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAPHI,Global SS port to bus instance mapping register - high" bitfld.long 0x04 0.--3. " BINUM9 ,SS USB instance number for port 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xC140++0x1F line.long 0x00 "GHWPARAMS0,Global hardware parameters register 0" hexmask.long.byte 0x00 24.--31. 1. " DWC_USB3_AWIDTH ,Master/Slave address bus width" hexmask.long.byte 0x00 16.--23. 1. " DWC_USB3_SDWIDTH ,Slave bus data bus width" textline " " hexmask.long.byte 0x00 8.--15. 1. " DWC_USB3_MDWIDTH ,Master bus data bus width" bitfld.long 0x00 6.--7. " DWC_USB3_SBUS_TYPE ,Slave bus interface type" "AHB,,," textline " " bitfld.long 0x00 3.--5. " DWC_USB3_MBUS_TYPE ,Master bus interface type" ",AXI,?..." bitfld.long 0x00 0.--2. " DWC_USB3_MODE ,Mode of operation" ",,DRD,?..." line.long 0x04 "GHWPARAMS1,Global hardware parameters register 1" bitfld.long 0x04 31. " DWC_USB3_EN_DBC ,Enables xHCI debug capability" "No,Yes" bitfld.long 0x04 30. " DWC_USB3_RM_OPT_FEATURES ,Removing optional features" "No,Yes" textline " " bitfld.long 0x04 28. " DWC_USB3_RAM_BUS_CLKS_SYNC ,RAM clock and the Bus clock are synchronous to each other" "No,Yes" bitfld.long 0x04 27. " DWC_USB3_MAC_BUS_CLKS_SYNC ,MAC clock and the Bus clock are synchronous to each other" "No,Yes" textline " " bitfld.long 0x04 26. " DWC_USB3_MAC_PHY_CLKS_SYNC ,MAC clock and the PHY clock are synchronous to each other" "No,Yes" bitfld.long 0x04 24.--25. " DWC_USB3_EN_PWROPT ,Power optimization mode" "No power optimization,Clock gating only,," textline " " bitfld.long 0x04 23. " DWC_USB3_SPRAM_TYP ,Synchronous static RAM type" "2-port RAM,Single-port RAM" bitfld.long 0x04 21.--22. " DWC_USB3_NUM_RAMS ,NUMBER of RAMS" "1,2,3," textline " " bitfld.long 0x04 15.--20. " DWC_USB3_DEVICE_NUM_INT ,Number of device mode event buffers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 12.--14. " DWC_USB3_ASPACEWIDTH ,the address space port width of the master and slave bus interfaces" "1,2,3,4,5,6,," textline " " bitfld.long 0x04 9.--11. " DWC_USB3_REQINFOWIDTH ,request/response info port width of the master and slave bus interfaces" ",,,4,5,6,," bitfld.long 0x04 6.--8. " DWC_USB3_DATAINFOWIDTH ,Data info port width of the master and slave bus interfaces" "1,2,3,4,5,6,," textline " " bitfld.long 0x04 3.--5. " DWC_USB3_BURSTINFOWIDTH ,Burst port width of the master and slave bus interfaces" "1,2,3,4,5,6,7,8" bitfld.long 0x04 0.--2. " DWC_USB3_IDWIDTH1 ,Master ID port width" ",,,4,5,6,7,8" line.long 0x08 "GHWPARAMS2,Global hardware parameters register 2" line.long 0x0C "GHWPARAMS3,Global hardware parameters register 3" hexmask.long.word 0x0C 23.--31. 1. " DWC_USB3_CACHE_TOTAL_XFER_RESOURCES ,Maximum number of transfer resources in the core" bitfld.long 0x0C 18.--22. " DWC_USB3_NUM_IN_EPS ,Number of device mode active IN endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0C 12.--17. " DWC_USB3_NUM_EPS ,Number of device mode endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 10. " DWC_USB3_VENDOR_CTL_INTERAFACE ,Enabling the UTMI+ PHY vendor control interface" "Disabled,Enabled" textline " " bitfld.long 0x0C 6.--7. " DWC_USB3_HSPHY_DWIDTH ,Enabling the UTMI+ PHY vendor control interface" ",,8/16 bits," bitfld.long 0x0C 2.--3. " DWC_USB3_HSPHY_INTERFACE ,high-speed PHY interface" "0,1,2,3" textline " " bitfld.long 0x0C 0.--1. " DWC_USB3_SSPHY_INTERFACE ,high-speed PHY interface" "0,1,2,3" line.long 0x10 "GHWPARAMS4,Global hardware parameters register 4" bitfld.long 0x10 28.--31. " DWC_USB3_BMU_LSP_DEPTH ,depth of the BMU-LSP status buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. " DWC_USB3_BMU_PTL_DEPTH ,depth of the BMU-LSP source/sink buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 23. " DWC_USB3_EN_ISOC_SUPT ,Enabling isochronous endpoint capability" "Disabled,Enabled" textline " " bitfld.long 0x10 17.--20. " DWC_USB3_NUM_SS_USB_INSTANCES ,Number of SuperSpeed USB bus instances" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 0.--5. " DWC_USB3_CACHE_TRBS_PER_TRANSFER ,Number of cached TRBs per transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "GHWPARAMS5,Global hardware parameters register 5" bitfld.long 0x14 22.--27. " DWC_USB3_DFQ_FIFO_DEPT_H ,Size of the BMU descriptor fetch request queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 16.--21. " DWC_USB3_DWQ_FIFO_DEPT_H ,Size of the BMU descriptor write queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x14 10.--15. " DWC_USB3_TXQ_FIFO_DEPT_H ,Size of the BMU TX request queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 4.--9. " DWC_USB3_RXQ_FIFO_DEPT_H ,Size of the BMU RX request queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x14 0.--3. " DWC_USB3_BMU_BUSGM_DEPTH ,Depth of the BMU-BUSGM source/sink buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "GHWPARAMS6,Global hardware parameters register 6" hexmask.long.word 0x18 16.--31. 1. " DWC_USB3_RAM0_DEPTH ,Depth of RAM0" bitfld.long 0x18 15. " BUSFLTRSSUPPORT ,Adding a filter for VBUS and ID related control inputs from the PHY" "No,Yes" textline " " bitfld.long 0x18 12. " ADPSUPPORT ,Internal ADP capability of the USB 3.0 core enabled" "Disabled,Enabled" bitfld.long 0x18 11. " HNPSUPPORT ,HNP support enabled" "Disabled,Enabled" textline " " bitfld.long 0x18 10. " SRPSUPPORT ,SRP support enabled" "Disabled,Enabled" bitfld.long 0x18 7. " DWC_USB3_EN_FPGA ,Hardware validation/driver development with an FPGA platform" "No,Yes" textline " " bitfld.long 0x18 6. " DWC_USB3_EN_DBG_PORTS ,FPGA hardware validation of the core" "No,Yes" bitfld.long 0x18 0.--5. " DWC_USB3_PSQ_FIFIO_DEPTH ,size of the BMU protocol status queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "GHWPARAMS7,Global hardware parameters register 7" hexmask.long.word 0x1C 16.--31. 1. " DWC_USB3_RAM2_DEPTH ,Total RAM2 depth" hexmask.long.word 0x1C 0.--15. 1. " DWC_USB3_RAM1_DEPTH ,Total RAM1 depth" group.long 0xC180++0x07 line.long 0x00 "GPRTBIMAP_HSLO,Global high-speed port to bus instance mapping register - low" bitfld.long 0x00 0.--3. " BINUM1 ,HS USB instance number for port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAP_HSHI,Global high-speed port to bus instance mapping register - high" bitfld.long 0x04 0.--3. " BINUM9 ,HS USB instance number for port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x38200000+0xC118))&0x03)==0x00) group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFG,Global USB2 PHY configuration register" bitfld.long 0x00 31. " PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,USB 2.0 PHY free-running PHY clock exists" "No existed,Existed" textline " " bitfld.long 0x00 22.--24. " LSTRD ,LS turnaround time" "2-bit times,2.5-bit times,3-bit times,3.5-bit times,4-bit times,4.5-bit times,5-bit times,5.5-bit times" bitfld.long 0x00 19.--21. " LSPID ,LS inter-packet time" "2-bit times,2.5-bit times,3-bit times,3.5-bit times,4-bit times,4.5-bit times,5-bit times,5.5-bit times" textline " " bitfld.long 0x00 8. " ENBLSLPM ,Enable utmi_sleep_n and utmi_l1_suspend_n" "Not transferred,Transfered" bitfld.long 0x00 6. " SUSPENDUSB20 ,Suspend USB2.0 HS/FS/LS PHY" "Not suspended,Suspended" textline " " bitfld.long 0x00 3. " PHYIF ,PHY interface" "8-bit interface,Interface" else group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFG,Global USB2 PHY configuration register" bitfld.long 0x00 31. " PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,USB 2.0 PHY free-running PHY clock exists" "No existed,Existed" textline " " textline " " bitfld.long 0x00 8. " ENBLSLPM ,Enable utmi_sleep_n and utmi_l1_suspend_n" "Not transferred,Transfered" bitfld.long 0x00 6. " SUSPENDUSB20 ,Suspend USB2.0 HS/FS/LS PHY" "Not suspended,Suspended" textline " " bitfld.long 0x00 3. " PHYIF ,PHY interface" "8-bit interface,Interface" endif group.long 0xC2C0++0x03 line.long 0x00 "GUSB3PIPECTL,Global USB 3.0 PIPE control register" bitfld.long 0x00 31. " PHYSOFTRST ,USB3 PHY soft reset" "No soft reset,Soft reset" bitfld.long 0x00 29. " U2SSINACTP3OK ,P3 OK for U2/SSImactive" "P2,P3" textline " " bitfld.long 0x00 28. " DISRXDETP3 ,Disabled receiver detection in P3" "Enabled,Disabled" bitfld.long 0x00 25. " U1U2EXITFAIL_TO_RECOV ,U1U2exitfail to recovery" "No recovery,Recovery" textline " " rbitfld.long 0x00 15.--16. " DATWIDTH ,PIPE data width" "32 bits,16 bits,8bits,?..." textline " " bitfld.long 0x00 6. " TX_SWING ,Tx swing" "0,1" bitfld.long 0x00 3.--5. " TX_MARGING ,Tx margin[2:0]" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1.--2. " TX_DE_EPPHASIS ,Tx deemphasis" "0,1,2,3" bitfld.long 0x00 0. " ELASTIC_BUFFER_MODE ,Elastic buffer mode" "0,1" group.long 0xC300++0x03 line.long 0x00 "GTXFIFOSIZ_0,Global transmit FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_N ,Transmit FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " TXFDEP_N ,TXFIFO depth" group.long 0xC310++0x03 line.long 0x00 "GTXFIFOSIZ_1,Global transmit FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_N ,Transmit FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " TXFDEP_N ,TXFIFO depth" group.long 0xC320++0x03 line.long 0x00 "GTXFIFOSIZ_2,Global transmit FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_N ,Transmit FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " TXFDEP_N ,TXFIFO depth" group.long 0xC330++0x03 line.long 0x00 "GTXFIFOSIZ_3,Global transmit FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_N ,Transmit FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " TXFDEP_N ,TXFIFO depth" group.long 0xC380++0x03 line.long 0x00 "GRXFIFOSIZ_0,Global receive FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " RXFSTADDR_N ,RXt FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " RXFDEP_N ,RXFIFO depth" group.long 0xC390++0x03 line.long 0x00 "GRXFIFOSIZ_1,Global receive FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " RXFSTADDR_N ,RXt FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " RXFDEP_N ,RXFIFO depth" group.long 0xC3A0++0x03 line.long 0x00 "GRXFIFOSIZ_2,Global receive FIFO size register" hexmask.long.word 0x00 16.--31. 0x01 " RXFSTADDR_N ,RXt FIFOn RAM start address" hexmask.long.word 0x00 0.--15. 1. " RXFDEP_N ,RXFIFO depth" group.long 0xC400++0x0F line.long 0x00 "GEVNTADRLO,Global event buffer address (low) register" line.long 0x04 "GEVNTADRHI,Global event buffer address (high) register" line.long 0x08 "GEVNTSIZ,Global event buffer size register" bitfld.long 0x08 31. " EVNTINTRPTMASK ,Event interrupt mask" "Not masked,Masked" hexmask.long.word 0x08 0.--15. 0x01 " EVENTSIZ ,Event buffer size in bytes" line.long 0x0C "GEVNTCOUNT,Global event buffer count register" hexmask.long.word 0x0C 0.--15. 1. " EVNTCOUNT ,Event count" group.long 0xC600++0x03 line.long 0x00 "GHWPARAMS8,Global hardware parameters register 8" group.long 0xC610++0x03 line.long 0x00 "GTXFIFOPRIDEV,Global device TXFIFO DMA priority register" bitfld.long 0x00 0.--3. " GTXFIFOPRIDEV ,Device TXFIFO priority" "Low,High,?..." group.long 0xC618++0x07 line.long 0x00 "GTXFIFOPRIHT,Global host TXFIFO DMA priority register" bitfld.long 0x00 0.--2. " GTXFIFOPRIHST ,Host TXFIFO priority" "Low,High,?..." line.long 0x04 "RXFIFOPRIHST,Global host RXFIFO DMA priority register" bitfld.long 0x04 0.--2. " GRXFIFOPRIHST ,Host RXFIFO priority" "Low,High,?..." group.long 0xC624++0x03 line.long 0x00 "GDMAHLRATIO,Global host FIFO DMA high-low priority ratio register" bitfld.long 0x00 8.--12. " HSTRXFIFO ,Host RXFIFO DMA high-low priority ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " HSTTXFIFO ,Host TXFIFO DMA high-low priority ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC630++0x03 line.long 0x00 "GFLADJ,Global frame length adjustment register" hexmask.long.word 0x00 8.--21. 1. " GFLADJ_REFCLK_FLADJ ,the frame length adjustment to be applied when SOF/ITP counter is running on theref_clk" bitfld.long 0x00 7. " GFLADJ_30MHZ_REG_SEL ,GFLADJ 30MHZ REG select" "32,value in GFLADJ[GFLADJ_30MHZ]" textline " " bitfld.long 0x00 0.--5. " GFLADJ_30MHZ ,GFLADJ 30MHZ REG select" "59488 HS bit times,59504 HS bit times,59520 HS bit times,59536 HS bit times,59552 HS bit times,59568 HS bit times,59584 HS bit times,59600 HS bit times,59616 HS bit times,59632 HS bit times,59648 HS bit times,59664 HS bit times,59680 HS bit times,59696 HS bit times,59712 HS bit times,59728 HS bit times,59744 HS bit times,59760 HS bit times,59776 HS bit times,59792 HS bit times,59808 HS bit times,59824 HS bit times,59840 HS bit times,59856 HS bit times,59872 HS bit times,59888 HS bit times,59904 HS bit times,59920 HS bit times,59936 HS bit times,59952 HS bit times,59968 HS bit times,59984 HS bit times,60000 HS bit times,60016 HS bit times,60032 HS bit times,60048 HS bit times,60064 HS bit times,60080 HS bit times,60096 HS bit times,60112 HS bit times,60128 HS bit times,60144 HS bit times,60160 HS bit times,60176 HS bit times,60192 HS bit times,60208 HS bit times,60224 HS bit times,60240 HS bit times,60256 HS bit times,60272 HS bit times,60288 HS bit times,60304 HS bit times,60320 HS bit times,60336 HS bit times,60352 HS bit times,60368 HS bit times,60384 HS bit times,60400 HS bit times,60416 HS bit times,60432 HS bit times,60448 HS bit times,60464 HS bit times,60480 HS bit times,60496" if (((per.l(ad:0x38200000+0xC118))&0x03)==0x01) group.long 0xC700++0x03 line.long 0x00 "DCFG,Device configuration register" bitfld.long 0x00 23. " IGMSTRMPP ,Ignore stream PP" "Not ignored,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capable" "Disabled,Enabled" textline " " bitfld.long 0x00 17.--21. " NUMP ,Number of receive buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 12.--16. " ITRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" textline " " bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High speed,Full speed,,,SuperSpeed,?..." else group.long 0xC700++0x03 line.long 0x00 "DCFG,Device configuration register" bitfld.long 0x00 23. " IGMSTRMPP ,Ignore stream PP" "Not ignored,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capable" "Disabled,Enabled" textline " " textline " " bitfld.long 0x00 12.--16. " ITRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" textline " " bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High speed,Full speed,,,SuperSpeed,?..." endif if (((per.l(ad:0x38200000+0xC700))&0x07)==0x04) group.long 0xC704++0x03 line.long 0x00 "DCTL,Device control register" bitfld.long 0x00 31. " RUN_STOP ,Run stop" "Stop,Run" bitfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" textline " " bitfld.long 0x00 24.--28. " HIRDTHRES ,HIRD threshold" "0,?..." bitfld.long 0x00 20.--23. " LPM_NYET_THRES ,LPM NYET response threshold handshake" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 17. " CRS ,Controller restore data" "No effect,Start restoring process" bitfld.long 0x00 16. " CRS ,Controller save data" "No effect,Start saving data" textline " " bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Not initiated,Initiated" bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Not initiated,Initiated" bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" "No action,,,,SS disbanded,Rx detect,SS Inactive,,Recovery,?..." bitfld.long 0x00 1.--4. " TSTCL ,Test control" "Test mode disabled,Test_J mode,Test_K mode,Test_SE0_NAK,Test Packet mode,Test force enable,SS Inactive,?..." else group.long 0xC704++0x03 line.long 0x00 "DCTL,Device control register" bitfld.long 0x00 31. " RUN_STOP ,Run stop" "Stop,Run" bitfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" textline " " bitfld.long 0x00 24.--28. " HIRDTHRES ,HIRD threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--23. " LPM_NYET_THRES ,LPM NYET response threshold handshake" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 17. " CRS ,Controller restore data" "No effect,Start restoring process" bitfld.long 0x00 16. " CRS ,Controller save data" "No effect,Start saving data" textline " " bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Not initiated,Initiated" bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Not initiated,Initiated" bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" "No action,,,,SS disbanded,Rx detect,SS Inactive,,Recovery,?..." bitfld.long 0x00 1.--4. " TSTCL ,Test control" "Test mode disabled,Test_J mode,Test_K mode,Test_SE0_NAK,Test Packet mode,Test force enable,SS Inactive,?..." endif group.long 0xC708++0x03 line.long 0x00 "DEVTEN,Device event enable register" bitfld.long 0x00 12. " VENDEVTSTRCVDEN ,Vendor device test LPM received rvent" "Not received,Received" bitfld.long 0x00 9. " ERRTICERREVTEN ,Erratic error event enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SOFTEVTEN ,Start of frame enable" "Disabled,Enabled" bitfld.long 0x00 6. " U3L2L1SUSPEN ,U3/L2-L1 suspend event enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " WKUPEVTEN ,Resume/Remote wakeup detected event enable" "Disabled,Enabled" bitfld.long 0x00 3. " ULSTCNGEN ,USB/Link state change event enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " CONNECTDONEEVTEN ,Connection done enable" "Disabled,Enabled" bitfld.long 0x00 1. " USBRSTEVTEN ,USB reset enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DISSCONNEVTEN ,Disconnect detected event enable" "Disabled,Enabled" if (((per.l(ad:0x38200000+0xC700))&0x07)==0x04) rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device status register" bitfld.long 0x00 25. " RSS ,Restore state status" "No during restore process,During restore process" bitfld.long 0x00 24. " SSS ,Save state status" "No during save process,During save process" textline " " bitfld.long 0x00 23. " COREIDLE ,Core idle" "No idle,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Run,Stopped" textline " " bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state" "U0,U1,U2,U3,SS_DIS,RX_DET,SS_INACT,POLL,RECOV,HRESET,CMPLY,LPBK,,,,Resume/reset" bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High speed (30 or 60 MHz),Full speed (30 or 60 MHz),Low speed (6 MHz),Full speed (48 MHz),SuperSpeed(125 or 250 MHz),?..." else rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device status register" bitfld.long 0x00 25. " RSS ,Restore state status" "No during restore process,During restore process" bitfld.long 0x00 24. " SSS ,Save state status" "No during save process,During save process" textline " " bitfld.long 0x00 23. " COREIDLE ,Core idle" "No idle,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Run,Stopped" textline " " bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state" "On state,,Sleep state,Suspended state,Disconnected state,?..." bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High speed (30 or 60 MHz),Full speed (30 or 60 MHz),Low speed (6 MHz),Full speed (48 MHz),SuperSpeed(125 or 250 MHz),?..." endif group.long 0xC710++0x03 line.long 0x00 "DGCMDPAR,Device generic command parameter register" if (((per.l(ad:0x38200000+0xC704))&0x80000000)==0x80000000) group.long 0xC714++0x03 line.long 0x00 "DGCMD,Device generic command register" rbitfld.long 0x00 12.--15. " CMDSTATUS ,Command status" "No error,Error,?..." bitfld.long 0x00 10. " CMDACT ,Command active" "Command executing disabled,Command executing enabled" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" hexmask.long.byte 0x00 0.--7. 1. " CMDTYP ,Command type" else group.long 0xC714++0x03 line.long 0x00 "DGCMD,Device generic command register" rbitfld.long 0x00 12.--15. " CMDSTATUS ,Command status" "No error,Error,?..." bitfld.long 0x00 10. " CMDACT ,Command active" "Command executing disabled,Command executing enabled" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,?..." hexmask.long.byte 0x00 0.--7. 1. " CMDTYP ,Command type" endif group.long 0xC720++0x03 line.long 0x00 "DALEPENA,Device active USB endpoint enable register" hexmask.long.byte 0x00 0.--7. 1. " USBACTEP ,USB active endpoints" group.long 0xC800++0x0B line.long 0x00 "DEPCMDPAR2_0,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_0,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_0,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38200000+0xC704))&0x80000000)==0x80000000) group.long (0xC800+0x0C)++0x03 line.long 0x00 "DEPCMD_0,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC800+0x0C)++0x03 line.long 0x00 "DEPCMD_0,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC810++0x0B line.long 0x00 "DEPCMDPAR2_1,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_1,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_1,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38200000+0xC704))&0x80000000)==0x80000000) group.long (0xC810+0x0C)++0x03 line.long 0x00 "DEPCMD_1,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC810+0x0C)++0x03 line.long 0x00 "DEPCMD_1,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC820++0x0B line.long 0x00 "DEPCMDPAR2_2,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_2,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_2,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38200000+0xC704))&0x80000000)==0x80000000) group.long (0xC820+0x0C)++0x03 line.long 0x00 "DEPCMD_2,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC820+0x0C)++0x03 line.long 0x00 "DEPCMD_2,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC830++0x0B line.long 0x00 "DEPCMDPAR2_3,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_3,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_3,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38200000+0xC704))&0x80000000)==0x80000000) group.long (0xC830+0x0C)++0x03 line.long 0x00 "DEPCMD_3,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC830+0x0C)++0x03 line.long 0x00 "DEPCMD_3,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC840++0x0B line.long 0x00 "DEPCMDPAR2_4,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_4,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_4,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38200000+0xC704))&0x80000000)==0x80000000) group.long (0xC840+0x0C)++0x03 line.long 0x00 "DEPCMD_4,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC840+0x0C)++0x03 line.long 0x00 "DEPCMD_4,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC850++0x0B line.long 0x00 "DEPCMDPAR2_5,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_5,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_5,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38200000+0xC704))&0x80000000)==0x80000000) group.long (0xC850+0x0C)++0x03 line.long 0x00 "DEPCMD_5,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC850+0x0C)++0x03 line.long 0x00 "DEPCMD_5,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC860++0x0B line.long 0x00 "DEPCMDPAR2_6,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_6,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_6,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38200000+0xC704))&0x80000000)==0x80000000) group.long (0xC860+0x0C)++0x03 line.long 0x00 "DEPCMD_6,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC860+0x0C)++0x03 line.long 0x00 "DEPCMD_6,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xC870++0x0B line.long 0x00 "DEPCMDPAR2_7,Device physical endpoint-n command parameter 2 register" line.long 0x04 "DEPCMDPAR1_7,Device physical endpoint-n command parameter 1 register" line.long 0x08 "DEPCMDPAR0_7,Device physical endpoint-n command parameter 0 register" if (((per.l(ad:0x38200000+0xC704))&0x80000000)==0x80000000) group.long (0xC870+0x0C)++0x03 line.long 0x00 "DEPCMD_7,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt,Interrupt" bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transferEnd transfer,Start new configuration,?..." else group.long (0xC870+0x0C)++0x03 line.long 0x00 "DEPCMD_7,Device physical endpoint-n command register" hexmask.long.word 0x00 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x00 12.--15. " COMMANDPARAM[15] ,Command parameters [LST bit of the completed TRB]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x00 10. " CMDACT ,Command active" "Endpoint is ready,Generic command executed" textline " " bitfld.long 0x00 8. " CMDIOC ,Command interrupt on complete" "No interrupt," bitfld.long 0x00 0.--3. " CMDTYP ,Command type" ",Set endpoint configuration,Set endpoint transfer res. conf.,Get endpoint state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new configuration,?..." endif group.long 0xCC00++0x0F line.long 0x00 "OCFG,OTG configuration register" bitfld.long 0x00 5. " DISPRTPWRCUTOFF ,OTG disable port power cut off" "Disabled,Enabled" bitfld.long 0x00 3. " OTGSFTRSTMSK ,OTG soft reset mask" "Not masked,Masked" textline " " bitfld.long 0x00 1. " HNPCAP ,HNP capability" "Disabled,Enabled" bitfld.long 0x00 0. " SRPCAP ,SRP capability" "Disabled,Enabled" line.long 0x04 "OCTL,OTG control register" bitfld.long 0x04 6. " PERIMODE ,Peripheral mode" "Host,Peripheral" bitfld.long 0x04 5. " PRTPWRCTL ,Port power control" "Not initiated VBUS drive,Initiated VBUS drive" textline " " bitfld.long 0x04 4. " HNPREQ ,HNP request" "No HNP request,HNP request" bitfld.long 0x04 3. " SESREQ ,Session request" "No session request,Session request" textline " " bitfld.long 0x04 2. " TERMSELDLPULSE ,TermSel DLine pulsing selection" "Utmi_txvalid,Utmi_termsel" bitfld.long 0x04 1. " DEVSETHNPEN ,Device set HNP enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " HSTSETHNPEN ,Host set HNP enable" "Disabled,Enabled" line.long 0x08 "OEVT,OTG events register" rbitfld.long 0x08 31. " DEVICEMODE ,Device mode" "A-device,B-device" bitfld.long 0x08 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not occurred,Occurred" textline " " bitfld.long 0x08 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not occurred,Occurred" bitfld.long 0x08 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not occurred,Occurred" textline " " bitfld.long 0x08 21. " OTGADEVIDLEEVNT ,A-device A-IDLE event" "Not occurred," bitfld.long 0x08 20. " OTGADEVBHOSTENDEVNT ,A-device B-host event" "Not occurred," textline " " bitfld.long 0x08 19. " OTGADEVHOSTEVNT ,A-device host event" "Not occurred," bitfld.long 0x08 18. " OTGADEVHNPCHNGEVNT ,A-dev HNP change event" "Not occurred," textline " " bitfld.long 0x08 17. " OTGADEVSRPDETEVNT ,SRP detect event" "Not occurred," bitfld.long 0x08 16. " OTGADEVSESSENDDETEVNT ,Session end detected event" "Not occurred," textline " " bitfld.long 0x08 11. " OTGBDEVBHOSTENDEVNT ,B-device B-host event" "Not occurred,Occurred" bitfld.long 0x08 10. " OTGBDEVHNPCHNGEVNT ,B-dev HNP change event" "Not occurred,Occurred" textline " " bitfld.long 0x08 9. " OTGBDEVSESSVLDDETEVNT ,Session valid detected event" "Not occurred,Occurred" bitfld.long 0x08 8. " OTGBDEVVBUSCHNGEVNT ,VBUS change event" "Not occurred,Occurred" textline " " rbitfld.long 0x08 3. " BSESVLD ,B-Session valid" "Not valid,Valid" rbitfld.long 0x08 2. " HSTNEGSTS ,Host negotiation status" "Failure,Success" textline " " bitfld.long 0x08 0. " OEVTERROR ,Host negotiation status" "No error,Error" line.long 0x0C "OEVTEN,OTG events enable register" bitfld.long 0x0C 27. " OTGXHCIRUNSTPSETEVNTEN ,OTG host run stop set event enable" "Disabled,Enabled" bitfld.long 0x0C 26. " OTGDEVRUNSTPSETEVNTEN ,OTG device run stop set event enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 24. " OTGCONIDSTSCHNGEVNTEN ,Connector ID status change event enable" "Disabled,Enabled" bitfld.long 0x0C 23. " HRRCONFNOTIFEVNTEN ,HRRCONFNOTIF event enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 22. " HRRINITNOTIFEVNTEN ,HRRINITNOTIF event enable" "Disabled,Enabled" bitfld.long 0x0C 21. " OTGADEVIDLEEVNTEN ,A-device A-IDLE event" "Disabled,Enabled" textline " " bitfld.long 0x0C 20. " OTGADEVBHOSTENDEVNTEN ,A-device B-host end event enable" "Disabled,Enabled" bitfld.long 0x0C 19. " OTGADEVHOSTEVNTEN ,A-device host event" "Disabled,Enabled" textline " " bitfld.long 0x0C 18. " OTGADEVHNPCHNGEVNTEN ,A-Device HNP change event enable" "Disabled,Enabled" bitfld.long 0x0C 17. " OTGADEVSRPDETEVNTEN ,SRP detect event enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 16. " OTGADEVSESSENDDETEVNTEN ,Session end detected event enable" "Disabled,Enabled" bitfld.long 0x0C 11. " OTGBDEVBHOSTENDEVNTEN ,B-device B-host end event enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 10. " OTGBDEVHNPCHNGEVNTEN ,B-device HNP change event enable" "Disabled,Enabled" bitfld.long 0x0C 9. " OTGBDEVSESSVLDDETEVNTEN ,Session valid detected event enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 8. " OTGBDEVVBUSCHNGEVNTEN ,VBUS change event enable" "Disabled,Enabled" rgroup.long 0xCC10++0x03 line.long 0x00 "OSTS,OTG status register" bitfld.long 0x00 13. " DEVRUNSTP ,Deice run/stop status" "Stop,Run" bitfld.long 0x00 12. " XHCIRUNSTP ,OTG host run stop set event" "Stop,Run" textline " " bitfld.long 0x00 4. " PERIPHERALSTATE ,Core as peripheral or host" "Host,Peripheral" bitfld.long 0x00 2. " BSESVLD ,B-session valid" "Not valid,Valid" textline " " bitfld.long 0x00 1. " ASESVLD ,A-session valid" "Not valid,Valid" bitfld.long 0x00 0. " CONIDSTS ,Connector ID status" "A-device,B-device" group.long 0xCC20++0x0F line.long 0x00 "ADPCFG,ADP configuration register" bitfld.long 0x00 30.--31. " PRBPER ,Probe period" "775 ms,1550 ms,2275 ms,?..." bitfld.long 0x00 28.--29. " PRBDELTA ,Probe delta" "1 cycle,2 cycle,3 cycle,4 cycle" textline " " bitfld.long 0x00 26.--27. " PRBDSCHG ,Probe discharge" "4 ms,8 ms,16 ms,32 ms" line.long 0x04 "ADPCTL,ADP control register" bitfld.long 0x04 28. " ENAPRB ,Enable probe" "Disabled,Enabled" bitfld.long 0x04 27. " ENASNS ,Enable sense" "Disabled,Enabled" textline " " bitfld.long 0x04 26. " ADPEN ,ADP enable" "Suspend clock is gated,Sense/Probe operation is performed" bitfld.long 0x04 25. " ADPRES ,ADP reset" "No reset,Reset" textline " " rbitfld.long 0x04 24. " WB ,Write busy" "Completed,In progress" line.long 0x08 "ADPEVT,ADP event register" bitfld.long 0x08 28. " ADPPRBEVNT ,ADP probe event" "Not occurred,Occurred" bitfld.long 0x08 27. " ADPPRBEVNT ,ADP sense event" "Not occurred,Occurred" textline " " bitfld.long 0x08 26. " ADPTMOUTEVNT ,ADP timeout event" "Not occurred,Occurred" bitfld.long 0x08 25. " ADPRSTCMPLTEVNT ,ADP reset complete event" "Not occurred,Occurred" textline " " hexmask.long.word 0x08 0.--15. 1. " RTIM ,Ramp time" line.long 0x0C "ADPEVTEN,ADP event enable register" bitfld.long 0x0C 28. " ADPPRBEVNTEN ,ADP probe event enable" "Disabled,Enabled" bitfld.long 0x0C 27. " ADPPRBEVNTEN ,ADP sense event enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 26. " ADPTMOUTEVNTEN ,ADP timeout event enable" "Disabled,Enabled" bitfld.long 0x0C 25. " ADPRSTCMPLTEVNTEN ,ADP reset complete event enable" "Disabled,Enabled" width 0x0B tree.end tree.end tree.open "PCIe (PCI express)" tree "PCIe 1" base ad:0x33800000 ;Based one the PCI Express Base Specification 3.0 width 44. rgroup.long 0x00++0x03 line.long 0x00 "TYPE1_DEV_ID_VEND_ID_REG,PCIE0 Device ID And Vendor ID Register" hexmask.long.word 0x00 16.--31. 1. " DEVID ,Device ID" hexmask.long.word 0x00 0.--15. 1. " VENDID ,Vendor ID" group.long 0x04++0x0B line.long 0x00 "TYPE1_STATUS_COMMAND_REG,Command and Status Register" eventfld.long 0x00 31. " DETECTED_PARITY_ERROR ,Detected parity error" "No error,Error" eventfld.long 0x00 30. " SIGNALED_SYS_ERROR ,Signaled system error" "No error,Error" textline " " eventfld.long 0x00 29. " RCVD_MASTER_ABORT ,Received master abort" "No abort,Abort" eventfld.long 0x00 28. " RCVD_TARGET_ABORT ,Received target abort" "No abort,Abort" textline " " eventfld.long 0x00 27. " SIGNALED_TARGET_ABORT ,Signaled target abort" "No abort,Abort" rbitfld.long 0x00 25.--26. " DEV_SEL_TIMING ,Device select timing" "0,?..." textline " " eventfld.long 0x00 24. " MASTER_DPE ,Master data parity error" "No error,Error" rbitfld.long 0x00 23. " FASTB2B ,Fast back-to-back transactions enable" "Disabled," textline " " rbitfld.long 0x00 21. " FAST_66MHZ_CAP ,66 MHz capable" "0," rbitfld.long 0x00 20. " CAP_LIST ,Capabilities list" ",1" textline " " rbitfld.long 0x00 19. " INT_STATUS ,Interrupt status" "Disabled,Enabled" bitfld.long 0x00 10. " INT_EN ,Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " SERREN ,Reporting of non-fatal and fatal errors detected enable" "Disabled,Enabled" rbitfld.long 0x00 7. " IDSEL ,IDSEL stepping/wait cycle control" "0,1" textline " " bitfld.long 0x00 6. " PERREN ,Parity error enable" "Disabled,Enabled" rbitfld.long 0x00 5. " VGAPS ,VGA palette snoop" "Disabled,Enabled" textline " " rbitfld.long 0x00 4. " MWI_EN ,Memory write and invalidate enable" "Disabled,Enabled" rbitfld.long 0x00 3. " SCO ,Special cycle enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BME ,Bus master enable" "Disabled,Enabled" bitfld.long 0x00 1. " MSE ,Memory space enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " IO_EN ,I/O space enable" "Disabled,Enabled" line.long 0x04 "CCRID,Class Code and Revision ID Register" hexmask.long.byte 0x04 24.--31. 1. " BASE_CLASS_CODE ,Base class-memory controller" hexmask.long.byte 0x04 16.--23. 1. " SUBCLASS_CODE ,Sub class-other memory controller" textline " " hexmask.long.byte 0x04 8.--15. 1. " PROGRAM_INTF ,Register level programming interface" hexmask.long.byte 0x04 0.--7. 1. " REV_ID ,Device revision number" line.long 0x08 "BISTTCLSMLT,BIST Header Type Cache Line Size and Master Latency Timer Register" hexmask.long.byte 0x08 24.--31. 1. " BIST ,Built-in self test" bitfld.long 0x08 23. " MULTI_FUNC ,MULTI_FUNC" "0,1" textline " " hexmask.long.byte 0x08 16.--22. 1. " HEADER_TYPE ,Device configuration header type" hexmask.long.byte 0x08 8.--15. 1. " LAT_MASTER_TMR ,Latency master timer" textline " " hexmask.long.byte 0x08 0.--7. 1. " CACHE_LINE_SIZE ,Device cache line size" group.long 0x18++0x2B line.long 0x00 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Primary/Secondary/Subordinate Bus Numbers and Latency Timer Registers" hexmask.long.byte 0x00 24.--31. 1. " SEC_LAT_TIMER ,Latency timer" hexmask.long.byte 0x00 16.--23. 1. " SUB_BUS ,Subordinate bus number" textline " " hexmask.long.byte 0x00 8.--15. 1. " SEC_BUS ,Secondary bus number" hexmask.long.byte 0x00 0.--7. 1. " PRIM_BUS ,Primary bus number" line.long 0x04 "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status and I/O Base and Limit Registers" eventfld.long 0x04 31. " SEC_STAT_DPE ,Detected parity error" "Not error,Error" eventfld.long 0x04 30. " SEC_STAT_RCVD_SYS_ERR ,Received system error" "Not error,Error" textline " " eventfld.long 0x04 29. " SEC_STAT_RCVD_MSTR_ABRT ,Received master abort" "Not received,Received" eventfld.long 0x04 28. " SEC_STAT_RCVD_TRGT_ABRT ,Received target abort" "Not received,Received" textline " " eventfld.long 0x04 27. " SEC_STAT_SIG_TRGT_ABRT ,Signaled target abort" "Not error,Error" eventfld.long 0x04 24. " SEC_STAT_MDPE ,Master data parity error" "Nor error,Error" textline " " bitfld.long 0x04 12.--15. " IO_LIMIT ,I/O limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8. " IO_DECODE_BIT8 ,I/O addressing encode" "16 bit supported,32 bit supported" textline " " bitfld.long 0x04 4.--7. " IO_BASE ,I/O base" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0. " IO_DECODE ,I/O decode" "16 bit supported,32 bit supported" line.long 0x08 "MEM_LIMIT_MEM_BASE_REG,Memory Base and Memory Limit Register" hexmask.long.word 0x08 20.--31. 0x10 " MEM_LIMIT ,Memory limit address" hexmask.long.word 0x08 4.--15. 0x10 " MEM_BASE ,Memory base address" line.long 0x0C "MEM_LIMIT_MEM_BASE_REG,Prefetchable Memory Base and Limit Register" hexmask.long.word 0x0C 20.--31. 1. " PREF_MEM_LIMIT ,Prefetchable memory limit address" rbitfld.long 0x0C 16. " PREF_MEM_LIMIT_DECODE ,Prefetchable memory limit decode " "32 bit supported,64 bit supported" textline " " hexmask.long.word 0x0C 4.--15. 1. " PREF_MEM_BASE ,Prefetchable memory base" rbitfld.long 0x0C 0. " PREF_MEM_DECODE ,Prefetchable memory decode" "32 bit supported,64 bit supported" line.long 0x10 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register" line.long 0x14 "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register" line.long 0x18 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Base and Limit Upper 16 Bits Register" hexmask.long.word 0x18 16.--31. 1. " IO_LIMIT_UPPER ,I/O limit upper 16 bits" hexmask.long.word 0x18 0.--15. 1. " IO_BASE_UPPER ,I/O base upper 16 bits" line.long 0x1C "TYPE1_CAP_PTR_REG,Capability Pointer Register" hexmask.long.byte 0x1C 0.--7. 1. " CAP_PTR ,Capability list pointer" line.long 0x20 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM BAR and Mask Register" hexmask.long.tbyte 0x20 11.--31. 0x08 " EXP_ROM_BASE_ADDR ,Expansion ROM BAR and mask register" rbitfld.long 0x20 0. " ROM_BAR_EN ,ROM BAR enable" "Disabled,Enabled" line.long 0x24 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Interrupt Line and Pin and Bridge Control Registers" bitfld.long 0x24 22. " SBR ,Secondary bus hot reset" "No effect,Hot reset" textline " " rbitfld.long 0x24 21. " MSTR_ABORT_MODE ,Master abort mode" "0," rbitfld.long 0x24 20. " VGA_16B_DEC ,VGA 16-bit decode" "10 bit,16 bit" textline " " rbitfld.long 0x24 19. " VGA_EN ,VGA enable" "Disabled,Enabled" bitfld.long 0x24 18. " ISA_EN ,ISA enable" "Disabled,Enabled" textline " " bitfld.long 0x24 17. " SERR_EN ,SERR enable" "Disabled,Enabled" bitfld.long 0x24 16. " PERE ,Parity error response enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x24 8.--15. 1. " INT_PIN ,Interrupt PIN" hexmask.long.byte 0x24 0.--7. 1. " INT_LINE ,Interrupt line" if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x40++0x07 line.long 0x00 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register" bitfld.long 0x00 27.--31. " PME_SUPPORT ,Support PM Event support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 26. " D2_SUPPORT ,D2 state support" "Not supported,Supported" textline " " bitfld.long 0x00 25. " D1_SUPPORT ,D1 state support" "Not supported,Supported" bitfld.long 0x00 22.--24. " AUX_CURR ,Auxiliary current requirements" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 21. " DSI ,Device specific initialization" "Low,High" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 19. " PME_CLK ,PCI clock requirement" "0,1" textline " " bitfld.long 0x00 16.--18. " PM_SPEC_VER ,PCI power management capability version" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 8.--15. 0x01 " PM_NEXT_PTR ,Next capability pointer" textline " " hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID ,Power management capability ID" else bitfld.long 0x00 20. " PME_IMM_READI_RETURN_D0 ,Immediate readiness on return to D0" "0,1" textline " " bitfld.long 0x00 19. " PME_CLK ,PCI clock requirement" "0,1" bitfld.long 0x00 16.--18. " PM_SPEC_VER ,PCI power management capability version" "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x00 8.--15. 0x01 " PM_NEXT_PTR ,Next capability pointer" hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID ,Power management capability ID" endif line.long 0x04 "PCIEPMCS,PCI Express Power Management Control and Status Register" hexmask.long.byte 0x04 24.--31. 1. " DATA_REG_ADD_INFO ,Power data information" rbitfld.long 0x04 23. " BUS_PWR_CLK_CON_EN ,Bus power/clock control enable" "Disabled,Enabled" textline " " rbitfld.long 0x04 22. " B2_B3_SUPPORT ,B2 B3 support for D3hot" "Not supported,Supported" eventfld.long 0x04 15. " PME_STATUS ,PME Status" "0,1" textline " " rbitfld.long 0x04 13.--14. " DATA_SCALE ,Data scale" "0,1,2,3" rbitfld.long 0x04 9.--12. " DATA_SEL ,Data select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 8. " PME_EN ,PM_PME message generation enable" "Disabled,Enabled" bitfld.long 0x04 3. " NO_SOFT_RST ,No soft reset" "Low,High" textline " " bitfld.long 0x04 0.--1. " POWER_STATE ,Power state" "0,1,2,3" else group.long 0x40++0x07 line.long 0x00 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register" rbitfld.long 0x00 27.--31. " PME_SUPPORT ,Support PM Event support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 26. " D2_SUPPORT ,D2 state support" "Not supported,Supported" textline " " rbitfld.long 0x00 25. " D1_SUPPORT ,D1 state support" "Not supported,Supported" rbitfld.long 0x00 22.--24. " AUX_CURR ,Auxiliary current requirements" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x00 21. " DSI ,Device specific initialization" "Low,High" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 19. " PME_CLK ,PCI clock requirement" "0,1" textline " " rbitfld.long 0x00 16.--18. " PM_SPEC_VER ,PCI power management capability version" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 8.--15. 0x01 " PM_NEXT_PTR ,Next capability pointer" textline " " hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID ,Power management capability ID" else bitfld.long 0x00 20. " PME_IMM_READI_RETURN_D0 ,Immediate readiness on return to D0" "0,1" textline " " bitfld.long 0x00 19. " PME_CLK ,PCI clock requirement" "0,1" rbitfld.long 0x00 16.--18. " PM_SPEC_VER ,PCI power management capability version" "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x00 8.--15. 0x01 " PM_NEXT_PTR ,Next capability pointer" hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID ,Power management capability ID" endif line.long 0x04 "PCIEPMCS,PCI Express Power Management Control and Status Register" hexmask.long.byte 0x04 24.--31. 1. " DATA_REG_ADD_INFO ,Power data information" rbitfld.long 0x04 23. " BUS_PWR_CLK_CON_EN ,Bus power/clock control enable" "Disabled,Enabled" textline " " rbitfld.long 0x04 22. " B2_B3_SUPPORT ,B2 B3 support" "Not supported,Supported" eventfld.long 0x04 15. " PME_STATUS ,PME Status" "0,1" textline " " rbitfld.long 0x04 13.--14. " DATA_SCALE ,Data scale" "0,1,2,3" rbitfld.long 0x04 9.--12. " DATA_SEL ,Data select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 8. " PME_EN ,PM_PME message generation enable" "Disabled,Enabled" rbitfld.long 0x04 3. " NO_SOFT_RST ,No soft reset" "Low,High" textline " " bitfld.long 0x04 0.--1. " POWER_STATE ,Power state" "0,1,2,3" endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x50++0x03 line.long 0x00 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID Next Pointer Control Registers" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 26. " PCI_MSI_EXT_DATA_EN ,Extended message data enable" "Not enabled,Enabled" bitfld.long 0x00 25. " PCI_MSI_EXT_DATA_CAP ,Extended message data Capable" "Not capable,Capable" textline " " endif rbitfld.long 0x00 24. " PCI_PVM_SUPPORT ,MSI per vector masking capable" "Not supported,Supported" bitfld.long 0x00 23. " PCI_MSI_64_BIT_ADDR_CAP ,MSI 64-bit addressing capable" "0,1" textline " " bitfld.long 0x00 20.--22. " PCI_MSI_MULTIPLE_MSG_EN ,Multiple messages enable" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " PCI_MSI_MULTIPLE_MSG_CAP ,MSI Multiple message capable" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 16. " PCI_MSI_EN ,MSI enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 0x01 " PCI_MSI_CAP_NEXT_OFFSET ,MSI capability next pointer" textline " " hexmask.long.byte 0x00 0.--7. 1. " PCI_MSI_CAP_ID ,MSI capability ID" else group.long 0x50++0x03 line.long 0x00 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID Next Pointer Control Registers" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 26. " PCI_MSI_EXT_DATA_EN ,Extended message data enable" "Not enabled,Enabled" rbitfld.long 0x00 25. " PCI_MSI_EXT_DATA_CAP ,Extended message data Capable" "Not capable,Capable" textline " " endif rbitfld.long 0x00 24. " PCI_PVM_SUPPORT ,MSI per vector masking capable" "Not supported,Supported" rbitfld.long 0x00 23. " PCI_MSI_64_BIT_ADDR_CAP ,MSI 64-bit addressing capable" "0,1" textline " " bitfld.long 0x00 20.--22. " PCI_MSI_MULTIPLE_MSG_EN ,Multiple messages enable" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--19. " PCI_MSI_MULTIPLE_MSG_CAP ,MSI Multiple message capable" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 16. " PCI_MSI_EN ,MSI enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 0x01 " PCI_MSI_CAP_NEXT_OFFSET ,MSI capability next pointer" textline " " hexmask.long.byte 0x00 0.--7. 1. " PCI_MSI_CAP_ID ,MSI capability ID" endif group.long 0x54++0x0B line.long 0x00 "MSI_CAP_OFF_04H_REG,MSI Capability ID Next Pointer Control 04H Registers" hexmask.long 0x00 2.--31. 0x04 " PCI_MSI_CAP_OFF_04H ,MSI message lower address field" line.long 0x04 "MSI_CAP_OFF_08H_REG,MSI Capability ID Next Pointer Control 08H Registers" hexmask.long.word 0x04 16.--31. 0x01 " PCI_MSI_CAP_OFF_0AH ,Capability offset 0AH" hexmask.long.word 0x04 0.--15. 0x01 " PCI_MSI_CAP_OFF_08H ,Capability offset 08H" line.long 0x08 "MSI_CAP_OFF_0CH_REG,MSI Capability ID Next Pointer Control 0CH Registers" hexmask.long.word 0x08 16.--31. 0x01 " PCI_MSI_CAP_OFF_0EH ,Capability offset 0EH" hexmask.long.word 0x08 0.--15. 0x01 " PCI_MSI_CAP_OFF_0CH ,Capability offset 0CH" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") group.long 0x60++0x03 line.long 0x00 "MSI_CAP_OFF_10H_REG,Used for MSI when Vector Masking Capable" rgroup.long 0x64++0x03 line.long 0x00 "MSI_CAP_OFF_14H_REG,Used for MSI 64bit messaging when Vector Masking Capable" endif base ad:0x33800000+0x70 if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x00++0x07 line.long 0x00 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities ID Next Pointer Register" rbitfld.long 0x00 25.--29. " PCIE_INT_MSG_NUM ,Interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 24. " PCIE_SLOT_IMP ,Slot implemented" "Not valid,Valid" textline " " bitfld.long 0x00 20.--23. " PCIE_DEV_PORT_TYPE ,Device/Port type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " PCIE_CAP_REG ,Capability version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " PCIE_CAP_NEXT_PTR ,Next item pointer" hexmask.long.byte 0x00 0.--7. 1. " PCIE_CAP_ID ,Capability ID" line.long 0x04 "DEVICE_CAPABILITIES_REG ,Device Capabilities Register" bitfld.long 0x04 15. " PCIE_CAP_ROLE_BASED_ERR_REPORT ,Role based error reporting" "No error,Error" bitfld.long 0x04 5. " PCIE_CAP_EXT_TAG_SUPP ,Extended tag field support" "Not supported,Supported" textline " " bitfld.long 0x04 3.--4. " PCIE_CAP_PHANTOM_FUNC_SUPP ,Phantom functions support" "0,1,2,3" bitfld.long 0x04 0.--2. " PCIE_CAP_MAX_PAYLOAD_SIZE ,Max payload size" "0,1,2,3,4,5,6,7" else rgroup.long 0x00++0x07 line.long 0x00 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities ID Next Pointer Register" bitfld.long 0x00 25.--29. " PCIE_INT_MSG_NUM ,Interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " PCIE_SLOT_IMP ,Slot implemented" "Not valid,Valid" textline " " bitfld.long 0x00 20.--23. " PCIE_DEV_PORT_TYPE ,Device/Port type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " PCIE_CAP_REG ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " PCIE_CAP_NEXT_PTR ,Next item pointer" hexmask.long.byte 0x00 0.--7. 1. " PCIE_CAP_ID ,Capability ID" line.long 0x04 "DEVICE_CAPABILITIES_REG ,Device Capabilities Register" bitfld.long 0x04 15. " PCIE_CAP_ROLE_BASED_ERR_REPORT ,Role based error reporting" "No error,Error" bitfld.long 0x04 5. " PCIE_CAP_EXT_TAG_SUPP ,Extended tag field support" "Not supported,Supported" textline " " bitfld.long 0x04 3.--4. " PCIE_CAP_PHANTOM_FUNC_SUPP ,Phantom functions support" "0,1,2,3" bitfld.long 0x04 0.--2. " PCIE_CAP_MAX_PAYLOAD_SIZE ,Max payload size" "0,1,2,3,4,5,6,7" endif width 36. textline " " if (((per.l(ad:0x33800000+0x74))&0x18)==0x00) group.long 0x08++0x03 line.long 0x00 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Status Register" rbitfld.long 0x00 21. "PCIE_CAP_TRANS_PEND ,Transactions pending" "Completed,Not completed" rbitfld.long 0x00 20. " PCIE_CAP_AUX_POWER_DET ,AUX power detected" "Not detected,Detected" textline " " eventfld.long 0x00 19. " PCIE_CAP_UNSUPP_REQ_DET ,Unsupported request detected" "Not detected,Detected" eventfld.long 0x00 18. " PCIE_CAP_FATAL_ERR_DET ,Fatal error detected" "Not detected,Detected" textline " " eventfld.long 0x00 17. " PCIE_CAP_NON_FATAL_ERR_DET ,Non-fatal error detected" "Not detected,Detected" eventfld.long 0x00 16. " PCIE_CAP_CORR_ERR_DET ,Correctable error detected" "Not detected,Detected" textline " " bitfld.long 0x00 15. " PCIE_CAP_INIT_FLR ,Initiate function level reset" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PCIE_CAP_MAX_READ_REQ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x00 11. " PCIE_CAP_EN_NO_SNOOP ,Enable no snoop" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_AUX_POWER_PM_EN ,Auxiliary power PM enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " PCIE_CAP_PHANTOM_FUNC_EN ,Phantom functions support" "Not supported,Supported" rbitfld.long 0x00 8. " PCIE_CAP_EXT_TAG_EN ,Extended tag field support" "Not supported,Supported" textline " " bitfld.long 0x00 5.--7. " PCIE_CAP_MAX_PAYLOAD_SIZE_CS ,Maximum payload size supported" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. " PCIE_CAP_EN_REL_ORDER ,Enable relaxed ordering" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_UNSUPPORT_REQ_REP_EN ,Unsupported request reporting enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_FATAL_ERR_REPORT_EN ,Fatal error reporting enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_NON_FATAL_ERR_REPORT_EN ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_CORR_ERR_REPORT_EN ,Correctable error reporting enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Status Register" rbitfld.long 0x00 21. "PCIE_CAP_TRANS_PEND ,Transactions pending" "Completed,Not completed" rbitfld.long 0x00 20. " PCIE_CAP_AUX_POWER_DET ,AUX power detected" "Not detected,Detected" textline " " eventfld.long 0x00 19. " PCIE_CAP_UNSUPP_REQ_DET ,Unsupported request detected" "Not detected,Detected" eventfld.long 0x00 18. " PCIE_CAP_FATAL_ERR_DET ,Fatal error detected" "Not detected,Detected" textline " " eventfld.long 0x00 17. " PCIE_CAP_NON_FATAL_ERR_DET ,Non-fatal error detected" "Not detected,Detected" eventfld.long 0x00 16. " PCIE_CAP_CORR_ERR_DET ,Correctable error detected" "Not detected,Detected" textline " " bitfld.long 0x00 15. " PCIE_CAP_INIT_FLR ,Initiate function level reset" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PCIE_CAP_MAX_READ_REQ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x00 11. " PCIE_CAP_EN_NO_SNOOP ,Enable no snoop" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_AUX_POWER_PM_EN ,Auxiliary power PM enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_PHANTOM_FUNC_EN ,Phantom functions support" "Not supported,Supported" bitfld.long 0x00 8. " PCIE_CAP_EXT_TAG_EN ,Extended tag field support" "Not supported,Supported" textline " " bitfld.long 0x00 5.--7. " PCIE_CAP_MAX_PAYLOAD_SIZE_CS ,Maximum payload size supported" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. " PCIE_CAP_EN_REL_ORDER ,Enable relaxed ordering" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_UNSUPPORT_REQ_REP_EN ,Unsupported request reporting enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_FATAL_ERR_REPORT_EN ,Fatal error reporting enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_NON_FATAL_ERR_REPORT_EN ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_CORR_ERR_REPORT_EN ,Correctable error reporting enable" "Disabled,Enabled" endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "LINK_CAPABILITIES_REG,Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. "PCIE_CAP_PORT_NUM ,Port number" bitfld.long 0x00 22. " PCIE_CAP_ASPM_OPT_COMPL ,ASPM optionality compliance" "Not compliant,Compliant" textline " " bitfld.long 0x00 21. " PCIE_CAP_LINK_BW_NOT_CAP ,Link bandwidth notification capable" "0,1" rbitfld.long 0x00 20. " PCIE_CAP_DLL_ACTIVE_REP_CAP ,Data link layer link active reporting capable" "0,1" textline " " bitfld.long 0x00 19. " PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ,Surprise down error reporting capable" "0,1" rbitfld.long 0x00 18. " PCIE_CAP_CLK_POWER_MAN ,Clock power management" "0,1" textline " " rbitfld.long 0x00 15.--17. " PCIE_CAP_L1_EXIT_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 12.--14. " PCIE_CAP_L0S_EXIT_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 10.--11. " PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPP ,Level of ASPM support" "0,1,2,3" bitfld.long 0x00 4.--9. " PCIE_CAP_MAX_LINK_WIDTH ,Maximum link width supported by the port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0.--3. " PCIE_CAP_MAX_LINK_SPEED ,Maximum link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "LINK_CAPABILITIES_REG,Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. "PCIE_CAP_PORT_NUM ,Port number" bitfld.long 0x00 22. " PCIE_CAP_ASPM_OPT_COMPL ,ASPM optionality compliance" "Not compliant,Compliant" textline " " bitfld.long 0x00 21. " PCIE_CAP_LINK_BW_NOT_CAP ,Link bandwidth notification capable" "0,1" bitfld.long 0x00 20. " PCIE_CAP_DLL_ACTIVE_REP_CAP ,Data link layer link active reporting capable" "0,1" textline " " bitfld.long 0x00 19. " PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ,Surprise down error reporting capable" "0,1" bitfld.long 0x00 18. " PCIE_CAP_CLK_POWER_MAN ,Clock power management" "0,1" textline " " bitfld.long 0x00 15.--17. " PCIE_CAP_L1_EXIT_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " PCIE_CAP_L0S_EXIT_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 10.--11. " PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPP ,Level of ASPM support" "0,1,2,3" bitfld.long 0x00 4.--9. " PCIE_CAP_MAX_LINK_WIDTH ,Maximum link width supported by the port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0.--3. " PCIE_CAP_MAX_LINK_SPEED ,Maximum link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33800000+0x7C))&0x100000)==0x100000)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x40000) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" bitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Current link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " bitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " bitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" bitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33800000+0x7C))&0x100000)==0x100000)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x00) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" bitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Current link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " bitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" bitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33800000+0x7C))&0x100000)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x40000) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" bitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " rbitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " bitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" bitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33800000+0x7C))&0x100000)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x00) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" bitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " rbitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" bitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x100000)==0x100000)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x40000) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" rbitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " bitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " bitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" rbitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x100000)==0x100000)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x00) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" rbitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " bitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" rbitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x100000)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x40000) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" rbitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Current link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " rbitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " bitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" rbitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x100000)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x00) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" rbitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " rbitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" rbitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x14++0x03 line.long 0x00 "SLOT_CAPABILITIES_REG,Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM ,PHY slot number" bitfld.long 0x00 18. " PCIE_CAP_NO_CMD_CPL_SUPP ,No command completion support" "Not supported,Supported" textline " " bitfld.long 0x00 17. " PCIE_CAP_ELECTROMECH_INTERLOCK ,Electromechanical interlock present" "0,1" bitfld.long 0x00 15.--16. " PCIE_CAP_SLOT_POWER_LIMIT_SCALE ,Slot power limit scale" "1.0x,0.1x,0.01x,0.001x" textline " " hexmask.long.byte 0x00 7.--14. 1. " PCIE_CAP_SLOT_POWER_LIMIT_VAL ,Slot power limit value" bitfld.long 0x00 6. " PCIE_CAP_HOT_PLUG_CAPABLE ,Hot plug capable" "0,1" textline " " bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_SURPRISE ,Hot plug surprise possible" "0,1" bitfld.long 0x00 4. " PCIE_CAP_POWER_IND ,Power indicator present" "0,1" textline " " bitfld.long 0x00 3. " PCIE_CAP_ATT_IND ,Attention indicator present" "0,1" bitfld.long 0x00 2. " PCIE_CAP_MRL_SENSOR ,MRL present" "0,1" textline " " bitfld.long 0x00 1. " PCIE_CAP_POWER_CONTROLLER ,Power controller present" "0,1" bitfld.long 0x00 0. " PCIE_CAP_ATT_IND_BUTTON ,Attention button present" "0,1" else rgroup.long 0x14++0x03 line.long 0x00 "SLOT_CAPABILITIES_REG,Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM ,PHY slot number" bitfld.long 0x00 18. " PCIE_CAP_NO_CMD_CPL_SUPP ,No command completion support" "Not supported,Supported" textline " " bitfld.long 0x00 17. " PCIE_CAP_ELECTROMECH_INTERLOCK ,Electromechanical interlock present" "0,1" bitfld.long 0x00 15.--16. " PCIE_CAP_SLOT_POWER_LIMIT_SCALE ,Slot power limit scale" "1.0x,0.1x,0.01x,0.001x" textline " " hexmask.long.byte 0x00 7.--14. 1. " PCIE_CAP_SLOT_POWER_LIMIT_VAL ,Slot power limit value" bitfld.long 0x00 6. " PCIE_CAP_HOT_PLUG_CAPABLE ,Hot plug capable" "0,1" textline " " bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_SURPRISE ,Hot plug surprise possible" "0,1" bitfld.long 0x00 4. " PCIE_CAP_POWER_IND ,Power indicator present" "0,1" textline " " bitfld.long 0x00 3. " PCIE_CAP_ATT_IND ,Attention indicator present" "0,1" bitfld.long 0x00 2. " PCIE_CAP_MRL_SENSOR ,MRL present" "0,1" textline " " bitfld.long 0x00 1. " PCIE_CAP_POWER_CONTROLLER ,Power controller present" "0,1" bitfld.long 0x00 0. " PCIE_CAP_ATT_IND_BUTTON ,Attention button present" "0,1" endif if (((per.l(ad:0x33800000+0x84))&0x40000)==0x40000) group.long 0x18++0x03 line.long 0x00 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register" eventfld.long 0x00 24. "PCIE_CAP_DLL_STATE_CHANGED ,DLL state changed" "Not changed,Changed" rbitfld.long 0x00 23. " PCIE_CAP_ELECTROMECH_INTERLOCK_STAT ,Electromechanical interlock status" "0,1" textline " " rbitfld.long 0x00 22. " PCIE_CAP_PRESENCE_DET_STATE ,Presence detect state" "Not detected,Detected" rbitfld.long 0x00 21. " PCIE_CAP_MRL_SENSOR_STATE ,MRL sensor state" "0,1" textline " " eventfld.long 0x00 20. " PCIE_CAP_CMD_CPLD ,Command completed" "0,1" eventfld.long 0x00 19. " PCIE_CAP_PRESENCE_DET_CHANGED ,Presence detect changed" "Not changed,Changed" textline " " eventfld.long 0x00 18. " PCIE_CAP_MRL_SENSOR_CHANGED ,MRL sensor changed" "Not changed,Changed" eventfld.long 0x00 17. " PCIE_CAP_POWER_FAULT_DET ,Power fault detect" "Not detected,Detected" textline " " eventfld.long 0x00 16. " PCIE_CAP_ATT_BUTTON_PRESSED ,Attention button pressed" "Not pressed,Pressed" bitfld.long 0x00 12. " PCIE_CAP_DLL_STATE_CHANGED_EN ,Data link layer state changed enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL ,Electromechanical interlock control" "No effect,Toggle" bitfld.long 0x00 10. " PCIE_CAP_POWER_CONTROLLER_CTRL ,Power controller control" "On,Off" textline " " bitfld.long 0x00 8.--9. " PCIE_CAP_POWER_IND_CTRL ,Power indicator control" ",On,Blink,On" bitfld.long 0x00 6.--7. " PCIE_CAP_ATT_IND_CTRL ,Attention indicator control" ",On,Blink,On" textline " " bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_INT_EN ,Hot plug indicator enable" "Disabled,Enabled" rbitfld.long 0x00 4. " PCIE_CAP_CMD_CPL_INT_EN ,Command CPL indicator enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_PRESENCE_DET_CHANGE_EN ,Presence detect changed enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SENSOR_CHANGED_EN ,Sensor changed enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_POWER_FAULT_DET_EN ,Power fault detect enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_ATT_BUTTON_PRESSED_EN ,Attention button pressed enable" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register" eventfld.long 0x00 24. "PCIE_CAP_DLL_STATE_CHANGED ,DLL state changed" "Not changed,Changed" rbitfld.long 0x00 23. " PCIE_CAP_ELECTROMECH_INTERLOCK_STAT ,Electromechanical interlock status" "0,1" textline " " rbitfld.long 0x00 22. " PCIE_CAP_PRESENCE_DET_STATE ,Presence detect state" "Not detected,Detected" rbitfld.long 0x00 21. " PCIE_CAP_MRL_SENSOR_STATE ,MRL sensor state" "0,1" textline " " eventfld.long 0x00 20. " PCIE_CAP_CMD_CPLD ,Command completed" "0,1" eventfld.long 0x00 19. " PCIE_CAP_PRESENCE_DET_CHANGED ,Presence detect changed" "Not changed,Changed" textline " " eventfld.long 0x00 18. " PCIE_CAP_MRL_SENSOR_CHANGED ,MRL sensor changed" "Not changed,Changed" eventfld.long 0x00 17. " PCIE_CAP_POWER_FAULT_DET ,Power fault detect" "Not detected,Detected" textline " " eventfld.long 0x00 16. " PCIE_CAP_ATT_BUTTON_PRESSED ,Attention button pressed" "Not pressed,Pressed" bitfld.long 0x00 12. " PCIE_CAP_DLL_STATE_CHANGED_EN ,Data link layer state changed enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL ,Electromechanical interlock control" "No effect,Toggle" bitfld.long 0x00 10. " PCIE_CAP_POWER_CONTROLLER_CTRL ,Power controller control" "On,Off" textline " " bitfld.long 0x00 8.--9. " PCIE_CAP_POWER_IND_CTRL ,Power indicator control" ",On,Blink,On" bitfld.long 0x00 6.--7. " PCIE_CAP_ATT_IND_CTRL ,Attention indicator control" ",On,Blink,On" textline " " bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_INT_EN ,Hot plug indicator enable" "Disabled,Enabled" bitfld.long 0x00 4. " PCIE_CAP_CMD_CPL_INT_EN ,Command CPL indicator enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_PRESENCE_DET_CHANGE_EN ,Presence detect changed enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SENSOR_CHANGED_EN ,Sensor changed enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_POWER_FAULT_DET_EN ,Power fault detect enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_ATT_BUTTON_PRESSED_EN ,Attention button pressed enable" "Disabled,Enabled" endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33800000+0x8C))&0x10000)==0x10000) group.long 0x1C++0x03 line.long 0x00 "ROOT_CONTROL_ROOT_CAPABILITIES,Root Control and Capabilities Register" bitfld.long 0x00 16. "PCIE_CAP_CRS_SW_VISIBILITY ,CRS software visibility capable" "0,1" bitfld.long 0x00 4. " PCIE_CAP_CRS_SW_VISIBILITY_EN ,Configuration request retry status (CRS) software visibility enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN ,PME interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN ,System error on fatal error enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN ,System error on correctable error enable" "Disabled,Enabled" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33800000+0x8C))&0x10000)==0x00) group.long 0x1C++0x03 line.long 0x00 "ROOT_CONTROL_ROOT_CAPABILITIES,Root Control and Capabilities Register" bitfld.long 0x00 16. "PCIE_CAP_CRS_SW_VISIBILITY ,CRS software visibility capable" "0,1" rbitfld.long 0x00 4. " PCIE_CAP_CRS_SW_VISIBILITY_EN ,Configuration request retry status (CRS) software visibility enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN ,PME interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN ,System error on fatal error enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN ,System error on correctable error enable" "Disabled,Enabled" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33800000+0x8C))&0x10000)==0x10000) group.long 0x1C++0x03 line.long 0x00 "ROOT_CONTROL_ROOT_CAPABILITIES,Root Control and Capabilities Register" rbitfld.long 0x00 16. "PCIE_CAP_CRS_SW_VISIBILITY ,CRS software visibility capable" "0,1" bitfld.long 0x00 4. " PCIE_CAP_CRS_SW_VISIBILITY_EN ,Configuration request retry status (CRS) software visibility enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN ,PME interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN ,System error on fatal error enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN ,System error on correctable error enable" "Disabled,Enabled" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33800000+0x8C))&0x10000)==0x00) group.long 0x1C++0x03 line.long 0x00 "ROOT_CONTROL_ROOT_CAPABILITIES,Root Control and Capabilities Register" rbitfld.long 0x00 16. "PCIE_CAP_CRS_SW_VISIBILITY ,CRS software visibility capable" "0,1" rbitfld.long 0x00 4. " PCIE_CAP_CRS_SW_VISIBILITY_EN ,Configuration request retry status (CRS) software visibility enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN ,PME interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN ,System error on fatal error enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN ,System error on correctable error enable" "Disabled,Enabled" endif group.long 0x20++0x03 line.long 0x00 "ROOT_STATUS_REG,Root Status Register" rbitfld.long 0x00 17. "PCIE_CAP_PME_PEND ,PME pending" "Not pending,Pending" eventfld.long 0x00 16. " PCIE_CAP_PME_STATUS ,PME status" "0,1" textline " " hexmask.long.word 0x00 0.--15. 1. " PCIE_CAP_PME_REQ_ID ,PME requester ID" rgroup.long 0x24++0x03 line.long 0x00 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 18.--19. "PCIE_CAP_OBFF_SUPPORT ,Optimized buffer flush/fill supported" "Not supported,Msg,WAKE# ,Both" bitfld.long 0x00 17. " PCIE_CAP2_10_BIT_TAG_ERQ_SUPPORT ,10-bit tag request supported" "Not supported,Supported" textline " " bitfld.long 0x00 16. " PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT ,10-bit tag completer supported" "Not supported,Supported" bitfld.long 0x00 13. " PCIE_CAP_TPH_CMPLT_SUPP_1 ,TPH completer supported bit 1" "0,1" textline " " bitfld.long 0x00 12. " PCIE_CAP_TPH_CMPLT_SUPP_0 ,TPH completer supported bit 0" "0,1" bitfld.long 0x00 11. " PCIE_CAP_LTR_SUPP ,LTR mechanism supported" "0,1" textline " " bitfld.long 0x00 10. " PCIE_CAP_NO_RO_EN_PR2PR_PAR ,No relaxed ordering enabled PR-PR passing" "0,1" bitfld.long 0x00 9. " PCIE_CAP_128_CAS_CPL_SUPP ,128 atomic CAS support" "Not supported,Supported" textline " " bitfld.long 0x00 8. " PCIE_CAP_64_ATOMIC_CPL_SUPP ,64 atomic support" "Not supported,Supported" bitfld.long 0x00 7. " PCIE_CAP_32_ATOMIC_CPL_SUPP ,32 atomic support" "Not supported,Supported" textline " " bitfld.long 0x00 6. " PCIE_CAP_ATOMIC_ROUTING_SUPP ,Atomic routing support" "Not supported,Supported" bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT ,ARI forward support" "Not supported,Supported" textline " " bitfld.long 0x00 4. " PCIE_CAP_CPL_TIMEOUT_DIS_SUPP ,Completion timeout disable support" "Not supported,Supported" bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_RANGE ,Completion timeout ranges supported" "A,B,A/B,,,,B/C,A/B/C,,,,,,,B/C/D,A/B/C/D" else bitfld.long 0x00 18.--19. "PCIE_CAP_OBFF_SUPPORT ,Optimized buffer flush/fill supported" "Not supported,Msg,WAKE#,Both" bitfld.long 0x00 14.--15. " PCIE_CAP2_LN_SYS_CLS ,LN system CLS" "0,1,2,3" textline " " bitfld.long 0x00 13. " PCIE_CAP_TPH_CMPLT_SUPP_1 ,TPH completer supported bit 1" "0,1" bitfld.long 0x00 12. " PCIE_CAP_TPH_CMPLT_SUPP_0 ,TPH completer supported bit 0" "0,1" textline " " bitfld.long 0x00 11. " PCIE_CAP_LTR_SUPP ,LTR mechanism supported" "0,1" bitfld.long 0x00 10. " PCIE_CAP_NO_RO_EN_PR2PR_PAR ,No relaxed ordering enabled PR-PR passing" "0,1" textline " " bitfld.long 0x00 9. " PCIE_CAP_128_CAS_CPL_SUPP ,128 atomic CAS support" "Not supported,Supported" bitfld.long 0x00 8. " PCIE_CAP_64_ATOMIC_CPL_SUPP ,64 atomic support" "Not supported,Supported" textline " " bitfld.long 0x00 7. " PCIE_CAP_32_ATOMIC_CPL_SUPP ,32 atomic support" "Not supported,Supported" bitfld.long 0x00 6. " PCIE_CAP_ATOMIC_ROUTING_SUPP ,Atomic routing support" "Not supported,Supported" textline " " bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT ,ARI forward support" "Not supported,Supported" bitfld.long 0x00 4. " PCIE_CAP_CPL_TIMEOUT_DIS_SUPP ,Completion timeout disable support" "Not supported,Supported" textline " " bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_RANGE ,Completion timeout ranges supported" "A,B,A/B,,,,B/C,A/B/C,,,,,,,B/C/D,A/B/C/D" endif group.long 0x28++0x03 line.long 0x00 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register" sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") bitfld.long 0x00 9. "PCIE_CAP_IDO_CPL_EN ,IDO completion enable" "Disabled,Enabled" bitfld.long 0x00 8. " PCIE_CAP_IDO_REQ_EN ,IDO request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT_CS ,ARI forwarding enable" "Disabled,Enabled" bitfld.long 0x00 4. " PCIE_CAP_CPL_TIMEOUT_DIS ,Completion timeout disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_VAL ,Completion timeout value" "50us to 50ms,50us to 100us,1ms to 10ms,,,16ms to 55ms,65ms to 210ms,,,260ms to 900ms,1s to 3.5s,,,4s to 13s,17s to 64s," else bitfld.long 0x00 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS ,ARI forwarding enable" "Disabled,Enabled" bitfld.long 0x00 4. " PCIE_CAP_CPL_TIMEOUT_DIS ,Completion timeout disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_VAL ,Completion timeout value" "50us to 50ms,50us to 100us,1ms to 10ms,,,16ms to 55ms,65ms to 210ms,,,260ms to 900ms,1s to 3.5s,,,4s to 13s,17s to 64s," endif rgroup.long 0x2C++0x03 line.long 0x00 "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register" sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") bitfld.long 0x00 31. "DRS_SUPPORTED ,DRS supported" "Not supported,Supported" bitfld.long 0x00 8. " PCIE_CAP_CROSS_LINK_SUPPORT ,Cross link support" "Not supported,Supported" textline " " hexmask.long.byte 0x00 1.--7. 1. " PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR ,Supported link speed vector" else bitfld.long 0x00 8. "PCIE_CAP_CROSS_LINK_SUPPORT ,Cross link support" "Not supported,Supported" hexmask.long.byte 0x00 1.--7. 1. " PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR ,Supported link speed vector" endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x30++0x03 line.long 0x00 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register" eventfld.long 0x00 31. "DRS_MESSAGE_RECEIVED ,DRS message received" "0,1" rbitfld.long 0x00 28.--30. " DOWNSTREAM_COMPO_PRESENCE ,Downstream component presence" "0,1,2,3,4,5,,?..." textline " " sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") bitfld.long 0x00 21. " PCIE_CAP_LINK_EQ_REQ ,Link equalization request 8.0GT/s" "Not requested,Requested" bitfld.long 0x00 20. " PCIE_CAP_EQ_CPL_P3 ,Equalization 8.0GT/s phase 3 successful" "Not successful,Successful" textline " " bitfld.long 0x00 19. " PCIE_CAP_EQ_CPL_P2 ,Equalization 8.0GT/s phase 2 successful" "Not successful,Successful" bitfld.long 0x00 18. " PCIE_CAP_EQ_CPL_P1 ,Equalization 8.0GT/s phase 1 successful" "Not successful,Successful" textline " " bitfld.long 0x00 17. " PCIE_CAP_EQ_CPL ,Equalization 8.0GT/s complete" "Not completed,Completed" rbitfld.long 0x00 16. " PCIE_CAP_CURR_DEEMPHASIS ,Current de-emphasis level" "-6dB,-3.5dB" textline " " else rbitfld.long 0x00 16. " PCIE_CAP_CURR_DEEMPHASIS ,Current de-emphasis level" "-6dB,-3.5dB" textline " " endif bitfld.long 0x00 12.--15. " PCIE_CAP_COMPLIANCE_PRESET ,Compliance preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " PCIE_CAP_COMPLIANCE_SOS ,Compliance SOS" "0,1" textline " " bitfld.long 0x00 10. " PCIE_CAP_ENTER_MODIFIED_COMPILANCE ,Enter modified compliance" "0,1" bitfld.long 0x00 7.--9. " PCIE_CAP_TX_MARGIN ,Controls transmit margin for debug or compliance" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6. " PCIE_CAP_SEL_DEEMPHASIS ,Controls selectable de-emphasis" "-3.5dB,-6dB" bitfld.long 0x00 5. " PCIE_CAP_HW_AUTO_SPEED_DISABLE ,Hardware autonomous speed disable" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " PCIE_CAP_ENTER_COMPLIANCE ,Enter compliance mode" "0,1" bitfld.long 0x00 0.--3. " PCIE_CAP_TARGET_LINK_SPEED ,Target link speed" ",0,1,2,3,4,5,6,,,,,,,,?..." else group.long 0x30++0x03 line.long 0x00 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register" eventfld.long 0x00 31. "DRS_MESSAGE_RECEIVED ,DRS message received" "0,1" rbitfld.long 0x00 28.--30. " DOWNSTREAM_COMPO_PRESENCE ,Downstream component presence" "0,1,2,3,4,5,6,7" textline " " sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") bitfld.long 0x00 21. " PCIE_CAP_LINK_EQ_REQ ,Link equalization request 8.0GT/s" "Not requested,Requested" bitfld.long 0x00 20. " PCIE_CAP_EQ_CPL_P3 ,Equalization 8.0GT/s phase 3 successful" "Not successful,Successful" textline " " bitfld.long 0x00 19. " PCIE_CAP_EQ_CPL_P2 ,Equalization 8.0GT/s phase 2 successful" "Not successful,Successful" bitfld.long 0x00 18. " PCIE_CAP_EQ_CPL_P1 ,Equalization 8.0GT/s phase 1 successful" "Not successful,Successful" textline " " bitfld.long 0x00 17. " PCIE_CAP_EQ_CPL ,Equalization 8.0GT/s complete" "Not completed,Completed" rbitfld.long 0x00 16. " PCIE_CAP_CURR_DEEMPHASIS ,Current de-emphasis level" "-6dB,-3.5dB" textline " " else rbitfld.long 0x00 16. " PCIE_CAP_CURR_DEEMPHASIS ,Current de-emphasis level" "-6dB,-3.5dB" textline " " endif bitfld.long 0x00 12.--15. " PCIE_CAP_COMPLIANCE_PRESET ,Compliance preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " PCIE_CAP_COMPLIANCE_SOS ,Compliance SOS" "0,1" textline " " bitfld.long 0x00 10. " PCIE_CAP_ENTER_MODIFIED_COMPILANCE ,Enter modified compliance" "0,1" bitfld.long 0x00 7.--9. " PCIE_CAP_TX_MARGIN ,Controls transmit margin for debug or compliance" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x00 6. " PCIE_CAP_SEL_DEEMPHASIS ,Controls selectable de-emphasis" "-3.5dB,-6dB" bitfld.long 0x00 5. " PCIE_CAP_HW_AUTO_SPEED_DISABLE ,Hardware autonomous speed disable" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " PCIE_CAP_ENTER_COMPLIANCE ,Enter compliance mode" "0,1" bitfld.long 0x00 0.--3. " PCIE_CAP_TARGET_LINK_SPEED ,Target link speed" ",0,1,2,3,4,5,6,,,,,,,,?..." endif base ad:0x33800000+0x100 width 27. textline " " if (((per.l(ad:0x33800000+0x8B4))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next capability offset" bitfld.long 0x00 16.--19. " CAP_VER ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " CAP_ID ,Capability ID" else rgroup.long 0x00++0x03 line.long 0x00 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VER ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " CAP_ID ,AER extended capability ID" endif group.long 0x04++0x03 line.long 0x00 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register" eventfld.long 0x00 25. " TLP_PRFX_BLOCKED_ERR_STAT ,TLP_PRFX blocked error status" "No error,Error" eventfld.long 0x00 22. " INTERNAL_ERR_STATUS ,Uncorrectable internal error status" "No error,Error" textline " " eventfld.long 0x00 20. " UNSUPPORTED_REQ_ERR_STAT ,Unsupported request error status" "No error,Error" eventfld.long 0x00 19. " ECRC_ERR_STAT ,ECRC error status" "No error,Error" textline " " eventfld.long 0x00 18. " MALF_TLP_ERR_STATUS ,Malformed TLP error status" "No error,Error" eventfld.long 0x00 17. " REC_OVRFLOW_ERR_STATUS ,Receiver overflow status" "No overflow,Overflow" textline " " eventfld.long 0x00 16. " UNEXP_CMPLT_ERR_STATUS ,Unexpected completion error status" "No error,Error" eventfld.long 0x00 15. " CMPLT_ABORT_ERR_STATUS ,Completer abort error status" "No error,Error" textline " " eventfld.long 0x00 14. " CMPLT_TIMEOUT_ERR_STATUS ,Completion timeout error status" "No timeout,Timeout" eventfld.long 0x00 13. " FC_PROTOCOL_ERR_STATUS ,Flow control protocol error status" "No error,Error" textline " " eventfld.long 0x00 12. " POIS_TLP_ERR_STATUS ,Poisoned TLP receive status" "No error,Error" eventfld.long 0x00 5. " SURPRISE_DOWN_ERR_STATUS ,Surprise down error status" "No error,Error" textline " " eventfld.long 0x00 4. " DL_PROTOCOL_ERR_STATUS ,Data link protocol error status" "No error,Error" if (((per.l(ad:0x33800000+0x8BC))&0x80000)==0x80000) group.long 0x08++0x07 line.long 0x00 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register" bitfld.long 0x00 25. " TLP_PRFX_BLOCKED_ERR_MASK ,TLP prefix blocked error mask" "Not masked,Masked" bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_MASK ,AtomicOp blocked mask" "Not masked,Masked" textline " " bitfld.long 0x00 22. " INTERNAL_ERR_MASK ,Internal error mask" "Not masked,Masked" bitfld.long 0x00 20. " UNSUPPORTED_REQ_ERR_MASK ,Unsupported request error mask" "Not masked,Masked" textline " " bitfld.long 0x00 19. " ECRC_ERR_MASK ,ECRC error mask" "Not masked,Masked" bitfld.long 0x00 18. " MALF_TLP_ERR_MASK ,Malformed TLP mask" "Not masked,Masked" textline " " bitfld.long 0x00 17. " REC_OVERFLOW_ERR_MASK ,Receiver overflow error mask" "Not masked,Masked" bitfld.long 0x00 16. " UNEXP_CMPLT_ERR_MASK ,Unexpected completion mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " CMPLT_ABORT_ERR_MASK ,Completer abort error mask" "Not masked,Masked" bitfld.long 0x00 14. " CMPLT_TIMEOUT_ERR_MASK ,Completion timeout error mask" "Not masked,Masked" textline " " bitfld.long 0x00 13. " FC_PROTOCOL_ERR_MASK ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x00 12. " POIS_TLP_ERR_ERR_MASK ,Poisoned TLP error mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " SURPRISE_DOWN_ERR_MASK ,Surprise down error mask" "Not masked,Masked" bitfld.long 0x00 4. " DL_PROTOCOL_ERR_MASK ,Data link protocol error mask" "Not masked,Masked" line.long 0x04 "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register" bitfld.long 0x04 25. " TLP_PRFX_BLOCKED_ERR_SEVERITY ,TLP prefix blocked error severity" "Not occurred,Occurred" bitfld.long 0x04 24. " ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY ,ATOMIC_EGRESS blocked error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 22. " INTERNAL_ERR_SEVEVERITY ,Internal error severity" "Not occurred,Occurred" bitfld.long 0x04 20. " UNSUPP_REQ_ERR_SEV ,Unsupported request error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 19. " ECRC_ERR_SEVERITY ,ECRC error severity" "Not occurred,Occurred" bitfld.long 0x04 18. " MALF_TLP_ERR_SEV ,Malformed TLP severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 17. " REC_OVRF_ERR_SEVERITY ,Received overflow error severity" "Not occurred,Occurred" bitfld.long 0x04 16. " UNEXP_CMPLT_ERR_SEVERITY ,Unexpected completion error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 15. " CMPLT_ABORT_ERR_SEVERITY ,Completer abort error severity" "Not occurred,Occurred" bitfld.long 0x04 14. " CMPLT_TIMEOUT_ERR_SEVERITY ,Completion timeout error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 13. " FC_PROTOCOL_ERR_SEVERITY ,Flow control protocol error severity" "Not occurred,Occurred" bitfld.long 0x04 12. " POIS_TLP_ERR_ERR_SEVERITY ,Poisoned TLP error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 5. " SUR_DWN_ERR_SEVERITY ,SUR_DWN error severity" "Not occurred,Occurred" bitfld.long 0x04 4. " DL_PROTOCOL_ERR_SEVERITY ,Data link protocol error severity" "Not occurred,Occurred" else group.long 0x08++0x07 line.long 0x00 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register" bitfld.long 0x00 25. " TLP_PRFX_BLOCKED_ERR_MASK ,TLP prefix blocked error mask" "Not masked,Masked" bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_MASK ,AtomicOp blocked mask" "Not masked,Masked" textline " " bitfld.long 0x00 22. " INTERNAL_ERR_MASK ,Internal error mask" "Not masked,Masked" bitfld.long 0x00 20. " UNSUPPORTED_REQ_ERR_MASK ,Unsupported request error mask" "Not masked,Masked" textline " " bitfld.long 0x00 19. " ECRC_ERR_MASK ,ECRC error mask" "Not masked,Masked" bitfld.long 0x00 18. " MALF_TLP_ERR_MASK ,Malformed TLP mask" "Not masked,Masked" textline " " bitfld.long 0x00 17. " REC_OVERFLOW_ERR_MASK ,Receiver overflow error mask" "Not masked,Masked" bitfld.long 0x00 16. " UNEXP_CMPLT_ERR_MASK ,Unexpected completion mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " CMPLT_ABORT_ERR_MASK ,Completer abort error mask" "Not masked,Masked" bitfld.long 0x00 14. " CMPLT_TIMEOUT_ERR_MASK ,Completion timeout error mask" "Not masked,Masked" textline " " bitfld.long 0x00 13. " FC_PROTOCOL_ERR_MASK ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x00 12. " POIS_TLP_ERR_ERR_MASK ,Poisoned TLP error mask" "Not masked,Masked" textline " " rbitfld.long 0x00 5. " SURPRISE_DOWN_ERR_MASK ,Surprise down error mask" "Not masked,Masked" bitfld.long 0x00 4. " DL_PROTOCOL_ERR_MASK ,Data link protocol error mask" "Not masked,Masked" line.long 0x04 "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register" bitfld.long 0x04 25. " TLP_PRFX_BLOCKED_ERR_SEVERITY ,TLP prefix blocked error severity" "Not occurred,Occurred" bitfld.long 0x04 24. " ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY ,ATOMIC_EGRESS blocked error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 22. " INTERNAL_ERR_SEVEVERITY ,Internal error severity" "Not occurred,Occurred" bitfld.long 0x04 20. " UNSUPP_REQ_ERR_SEV ,Unsupported request error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 19. " ECRC_ERR_SEVERITY ,ECRC error severity" "Not occurred,Occurred" bitfld.long 0x04 18. " MALF_TLP_ERR_SEV ,Malformed TLP severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 17. " REC_OVRF_ERR_SEVERITY ,Received overflow error severity" "Not occurred,Occurred" bitfld.long 0x04 16. " UNEXP_CMPLT_ERR_SEVERITY ,Unexpected completion error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 15. " CMPLT_ABORT_ERR_SEVERITY ,Completer abort error severity" "Not occurred,Occurred" bitfld.long 0x04 14. " CMPLT_TIMEOUT_ERR_SEVERITY ,Completion timeout error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 13. " FC_PROTOCOL_ERR_SEVERITY ,Flow control protocol error severity" "Not occurred,Occurred" bitfld.long 0x04 12. " POIS_TLP_ERR_ERR_SEVERITY ,Poisoned TLP error severity" "Not occurred,Occurred" textline " " rbitfld.long 0x04 5. " SUR_DWN_ERR_SEVERITY ,SUR_DWN error severity" "Not occurred,Occurred" bitfld.long 0x04 4. " DL_PROTOCOL_ERR_SEVERITY ,Data link protocol error severity" "Not occurred,Occurred" endif group.long 0x10++0x0B line.long 0x00 "CORR_ERR_STATUS_OFF,Correctable Error Status Register" eventfld.long 0x00 15. " HEADER_LOG_OVERFLOW_STATUS ,Header log overflow error status" "Not occurred,Occurred" eventfld.long 0x00 14. " CORRECTED_INT_ERR_STATUS ,Corrected internal error status" "Not occurred,Occurred" textline " " eventfld.long 0x00 13. " ADV_NON_FATAL_ERR_STATUS ,Advisory non-fatal error status" "Not occurred,Occurred" eventfld.long 0x00 12. " RPL_TIMER_TIMEOUT_STATUS ,Replay timer timeout status" "Not occurred,Occurred" textline " " eventfld.long 0x00 8. " RPL_NO_ROLLOVER_STATUS ,Replay number rollover status" "Not occurred,Occurred" eventfld.long 0x00 7. " BAD_DLLP_STATUS ,Bad DLLP status" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " BAD_TLP_STATUS ,Bad TLP status" "Not occurred,Occurred" eventfld.long 0x00 0. " RX_ERR_STATUS ,Receiver error status" "Not occurred,Occurred" line.long 0x04 "CORR_ERR_MASK_OFF,Correctable Error Mask Register" bitfld.long 0x04 15. " HEADER_LOG_OVERFLOW_MASK ,Header log overflow error mask" "Not occurred,Occurred" bitfld.long 0x04 14. " CORRECTED_INT_ERR_MASK ,Corrected internal error mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " ADVISORY_NON_FATAL_ERR_MASK ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x04 12. " RPL_TIMER_TIMEOUT_MASK ,Replay timer timeout mask" "Not masked,Masked" textline " " bitfld.long 0x04 8. " RPL_NO_ROLLOVER_MASK ,Replay number rollover mask" "Not masked,Masked" bitfld.long 0x04 7. " BAD_DLLP_MASK ,Bad DLLP mask" "Not masked,Masked" textline " " bitfld.long 0x04 6. " BAD_TLP_MASK ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x04 0. " RX_ERR_MASK ,Receiver error mask" "Not masked,Masked" line.long 0x08 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register" rbitfld.long 0x08 10. " MULTIPLE_HEADER_EN ,Multiple header recording enable" "Disabled,Enabled" rbitfld.long 0x08 9. " MULTIPLE_HEADER_CAP ,Multiple header recording capable" "Not capable,Capable" textline " " bitfld.long 0x08 8. " ECRC_CHECK_EN ,ECRC check enable" "Disabled,Enabled" rbitfld.long 0x08 7. " ECRC_CHECK_CAP ,ECRC check capable" "Not capable,Capable" textline " " bitfld.long 0x08 6. " ECRC_GEN_EN ,ECRC generation enable" "Disabled,Enabled" textline " " rbitfld.long 0x08 5. " ECRC_GEN_CAP ,ECRC generation capable" "Not capable,Capable" rbitfld.long 0x08 0.--4. " FIRST_ERR_POINTER ,First error pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1C++0x0F line.long 0x00 "HDR_LOG_0_OFF,Header Log Register 0" hexmask.long.byte 0x00 24.--31. 1. " FIRST_DWORD_FOURTH_BYTE ,Byte 3 of header log register of first 32 bit data word" hexmask.long.byte 0x00 16.--23. 1. " FIRST_DWORD_THIRD_BYTE ,Byte 2 of header log register of first 32 bit data word" textline " " hexmask.long.byte 0x00 8.--15. 1. " FIRST_DWORD_SECOND_BYTE ,Byte 1 of header log register of first 32 bit data word" hexmask.long.byte 0x00 0.--7. 1. " FIRST_DWORD_FIRST_BYTE_BYTE ,Byte 0 of header log register of first 32 bit data word" line.long 0x04 "HDR_LOG_1_OFF,Header Log Register 1" hexmask.long.byte 0x04 24.--31. 1. " SECOND_DWORD_FOURTH_BYTE ,Byte 3 of header log register of second 32 bit data word" hexmask.long.byte 0x04 16.--23. 1. " SECOND_DWORD_THIRD_BYTE ,Byte 2 of header log register of second 32 bit data word" textline " " hexmask.long.byte 0x04 8.--15. 1. " SECOND_DWORD_SECOND_BYTE ,Byte 1 of header log register of second 32 bit data word" hexmask.long.byte 0x04 0.--7. 1. " SECOND_DWORD_FIRST_BYTE ,Byte 0 of header log register of second 32 bit data word" line.long 0x08 "HDR_LOG_2_OFF,Header Log Register 2" hexmask.long.byte 0x08 24.--31. 1. " THIRD_DWORD_FOURTH_BYTE ,Byte 3 of header log register of third 32 bit data word" hexmask.long.byte 0x08 16.--23. 1. " THIRD_DWORD_THIRD_BYTE ,Byte 2 of header log register of third 32 bit data word" textline " " hexmask.long.byte 0x08 8.--15. 1. " THIRD_DWORD_SECOND_BYTE ,Byte 1 of header log register of third 32 bit data word" hexmask.long.byte 0x08 0.--7. 1. " THIRD_DWORD_FIRST_BYTE ,Byte 0 of header log register of third 32 bit data word" line.long 0x0C "HDR_LOG_3_OFF,Header Log Register 3" hexmask.long.byte 0x0C 24.--31. 1. " FOURTH_DWORD_FOURTH_BYTE ,Byte 3 of header log register of fourth 32 bit data word" hexmask.long.byte 0x0C 16.--23. 1. " FOURTH_DWORD_THIRD_BYTE ,Byte 2 of header log register of fourth 32 bit data word" textline " " hexmask.long.byte 0x0C 8.--15. 1. " FOURTH_DWORD_SECOND_BYTE ,Byte 1 of header log register of fourth 32 bit data word" hexmask.long.byte 0x0C 0.--7. 1. " FOURTH_DWORD_FIRST_BYTE ,Byte 0 of header log register of fourth 32 bit data word" group.long 0x2C++0x03 line.long 0x00 "ROOT_ERR_CMD_OFF,Root Error Command Register" bitfld.long 0x00 2. " FATAL_ERR_REPORTING_EN ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NON_FATAL_ERR_REPORTING_EN ,Non-fatal error reporting enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORR_ERR_REPORTING_EN ,Correctable error reporting enable" "Disabled,Enabled" if (((per.l(ad:0x33800000+0x8B4))&0x01)==0x01) group.long 0x30++0x03 line.long 0x00 "ROOT_ERR_STATUS_OFF,Root Error Status Register" bitfld.long 0x00 27.--31. " ADV_ERR_INT_MSG_NUM ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x00 6. " FATAL_ERR_MSG_RX ,Fatal error messages received" "Not received,Received" textline " " eventfld.long 0x00 5. " NON_FATAL_ERR_MSG_RX ,Non-fatal error messages received" "Not received,Received" eventfld.long 0x00 4. " FIRST_UNCORR_FATAL ,First uncorrectable fatal" "Not received,Received" textline " " eventfld.long 0x00 3. " MUL_ERR_FATAL_NON_FATAL_RX ,Multiple fatal or non-fatal errors received" "Not received,Received" eventfld.long 0x00 2. " ERR_FATAL_NON_FATAL_RX ,Fatal or non-fatal errors received" "Not received,Received" textline " " eventfld.long 0x00 1. " MUL_ERR_COR_RX ,Multiple correctable errors received" "Not received,Received" eventfld.long 0x00 0. " ERR_COR_RX ,Correctable error received received" "Not received,Received" else group.long 0x30++0x03 line.long 0x00 "ROOT_ERR_STATUS_OFF,Root Error Status Register" rbitfld.long 0x00 27.--31. " ADV_ERR_INT_MSG_NUM ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x00 6. " FATAL_ERR_MSG_RX ,Fatal error messages received" "Not received,Received" textline " " eventfld.long 0x00 5. " NON_FATAL_ERR_MSG_RX ,Non-fatal error messages received" "Not received,Received" eventfld.long 0x00 4. " FIRST_UNCORR_FATAL ,First uncorrectable fatal" "Not received,Received" textline " " eventfld.long 0x00 3. " MUL_ERR_FATAL_NON_FATAL_RX ,Multiple fatal or non-fatal errors received" "Not received,Received" eventfld.long 0x00 2. " ERR_FATAL_NON_FATAL_RX ,Fatal or non-fatal errors received" "Not received,Received" textline " " eventfld.long 0x00 1. " MUL_ERR_COR_RX ,Multiple correctable errors received" "Not received,Received" eventfld.long 0x00 0. " ERR_COR_RX ,Correctable error received received" "Not received,Received" endif rgroup.long 0x34++0x13 line.long 0x00 "ERR_SRC_ID_OFF,Error Source Identification Register" hexmask.long.word 0x00 16.--31. 1. " ERR_FATAL_NON_FATAL_SOURCE_ID ,Source of fatal/non-fatal error" hexmask.long.word 0x00 0.--15. 1. " ERR_COR_SOURCE_ID ,Source of correctable error" line.long 0x04 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1" hexmask.long.byte 0x04 24.--31. 1. " CFG_TLP_PFX_LOG_1_FOURTH_BYTE ,Byte 3 of error TLP prefix log 1" hexmask.long.byte 0x04 16.--23. 1. " CFG_TLP_PFX_LOG_1_THIRD_BYTE ,Byte 2 of error TLP prefix log 1" textline " " hexmask.long.byte 0x04 8.--15. 1. " CFG_TLP_PFX_LOG_1_SECOND_BYTE ,Byte 1 of error TLP prefix log 1" hexmask.long.byte 0x04 0.--7. 1. " CFG_TLP_PFX_LOG_1_FIRST_BYTE ,Byte 0 of error TLP prefix log 1" line.long 0x08 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2" hexmask.long.byte 0x08 24.--31. 1. " CFG_TLP_PFX_LOG_2_FOURTH_BYTE ,Byte 3 of error TLP prefix log 2" hexmask.long.byte 0x08 16.--23. 1. " CFG_TLP_PFX_LOG_2_THIRD_BYTE ,Byte 2 of error TLP prefix log 2" textline " " hexmask.long.byte 0x08 8.--15. 1. " CFG_TLP_PFX_LOG_2_SECOND_BYTE ,Byte 1 of error TLP prefix log 2" hexmask.long.byte 0x08 0.--7. 1. " CFG_TLP_PFX_LOG_2_FIRST_BYTE ,Byte 0 of error TLP prefix log 2" line.long 0x0C "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3" hexmask.long.byte 0x0C 24.--31. 1. " CFG_TLP_PFX_LOG_3_FOURTH_BYTE ,Byte 3 of error TLP prefix log 3" hexmask.long.byte 0x0C 16.--23. 1. " CFG_TLP_PFX_LOG_3_THIRD_BYTE ,Byte 2 of error TLP prefix log 3" textline " " hexmask.long.byte 0x0C 8.--15. 1. " CFG_TLP_PFX_LOG_3_SECOND_BYTE ,Byte 1 of error TLP prefix log 3" hexmask.long.byte 0x0C 0.--7. 1. " CFG_TLP_PFX_LOG_3_FIRST_BYTE ,Byte 0 of error TLP prefix log 3" line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4" hexmask.long.byte 0x10 24.--31. 1. " CFG_TLP_PFX_LOG_4_FOURTH_BYTE ,Byte 3 of error TLP prefix log 4" hexmask.long.byte 0x10 16.--23. 1. " CFG_TLP_PFX_LOG_4_THIRD_BYTE ,Byte 2 of error TLP prefix log 4" textline " " hexmask.long.byte 0x10 8.--15. 1. " CFG_TLP_PFX_LOG_4_SECOND_BYTE ,Byte 1 of error TLP prefix log 4" hexmask.long.byte 0x10 0.--7. 1. " CFG_TLP_PFX_LOG_4_FIRST_BYTE ,Byte 0 of error TLP prefix log 4" base ad:0x33800000+0x148 sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VERSION ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,L1SUB Extended capability ID" else rgroup.long 0x00++0x03 line.long 0x00 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VER ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " EX_CAP_ID ,Extended capability ID" endif group.long 0x04++0x0B line.long 0x00 "L1SUB_CAPABILITY_REG,L1 Substates Capability Header" bitfld.long 0x00 19.--23. " PWR_ON_VALUE_SUPPORT ,Port T power on value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " PWR_ON_SCALE_SUPPORT ,Port T power on scale" "2us,10us,100us,?..." textline " " hexmask.long.byte 0x00 8.--15. 1. " COME_MODE_SUPPORT ,Port common mode restore time" bitfld.long 0x00 4. " L1_PMSUB_SUPPORT ,L1 PM substates ECN supported" "Not supported,Supported" textline " " bitfld.long 0x00 3. " L1_1_ASPM_SUPPORT ,ASPM L11 supported" "Not supported,Supported" bitfld.long 0x00 2. " L1_2_ASPM_SUPPORT ,ASPM L12 supported" "Not supported,Supported" textline " " bitfld.long 0x00 1. " L1_1_PCI_PM_SUPPORT ,ASPM L11 supported" "Not supported,Supported" bitfld.long 0x00 0. " L1_2_PCI_PM_SUPPORT ,ASPM L12 supported" "Not supported,Supported" line.long 0x04 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register" bitfld.long 0x04 29.--31. " L1_2_TH_SCA ,LTR L12 Threshold Scale" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 16.--25. 1. " L1_2_TH_VAL ,LTR L12 Threshold Value" textline " " hexmask.long.byte 0x04 8.--15. 1. " T_COMMON_MODE ,Common mode restore time" bitfld.long 0x04 3. " L1_1_ASPM_EN ,ASPM L11 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " L1_2_ASPM_EN ,ASPM L12 Enable" "Disabled,Enabled" bitfld.long 0x04 1. " L1_1_PCIPM_EN ,PCI_PM L11 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " L1_2_PCIPM_EN ,PCI_PM L12 Enable" "Disabled,Enabled" line.long 0x08 "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register" bitfld.long 0x08 3.--7. " T_POWER_ON_VALUE ,T power on value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--1. " T_POWER_ON_SCALE ,T power on scale" "2us,10us,100us,?..." else rgroup.long 0x00++0x03 line.long 0x00 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VERSION ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,L1SUB Extended capability ID" group.long 0x04++0x07 line.long 0x00 "LINK_CONTROL3_REG,Link Control 3 Register" bitfld.long 0x00 1. " EQ_REQ_INT_EN ,Link equalization request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PERFORM_EQ ,Perform equalization" "Not performed,Performed" line.long 0x04 "LANE_ERR_STATUS_REG,Lane Error Status Register" eventfld.long 0x04 1. " LANE1_ERR_STATUS ,Lane 1 error status bit" "No error,Error" eventfld.long 0x04 0. " LANE0_ERR_STATUS ,Lane 0 error status bit" "No error,Error" rgroup.long 0x0C++0x03 line.long 0x00 "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register For Lanes 1 And 0" bitfld.long 0x00 28.--30. " USP_RX_PRESET_HINT1 ,Upstream port 8.0GT/s receiver preset hint 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--27. " USP_TX_PRESET1 ,Upstream port 8.0GT/s transmitter preset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--22. " DSP_RX_PRESET_HINT1 ,Downstream port 8.0GT/s receiver preset hint 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " DSP_TX_PRESET1 ,Downstream port 8.0GT/s transmitter preset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--14. " USP_RX_PRESET_HINT0 ,Upstream port 8.0GT/s receiver preset hint 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " USP_TX_PRESET0 ,Upstream port 8.0GT/s transmitter preset 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--6. " DSP_RX_PRESET_HINT0 ,Downstream port 8.0GT/s receiver preset hint 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " DSP_TX_PRESET0 ,Downstream port 8.0GT/s transmitter preset 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") base ad:0x33800000+0x168 if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VERSION ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,L1SUB Extended capability ID" else rgroup.long 0x00++0x03 line.long 0x00 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VER ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " EX_CAP_ID ,Extended capability ID" endif group.long 0x04++0x0B line.long 0x00 "L1SUB_CAPABILITY_REG,L1 Substates Capability Header" bitfld.long 0x00 19.--23. " PWR_ON_VALUE_SUPPORT ,Port T power on value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " PWR_ON_SCALE_SUPPORT ,Port T power on scale" "2us,10us,100us,?..." textline " " hexmask.long.byte 0x00 8.--15. 1. " COME_MODE_SUPPORT ,Port common mode restore time" bitfld.long 0x00 4. " L1_PMSUB_SUPPORT ,L1 PM substates ECN supported" "Not supported,Supported" textline " " bitfld.long 0x00 3. " L1_1_ASPM_SUPPORT ,ASPM L11 supported" "Not supported,Supported" bitfld.long 0x00 2. " L1_2_ASPM_SUPPORT ,ASPM L12 supported" "Not supported,Supported" textline " " bitfld.long 0x00 1. " L1_1_PCI_PM_SUPPORT ,ASPM L11 supported" "Not supported,Supported" bitfld.long 0x00 0. " L1_2_PCI_PM_SUPPORT ,ASPM L12 supported" "Not supported,Supported" line.long 0x04 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register" bitfld.long 0x04 29.--31. " L1_2_TH_SCA ,LTR L12 Threshold Scale" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 16.--25. 1. " L1_2_TH_VAL ,LTR L12 Threshold Value" textline " " hexmask.long.byte 0x04 8.--15. 1. " T_COMMON_MODE ,Common mode restore time" bitfld.long 0x04 3. " L1_1_ASPM_EN ,ASPM L11 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " L1_2_ASPM_EN ,ASPM L12 Enable" "Disabled,Enabled" bitfld.long 0x04 1. " L1_1_PCIPM_EN ,PCI_PM L11 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " L1_2_PCIPM_EN ,PCI_PM L12 Enable" "Disabled,Enabled" line.long 0x08 "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register" bitfld.long 0x08 3.--7. " T_POWER_ON_VALUE ,T power on value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--1. " T_POWER_ON_SCALE ,T power on scale" "2us,10us,100us,?..." endif base ad:0x33800000+0x700 group.long 0x00++0x27 line.long 0x00 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register" hexmask.long.word 0x00 16.--31. 1. " REPLAY_TIME_LIMIT ,Replay timer limit" hexmask.long.word 0x00 0.--15. 1. " ROUND_TRIP_LATENCY_TIME_LIMIT ,Ack latency timer limit" line.long 0x04 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register" line.long 0x08 "PORT_FORCE_OFF,Port Force Link Register" sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") hexmask.long.byte 0x08 24.--31. 1. " CPL_SENT_COUNT ,Low power entrance count" bitfld.long 0x08 16.--21. " LINK_STATE ,Forced LTSSM state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else bitfld.long 0x08 23. " DO_DESKEW_FOR_SRIS ,Use the transitions from TS2 to logical idle symbol" "0,1" bitfld.long 0x08 16.--21. " LINK_STATE ,Forced LTSSM state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif textline " " bitfld.long 0x08 15. " FORCE_EN ,Force link" "Disabled,Enabled" bitfld.long 0x08 8.--11. " FORCED_LTSSM ,Forced link command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x08 0.--7. 1. " LINK_NUM ,Link number" line.long 0x0C "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register" bitfld.long 0x0C 30. " ENTER_ASPM ,ASPM L1 entry control" "Not entered,Entered" bitfld.long 0x0C 27.--29. " L1_ENTRANCE_LAT ,L1 entrance latency" "1 us,2 us,4 us,8 us,16 us,32 us,64 us,64 us" textline " " bitfld.long 0x0C 24.--26. " L0S_ENTRANCE_LAT ,L0s entrance latency" "1 us,2 us,3 us,4 us,5 us,6 us,7 us,7 us" hexmask.long.byte 0x0C 16.--23. 1. " COMMON_CLK_N_FTS ,Common clock N_FTS" textline " " hexmask.long.byte 0x0C 8.--15. 1. " ACK_N_FTS ,Number of fast training sequence" hexmask.long.byte 0x0C 0.--7. 1. " ACK_FREQ ,Ack frequency" line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register" bitfld.long 0x10 16.--21. " LINK_CAPABLE ,Link mode enable" ",x1,,x2,,,,x4,,,,,,,,x8,,,,,,,,,,,,,,,,x16,?..." bitfld.long 0x10 7. " FAST_LINK_MODE ,Fast link mode" "No effect,Internal timers in fast mode" textline " " bitfld.long 0x10 5. " DLL_LINK_EN ,DLL link enable" "Disabled,Enabled" bitfld.long 0x10 3. " RST_ASSERT ,Reset assert" "No reset,Reset" textline " " bitfld.long 0x10 2. " LP_EN ,Loopback enable" "No reset,Reset" bitfld.long 0x10 1. " SCRAMBLE_DISABLE ,Scramble disable" "Enabled,Disabled" textline " " bitfld.long 0x10 0. " VENDOR_SPECIFIC_DLLP_REQ ,Vendor specific DLLP request" "Not requested,Requested" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x14 31. " DISABLE_LANE_TO_LANE_DESKEW ,Disable lane-to-lane deskew" "Enabled,Disabled" bitfld.long 0x14 27.--30. " IMPLEMENT_NUM_LANES ,Number of lanes" "1 lane,2 lane,,4 lane,,,,8 lane,,,,,,,,16 lane" textline " " bitfld.long 0x14 26. " GEN34_ELASTIC_BUFFER_MODE ,Select elasticity buffer operating mode in ge3 or gen4" "Half full,Empty" bitfld.long 0x14 25. " ACK_NAK_DISABLE ,Ack/nak disable" "Enabled,Disabled" else bitfld.long 0x14 31. " DISABLE_LANE_TO_LANE_DESKEW ,Disable lane-to-lane deskew" "Enabled,Disabled" bitfld.long 0x14 25. " ACK_NAK_DISABLE ,Ack/nak disable" "Enabled,Disabled" endif textline " " bitfld.long 0x14 24. " FLOW_CTRL_DISABLE ,Flow control disable" "Enabled,Disabled" hexmask.long.tbyte 0x14 0.--23. 1. " INSERT_LANE_SKEW ,Insert lane skew for transmit" line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register" bitfld.long 0x18 29.--30. " FAST_LINK_SCALING_FACTOR ,Fast link timer scaling factor" "1024,256,64,16" bitfld.long 0x18 19.--23. " TIMER_MOD_ACK_NAK ,Ack latency timer modifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x18 14.--18. " TIMER_MOD_REPLAY_TIMER ,Replay timer limit modifier" "Not modified,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x18 0.--7. 1. " MAX_FUNC_NUM ,Maximum function number" line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register" bitfld.long 0x1C 31. " CX_FLT_MASK_RC_CFG_DISCARD ,RC CFG discard mask" "Not masked,Masked" bitfld.long 0x1C 30. " CX_FLT_MASK_RC_IO_DISCARD ,RC IO discard mask" "Not masked,Masked" textline " " bitfld.long 0x1C 29. " CX_FLT_MASK_MSG_DROP ,Drop MSG TLP mask" "Not masked,Masked" bitfld.long 0x1C 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,Mask discarding completions with ECRC errors" "Not masked,Masked" textline " " bitfld.long 0x1C 27. " CX_FLT_MASK_ECRC_DISCARD ,Mask discarding TLPs with ECRC errors" "Not masked,Masked" bitfld.long 0x1C 26. " CX_FLT_MASK_CPL_LEN_MATCH ,Mask length match for completions" "Not masked,Masked" textline " " bitfld.long 0x1C 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,Mask attribute match for completions" "Not masked,Masked" bitfld.long 0x1C 24. " CX_FLT_MASK_CPL_TC_MATCH ,Mask traffic class match for completions" "Not masked,Masked" textline " " bitfld.long 0x1C 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,Mask function match for completions" "Not masked,Masked" bitfld.long 0x1C 22. " CX_FLT_MASK_CPL_REQID_MATCH ,Mask request ID match for completions" "Not masked,Masked" textline " " bitfld.long 0x1C 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,Mask tag error rules for completions" "Not masked,Masked" bitfld.long 0x1C 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,Mask treating locked read TLPs as UR for EP" "Not masked,Masked" textline " " bitfld.long 0x1C 19. " CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR ,Mask treating CFG type1 TLPs as UR for EP" "Not masked,Masked" bitfld.long 0x1C 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,Mask treating out-of-bar TLPs as UR" "Not masked,Masked" textline " " bitfld.long 0x1C 17. " CX_FLT_MASK_UR_POIS ,Mask treating poisoned TLPs as UR" "Not masked,Masked" bitfld.long 0x1C 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,Mask treating function mismatched TLPs as UR" "Not masked,Masked" textline " " sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") hexmask.long.word 0x1C 0.--10. 1. " SKP_INT_VAL ,SKP interval value" else bitfld.long 0x1C 15. " DISABLE_FCWD_TIMER ,Disable FX watchdog timer" "Enabled,Disabled" hexmask.long.word 0x1C 0.--10. 1. " SKP_INT_VAL ,SKP interval value" endif line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register" bitfld.long 0x20 7. " CX_FLT_MASK_PRS_DROP ,CX FLT mask PRS drop" "Not dropped,Dropped" bitfld.long 0x20 6. " CX_FLT_UNMASK_TD ,CX_FLT_UNMASK_TD" "Disabled,Enabled" textline " " bitfld.long 0x20 5. " CX_FLT_UNMASK_UR_POIS_TRGT0 ,CX_FLT_UNMASK_UR_POIS_TRGT0" "Disabled,Enabled" bitfld.long 0x20 4. " CX_FLT_MASK_LN_VENMSG1_DROP ,CX_FLT_MASK_LN_VENMSG1_DROP" "Not dropped,Dropped" textline " " bitfld.long 0x20 3. " CX_FLT_MASK_HANDLE_FLUSH ,Core filter enable" "Disabled,Enabled" bitfld.long 0x20 2. " CX_FLT_MASK_DABORT_4UCPL ,DLLP abort for unexpected completion enable" "Enabled,Disabled" textline " " bitfld.long 0x20 1. " CX_FLT_MASK_VENMSG1_DROP ,Vendor MSG Type 1 dropped silently" "Not dropped,Dropped" bitfld.long 0x20 0. " CX_FLT_MASK_VENMSG0_DROP ,Vendor MSG Type 0 dropped with UR error reporting" "Not dropped,Dropped" line.long 0x24 "AMBAMODNPSC,AMBA Multiple Outbound Decomposed NP SubRequests Control Register" bitfld.long 0x24 0. " OB_RD_SPLIT_BURST_EN ,Enable AMBA multiple outbound decomposed NP SubRequests" "Disabled,Enabled" rgroup.long 0x28++0x13 line.long 0x00 "PL_DEBUG0_OFF,Debug Register 0" line.long 0x04 "PL_DEBUG1_OFF,Debug Register 1" line.long 0x08 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.byte 0x08 12.--19. 1. " TX_P_HEADER_FC_CREDIT ,Transmit posted header FC credits" hexmask.long.word 0x08 0.--11. 1. " TX_P_DATA_FC_CREDIT ,Transmit posted data FC credits" line.long 0x0C "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status Register" hexmask.long.byte 0x0C 12.--19. 1. " TX_NP_HEADER_FC_CREDIT ,Transmit non-posted header FC credits" hexmask.long.word 0x0C 0.--11. 1. " TX_NP_DATA_FC_CREDIT ,Transmit non-posted data FC credits" line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status Register" hexmask.long.byte 0x10 12.--19. 1. " TX_CPL_HEADER_FC_CREDIT ,Transmit completion header FC credits" hexmask.long.word 0x10 0.--11. 1. " TX_CPL_DATA_FC_CREDIT ,Transmit completion data FC credits" group.long 0x3C++0x03 line.long 0x00 "QUEUE_STATUS_OFF,Queue Status Register" bitfld.long 0x00 31. " TIMER_MOD_FLOW_CONTROL_EN ,FC latency timer override enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--28. 1. " TIMER_MOD_FLOW_CONTROL ,FC latency timer override value" textline " " sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") eventfld.long 0x00 15. " RX_SERIALIZATION_Q_READ_ERR ,Received serialization read error" "No error,Error" eventfld.long 0x00 14. " RX_SERIALIZATION_Q_WRITE_ERR ,Received serialization queue write error" "No error,Error" textline " " rbitfld.long 0x00 13. " RX_SERIALIZATION_Q_NON_EMPTY ,Received serialization queue non empty" "Empty,Not empty" eventfld.long 0x00 3. " RX_QUEUE_OVERFLOW ,Received Credit queue overflow" "Not occurred,Occurred" textline " " endif rbitfld.long 0x00 2. " RX_QUEUE_NON_EMPTY ,Received queue not empty" "Not received,Received" rbitfld.long 0x00 1. " TX_RETRY_BUFFER_NE ,Transmit retry buffer not empty" "Not received,Received" textline " " rbitfld.long 0x00 0. " RX_TLP_FC_CRED_NON_RETURN ,Received TLP FC credits not returned" "Not received,Received" rgroup.long 0x40++0x07 line.long 0x00 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x00 24.--31. 1. " WRR_WEIGHT_VC_3 ,WRR weight for VC3" hexmask.long.byte 0x00 16.--23. 1. " WRR_WEIGHT_VC_2 ,WRR weight for VC2" textline " " hexmask.long.byte 0x00 8.--15. 1. " WRR_WEIGHT_VC_1 ,WRR weight for VC1" hexmask.long.byte 0x00 0.--7. 1. " WRR_WEIGHT_VC_0 ,WRR weight for VC0" line.long 0x04 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x04 24.--31. 1. " WRR_WEIGHT_VC_7 ,WRR weight for VC7" hexmask.long.byte 0x04 16.--23. 1. " WRR_WEIGHT_VC_6 ,WRR weight for VC6" textline " " hexmask.long.byte 0x04 8.--15. 1. " WRR_WEIGHT_VC_5 ,WRR weight for VC5" hexmask.long.byte 0x04 0.--7. 1. " WRR_WEIGHT_VC_4 ,WRR weight for VC4" group.long 0x48++0x0B line.long 0x00 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control" bitfld.long 0x00 31. " VC_ORDERING_RX_Q ,VC ordering for receive queues" "Round-robin,Strict" bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC0 ,TLP type ordering for VC0" "Strict,PCIe" textline " " sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 26.--27. " VC0_P_DATA_SCALE ,VC0 scale posted data credits" "0,1,2,3" bitfld.long 0x00 24.--25. " VC0_P_HDR_SCALE ,VC0 scale posted header credits" "0,1,2,3" textline " " endif hexmask.long.byte 0x00 12.--19. 1. " VC0_P_HEADER_CRED ,VC0 posted header credits" hexmask.long.word 0x00 0.--11. 1. " VC0_P_DATA_CRED ,VC0 posted data credits" line.long 0x04 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x04 26.--27. " VC0_NP_DATA_SCALE ,VC0 scale non-posted data credits" "0,1,2,3" bitfld.long 0x04 24.--25. " VC0_NP_HDR_SCALE ,VC0 scale non-posted header credits" "0,1,2,3" textline " " endif hexmask.long.byte 0x04 12.--19. 1. " VC0_NP_HEADER_CRED ,VC0 non-posted header credits" hexmask.long.word 0x04 0.--11. 1. " VC0_NP_DATA_CRED ,VC0 non-posted data credits" line.long 0x08 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x08 26.--27. " VC0_CPL_DATA_SCALE ,VC0 scale CPL data credits" "0,1,2,3" bitfld.long 0x08 24.--25. " VC0_CPL_HDR_SCALE ,VC0 scale CPL header credits" "0,1,2,3" textline " " endif hexmask.long.byte 0x08 12.--19. 1. " VC0_CPL_HEADER_CRED ,VC0 completion header credits" hexmask.long.word 0x08 0.--11. 1. " VC0_CPL_DATA_CRED ,VC0 completion data credits" group.long 0x10C++0x03 line.long 0x00 "GEN2_CTRL_OFF,Link Width and Speed Change Control Register" bitfld.long 0x00 21. " GEN1_EI_INFERENCE ,Electrical idle inference mode at Gen1 rate" "RxElecIdle,RxValid" bitfld.long 0x00 20. " SEL_DEEMPHASIS ,Select de-emphasis" "-6 dB,-3.5 dB" textline " " bitfld.long 0x00 19. " CONFIG_TX_COMP_RX ,Config Tx compliance receive bit" "No effect,LTSSM is signaled to transmit" bitfld.long 0x00 18. " CONFIG_PHY_TX_CHANGE ,Config PHY Tx swing" "Full,Low" textline " " bitfld.long 0x00 17. " DIRECT_SPEED_CHANGE ,Directed speed change" "No effect,Speed change to Gen2 or Gen3 initiated" bitfld.long 0x00 16. " AUTO_LANE_FLIP_CTRL_EN ,Enable auto flipping of the lanes" "Disabled,Enabled" textline " " bitfld.long 0x00 13.--15. " PRE_DET_LANE ,Predetermined lane for auto flip" "Phy L0,Phy L1,Phy L3,Phy L7,Phy L15,?..." bitfld.long 0x00 8.--12. " NUM_OF_LANES ,Predetermined number of lanes" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x00 0.--7. 1. " FAST_TRAIN_SEQ ,Number of fast training sequences" rgroup.long 0x110++0x03 line.long 0x00 "PHY_STATUS_OFF,PHY Status Register" group.long 0x114++0x03 line.long 0x00 "PHY_CONTROL_OFF,PHY Control Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") group.long 0x11C++0x03 line.long 0x00 "TRGT_MAP_CTRL_OFF,Programmable target map control register" bitfld.long 0x00 16.--20. " TARGET_MAP_INDEX ,The number of the PF function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " TARGET_MAP_ROM ,Target values for the ROM on the PF function" "0,1" textline " " bitfld.long 0x00 0.--5. " TARGET_MAP_PF ,Target values for each BAR on the PF function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x120++0x07 line.long 0x00 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register" line.long 0x04 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register" group.long 0x128++0x0B line.long 0x00 "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_0_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_0_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_0_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x134++0x0B line.long 0x00 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_1_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_1_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_1_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x140++0x0B line.long 0x00 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_2_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_2_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_2_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x14C++0x0B line.long 0x00 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_3_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_3_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_3_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x158++0x0B line.long 0x00 "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_4_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_4_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_4_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x164++0x0B line.long 0x00 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_5_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_5_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_5_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x170++0x0B line.long 0x00 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_6_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_6_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_6_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x17C++0x0B line.long 0x00 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_7_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_7_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_7_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x188++0x03 line.long 0x00 "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") group.long 0x18C++0x03 line.long 0x00 "CLOCK_GATING_CTRL_OFF,RADM clock gating enable control register" bitfld.long 0x00 0. " RADM_CLK_GAITNG_EN ,Enable Radm clock gating features" "Disabled,Enabled" group.long 0x1B4++0x03 line.long 0x00 "ORDER_RULE_CTRL_OFF,Order Rule Control Register" hexmask.long.byte 0x00 8.--15. 1. " CPL_PASS_P ,Completion passing posted ordering rule control" hexmask.long.byte 0x00 0.--7. 1. " NP_PASS_P ,Non-posted passing posted ordering rule control" else group.long 0x190++0x03 line.long 0x00 "GEN3_RELATED_OFF,Gen3 Control Register" bitfld.long 0x00 23. " GEN3_EQ_INVREQ_EVAL_DIFF_DIS ,RxEqEval different time assertion disable" "Enabled,Disabled" bitfld.long 0x00 18. " GEN3_DC_BALANCE_DISABLE ,DC balance disable" "Enabled,Disabled" textline " " bitfld.long 0x00 17. " GEN3_DLLP_XMT_DELAY_DISABLE ,DLLP transmission delay disable" "Enabled,Disabled" bitfld.long 0x00 16. " GEN3_EQUALIZATION_DISABLE ,Equalization disable" "Enabled,Disabled" textline " " bitfld.long 0x00 13. " RXEQ_RGRDLESS_RXTS ,RxEqEval adaptation and evaluation" "After 1us,After 500ns" bitfld.long 0x00 12. " RXEQ_PH01_EN ,Rx equalization phase 0/1 hold enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " EQ_REDO ,Equalization redo disable" "Enabled,Disabled" bitfld.long 0x00 10. " EQ_EIEOS_CNT ,Equalization EIEOS count reset disable" "Enabled,Disabled" textline " " bitfld.long 0x00 9. " EQ_PHASE_2_3 ,Equalization phase 2/3 disable" "Enabled,Disabled" bitfld.long 0x00 8. " DISABLE_SCRAMBLER_GEN_3 ,Disable scrambler for gen3 and gen 4 data rate" "Enabled,Disabled" textline " " bitfld.long 0x00 0. " GEN3_ZRXDC_NONCOMPL ,Gen3 receiver impedance ZRX-DC not compliant" "Not compliant,Compliant" group.long 0x1A8++0x03 line.long 0x00 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register" bitfld.long 0x00 26. " GEN3_RSC_EIEOS_PSET_MAP ,Request core to send back-to-back EIEOS in RcvrLock state" "Not requested,Requested" bitfld.long 0x00 24. " GEN3_EQ_FOM_INC_INITIAL_EVAL ,Include initial FOM" "Not included,Included" textline " " hexmask.long.word 0x00 8.--23. 1. " GEN3_EQ_PSET_REQ_VEC ,Preset request vector" bitfld.long 0x00 5. " GEN3_EQ_EVAL_2MS_DISABLE ,Phase2_3 2ms timeout disable" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " GEN3_EQ_PHASE23_EXIT_MODE ,Behavior after 24ms timeout" "Recovery speed,Recovery equalization" bitfld.long 0x00 0.--3. " GEN3_EQ_FB_MODE ,Feedback mode" "Direction change,Figure out merit,?..." group.long 0x1B4++0x03 line.long 0x00 "ORDER_RULE_CTRL_OFF,Order Rule Control Register" hexmask.long.byte 0x00 8.--15. 1. " CPL_PASS_P ,Completion passing posted ordering rule control" hexmask.long.byte 0x00 0.--7. 1. " NP_PASS_P ,Non-posted passing posted ordering rule control" endif width 40. textline " " group.long 0x1B8++0x23 line.long 0x00 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register" bitfld.long 0x00 31. " PIPE_LOOPBACK ,PIPE loopback enable" "Disabled,Enabled" line.long 0x04 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x04 5. " ARI_DEVICE_NUMBER ,This field enables use of the device ID" "0,1" bitfld.long 0x04 3. " SIMPLIFIED_REPLAY_TIMER ,Enables Simplified Replay Timer" "24.000 to 31.000 Symbol Times,80.000 to 100.000 Symbol Times" textline " " bitfld.long 0x04 2. " UR_CA_MASK_4_TRGT1 ,UR CA mask 4 target 1" "No effect,Suppressed" bitfld.long 0x04 1. " DEFAULT_TARGET ,Default target" "Drop,Forward" textline " " bitfld.long 0x04 0. " DBI_RO_WR_EN ,Write to RO registers using DBI enable" "Disabled,Enabled" else bitfld.long 0x04 0. " DBI_RO_WR_EN ,Write to RO registers using DBI enable" "Disabled,Enabled" endif line.long 0x08 "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register" bitfld.long 0x08 7. " UPCONFIGURE_SUPPORT ,Upconfigure support" "0,1" bitfld.long 0x08 6. " DIRECT_LINK_WIDTH_CHANGE ,Directed link width change" "0,1" textline " " bitfld.long 0x08 0.--5. " TARGET_LINK_WIDTH ,Target link width" "No start,x1,x2,,x4,,,,x8,,,,,,,,x16,,,,,,,,,,,,,,,,x32,?..." line.long 0x0C "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x0C 10. " L1_CLK_SEL ,L1 clock control bit" "Requested,Not requested" bitfld.long 0x0C 9. " L1_NOWAIT_P1 ,L1 entry control bit" "Wait,No wait" textline " " bitfld.long 0x0C 8. " L1SUB_EXIT_MODE ,L1 exit control using phy_mac_pclkack_n" "Wait,Exit" hexmask.long.byte 0x0C 0.--6. 1. " RXSTANDBY_CONTROL ,RxStandby Control" else bitfld.long 0x0C 9. " L1_NOWAIT_P1 ,L1 entry control bit" "Wait,No wait" textline " " bitfld.long 0x0C 8. " L1SUB_EXIT_MODE ,L1 exit control using phy_mac_pclkack_n" "Wait,Exit" hexmask.long.byte 0x0C 0.--6. 1. " RXSTANDBY_CONTROL ,RxStandby Control" endif line.long 0x10 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control Register" eventfld.long 0x10 31. " DELETE_EN ,This is a one shot bit" "Not triggered,Triggered" hexmask.long 0x10 0.--30. 1. " LOOK_UP_ID ,This number selects one entry to delete of the TRGT_CPL_LUT" line.long 0x14 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register" bitfld.long 0x14 0. " AUTO_FLUSH_EN ,Enables automatic flushing" "Disabled,Enabled" line.long 0x18 "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register" bitfld.long 0x18 15. " AMBA_ERROR_RESPONSE_MAP[UR] ,AXI slave response error map - unsupported request" "DECERR,SLVERR" textline " " bitfld.long 0x18 14. " AMBA_ERROR_RESPONSE_MAP[CRS] ,AXI slave response error map - configuration retry status" "DECERR,SLVERR" bitfld.long 0x18 13. " AMBA_ERROR_RESPONSE_MAP[CA] ,AXI slave response error map - completer abort" "DECERR,SLVERR" textline " " bitfld.long 0x18 10. " AMBA_ERROR_RESPONSE_MAP[CT] ,AXI slave response error map - complete timeout" "DECERR,SLVERR" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x18 3.--4. " AMBA_ERROR_RESPONSE_CRS ,CRS slave error response mapping" "OKAY,OKAY with all FFFF_FFFF data,OKAY with FFFF_0001 data to vendor ID request adn FFFF_FFFF for others,DECERR/SLVERR" textline " " bitfld.long 0x18 2. " AMBA_ERROR_RESPONSE_VENDORID ,Vendor ID Non-existent slave error response mapping" "OKAY,ERROR AXI" bitfld.long 0x18 0. " AMBA_ERROR_RESPONSE_GLOBAL ,Global slave error response mapping" "OKAY,ERROR for normal link accesses" else bitfld.long 0x18 2. " AMBA_ERROR_RESPONSE_VEN_ID ,Vendor ID Non-existent slave error response mapping" "OKAY,ERROR AXI" textline " " bitfld.long 0x18 0. " AMBA_ERROR_RESPONSE_GLOBAL ,Global slave error response mapping" "OKAY,ERROR" endif line.long 0x1C "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register" bitfld.long 0x1C 8. " LINK_TIMEOUT_ENABLE_DFL ,Disable flush" "No effect,Enabled" hexmask.long.byte 0x1C 0.--7. 1. " LINK_TIMEOUT_PERIOD_DFL ,Timeout value (ms)" line.long 0x20 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x20 7. " AX_MSTR_ZEROLREAD_FW ,AXI master zero length read forward to he application" "DW PCIe AXI bridge master,Forward to the application" bitfld.long 0x20 3.--4. " AX_MSTR_ORDR_P_EVENT_SEL ,AXI master posted ordering event selector" "B'last,AW'last,W'last,?..." textline " " bitfld.long 0x20 1. " AX_SNP_EN ,AXI Serialize Non-Posted Requests Enable" "Disabled,Enabled" else bitfld.long 0x20 3.--4. " AX_MSTR_ORDR_P_EVENT_SEL ,AXI master posted ordering event selector" "B'last,AW'last,W'last,?..." bitfld.long 0x20 2. " AX_IB_CPL_PASS_P ,AXI inbound CPL must not pass P rule disable" "Enabled,Disabled" textline " " bitfld.long 0x20 1. " AX_SNP_EN ,AXI Serialize Non-Posted Requests Enable" "Disabled,Enabled" bitfld.long 0x20 0. " AX_MSTR_NP_PASS_P ,AXI master NP can pass P" "Disabled,Enabled" endif group.long 0x1E0++0x0B line.long 0x00 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BD_L_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VAL ,Memory type for the lower and upper parts of the address space select" "L:Periph UP:Mem,L:Mem UP:Periph" line.long 0x04 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" line.long 0x08 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" bitfld.long 0x08 27.--30. " CFG_MSTR_AWCACHE_VAL ,Master write CACHE signal value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 19.--22. " CFG_MSTR_ARCACHE_VAL ,Master read CACHE signal value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 11.--14. " CFG_MSTR_AWCACHE_MODE ,Master write CACHE signal behavior" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 3.--6. " CFG_MSTR_ARCACHE_MODE ,Master read CACHE signal behavior" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1F0++0x07 line.long 0x00 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to" hexmask.long.tbyte 0x00 12.--31. 1. " CFG_AXIMSTR_MSG_ADDR_LOW ,Lower 20 bits of the programmable AXI address for Messages" line.long 0x04 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") rgroup.long 0x1F8++0x07 line.long 0x00 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number" line.long 0x04 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type" group.long 0x440++0x07 line.long 0x00 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register" hexmask.long.word 0x00 0.--9. 1. " AUX_CLK_FREQ ,The aux_clk frequency in MHz" line.long 0x04 "L1_SUBSTATES_OFF,L1 Substates Timing Register" bitfld.long 0x04 6.--7. " L1SUB_T_PCLKACK ,Max delay" "0,1 us,2 us,3 us" bitfld.long 0x04 2.--5. " L1SUB_T_L1_2 ,Duration of L1.2" "0,1 us,2 us,3 us,4 us,5 us,6 us,7 us,8 us,9 us,10 us,11 us,12 us,13 us,14 us,15 us" textline " " bitfld.long 0x04 0.--1. " L1SUB_T_POWER_OFF ,Duration of L1.2.Entry" "0,1 us,2 us,3 us" endif sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") base ad:0x33800000+0x80000000 else base ad:0x33800000+0x904 group.long (0x00-0x04)++0x03 line.long 0x00 "IATU_VIEWPORT_OFF,IATU Index Register" bitfld.long 0x00 31. " REGION_DIR ,Region direction" "Outbound,Inbound" bitfld.long 0x00 0.--2. " REGIOX_INDEX ,Region index" "0,1,2,3,4,5,6,7" endif sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") group.long 0x0++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Maximum ATU region size - 4GB,Determined by CX_ATU_MAX_REGION_SIZE" textline " " bitfld.long 0x00 11. " IDO ,IDO" "0,1" bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" textline " " bitfld.long 0x00 8. " TD ,TD" "0,1" bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" textline " " bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Disabled,Enabled" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "0,1" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x04 8.--15. 1. " TAG ,TAG" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,iATU Upper Target Address Register" group.long (0x0+0x100)++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU Region size" "0,1" textline " " bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" textline " " bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID match mode,BAR/Accept/Vendor ID match mode (MSG/MSGD)" textline " " bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" textline " " bitfld.long 0x04 27. " Disabled ,Fuzzy type match mode" "Disabled,Enabled" bitfld.long 0x04 24.--25. " RESPONSE_CODE ,Response code" "Normal RADM filter response,Unsupported request,Completer abort," textline " " bitfld.long 0x04 23. " SINGLE_ADDR_LOC_TRANS_EN ,Single address location translate enable" "Disabled,Enabled" bitfld.long 0x04 21. " MSG_CODE_MATCH_EN ,message code match enable" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 16. " TAG_MATCH_EN ,ATTR match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " TD_MATCH_EN ,TD match enable" "Disabled,Enabled" bitfld.long 0x04 14. " TC_MATCH_EN ,TC match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " MSG_TYPE_MATCH_MODE ,Massage type match mode" "Disabled,Enabled" bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM," textline " " hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_0,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,iATU Upper Target Address Register" group.long 0x200++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_1,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Maximum ATU region size - 4GB,Determined by CX_ATU_MAX_REGION_SIZE" textline " " bitfld.long 0x00 11. " IDO ,IDO" "0,1" bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" textline " " bitfld.long 0x00 8. " TD ,TD" "0,1" bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_1,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" textline " " bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Disabled,Enabled" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "0,1" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x04 8.--15. 1. " TAG ,TAG" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_1,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1,iATU Upper Target Address Register" group.long (0x200+0x100)++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_1,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU Region size" "0,1" textline " " bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" textline " " bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_1,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID match mode,BAR/Accept/Vendor ID match mode (MSG/MSGD)" textline " " bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" textline " " bitfld.long 0x04 27. " Disabled ,Fuzzy type match mode" "Disabled,Enabled" bitfld.long 0x04 24.--25. " RESPONSE_CODE ,Response code" "Normal RADM filter response,Unsupported request,Completer abort," textline " " bitfld.long 0x04 23. " SINGLE_ADDR_LOC_TRANS_EN ,Single address location translate enable" "Disabled,Enabled" bitfld.long 0x04 21. " MSG_CODE_MATCH_EN ,message code match enable" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 16. " TAG_MATCH_EN ,ATTR match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " TD_MATCH_EN ,TD match enable" "Disabled,Enabled" bitfld.long 0x04 14. " TC_MATCH_EN ,TC match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " MSG_TYPE_MATCH_MODE ,Massage type match mode" "Disabled,Enabled" bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM," textline " " hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_1,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_1,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_1,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_1,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1,iATU Upper Target Address Register" group.long 0x400++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_2,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Maximum ATU region size - 4GB,Determined by CX_ATU_MAX_REGION_SIZE" textline " " bitfld.long 0x00 11. " IDO ,IDO" "0,1" bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" textline " " bitfld.long 0x00 8. " TD ,TD" "0,1" bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_2,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" textline " " bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Disabled,Enabled" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "0,1" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x04 8.--15. 1. " TAG ,TAG" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_2,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2,iATU Upper Target Address Register" group.long (0x400+0x100)++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_2,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU Region size" "0,1" textline " " bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" textline " " bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_2,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID match mode,BAR/Accept/Vendor ID match mode (MSG/MSGD)" textline " " bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" textline " " bitfld.long 0x04 27. " Disabled ,Fuzzy type match mode" "Disabled,Enabled" bitfld.long 0x04 24.--25. " RESPONSE_CODE ,Response code" "Normal RADM filter response,Unsupported request,Completer abort," textline " " bitfld.long 0x04 23. " SINGLE_ADDR_LOC_TRANS_EN ,Single address location translate enable" "Disabled,Enabled" bitfld.long 0x04 21. " MSG_CODE_MATCH_EN ,message code match enable" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 16. " TAG_MATCH_EN ,ATTR match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " TD_MATCH_EN ,TD match enable" "Disabled,Enabled" bitfld.long 0x04 14. " TC_MATCH_EN ,TC match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " MSG_TYPE_MATCH_MODE ,Massage type match mode" "Disabled,Enabled" bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM," textline " " hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_2,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_2,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_2,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_2,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2,iATU Upper Target Address Register" group.long 0x600++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_3,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Maximum ATU region size - 4GB,Determined by CX_ATU_MAX_REGION_SIZE" textline " " bitfld.long 0x00 11. " IDO ,IDO" "0,1" bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" textline " " bitfld.long 0x00 8. " TD ,TD" "0,1" bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_3,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" textline " " bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Disabled,Enabled" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "0,1" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x04 8.--15. 1. " TAG ,TAG" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_3,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3,iATU Upper Target Address Register" group.long (0x600+0x100)++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_3,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU Region size" "0,1" textline " " bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" textline " " bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_3,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID match mode,BAR/Accept/Vendor ID match mode (MSG/MSGD)" textline " " bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" textline " " bitfld.long 0x04 27. " Disabled ,Fuzzy type match mode" "Disabled,Enabled" bitfld.long 0x04 24.--25. " RESPONSE_CODE ,Response code" "Normal RADM filter response,Unsupported request,Completer abort," textline " " bitfld.long 0x04 23. " SINGLE_ADDR_LOC_TRANS_EN ,Single address location translate enable" "Disabled,Enabled" bitfld.long 0x04 21. " MSG_CODE_MATCH_EN ,message code match enable" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 16. " TAG_MATCH_EN ,ATTR match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " TD_MATCH_EN ,TD match enable" "Disabled,Enabled" bitfld.long 0x04 14. " TC_MATCH_EN ,TC match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " MSG_TYPE_MATCH_MODE ,Massage type match mode" "Disabled,Enabled" bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM," textline " " hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_3,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_3,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_3,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_3,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3,iATU Upper Target Address Register" else group.long 0x00++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " AT ,AT" "0,1,2,3" textline " " bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "4GB,CX_ATU_MAX_REGION_SIZE" bitfld.long 0x00 11. " IDO ,IDO" "0,1" textline " " bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" textline " " bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" textline " " bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Disabled,Enabled" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "0,1" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x04 8.--15. 1. " TAG ,TAG" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND,IATU Lower Base Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--11. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$2,IATU Limit Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--11. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$2,iATU Upper Target Address Register" endif sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") base ad:0x33800000+0x80080000 else base ad:0x33800000+0x970 endif group.long 0x00++0x03 line.long 0x00 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface" bitfld.long 0x00 9.--11. " RDBUFF_TRGT_WEIGHT ,DMA read channel MWr requests" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " RD_CTRL_TRGT_WEIGHT ,DMA Read channel MRd requests" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--5. " WR_CTRL_TRGT_WEIGHT ,DMA Write channel MRd requests" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " RTRGT1_WEIGHT ,Non-DMA Rx Requests" "0,1,2,3,4,5,6,7" group.long 0x08++0x0B line.long 0x00 "DMA_CTRL_OFF,DMA Number of Channels Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 25. " DIS_C2W_CAC_HE_RD ,Disable DMA read Channels" "Enabled,Disabled" bitfld.long 0x00 24. " DIS_C2W_CAC_HE_WR ,Disable DMA write Channels" "Enabled,Disabled" textline " " bitfld.long 0x00 16.--19. " NUM_DMA_RD_CHAN ,Number of read channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NUM_DMA_WR_CHAN ,Number of write channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x00 16.--19. " NUM_DMA_RD_CHAN ,Number of read channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NUM_DMA_WR_CHAN ,Number of write channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.long 0x04 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register" bitfld.long 0x04 0. " DMA_WRITE_ENGINE ,DMA write engine enable" "Disabled,Enabled" line.long 0x08 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register" bitfld.long 0x08 31. " WR_STOP ,Stop" "Not stopped,Stopped" bitfld.long 0x08 0.--2. " WR_DOORBELL_NUM ,Doorbell number" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" group.long 0x18++0x07 line.long 0x00 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register" bitfld.long 0x00 15.--19. " WRITE_CHANNEL3_WEIGHT ,Channel 3 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " WRITE_CHANNEL2_WEIGHT ,Channel 2 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " WRITE_CHANNEL1_WEIGHT ,Channel 1 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " WRITE_CHANNEL0_WEIGHT ,Channel 0 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register" bitfld.long 0x04 15.--19. " WRITE_CHANNEL7_WEIGHT ,Channel 7 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 10.--14. " WRITE_CHANNEL6_WEIGHT ,Channel 6 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 5.--9. " WRITE_CHANNEL5_WEIGHT ,Channel 5 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " WRITE_CHANNEL4_WEIGHT ,Channel 4 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2C++0x07 line.long 0x00 "DMA_READ_ENGINE_EN_OFF ,DMA Read Engine Enable Register" bitfld.long 0x00 0. " DMA_READ_ENGINE ,DMA read engine enable" "Disabled,Enabled" line.long 0x04 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register" bitfld.long 0x04 31. " RD_STOP ,Stop" "Not stopped,Stopped" bitfld.long 0x04 0.--2. " WR_DOORBELL_NUM ,Doorbell number" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" group.long 0x38++0x07 line.long 0x00 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register" bitfld.long 0x00 15.--19. " READ_CHANNEL3_WEIGHT ,Channel 3 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " READ_CHANNEL2_WEIGHT ,Channel 2 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " READ_CHANNEL1_WEIGHT ,Channel 1 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " READ_CHANNEL0_WEIGHT ,Channel 0 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register" bitfld.long 0x04 15.--19. " READ_CHANNEL7_WEIGHT ,Channel 7 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 10.--14. " READ_CHANNEL6_WEIGHT ,Channel 6 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 5.--9. " READ_CHANNEL5_WEIGHT ,Channel 5 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " READ_CHANNEL4_WEIGHT ,Channel 4 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4C++0x03 line.long 0x00 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register" bitfld.long 0x00 23. " WR_ABORT_INT_STATUS[7] ,Abort interrupt status for channel 7" "Not aborted,Aborted" bitfld.long 0x00 22. " [6] ,Abort interrupt status for channel 6" "Not aborted,Aborted" textline " " bitfld.long 0x00 21. " [5] ,Abort interrupt status for channel 5" "Not aborted,Aborted" bitfld.long 0x00 20. " [4] ,Abort interrupt status for channel 4" "Not aborted,Aborted" textline " " bitfld.long 0x00 19. " [3] ,Abort interrupt status for channel 3" "Not aborted,Aborted" bitfld.long 0x00 18. " [2] ,Abort interrupt status for channel 2" "Not aborted,Aborted" textline " " bitfld.long 0x00 17. " [1] ,Abort interrupt status for channel 1" "Not aborted,Aborted" bitfld.long 0x00 16. " [0] ,Abort interrupt status for channel 0" "Not aborted,Aborted" textline " " bitfld.long 0x00 7. " WR_DONE_INT_STATUS[7] ,Done interrupt status for channel 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Done interrupt status for channel 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " [5] ,Done interrupt status for channel 5" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Done interrupt status for channel 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Done interrupt status for channel 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Done interrupt status for channel 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " [1] ,Done interrupt status for channel 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Done interrupt status for channel 0" "Not masked,Masked" group.long 0x54++0x07 line.long 0x00 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register" bitfld.long 0x00 16. " WR_ABORT_INT_MASK ,Abort interrupt mask for channel 0" "Not aborted,Aborted" bitfld.long 0x00 0. " WR_DONE_INT_MASK ,Done interrupt mask for channel 0" "Not done,Done" line.long 0x04 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register" bitfld.long 0x04 23. " WR_ABORT_INT_CLEAR[7] ,Abort interrupt clear for channel 7" "Not interrupted,Interrupted" bitfld.long 0x04 22. " [6] ,Abort interrupt clear for channel 6" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 21. " [5] ,Abort interrupt clear for channel 5" "Not interrupted,Interrupted" bitfld.long 0x04 20. " [4] ,Abort interrupt clear for channel 4" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 19. " [3] ,Abort interrupt clear for channel 3" "Not interrupted,Interrupted" bitfld.long 0x04 18. " [2] ,Abort interrupt clear for channel 2" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 17. " [1] ,Abort interrupt clear for channel 1" "Not interrupted,Interrupted" bitfld.long 0x04 16. " [0] ,Abort interrupt clear for channel 0" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 7. " WR_DONE_INT_CLEAR[7] ,Done interrupt clear for channel 7" "Not interrupted,Interrupted" bitfld.long 0x04 6. " [6] ,Done interrupt clear for channel 6" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 5. " [5] ,Done interrupt clear for channel 5" "Not interrupted,Interrupted" bitfld.long 0x04 4. " [4] ,Done interrupt clear for channel 4" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 3. " [3] ,Done interrupt clear for channel 3" "Not interrupted,Interrupted" bitfld.long 0x04 2. " [2] ,Done interrupt clear for channel 2" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 1. " [1] ,Done interrupt clear for channel 1" "Not interrupted,Interrupted" bitfld.long 0x04 0. " [0] ,Done interrupt clear for channel 0" "Not interrupted,Interrupted" rgroup.long 0x5C++0x03 line.long 0x00 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" bitfld.long 0x00 23. " LINKLIST_ELEMENT_FETCH_ERR_DETECT[7] ,Linked list element fetch error detected for channel 7" "Not occurred,Occurred" bitfld.long 0x00 22. " [6] ,Linked list element fetch error detected for channel 6" "Not occurred,Occurred" textline " " bitfld.long 0x00 21. " [5] ,Linked list element fetch error detected for channel 5" "Not occurred,Occurred" bitfld.long 0x00 20. " [4] ,Linked list element fetch error detected for channel 4" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [3] ,Linked list element fetch error detected for channel 3" "Not occurred,Occurred" bitfld.long 0x00 18. " [2] ,Linked list element fetch error detected for channel 2" "Not occurred,Occurred" textline " " bitfld.long 0x00 17. " [1] ,Linked list element fetch error detected for channel 1" "Not occurred,Occurred" bitfld.long 0x00 16. " [0] ,Linked list element fetch error detected for channel 0" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " APP_READ_ERR_DETECT[7] ,Application read error detected for channel 7" "Not occurred,Occurred" bitfld.long 0x00 6. " [6] ,Application read error detected for channel 6" "Not occurred,Occurred" textline " " bitfld.long 0x00 5. " [5] ,Application read error detected for channel 5" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Application read error detected for channel 4" "Not occurred,Occurred" textline " " bitfld.long 0x00 3. " [3] ,Application read error detected for channel 3" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Application read error detected for channel 2" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " [1] ,Application read error detected for channel 1" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Application read error detected for channel 0" "Not occurred,Occurred" group.long 0x60++0x1F line.long 0x00 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register" line.long 0x04 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register" line.long 0x08 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register" line.long 0x0C "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register" hexmask.long.word 0x10 16.--31. 1. " WR_CHANNEL_1_DATA ,Write channel 1 data" hexmask.long.word 0x10 0.--15. 1. " WR_CHANNEL_0_DATA ,Write channel 0 data" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register" hexmask.long.word 0x14 16.--31. 1. " WR_CHANNEL_3_DATA ,Write channel 3 data" hexmask.long.word 0x14 0.--15. 1. " WR_CHANNEL_2_DATA ,Write channel 2 data" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register" hexmask.long.word 0x18 16.--31. 1. " WR_CHANNEL_5_DATA ,Write channel 5 data" hexmask.long.word 0x18 0.--15. 1. " WR_CHANNEL_4_DATA ,Write channel 4 data" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register" hexmask.long.word 0x1C 16.--31. 1. " WR_CHANNEL_7_DATA ,Write channel 7 data" hexmask.long.word 0x1C 0.--15. 1. " WR_CHANNEL_6_DATA ,Write channel 6 data" if (((per.l(ad:0x33800000+0x370+0x700))&0x200)==0x200) group.long 0x90++0x03 line.long 0x00 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register" bitfld.long 0x00 16. " WR_CHANNEL_LLLAIE ,Write channel LL local abort interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " WR_CHANNEL_LLRAIE ,Write channel LL remote abort interrupt enable" "Disabled,Enabled" else hgroup.long 0x90++0x03 hide.long 0x00 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register" endif group.long (0x00+0xA0)++0x03 line.long 0x00 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register" bitfld.long 0x00 23. " RD_ABORT_INT_STATUS[7] ,Abort interrupt status for channel 7" "Not aborted,Aborted" bitfld.long 0x00 22. " [6] ,Abort interrupt status for channel 6" "Not aborted,Aborted" textline " " bitfld.long 0x00 21. " [5] ,Abort interrupt status for channel 5" "Not aborted,Aborted" bitfld.long 0x00 20. " [4] ,Abort interrupt status for channel 4" "Not aborted,Aborted" textline " " bitfld.long 0x00 19. " [3] ,Abort interrupt status for channel 3" "Not aborted,Aborted" bitfld.long 0x00 18. " [2] ,Abort interrupt status for channel 2" "Not aborted,Aborted" textline " " bitfld.long 0x00 17. " [1] ,Abort interrupt status for channel 1" "Not aborted,Aborted" bitfld.long 0x00 16. " [0] ,Abort interrupt status for channel 0" "Not aborted,Aborted" textline " " bitfld.long 0x00 7. " RD_DONE_INT_STATUS[7] ,Done interrupt status for channel 7" "Not done,Done" bitfld.long 0x00 6. " [6] ,Done interrupt status for channel 6" "Not done,Done" textline " " bitfld.long 0x00 5. " [5] ,Done interrupt status for channel 5" "Not done,Done" bitfld.long 0x00 4. " [4] ,Done interrupt status for channel 4" "Not done,Done" textline " " bitfld.long 0x00 3. " [3] ,Done interrupt status for channel 3" "Not done,Done" bitfld.long 0x00 2. " [2] ,Done interrupt status for channel 2" "Not done,Done" textline " " bitfld.long 0x00 1. " [1] ,Done interrupt status for channel 1" "Not done,Done" bitfld.long 0x00 0. " [0] ,Done interrupt status for channel 0" "Not done,Done" group.long (0x00+0xA8)++0x03 line.long 0x00 "DMA_READ_INT_MASK_OFF,DMA read interrupt mask register" bitfld.long 0x00 16. " RD_ABORT_INT_MASK ,Abort interrupt mask" "Not aborted,Aborted" bitfld.long 0x00 0. " RD_DONE_INT_MASK ,Done interrupt mask" "Not done,Done" wgroup.long (0x00+0xAC)++0x03 line.long 0x00 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register" bitfld.long 0x00 23. " RD_ABORT_INT_CLEAR[7] ,Abort interrupt clear for channel 7" "Not aborted,Aborted" bitfld.long 0x00 22. " [6] ,Abort interrupt clear for channel 6" "Not aborted,Aborted" textline " " bitfld.long 0x00 21. " [5] ,Abort interrupt clear for channel 5" "Not aborted,Aborted" bitfld.long 0x00 20. " [4] ,Abort interrupt clear for channel 4" "Not aborted,Aborted" textline " " bitfld.long 0x00 19. " [3] ,Abort interrupt clear for channel 3" "Not aborted,Aborted" bitfld.long 0x00 18. " [2] ,Abort interrupt clear for channel 2" "Not aborted,Aborted" textline " " bitfld.long 0x00 17. " [1] ,Abort interrupt clear for channel 1" "Not aborted,Aborted" bitfld.long 0x00 16. " [0] ,Abort interrupt clear for channel 0" "Not aborted,Aborted" textline " " bitfld.long 0x00 7. " RD_DONE_INT_CLEAR[7] ,Done interrupt clear for channel 7" "Not done,Done" bitfld.long 0x00 6. " [6] ,Done interrupt clear for channel 6" "Not done,Done" textline " " bitfld.long 0x00 5. " [5] ,Done interrupt clear for channel 5" "Not done,Done" bitfld.long 0x00 4. " [4] ,Done interrupt clear for channel 4" "Not done,Done" textline " " bitfld.long 0x00 3. " [3] ,Done interrupt clear for channel 3" "Not done,Done" bitfld.long 0x00 2. " [2] ,Done interrupt clear for channel 2" "Not done,Done" textline " " bitfld.long 0x00 1. " [1] ,Done interrupt clear for channel 1" "Not done,Done" bitfld.long 0x00 0. " [0] ,Done interrupt clear for channel 0" "Not done,Done" rgroup.long (0x00+0xB4)++0x07 line.long 0x00 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register" bitfld.long 0x00 23. " LINK_LIST_ELEMENT_FETCH_ERR_DETECT[7] ,Linked list element fetch error detected for channel 7" "Not detected,Detected" bitfld.long 0x00 22. " [6] ,Linked list element fetch error detected for channel 6" "Not detected,Detected" textline " " bitfld.long 0x00 21. " [5] ,Linked list element fetch error detected for channel 5" "Not detected,Detected" bitfld.long 0x00 20. " [4] ,Linked list element fetch error detected for channel 4" "Not detected,Detected" textline " " bitfld.long 0x00 19. " [3] ,Linked list element fetch error detected for channel 3" "Not detected,Detected" bitfld.long 0x00 18. " [2] ,Linked list element fetch error detected for channel 2" "Not detected,Detected" textline " " bitfld.long 0x00 17. " [1] ,Linked list element fetch error detected for channel 1" "Not detected,Detected" bitfld.long 0x00 16. " [0] ,Linked list element fetch error detected for channel 0" "Not detected,Detected" textline " " bitfld.long 0x00 7. " APP_WR_ERR_DETECT[7] ,Application write error detected for channel 7" "Not detected,Detected" bitfld.long 0x00 6. " [6] ,Application write error detected for channel 6" "Not detected,Detected" textline " " bitfld.long 0x00 5. " [5] ,Application write error detected for channel 5" "Not detected,Detected" bitfld.long 0x00 4. " [4] ,Application write error detected for channel 4" "Not detected,Detected" textline " " bitfld.long 0x00 3. " [3] ,Application write error detected for channel 3" "Not detected,Detected" bitfld.long 0x00 2. " [2] ,Application write error detected for channel 2" "Not detected,Detected" textline " " bitfld.long 0x00 1. " [1] ,Application write error detected for channel 1" "Not detected,Detected" bitfld.long 0x00 0. " [0] ,Application write error detected for channel 0" "Not detected,Detected" line.long 0x04 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register" bitfld.long 0x04 31. " DATA_POISIONING[7] ,Data poisoning for channel 7" "Disabled,Enabled" bitfld.long 0x04 30. " [6] ,Data poisoning for channel 6" "Disabled,Enabled" textline " " bitfld.long 0x04 29. " [5] ,Data poisoning for channel 5" "Disabled,Enabled" bitfld.long 0x04 28. " [4] ,Data poisoning for channel 4" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " [3] ,Data poisoning for channel 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Data poisoning for channel 2" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " [1] ,Data poisoning for channel 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Data poisoning for channel 0" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " CPL_TIMEOUT[7] ,Completion time out for channel 7" "Disabled,Enabled" bitfld.long 0x04 22. " [6] ,Completion time out for channel 6" "Disabled,Enabled" textline " " bitfld.long 0x04 21. " [5] ,Completion time out for channel 5" "Disabled,Enabled" bitfld.long 0x04 20. " [4] ,Completion time out for channel 4" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " [3] ,Completion time out for channel 3" "Disabled,Enabled" bitfld.long 0x04 18. " [2] ,Completion time out for channel 2" "Disabled,Enabled" textline " " bitfld.long 0x04 17. " [1] ,Completion time out for channel 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Completion time out for channel 0" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " CPL_ABORT[7] ,Completer abort for channel 7" "Not Received,Received" bitfld.long 0x04 14. " [6] ,Completer abort for channel 6" "Not Received,Received" textline " " bitfld.long 0x04 13. " [5] ,Completer abort for channel 5" "Not Received,Received" bitfld.long 0x04 12. " [4] ,Completer abort for channel 4" "Not Received,Received" textline " " bitfld.long 0x04 11. " [3] ,Completer abort for channel 3" "Not Received,Received" bitfld.long 0x04 10. " [2] ,Completer abort for channel 2" "Not Received,Received" textline " " bitfld.long 0x04 9. " [1] ,Completer abort for channel 1" "Not Received,Received" bitfld.long 0x04 8. " [0] ,Completer abort for channel 0" "Not Received,Received" textline " " bitfld.long 0x04 7. " UNSUPPORTED_REQ[7] ,Unsupported request for channel 7" "Not Received,Received" bitfld.long 0x04 6. " [6] ,Unsupported request for channel 6" "Not Received,Received" textline " " bitfld.long 0x04 5. " [5] ,Unsupported request for channel 5" "Not Received,Received" bitfld.long 0x04 4. " [4] ,Unsupported request for channel 4" "Not Received,Received" textline " " bitfld.long 0x04 3. " [3] ,Unsupported request for channel 3" "Not Received,Received" bitfld.long 0x04 2. " [2] ,Unsupported request for channel 2" "Not Received,Received" textline " " bitfld.long 0x04 1. " [1] ,Unsupported request for channel 1" "Not Received,Received" bitfld.long 0x04 0. " [0] ,Unsupported request for channel 0" "Not Received,Received" if (((per.l(ad:0x33800000+0x370+0x700))&0x200)==0x200) group.long 0xC4++0x03 line.long 0x00 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register" bitfld.long 0x00 16. " RD_CHANNEL_LLLAIE ,Read channel LL local abort interrupt enable" "Enabled,Disabled" bitfld.long 0x00 0. " RD_CHANNEL_LLRAIE ,Read channel LL remote abort interrupt enable" "Enabled,Disabled" else hgroup.long 0xC4++0x03 hide.long 0x00 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register" endif group.long (0x00+0xCC)++0x1F line.long 0x00 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register" line.long 0x04 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register" line.long 0x08 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register" line.long 0x0C "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register" hexmask.long.word 0x10 16.--31. 1. " RD_CHANNEL_1_DATA , Read channel 1 data" hexmask.long.word 0x10 0.--15. 1. " RD_CHANNEL_0_DATA , Read channel 0 data" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register" hexmask.long.word 0x14 16.--31. 1. " RD_CHANNEL_3_DATA , Read channel 3 data" hexmask.long.word 0x14 0.--15. 1. " RD_CHANNEL_2_DATA , Read channel 2 data" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register" hexmask.long.word 0x18 16.--31. 1. " RD_CHANNEL_5_DATA , Read channel 5 data" hexmask.long.word 0x18 0.--15. 1. " RD_CHANNEL_4_DATA , Read channel 4 data" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register" hexmask.long.word 0x1C 16.--31. 1. " RD_CHANNEL_7_DATA , Read channel 7 data" hexmask.long.word 0x1C 0.--15. 1. " RD_CHANNEL_6_DATA , Read channel 6 data" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") if (((per.l(ad:0x33800000+0x80080200))&0x200)==0x200) group.long 0x80200++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" textline " " bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCS ,Consumer cycle state" "0,1" textline " " rbitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " LLP ,Load link pointer" "0,1" textline " " bitfld.long 0x00 1. " TCB ,Toggle cycle bit" "0,1" bitfld.long 0x00 0. " CB ,Cycle bit" "0,1" else group.long 0x80200++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" textline " " bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" endif group.long 0x80208++0x1B line.long 0x00 "DMA_TRANSFER_SIZE_OFF_WRCH_0,DMA Write Transfer Size Register" line.long 0x04 "DMA_SAR_LOW_OFF_WRCH_0,DMA Write SAR Low Register" line.long 0x08 "DMA_SAR_HIGH_OFF_WRCH_0,DMA Write SAR High Register" line.long 0x0C "DMA_DAR_LOW_OFF_WRCH_0,DMA Write DAR Low Register" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_0,DMA Write DAR High Register" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_0,DMA Write Linked List Pointer Low Register" line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_0,DMA Write Linked List Pointer High Register" if (((per.l(ad:0x33800000+0x80080300))&0x200)==0x200) group.long 0x80300++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" textline " " bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCS ,Consumer cycle state" "0,1" textline " " rbitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " LLP ,Load link pointer" "0,1" textline " " bitfld.long 0x00 1. " TCB ,Toggle cycle bit" "0,1" bitfld.long 0x00 0. " CB ,Cycle bit" "0,1" else group.long 0x80300++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" textline " " bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" endif group.long 0x80308++0x1B line.long 0x00 "DMA_TRANSFER_SIZE_OFF_WRCH_0,DMA Write Transfer Size Register" line.long 0x04 "DMA_SAR_LOW_OFF_WRCH_0,DMA Write SAR Low Register" line.long 0x08 "DMA_SAR_HIGH_OFF_WRCH_0,DMA Write SAR High Register" line.long 0x0C "DMA_DAR_LOW_OFF_WRCH_0,DMA Write DAR Low Register" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_0,DMA Write DAR High Register" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_0,DMA Write Linked List Pointer Low Register" line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_0,DMA Write Linked List Pointer High Register" else group.long 0xFC++0x03 line.long 0x00 "DMA_VIEWPORT_SEL_OFF,DMA Channel Context Index Register" bitfld.long 0x00 31. " CHANNEL_DIR ,Channel direction" "Write,Read" bitfld.long 0x00 0.--2. " CHANNEL_NUM ,Channel index" "Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7" if (((per.l(ad:0x33800000+0x370+0x700))&0x200)==0x200) group.long 0x100++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" textline " " bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCS ,Consumer cycle state" "0,1" textline " " rbitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " LLP ,Load link pointer" "0,1" textline " " bitfld.long 0x00 1. " TCB ,Toggle cycle bit" "0,1" bitfld.long 0x00 0. " CB ,Cycle bit" "0,1" else group.long 0x100++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" textline " " bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" endif group.long 0x108++0x1B line.long 0x00 "DMA_TRANSFER_SIZE_OFF_WRCH_0,DMA Write Transfer Size Register" line.long 0x04 "DMA_SAR_LOW_OFF_WRCH_0,DMA Write SAR Low Register" line.long 0x08 "DMA_SAR_HIGH_OFF_WRCH_0,DMA Write SAR High Register" line.long 0x0C "DMA_DAR_LOW_OFF_WRCH_0,DMA Write DAR Low Register" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_0,DMA Write DAR High Register" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_0,DMA Write Linked List Pointer Low Register" line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_0,DMA Write Linked List Pointer High Register" group.long 0x1D0++0x03 line.long 0x00 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register" hexmask.long.word 0x00 0.--9. 1. " AUX_CLK_FREQ ,The auxiliary clock frequency in MHz" group.long 0x1D4++0x03 line.long 0x00 "L1_SUBSTATER_OFF,L1 Substates Timing Register" bitfld.long 0x00 6.--7. " L1SUB_T_PCLKACK ,Max delay between a MAC remove request and a PHY response" "0,1,2,3,?..." bitfld.long 0x00 2.--5. " L1SUB_T_L1_2 ,Duration of L1.2" "0,1us,2us,3us,4us,5us,6us,7us,8us,9us,10us,11us,12us,13us,14us,15us" textline " " bitfld.long 0x00 0.--1. " L1SUB_T_POWER_OFF ,Duration of L1.2 entry" "0us,1us,2us,3us" endif width 0x0B tree.end tree "PCIe 2" base ad:0x33c00000 ;Based one the PCI Express Base Specification 3.0 width 44. rgroup.long 0x00++0x03 line.long 0x00 "TYPE1_DEV_ID_VEND_ID_REG,PCIE0 Device ID And Vendor ID Register" hexmask.long.word 0x00 16.--31. 1. " DEVID ,Device ID" hexmask.long.word 0x00 0.--15. 1. " VENDID ,Vendor ID" group.long 0x04++0x0B line.long 0x00 "TYPE1_STATUS_COMMAND_REG,Command and Status Register" eventfld.long 0x00 31. " DETECTED_PARITY_ERROR ,Detected parity error" "No error,Error" eventfld.long 0x00 30. " SIGNALED_SYS_ERROR ,Signaled system error" "No error,Error" textline " " eventfld.long 0x00 29. " RCVD_MASTER_ABORT ,Received master abort" "No abort,Abort" eventfld.long 0x00 28. " RCVD_TARGET_ABORT ,Received target abort" "No abort,Abort" textline " " eventfld.long 0x00 27. " SIGNALED_TARGET_ABORT ,Signaled target abort" "No abort,Abort" rbitfld.long 0x00 25.--26. " DEV_SEL_TIMING ,Device select timing" "0,?..." textline " " eventfld.long 0x00 24. " MASTER_DPE ,Master data parity error" "No error,Error" rbitfld.long 0x00 23. " FASTB2B ,Fast back-to-back transactions enable" "Disabled," textline " " rbitfld.long 0x00 21. " FAST_66MHZ_CAP ,66 MHz capable" "0," rbitfld.long 0x00 20. " CAP_LIST ,Capabilities list" ",1" textline " " rbitfld.long 0x00 19. " INT_STATUS ,Interrupt status" "Disabled,Enabled" bitfld.long 0x00 10. " INT_EN ,Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " SERREN ,Reporting of non-fatal and fatal errors detected enable" "Disabled,Enabled" rbitfld.long 0x00 7. " IDSEL ,IDSEL stepping/wait cycle control" "0,1" textline " " bitfld.long 0x00 6. " PERREN ,Parity error enable" "Disabled,Enabled" rbitfld.long 0x00 5. " VGAPS ,VGA palette snoop" "Disabled,Enabled" textline " " rbitfld.long 0x00 4. " MWI_EN ,Memory write and invalidate enable" "Disabled,Enabled" rbitfld.long 0x00 3. " SCO ,Special cycle enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BME ,Bus master enable" "Disabled,Enabled" bitfld.long 0x00 1. " MSE ,Memory space enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " IO_EN ,I/O space enable" "Disabled,Enabled" line.long 0x04 "CCRID,Class Code and Revision ID Register" hexmask.long.byte 0x04 24.--31. 1. " BASE_CLASS_CODE ,Base class-memory controller" hexmask.long.byte 0x04 16.--23. 1. " SUBCLASS_CODE ,Sub class-other memory controller" textline " " hexmask.long.byte 0x04 8.--15. 1. " PROGRAM_INTF ,Register level programming interface" hexmask.long.byte 0x04 0.--7. 1. " REV_ID ,Device revision number" line.long 0x08 "BISTTCLSMLT,BIST Header Type Cache Line Size and Master Latency Timer Register" hexmask.long.byte 0x08 24.--31. 1. " BIST ,Built-in self test" bitfld.long 0x08 23. " MULTI_FUNC ,MULTI_FUNC" "0,1" textline " " hexmask.long.byte 0x08 16.--22. 1. " HEADER_TYPE ,Device configuration header type" hexmask.long.byte 0x08 8.--15. 1. " LAT_MASTER_TMR ,Latency master timer" textline " " hexmask.long.byte 0x08 0.--7. 1. " CACHE_LINE_SIZE ,Device cache line size" group.long 0x18++0x2B line.long 0x00 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Primary/Secondary/Subordinate Bus Numbers and Latency Timer Registers" hexmask.long.byte 0x00 24.--31. 1. " SEC_LAT_TIMER ,Latency timer" hexmask.long.byte 0x00 16.--23. 1. " SUB_BUS ,Subordinate bus number" textline " " hexmask.long.byte 0x00 8.--15. 1. " SEC_BUS ,Secondary bus number" hexmask.long.byte 0x00 0.--7. 1. " PRIM_BUS ,Primary bus number" line.long 0x04 "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status and I/O Base and Limit Registers" eventfld.long 0x04 31. " SEC_STAT_DPE ,Detected parity error" "Not error,Error" eventfld.long 0x04 30. " SEC_STAT_RCVD_SYS_ERR ,Received system error" "Not error,Error" textline " " eventfld.long 0x04 29. " SEC_STAT_RCVD_MSTR_ABRT ,Received master abort" "Not received,Received" eventfld.long 0x04 28. " SEC_STAT_RCVD_TRGT_ABRT ,Received target abort" "Not received,Received" textline " " eventfld.long 0x04 27. " SEC_STAT_SIG_TRGT_ABRT ,Signaled target abort" "Not error,Error" eventfld.long 0x04 24. " SEC_STAT_MDPE ,Master data parity error" "Nor error,Error" textline " " bitfld.long 0x04 12.--15. " IO_LIMIT ,I/O limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8. " IO_DECODE_BIT8 ,I/O addressing encode" "16 bit supported,32 bit supported" textline " " bitfld.long 0x04 4.--7. " IO_BASE ,I/O base" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0. " IO_DECODE ,I/O decode" "16 bit supported,32 bit supported" line.long 0x08 "MEM_LIMIT_MEM_BASE_REG,Memory Base and Memory Limit Register" hexmask.long.word 0x08 20.--31. 0x10 " MEM_LIMIT ,Memory limit address" hexmask.long.word 0x08 4.--15. 0x10 " MEM_BASE ,Memory base address" line.long 0x0C "MEM_LIMIT_MEM_BASE_REG,Prefetchable Memory Base and Limit Register" hexmask.long.word 0x0C 20.--31. 1. " PREF_MEM_LIMIT ,Prefetchable memory limit address" rbitfld.long 0x0C 16. " PREF_MEM_LIMIT_DECODE ,Prefetchable memory limit decode " "32 bit supported,64 bit supported" textline " " hexmask.long.word 0x0C 4.--15. 1. " PREF_MEM_BASE ,Prefetchable memory base" rbitfld.long 0x0C 0. " PREF_MEM_DECODE ,Prefetchable memory decode" "32 bit supported,64 bit supported" line.long 0x10 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register" line.long 0x14 "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register" line.long 0x18 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Base and Limit Upper 16 Bits Register" hexmask.long.word 0x18 16.--31. 1. " IO_LIMIT_UPPER ,I/O limit upper 16 bits" hexmask.long.word 0x18 0.--15. 1. " IO_BASE_UPPER ,I/O base upper 16 bits" line.long 0x1C "TYPE1_CAP_PTR_REG,Capability Pointer Register" hexmask.long.byte 0x1C 0.--7. 1. " CAP_PTR ,Capability list pointer" line.long 0x20 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM BAR and Mask Register" hexmask.long.tbyte 0x20 11.--31. 0x08 " EXP_ROM_BASE_ADDR ,Expansion ROM BAR and mask register" rbitfld.long 0x20 0. " ROM_BAR_EN ,ROM BAR enable" "Disabled,Enabled" line.long 0x24 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Interrupt Line and Pin and Bridge Control Registers" bitfld.long 0x24 22. " SBR ,Secondary bus hot reset" "No effect,Hot reset" textline " " rbitfld.long 0x24 21. " MSTR_ABORT_MODE ,Master abort mode" "0," rbitfld.long 0x24 20. " VGA_16B_DEC ,VGA 16-bit decode" "10 bit,16 bit" textline " " rbitfld.long 0x24 19. " VGA_EN ,VGA enable" "Disabled,Enabled" bitfld.long 0x24 18. " ISA_EN ,ISA enable" "Disabled,Enabled" textline " " bitfld.long 0x24 17. " SERR_EN ,SERR enable" "Disabled,Enabled" bitfld.long 0x24 16. " PERE ,Parity error response enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x24 8.--15. 1. " INT_PIN ,Interrupt PIN" hexmask.long.byte 0x24 0.--7. 1. " INT_LINE ,Interrupt line" if (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01) group.long 0x40++0x07 line.long 0x00 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register" bitfld.long 0x00 27.--31. " PME_SUPPORT ,Support PM Event support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 26. " D2_SUPPORT ,D2 state support" "Not supported,Supported" textline " " bitfld.long 0x00 25. " D1_SUPPORT ,D1 state support" "Not supported,Supported" bitfld.long 0x00 22.--24. " AUX_CURR ,Auxiliary current requirements" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 21. " DSI ,Device specific initialization" "Low,High" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 19. " PME_CLK ,PCI clock requirement" "0,1" textline " " bitfld.long 0x00 16.--18. " PM_SPEC_VER ,PCI power management capability version" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 8.--15. 0x01 " PM_NEXT_PTR ,Next capability pointer" textline " " hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID ,Power management capability ID" else bitfld.long 0x00 20. " PME_IMM_READI_RETURN_D0 ,Immediate readiness on return to D0" "0,1" textline " " bitfld.long 0x00 19. " PME_CLK ,PCI clock requirement" "0,1" bitfld.long 0x00 16.--18. " PM_SPEC_VER ,PCI power management capability version" "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x00 8.--15. 0x01 " PM_NEXT_PTR ,Next capability pointer" hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID ,Power management capability ID" endif line.long 0x04 "PCIEPMCS,PCI Express Power Management Control and Status Register" hexmask.long.byte 0x04 24.--31. 1. " DATA_REG_ADD_INFO ,Power data information" rbitfld.long 0x04 23. " BUS_PWR_CLK_CON_EN ,Bus power/clock control enable" "Disabled,Enabled" textline " " rbitfld.long 0x04 22. " B2_B3_SUPPORT ,B2 B3 support for D3hot" "Not supported,Supported" eventfld.long 0x04 15. " PME_STATUS ,PME Status" "0,1" textline " " rbitfld.long 0x04 13.--14. " DATA_SCALE ,Data scale" "0,1,2,3" rbitfld.long 0x04 9.--12. " DATA_SEL ,Data select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 8. " PME_EN ,PM_PME message generation enable" "Disabled,Enabled" bitfld.long 0x04 3. " NO_SOFT_RST ,No soft reset" "Low,High" textline " " bitfld.long 0x04 0.--1. " POWER_STATE ,Power state" "0,1,2,3" else group.long 0x40++0x07 line.long 0x00 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register" rbitfld.long 0x00 27.--31. " PME_SUPPORT ,Support PM Event support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 26. " D2_SUPPORT ,D2 state support" "Not supported,Supported" textline " " rbitfld.long 0x00 25. " D1_SUPPORT ,D1 state support" "Not supported,Supported" rbitfld.long 0x00 22.--24. " AUX_CURR ,Auxiliary current requirements" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x00 21. " DSI ,Device specific initialization" "Low,High" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 19. " PME_CLK ,PCI clock requirement" "0,1" textline " " rbitfld.long 0x00 16.--18. " PM_SPEC_VER ,PCI power management capability version" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 8.--15. 0x01 " PM_NEXT_PTR ,Next capability pointer" textline " " hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID ,Power management capability ID" else bitfld.long 0x00 20. " PME_IMM_READI_RETURN_D0 ,Immediate readiness on return to D0" "0,1" textline " " bitfld.long 0x00 19. " PME_CLK ,PCI clock requirement" "0,1" rbitfld.long 0x00 16.--18. " PM_SPEC_VER ,PCI power management capability version" "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x00 8.--15. 0x01 " PM_NEXT_PTR ,Next capability pointer" hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID ,Power management capability ID" endif line.long 0x04 "PCIEPMCS,PCI Express Power Management Control and Status Register" hexmask.long.byte 0x04 24.--31. 1. " DATA_REG_ADD_INFO ,Power data information" rbitfld.long 0x04 23. " BUS_PWR_CLK_CON_EN ,Bus power/clock control enable" "Disabled,Enabled" textline " " rbitfld.long 0x04 22. " B2_B3_SUPPORT ,B2 B3 support" "Not supported,Supported" eventfld.long 0x04 15. " PME_STATUS ,PME Status" "0,1" textline " " rbitfld.long 0x04 13.--14. " DATA_SCALE ,Data scale" "0,1,2,3" rbitfld.long 0x04 9.--12. " DATA_SEL ,Data select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 8. " PME_EN ,PM_PME message generation enable" "Disabled,Enabled" rbitfld.long 0x04 3. " NO_SOFT_RST ,No soft reset" "Low,High" textline " " bitfld.long 0x04 0.--1. " POWER_STATE ,Power state" "0,1,2,3" endif if (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01) group.long 0x50++0x03 line.long 0x00 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID Next Pointer Control Registers" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 26. " PCI_MSI_EXT_DATA_EN ,Extended message data enable" "Not enabled,Enabled" bitfld.long 0x00 25. " PCI_MSI_EXT_DATA_CAP ,Extended message data Capable" "Not capable,Capable" textline " " endif rbitfld.long 0x00 24. " PCI_PVM_SUPPORT ,MSI per vector masking capable" "Not supported,Supported" bitfld.long 0x00 23. " PCI_MSI_64_BIT_ADDR_CAP ,MSI 64-bit addressing capable" "0,1" textline " " bitfld.long 0x00 20.--22. " PCI_MSI_MULTIPLE_MSG_EN ,Multiple messages enable" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " PCI_MSI_MULTIPLE_MSG_CAP ,MSI Multiple message capable" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 16. " PCI_MSI_EN ,MSI enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 0x01 " PCI_MSI_CAP_NEXT_OFFSET ,MSI capability next pointer" textline " " hexmask.long.byte 0x00 0.--7. 1. " PCI_MSI_CAP_ID ,MSI capability ID" else group.long 0x50++0x03 line.long 0x00 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID Next Pointer Control Registers" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 26. " PCI_MSI_EXT_DATA_EN ,Extended message data enable" "Not enabled,Enabled" rbitfld.long 0x00 25. " PCI_MSI_EXT_DATA_CAP ,Extended message data Capable" "Not capable,Capable" textline " " endif rbitfld.long 0x00 24. " PCI_PVM_SUPPORT ,MSI per vector masking capable" "Not supported,Supported" rbitfld.long 0x00 23. " PCI_MSI_64_BIT_ADDR_CAP ,MSI 64-bit addressing capable" "0,1" textline " " bitfld.long 0x00 20.--22. " PCI_MSI_MULTIPLE_MSG_EN ,Multiple messages enable" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--19. " PCI_MSI_MULTIPLE_MSG_CAP ,MSI Multiple message capable" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 16. " PCI_MSI_EN ,MSI enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 0x01 " PCI_MSI_CAP_NEXT_OFFSET ,MSI capability next pointer" textline " " hexmask.long.byte 0x00 0.--7. 1. " PCI_MSI_CAP_ID ,MSI capability ID" endif group.long 0x54++0x0B line.long 0x00 "MSI_CAP_OFF_04H_REG,MSI Capability ID Next Pointer Control 04H Registers" hexmask.long 0x00 2.--31. 0x04 " PCI_MSI_CAP_OFF_04H ,MSI message lower address field" line.long 0x04 "MSI_CAP_OFF_08H_REG,MSI Capability ID Next Pointer Control 08H Registers" hexmask.long.word 0x04 16.--31. 0x01 " PCI_MSI_CAP_OFF_0AH ,Capability offset 0AH" hexmask.long.word 0x04 0.--15. 0x01 " PCI_MSI_CAP_OFF_08H ,Capability offset 08H" line.long 0x08 "MSI_CAP_OFF_0CH_REG,MSI Capability ID Next Pointer Control 0CH Registers" hexmask.long.word 0x08 16.--31. 0x01 " PCI_MSI_CAP_OFF_0EH ,Capability offset 0EH" hexmask.long.word 0x08 0.--15. 0x01 " PCI_MSI_CAP_OFF_0CH ,Capability offset 0CH" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") group.long 0x60++0x03 line.long 0x00 "MSI_CAP_OFF_10H_REG,Used for MSI when Vector Masking Capable" rgroup.long 0x64++0x03 line.long 0x00 "MSI_CAP_OFF_14H_REG,Used for MSI 64bit messaging when Vector Masking Capable" endif base ad:0x33c00000+0x70 if (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01) group.long 0x00++0x07 line.long 0x00 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities ID Next Pointer Register" rbitfld.long 0x00 25.--29. " PCIE_INT_MSG_NUM ,Interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 24. " PCIE_SLOT_IMP ,Slot implemented" "Not valid,Valid" textline " " bitfld.long 0x00 20.--23. " PCIE_DEV_PORT_TYPE ,Device/Port type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " PCIE_CAP_REG ,Capability version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " PCIE_CAP_NEXT_PTR ,Next item pointer" hexmask.long.byte 0x00 0.--7. 1. " PCIE_CAP_ID ,Capability ID" line.long 0x04 "DEVICE_CAPABILITIES_REG ,Device Capabilities Register" bitfld.long 0x04 15. " PCIE_CAP_ROLE_BASED_ERR_REPORT ,Role based error reporting" "No error,Error" bitfld.long 0x04 5. " PCIE_CAP_EXT_TAG_SUPP ,Extended tag field support" "Not supported,Supported" textline " " bitfld.long 0x04 3.--4. " PCIE_CAP_PHANTOM_FUNC_SUPP ,Phantom functions support" "0,1,2,3" bitfld.long 0x04 0.--2. " PCIE_CAP_MAX_PAYLOAD_SIZE ,Max payload size" "0,1,2,3,4,5,6,7" else rgroup.long 0x00++0x07 line.long 0x00 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities ID Next Pointer Register" bitfld.long 0x00 25.--29. " PCIE_INT_MSG_NUM ,Interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " PCIE_SLOT_IMP ,Slot implemented" "Not valid,Valid" textline " " bitfld.long 0x00 20.--23. " PCIE_DEV_PORT_TYPE ,Device/Port type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " PCIE_CAP_REG ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " PCIE_CAP_NEXT_PTR ,Next item pointer" hexmask.long.byte 0x00 0.--7. 1. " PCIE_CAP_ID ,Capability ID" line.long 0x04 "DEVICE_CAPABILITIES_REG ,Device Capabilities Register" bitfld.long 0x04 15. " PCIE_CAP_ROLE_BASED_ERR_REPORT ,Role based error reporting" "No error,Error" bitfld.long 0x04 5. " PCIE_CAP_EXT_TAG_SUPP ,Extended tag field support" "Not supported,Supported" textline " " bitfld.long 0x04 3.--4. " PCIE_CAP_PHANTOM_FUNC_SUPP ,Phantom functions support" "0,1,2,3" bitfld.long 0x04 0.--2. " PCIE_CAP_MAX_PAYLOAD_SIZE ,Max payload size" "0,1,2,3,4,5,6,7" endif width 36. textline " " if (((per.l(ad:0x33c00000+0x74))&0x18)==0x00) group.long 0x08++0x03 line.long 0x00 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Status Register" rbitfld.long 0x00 21. "PCIE_CAP_TRANS_PEND ,Transactions pending" "Completed,Not completed" rbitfld.long 0x00 20. " PCIE_CAP_AUX_POWER_DET ,AUX power detected" "Not detected,Detected" textline " " eventfld.long 0x00 19. " PCIE_CAP_UNSUPP_REQ_DET ,Unsupported request detected" "Not detected,Detected" eventfld.long 0x00 18. " PCIE_CAP_FATAL_ERR_DET ,Fatal error detected" "Not detected,Detected" textline " " eventfld.long 0x00 17. " PCIE_CAP_NON_FATAL_ERR_DET ,Non-fatal error detected" "Not detected,Detected" eventfld.long 0x00 16. " PCIE_CAP_CORR_ERR_DET ,Correctable error detected" "Not detected,Detected" textline " " bitfld.long 0x00 15. " PCIE_CAP_INIT_FLR ,Initiate function level reset" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PCIE_CAP_MAX_READ_REQ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x00 11. " PCIE_CAP_EN_NO_SNOOP ,Enable no snoop" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_AUX_POWER_PM_EN ,Auxiliary power PM enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " PCIE_CAP_PHANTOM_FUNC_EN ,Phantom functions support" "Not supported,Supported" rbitfld.long 0x00 8. " PCIE_CAP_EXT_TAG_EN ,Extended tag field support" "Not supported,Supported" textline " " bitfld.long 0x00 5.--7. " PCIE_CAP_MAX_PAYLOAD_SIZE_CS ,Maximum payload size supported" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. " PCIE_CAP_EN_REL_ORDER ,Enable relaxed ordering" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_UNSUPPORT_REQ_REP_EN ,Unsupported request reporting enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_FATAL_ERR_REPORT_EN ,Fatal error reporting enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_NON_FATAL_ERR_REPORT_EN ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_CORR_ERR_REPORT_EN ,Correctable error reporting enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Status Register" rbitfld.long 0x00 21. "PCIE_CAP_TRANS_PEND ,Transactions pending" "Completed,Not completed" rbitfld.long 0x00 20. " PCIE_CAP_AUX_POWER_DET ,AUX power detected" "Not detected,Detected" textline " " eventfld.long 0x00 19. " PCIE_CAP_UNSUPP_REQ_DET ,Unsupported request detected" "Not detected,Detected" eventfld.long 0x00 18. " PCIE_CAP_FATAL_ERR_DET ,Fatal error detected" "Not detected,Detected" textline " " eventfld.long 0x00 17. " PCIE_CAP_NON_FATAL_ERR_DET ,Non-fatal error detected" "Not detected,Detected" eventfld.long 0x00 16. " PCIE_CAP_CORR_ERR_DET ,Correctable error detected" "Not detected,Detected" textline " " bitfld.long 0x00 15. " PCIE_CAP_INIT_FLR ,Initiate function level reset" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PCIE_CAP_MAX_READ_REQ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x00 11. " PCIE_CAP_EN_NO_SNOOP ,Enable no snoop" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_AUX_POWER_PM_EN ,Auxiliary power PM enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_PHANTOM_FUNC_EN ,Phantom functions support" "Not supported,Supported" bitfld.long 0x00 8. " PCIE_CAP_EXT_TAG_EN ,Extended tag field support" "Not supported,Supported" textline " " bitfld.long 0x00 5.--7. " PCIE_CAP_MAX_PAYLOAD_SIZE_CS ,Maximum payload size supported" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. " PCIE_CAP_EN_REL_ORDER ,Enable relaxed ordering" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_UNSUPPORT_REQ_REP_EN ,Unsupported request reporting enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_FATAL_ERR_REPORT_EN ,Fatal error reporting enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_NON_FATAL_ERR_REPORT_EN ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_CORR_ERR_REPORT_EN ,Correctable error reporting enable" "Disabled,Enabled" endif if (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "LINK_CAPABILITIES_REG,Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. "PCIE_CAP_PORT_NUM ,Port number" bitfld.long 0x00 22. " PCIE_CAP_ASPM_OPT_COMPL ,ASPM optionality compliance" "Not compliant,Compliant" textline " " bitfld.long 0x00 21. " PCIE_CAP_LINK_BW_NOT_CAP ,Link bandwidth notification capable" "0,1" rbitfld.long 0x00 20. " PCIE_CAP_DLL_ACTIVE_REP_CAP ,Data link layer link active reporting capable" "0,1" textline " " bitfld.long 0x00 19. " PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ,Surprise down error reporting capable" "0,1" rbitfld.long 0x00 18. " PCIE_CAP_CLK_POWER_MAN ,Clock power management" "0,1" textline " " rbitfld.long 0x00 15.--17. " PCIE_CAP_L1_EXIT_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 12.--14. " PCIE_CAP_L0S_EXIT_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 10.--11. " PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPP ,Level of ASPM support" "0,1,2,3" bitfld.long 0x00 4.--9. " PCIE_CAP_MAX_LINK_WIDTH ,Maximum link width supported by the port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0.--3. " PCIE_CAP_MAX_LINK_SPEED ,Maximum link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "LINK_CAPABILITIES_REG,Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. "PCIE_CAP_PORT_NUM ,Port number" bitfld.long 0x00 22. " PCIE_CAP_ASPM_OPT_COMPL ,ASPM optionality compliance" "Not compliant,Compliant" textline " " bitfld.long 0x00 21. " PCIE_CAP_LINK_BW_NOT_CAP ,Link bandwidth notification capable" "0,1" bitfld.long 0x00 20. " PCIE_CAP_DLL_ACTIVE_REP_CAP ,Data link layer link active reporting capable" "0,1" textline " " bitfld.long 0x00 19. " PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ,Surprise down error reporting capable" "0,1" bitfld.long 0x00 18. " PCIE_CAP_CLK_POWER_MAN ,Clock power management" "0,1" textline " " bitfld.long 0x00 15.--17. " PCIE_CAP_L1_EXIT_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " PCIE_CAP_L0S_EXIT_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 10.--11. " PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPP ,Level of ASPM support" "0,1,2,3" bitfld.long 0x00 4.--9. " PCIE_CAP_MAX_LINK_WIDTH ,Maximum link width supported by the port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0.--3. " PCIE_CAP_MAX_LINK_SPEED ,Maximum link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33c00000+0x7C))&0x100000)==0x100000)&&(((per.l(ad:0x33c00000+0x7C))&0x40000)==0x40000) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" bitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Current link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " bitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " bitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" bitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33c00000+0x7C))&0x100000)==0x100000)&&(((per.l(ad:0x33c00000+0x7C))&0x40000)==0x00) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" bitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Current link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " bitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" bitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33c00000+0x7C))&0x100000)==0x00)&&(((per.l(ad:0x33c00000+0x7C))&0x40000)==0x40000) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" bitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " rbitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " bitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" bitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33c00000+0x7C))&0x100000)==0x00)&&(((per.l(ad:0x33c00000+0x7C))&0x40000)==0x00) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" bitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " rbitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" bitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33c00000+0x7C))&0x100000)==0x100000)&&(((per.l(ad:0x33c00000+0x7C))&0x40000)==0x40000) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" rbitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " bitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " bitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" rbitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33c00000+0x7C))&0x100000)==0x100000)&&(((per.l(ad:0x33c00000+0x7C))&0x40000)==0x00) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" rbitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " bitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" rbitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33c00000+0x7C))&0x100000)==0x00)&&(((per.l(ad:0x33c00000+0x7C))&0x40000)==0x40000) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" rbitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Current link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " rbitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " bitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" rbitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33c00000+0x7C))&0x100000)==0x00)&&(((per.l(ad:0x33c00000+0x7C))&0x40000)==0x00) group.long 0x10++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register" eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" textline " " rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" rbitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" textline " " rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" textline " " rbitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" textline " " bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" textline " " bitfld.long 0x00 4. " PCIE_CAP_LINK_DIS ,Initiate link disable" "Enabled,Disabled" rbitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" textline " " bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" endif if (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01) group.long 0x14++0x03 line.long 0x00 "SLOT_CAPABILITIES_REG,Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM ,PHY slot number" bitfld.long 0x00 18. " PCIE_CAP_NO_CMD_CPL_SUPP ,No command completion support" "Not supported,Supported" textline " " bitfld.long 0x00 17. " PCIE_CAP_ELECTROMECH_INTERLOCK ,Electromechanical interlock present" "0,1" bitfld.long 0x00 15.--16. " PCIE_CAP_SLOT_POWER_LIMIT_SCALE ,Slot power limit scale" "1.0x,0.1x,0.01x,0.001x" textline " " hexmask.long.byte 0x00 7.--14. 1. " PCIE_CAP_SLOT_POWER_LIMIT_VAL ,Slot power limit value" bitfld.long 0x00 6. " PCIE_CAP_HOT_PLUG_CAPABLE ,Hot plug capable" "0,1" textline " " bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_SURPRISE ,Hot plug surprise possible" "0,1" bitfld.long 0x00 4. " PCIE_CAP_POWER_IND ,Power indicator present" "0,1" textline " " bitfld.long 0x00 3. " PCIE_CAP_ATT_IND ,Attention indicator present" "0,1" bitfld.long 0x00 2. " PCIE_CAP_MRL_SENSOR ,MRL present" "0,1" textline " " bitfld.long 0x00 1. " PCIE_CAP_POWER_CONTROLLER ,Power controller present" "0,1" bitfld.long 0x00 0. " PCIE_CAP_ATT_IND_BUTTON ,Attention button present" "0,1" else rgroup.long 0x14++0x03 line.long 0x00 "SLOT_CAPABILITIES_REG,Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM ,PHY slot number" bitfld.long 0x00 18. " PCIE_CAP_NO_CMD_CPL_SUPP ,No command completion support" "Not supported,Supported" textline " " bitfld.long 0x00 17. " PCIE_CAP_ELECTROMECH_INTERLOCK ,Electromechanical interlock present" "0,1" bitfld.long 0x00 15.--16. " PCIE_CAP_SLOT_POWER_LIMIT_SCALE ,Slot power limit scale" "1.0x,0.1x,0.01x,0.001x" textline " " hexmask.long.byte 0x00 7.--14. 1. " PCIE_CAP_SLOT_POWER_LIMIT_VAL ,Slot power limit value" bitfld.long 0x00 6. " PCIE_CAP_HOT_PLUG_CAPABLE ,Hot plug capable" "0,1" textline " " bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_SURPRISE ,Hot plug surprise possible" "0,1" bitfld.long 0x00 4. " PCIE_CAP_POWER_IND ,Power indicator present" "0,1" textline " " bitfld.long 0x00 3. " PCIE_CAP_ATT_IND ,Attention indicator present" "0,1" bitfld.long 0x00 2. " PCIE_CAP_MRL_SENSOR ,MRL present" "0,1" textline " " bitfld.long 0x00 1. " PCIE_CAP_POWER_CONTROLLER ,Power controller present" "0,1" bitfld.long 0x00 0. " PCIE_CAP_ATT_IND_BUTTON ,Attention button present" "0,1" endif if (((per.l(ad:0x33c00000+0x84))&0x40000)==0x40000) group.long 0x18++0x03 line.long 0x00 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register" eventfld.long 0x00 24. "PCIE_CAP_DLL_STATE_CHANGED ,DLL state changed" "Not changed,Changed" rbitfld.long 0x00 23. " PCIE_CAP_ELECTROMECH_INTERLOCK_STAT ,Electromechanical interlock status" "0,1" textline " " rbitfld.long 0x00 22. " PCIE_CAP_PRESENCE_DET_STATE ,Presence detect state" "Not detected,Detected" rbitfld.long 0x00 21. " PCIE_CAP_MRL_SENSOR_STATE ,MRL sensor state" "0,1" textline " " eventfld.long 0x00 20. " PCIE_CAP_CMD_CPLD ,Command completed" "0,1" eventfld.long 0x00 19. " PCIE_CAP_PRESENCE_DET_CHANGED ,Presence detect changed" "Not changed,Changed" textline " " eventfld.long 0x00 18. " PCIE_CAP_MRL_SENSOR_CHANGED ,MRL sensor changed" "Not changed,Changed" eventfld.long 0x00 17. " PCIE_CAP_POWER_FAULT_DET ,Power fault detect" "Not detected,Detected" textline " " eventfld.long 0x00 16. " PCIE_CAP_ATT_BUTTON_PRESSED ,Attention button pressed" "Not pressed,Pressed" bitfld.long 0x00 12. " PCIE_CAP_DLL_STATE_CHANGED_EN ,Data link layer state changed enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL ,Electromechanical interlock control" "No effect,Toggle" bitfld.long 0x00 10. " PCIE_CAP_POWER_CONTROLLER_CTRL ,Power controller control" "On,Off" textline " " bitfld.long 0x00 8.--9. " PCIE_CAP_POWER_IND_CTRL ,Power indicator control" ",On,Blink,On" bitfld.long 0x00 6.--7. " PCIE_CAP_ATT_IND_CTRL ,Attention indicator control" ",On,Blink,On" textline " " bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_INT_EN ,Hot plug indicator enable" "Disabled,Enabled" rbitfld.long 0x00 4. " PCIE_CAP_CMD_CPL_INT_EN ,Command CPL indicator enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_PRESENCE_DET_CHANGE_EN ,Presence detect changed enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SENSOR_CHANGED_EN ,Sensor changed enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_POWER_FAULT_DET_EN ,Power fault detect enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_ATT_BUTTON_PRESSED_EN ,Attention button pressed enable" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register" eventfld.long 0x00 24. "PCIE_CAP_DLL_STATE_CHANGED ,DLL state changed" "Not changed,Changed" rbitfld.long 0x00 23. " PCIE_CAP_ELECTROMECH_INTERLOCK_STAT ,Electromechanical interlock status" "0,1" textline " " rbitfld.long 0x00 22. " PCIE_CAP_PRESENCE_DET_STATE ,Presence detect state" "Not detected,Detected" rbitfld.long 0x00 21. " PCIE_CAP_MRL_SENSOR_STATE ,MRL sensor state" "0,1" textline " " eventfld.long 0x00 20. " PCIE_CAP_CMD_CPLD ,Command completed" "0,1" eventfld.long 0x00 19. " PCIE_CAP_PRESENCE_DET_CHANGED ,Presence detect changed" "Not changed,Changed" textline " " eventfld.long 0x00 18. " PCIE_CAP_MRL_SENSOR_CHANGED ,MRL sensor changed" "Not changed,Changed" eventfld.long 0x00 17. " PCIE_CAP_POWER_FAULT_DET ,Power fault detect" "Not detected,Detected" textline " " eventfld.long 0x00 16. " PCIE_CAP_ATT_BUTTON_PRESSED ,Attention button pressed" "Not pressed,Pressed" bitfld.long 0x00 12. " PCIE_CAP_DLL_STATE_CHANGED_EN ,Data link layer state changed enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL ,Electromechanical interlock control" "No effect,Toggle" bitfld.long 0x00 10. " PCIE_CAP_POWER_CONTROLLER_CTRL ,Power controller control" "On,Off" textline " " bitfld.long 0x00 8.--9. " PCIE_CAP_POWER_IND_CTRL ,Power indicator control" ",On,Blink,On" bitfld.long 0x00 6.--7. " PCIE_CAP_ATT_IND_CTRL ,Attention indicator control" ",On,Blink,On" textline " " bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_INT_EN ,Hot plug indicator enable" "Disabled,Enabled" bitfld.long 0x00 4. " PCIE_CAP_CMD_CPL_INT_EN ,Command CPL indicator enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_PRESENCE_DET_CHANGE_EN ,Presence detect changed enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SENSOR_CHANGED_EN ,Sensor changed enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_POWER_FAULT_DET_EN ,Power fault detect enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_ATT_BUTTON_PRESSED_EN ,Attention button pressed enable" "Disabled,Enabled" endif if (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33c00000+0x8C))&0x10000)==0x10000) group.long 0x1C++0x03 line.long 0x00 "ROOT_CONTROL_ROOT_CAPABILITIES,Root Control and Capabilities Register" bitfld.long 0x00 16. "PCIE_CAP_CRS_SW_VISIBILITY ,CRS software visibility capable" "0,1" bitfld.long 0x00 4. " PCIE_CAP_CRS_SW_VISIBILITY_EN ,Configuration request retry status (CRS) software visibility enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN ,PME interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN ,System error on fatal error enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN ,System error on correctable error enable" "Disabled,Enabled" elif (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33c00000+0x8C))&0x10000)==0x00) group.long 0x1C++0x03 line.long 0x00 "ROOT_CONTROL_ROOT_CAPABILITIES,Root Control and Capabilities Register" bitfld.long 0x00 16. "PCIE_CAP_CRS_SW_VISIBILITY ,CRS software visibility capable" "0,1" rbitfld.long 0x00 4. " PCIE_CAP_CRS_SW_VISIBILITY_EN ,Configuration request retry status (CRS) software visibility enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN ,PME interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN ,System error on fatal error enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN ,System error on correctable error enable" "Disabled,Enabled" elif (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33c00000+0x8C))&0x10000)==0x10000) group.long 0x1C++0x03 line.long 0x00 "ROOT_CONTROL_ROOT_CAPABILITIES,Root Control and Capabilities Register" rbitfld.long 0x00 16. "PCIE_CAP_CRS_SW_VISIBILITY ,CRS software visibility capable" "0,1" bitfld.long 0x00 4. " PCIE_CAP_CRS_SW_VISIBILITY_EN ,Configuration request retry status (CRS) software visibility enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN ,PME interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN ,System error on fatal error enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN ,System error on correctable error enable" "Disabled,Enabled" elif (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33c00000+0x8C))&0x10000)==0x00) group.long 0x1C++0x03 line.long 0x00 "ROOT_CONTROL_ROOT_CAPABILITIES,Root Control and Capabilities Register" rbitfld.long 0x00 16. "PCIE_CAP_CRS_SW_VISIBILITY ,CRS software visibility capable" "0,1" rbitfld.long 0x00 4. " PCIE_CAP_CRS_SW_VISIBILITY_EN ,Configuration request retry status (CRS) software visibility enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN ,PME interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN ,System error on fatal error enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN ,System error on correctable error enable" "Disabled,Enabled" endif group.long 0x20++0x03 line.long 0x00 "ROOT_STATUS_REG,Root Status Register" rbitfld.long 0x00 17. "PCIE_CAP_PME_PEND ,PME pending" "Not pending,Pending" eventfld.long 0x00 16. " PCIE_CAP_PME_STATUS ,PME status" "0,1" textline " " hexmask.long.word 0x00 0.--15. 1. " PCIE_CAP_PME_REQ_ID ,PME requester ID" rgroup.long 0x24++0x03 line.long 0x00 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 18.--19. "PCIE_CAP_OBFF_SUPPORT ,Optimized buffer flush/fill supported" "Not supported,Msg,WAKE# ,Both" bitfld.long 0x00 17. " PCIE_CAP2_10_BIT_TAG_ERQ_SUPPORT ,10-bit tag request supported" "Not supported,Supported" textline " " bitfld.long 0x00 16. " PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT ,10-bit tag completer supported" "Not supported,Supported" bitfld.long 0x00 13. " PCIE_CAP_TPH_CMPLT_SUPP_1 ,TPH completer supported bit 1" "0,1" textline " " bitfld.long 0x00 12. " PCIE_CAP_TPH_CMPLT_SUPP_0 ,TPH completer supported bit 0" "0,1" bitfld.long 0x00 11. " PCIE_CAP_LTR_SUPP ,LTR mechanism supported" "0,1" textline " " bitfld.long 0x00 10. " PCIE_CAP_NO_RO_EN_PR2PR_PAR ,No relaxed ordering enabled PR-PR passing" "0,1" bitfld.long 0x00 9. " PCIE_CAP_128_CAS_CPL_SUPP ,128 atomic CAS support" "Not supported,Supported" textline " " bitfld.long 0x00 8. " PCIE_CAP_64_ATOMIC_CPL_SUPP ,64 atomic support" "Not supported,Supported" bitfld.long 0x00 7. " PCIE_CAP_32_ATOMIC_CPL_SUPP ,32 atomic support" "Not supported,Supported" textline " " bitfld.long 0x00 6. " PCIE_CAP_ATOMIC_ROUTING_SUPP ,Atomic routing support" "Not supported,Supported" bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT ,ARI forward support" "Not supported,Supported" textline " " bitfld.long 0x00 4. " PCIE_CAP_CPL_TIMEOUT_DIS_SUPP ,Completion timeout disable support" "Not supported,Supported" bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_RANGE ,Completion timeout ranges supported" "A,B,A/B,,,,B/C,A/B/C,,,,,,,B/C/D,A/B/C/D" else bitfld.long 0x00 18.--19. "PCIE_CAP_OBFF_SUPPORT ,Optimized buffer flush/fill supported" "Not supported,Msg,WAKE#,Both" bitfld.long 0x00 14.--15. " PCIE_CAP2_LN_SYS_CLS ,LN system CLS" "0,1,2,3" textline " " bitfld.long 0x00 13. " PCIE_CAP_TPH_CMPLT_SUPP_1 ,TPH completer supported bit 1" "0,1" bitfld.long 0x00 12. " PCIE_CAP_TPH_CMPLT_SUPP_0 ,TPH completer supported bit 0" "0,1" textline " " bitfld.long 0x00 11. " PCIE_CAP_LTR_SUPP ,LTR mechanism supported" "0,1" bitfld.long 0x00 10. " PCIE_CAP_NO_RO_EN_PR2PR_PAR ,No relaxed ordering enabled PR-PR passing" "0,1" textline " " bitfld.long 0x00 9. " PCIE_CAP_128_CAS_CPL_SUPP ,128 atomic CAS support" "Not supported,Supported" bitfld.long 0x00 8. " PCIE_CAP_64_ATOMIC_CPL_SUPP ,64 atomic support" "Not supported,Supported" textline " " bitfld.long 0x00 7. " PCIE_CAP_32_ATOMIC_CPL_SUPP ,32 atomic support" "Not supported,Supported" bitfld.long 0x00 6. " PCIE_CAP_ATOMIC_ROUTING_SUPP ,Atomic routing support" "Not supported,Supported" textline " " bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT ,ARI forward support" "Not supported,Supported" bitfld.long 0x00 4. " PCIE_CAP_CPL_TIMEOUT_DIS_SUPP ,Completion timeout disable support" "Not supported,Supported" textline " " bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_RANGE ,Completion timeout ranges supported" "A,B,A/B,,,,B/C,A/B/C,,,,,,,B/C/D,A/B/C/D" endif group.long 0x28++0x03 line.long 0x00 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register" sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") bitfld.long 0x00 9. "PCIE_CAP_IDO_CPL_EN ,IDO completion enable" "Disabled,Enabled" bitfld.long 0x00 8. " PCIE_CAP_IDO_REQ_EN ,IDO request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT_CS ,ARI forwarding enable" "Disabled,Enabled" bitfld.long 0x00 4. " PCIE_CAP_CPL_TIMEOUT_DIS ,Completion timeout disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_VAL ,Completion timeout value" "50us to 50ms,50us to 100us,1ms to 10ms,,,16ms to 55ms,65ms to 210ms,,,260ms to 900ms,1s to 3.5s,,,4s to 13s,17s to 64s," else bitfld.long 0x00 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS ,ARI forwarding enable" "Disabled,Enabled" bitfld.long 0x00 4. " PCIE_CAP_CPL_TIMEOUT_DIS ,Completion timeout disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_VAL ,Completion timeout value" "50us to 50ms,50us to 100us,1ms to 10ms,,,16ms to 55ms,65ms to 210ms,,,260ms to 900ms,1s to 3.5s,,,4s to 13s,17s to 64s," endif rgroup.long 0x2C++0x03 line.long 0x00 "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register" sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") bitfld.long 0x00 31. "DRS_SUPPORTED ,DRS supported" "Not supported,Supported" bitfld.long 0x00 8. " PCIE_CAP_CROSS_LINK_SUPPORT ,Cross link support" "Not supported,Supported" textline " " hexmask.long.byte 0x00 1.--7. 1. " PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR ,Supported link speed vector" else bitfld.long 0x00 8. "PCIE_CAP_CROSS_LINK_SUPPORT ,Cross link support" "Not supported,Supported" hexmask.long.byte 0x00 1.--7. 1. " PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR ,Supported link speed vector" endif if (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01) group.long 0x30++0x03 line.long 0x00 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register" eventfld.long 0x00 31. "DRS_MESSAGE_RECEIVED ,DRS message received" "0,1" rbitfld.long 0x00 28.--30. " DOWNSTREAM_COMPO_PRESENCE ,Downstream component presence" "0,1,2,3,4,5,,?..." textline " " sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") bitfld.long 0x00 21. " PCIE_CAP_LINK_EQ_REQ ,Link equalization request 8.0GT/s" "Not requested,Requested" bitfld.long 0x00 20. " PCIE_CAP_EQ_CPL_P3 ,Equalization 8.0GT/s phase 3 successful" "Not successful,Successful" textline " " bitfld.long 0x00 19. " PCIE_CAP_EQ_CPL_P2 ,Equalization 8.0GT/s phase 2 successful" "Not successful,Successful" bitfld.long 0x00 18. " PCIE_CAP_EQ_CPL_P1 ,Equalization 8.0GT/s phase 1 successful" "Not successful,Successful" textline " " bitfld.long 0x00 17. " PCIE_CAP_EQ_CPL ,Equalization 8.0GT/s complete" "Not completed,Completed" rbitfld.long 0x00 16. " PCIE_CAP_CURR_DEEMPHASIS ,Current de-emphasis level" "-6dB,-3.5dB" textline " " else rbitfld.long 0x00 16. " PCIE_CAP_CURR_DEEMPHASIS ,Current de-emphasis level" "-6dB,-3.5dB" textline " " endif bitfld.long 0x00 12.--15. " PCIE_CAP_COMPLIANCE_PRESET ,Compliance preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " PCIE_CAP_COMPLIANCE_SOS ,Compliance SOS" "0,1" textline " " bitfld.long 0x00 10. " PCIE_CAP_ENTER_MODIFIED_COMPILANCE ,Enter modified compliance" "0,1" bitfld.long 0x00 7.--9. " PCIE_CAP_TX_MARGIN ,Controls transmit margin for debug or compliance" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6. " PCIE_CAP_SEL_DEEMPHASIS ,Controls selectable de-emphasis" "-3.5dB,-6dB" bitfld.long 0x00 5. " PCIE_CAP_HW_AUTO_SPEED_DISABLE ,Hardware autonomous speed disable" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " PCIE_CAP_ENTER_COMPLIANCE ,Enter compliance mode" "0,1" bitfld.long 0x00 0.--3. " PCIE_CAP_TARGET_LINK_SPEED ,Target link speed" ",0,1,2,3,4,5,6,,,,,,,,?..." else group.long 0x30++0x03 line.long 0x00 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register" eventfld.long 0x00 31. "DRS_MESSAGE_RECEIVED ,DRS message received" "0,1" rbitfld.long 0x00 28.--30. " DOWNSTREAM_COMPO_PRESENCE ,Downstream component presence" "0,1,2,3,4,5,6,7" textline " " sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") bitfld.long 0x00 21. " PCIE_CAP_LINK_EQ_REQ ,Link equalization request 8.0GT/s" "Not requested,Requested" bitfld.long 0x00 20. " PCIE_CAP_EQ_CPL_P3 ,Equalization 8.0GT/s phase 3 successful" "Not successful,Successful" textline " " bitfld.long 0x00 19. " PCIE_CAP_EQ_CPL_P2 ,Equalization 8.0GT/s phase 2 successful" "Not successful,Successful" bitfld.long 0x00 18. " PCIE_CAP_EQ_CPL_P1 ,Equalization 8.0GT/s phase 1 successful" "Not successful,Successful" textline " " bitfld.long 0x00 17. " PCIE_CAP_EQ_CPL ,Equalization 8.0GT/s complete" "Not completed,Completed" rbitfld.long 0x00 16. " PCIE_CAP_CURR_DEEMPHASIS ,Current de-emphasis level" "-6dB,-3.5dB" textline " " else rbitfld.long 0x00 16. " PCIE_CAP_CURR_DEEMPHASIS ,Current de-emphasis level" "-6dB,-3.5dB" textline " " endif bitfld.long 0x00 12.--15. " PCIE_CAP_COMPLIANCE_PRESET ,Compliance preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " PCIE_CAP_COMPLIANCE_SOS ,Compliance SOS" "0,1" textline " " bitfld.long 0x00 10. " PCIE_CAP_ENTER_MODIFIED_COMPILANCE ,Enter modified compliance" "0,1" bitfld.long 0x00 7.--9. " PCIE_CAP_TX_MARGIN ,Controls transmit margin for debug or compliance" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x00 6. " PCIE_CAP_SEL_DEEMPHASIS ,Controls selectable de-emphasis" "-3.5dB,-6dB" bitfld.long 0x00 5. " PCIE_CAP_HW_AUTO_SPEED_DISABLE ,Hardware autonomous speed disable" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " PCIE_CAP_ENTER_COMPLIANCE ,Enter compliance mode" "0,1" bitfld.long 0x00 0.--3. " PCIE_CAP_TARGET_LINK_SPEED ,Target link speed" ",0,1,2,3,4,5,6,,,,,,,,?..." endif base ad:0x33c00000+0x100 width 27. textline " " if (((per.l(ad:0x33c00000+0x8B4))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next capability offset" bitfld.long 0x00 16.--19. " CAP_VER ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " CAP_ID ,Capability ID" else rgroup.long 0x00++0x03 line.long 0x00 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VER ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " CAP_ID ,AER extended capability ID" endif group.long 0x04++0x03 line.long 0x00 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register" eventfld.long 0x00 25. " TLP_PRFX_BLOCKED_ERR_STAT ,TLP_PRFX blocked error status" "No error,Error" eventfld.long 0x00 22. " INTERNAL_ERR_STATUS ,Uncorrectable internal error status" "No error,Error" textline " " eventfld.long 0x00 20. " UNSUPPORTED_REQ_ERR_STAT ,Unsupported request error status" "No error,Error" eventfld.long 0x00 19. " ECRC_ERR_STAT ,ECRC error status" "No error,Error" textline " " eventfld.long 0x00 18. " MALF_TLP_ERR_STATUS ,Malformed TLP error status" "No error,Error" eventfld.long 0x00 17. " REC_OVRFLOW_ERR_STATUS ,Receiver overflow status" "No overflow,Overflow" textline " " eventfld.long 0x00 16. " UNEXP_CMPLT_ERR_STATUS ,Unexpected completion error status" "No error,Error" eventfld.long 0x00 15. " CMPLT_ABORT_ERR_STATUS ,Completer abort error status" "No error,Error" textline " " eventfld.long 0x00 14. " CMPLT_TIMEOUT_ERR_STATUS ,Completion timeout error status" "No timeout,Timeout" eventfld.long 0x00 13. " FC_PROTOCOL_ERR_STATUS ,Flow control protocol error status" "No error,Error" textline " " eventfld.long 0x00 12. " POIS_TLP_ERR_STATUS ,Poisoned TLP receive status" "No error,Error" eventfld.long 0x00 5. " SURPRISE_DOWN_ERR_STATUS ,Surprise down error status" "No error,Error" textline " " eventfld.long 0x00 4. " DL_PROTOCOL_ERR_STATUS ,Data link protocol error status" "No error,Error" if (((per.l(ad:0x33c00000+0x8BC))&0x80000)==0x80000) group.long 0x08++0x07 line.long 0x00 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register" bitfld.long 0x00 25. " TLP_PRFX_BLOCKED_ERR_MASK ,TLP prefix blocked error mask" "Not masked,Masked" bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_MASK ,AtomicOp blocked mask" "Not masked,Masked" textline " " bitfld.long 0x00 22. " INTERNAL_ERR_MASK ,Internal error mask" "Not masked,Masked" bitfld.long 0x00 20. " UNSUPPORTED_REQ_ERR_MASK ,Unsupported request error mask" "Not masked,Masked" textline " " bitfld.long 0x00 19. " ECRC_ERR_MASK ,ECRC error mask" "Not masked,Masked" bitfld.long 0x00 18. " MALF_TLP_ERR_MASK ,Malformed TLP mask" "Not masked,Masked" textline " " bitfld.long 0x00 17. " REC_OVERFLOW_ERR_MASK ,Receiver overflow error mask" "Not masked,Masked" bitfld.long 0x00 16. " UNEXP_CMPLT_ERR_MASK ,Unexpected completion mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " CMPLT_ABORT_ERR_MASK ,Completer abort error mask" "Not masked,Masked" bitfld.long 0x00 14. " CMPLT_TIMEOUT_ERR_MASK ,Completion timeout error mask" "Not masked,Masked" textline " " bitfld.long 0x00 13. " FC_PROTOCOL_ERR_MASK ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x00 12. " POIS_TLP_ERR_ERR_MASK ,Poisoned TLP error mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " SURPRISE_DOWN_ERR_MASK ,Surprise down error mask" "Not masked,Masked" bitfld.long 0x00 4. " DL_PROTOCOL_ERR_MASK ,Data link protocol error mask" "Not masked,Masked" line.long 0x04 "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register" bitfld.long 0x04 25. " TLP_PRFX_BLOCKED_ERR_SEVERITY ,TLP prefix blocked error severity" "Not occurred,Occurred" bitfld.long 0x04 24. " ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY ,ATOMIC_EGRESS blocked error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 22. " INTERNAL_ERR_SEVEVERITY ,Internal error severity" "Not occurred,Occurred" bitfld.long 0x04 20. " UNSUPP_REQ_ERR_SEV ,Unsupported request error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 19. " ECRC_ERR_SEVERITY ,ECRC error severity" "Not occurred,Occurred" bitfld.long 0x04 18. " MALF_TLP_ERR_SEV ,Malformed TLP severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 17. " REC_OVRF_ERR_SEVERITY ,Received overflow error severity" "Not occurred,Occurred" bitfld.long 0x04 16. " UNEXP_CMPLT_ERR_SEVERITY ,Unexpected completion error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 15. " CMPLT_ABORT_ERR_SEVERITY ,Completer abort error severity" "Not occurred,Occurred" bitfld.long 0x04 14. " CMPLT_TIMEOUT_ERR_SEVERITY ,Completion timeout error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 13. " FC_PROTOCOL_ERR_SEVERITY ,Flow control protocol error severity" "Not occurred,Occurred" bitfld.long 0x04 12. " POIS_TLP_ERR_ERR_SEVERITY ,Poisoned TLP error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 5. " SUR_DWN_ERR_SEVERITY ,SUR_DWN error severity" "Not occurred,Occurred" bitfld.long 0x04 4. " DL_PROTOCOL_ERR_SEVERITY ,Data link protocol error severity" "Not occurred,Occurred" else group.long 0x08++0x07 line.long 0x00 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register" bitfld.long 0x00 25. " TLP_PRFX_BLOCKED_ERR_MASK ,TLP prefix blocked error mask" "Not masked,Masked" bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_MASK ,AtomicOp blocked mask" "Not masked,Masked" textline " " bitfld.long 0x00 22. " INTERNAL_ERR_MASK ,Internal error mask" "Not masked,Masked" bitfld.long 0x00 20. " UNSUPPORTED_REQ_ERR_MASK ,Unsupported request error mask" "Not masked,Masked" textline " " bitfld.long 0x00 19. " ECRC_ERR_MASK ,ECRC error mask" "Not masked,Masked" bitfld.long 0x00 18. " MALF_TLP_ERR_MASK ,Malformed TLP mask" "Not masked,Masked" textline " " bitfld.long 0x00 17. " REC_OVERFLOW_ERR_MASK ,Receiver overflow error mask" "Not masked,Masked" bitfld.long 0x00 16. " UNEXP_CMPLT_ERR_MASK ,Unexpected completion mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " CMPLT_ABORT_ERR_MASK ,Completer abort error mask" "Not masked,Masked" bitfld.long 0x00 14. " CMPLT_TIMEOUT_ERR_MASK ,Completion timeout error mask" "Not masked,Masked" textline " " bitfld.long 0x00 13. " FC_PROTOCOL_ERR_MASK ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x00 12. " POIS_TLP_ERR_ERR_MASK ,Poisoned TLP error mask" "Not masked,Masked" textline " " rbitfld.long 0x00 5. " SURPRISE_DOWN_ERR_MASK ,Surprise down error mask" "Not masked,Masked" bitfld.long 0x00 4. " DL_PROTOCOL_ERR_MASK ,Data link protocol error mask" "Not masked,Masked" line.long 0x04 "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register" bitfld.long 0x04 25. " TLP_PRFX_BLOCKED_ERR_SEVERITY ,TLP prefix blocked error severity" "Not occurred,Occurred" bitfld.long 0x04 24. " ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY ,ATOMIC_EGRESS blocked error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 22. " INTERNAL_ERR_SEVEVERITY ,Internal error severity" "Not occurred,Occurred" bitfld.long 0x04 20. " UNSUPP_REQ_ERR_SEV ,Unsupported request error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 19. " ECRC_ERR_SEVERITY ,ECRC error severity" "Not occurred,Occurred" bitfld.long 0x04 18. " MALF_TLP_ERR_SEV ,Malformed TLP severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 17. " REC_OVRF_ERR_SEVERITY ,Received overflow error severity" "Not occurred,Occurred" bitfld.long 0x04 16. " UNEXP_CMPLT_ERR_SEVERITY ,Unexpected completion error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 15. " CMPLT_ABORT_ERR_SEVERITY ,Completer abort error severity" "Not occurred,Occurred" bitfld.long 0x04 14. " CMPLT_TIMEOUT_ERR_SEVERITY ,Completion timeout error severity" "Not occurred,Occurred" textline " " bitfld.long 0x04 13. " FC_PROTOCOL_ERR_SEVERITY ,Flow control protocol error severity" "Not occurred,Occurred" bitfld.long 0x04 12. " POIS_TLP_ERR_ERR_SEVERITY ,Poisoned TLP error severity" "Not occurred,Occurred" textline " " rbitfld.long 0x04 5. " SUR_DWN_ERR_SEVERITY ,SUR_DWN error severity" "Not occurred,Occurred" bitfld.long 0x04 4. " DL_PROTOCOL_ERR_SEVERITY ,Data link protocol error severity" "Not occurred,Occurred" endif group.long 0x10++0x0B line.long 0x00 "CORR_ERR_STATUS_OFF,Correctable Error Status Register" eventfld.long 0x00 15. " HEADER_LOG_OVERFLOW_STATUS ,Header log overflow error status" "Not occurred,Occurred" eventfld.long 0x00 14. " CORRECTED_INT_ERR_STATUS ,Corrected internal error status" "Not occurred,Occurred" textline " " eventfld.long 0x00 13. " ADV_NON_FATAL_ERR_STATUS ,Advisory non-fatal error status" "Not occurred,Occurred" eventfld.long 0x00 12. " RPL_TIMER_TIMEOUT_STATUS ,Replay timer timeout status" "Not occurred,Occurred" textline " " eventfld.long 0x00 8. " RPL_NO_ROLLOVER_STATUS ,Replay number rollover status" "Not occurred,Occurred" eventfld.long 0x00 7. " BAD_DLLP_STATUS ,Bad DLLP status" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " BAD_TLP_STATUS ,Bad TLP status" "Not occurred,Occurred" eventfld.long 0x00 0. " RX_ERR_STATUS ,Receiver error status" "Not occurred,Occurred" line.long 0x04 "CORR_ERR_MASK_OFF,Correctable Error Mask Register" bitfld.long 0x04 15. " HEADER_LOG_OVERFLOW_MASK ,Header log overflow error mask" "Not occurred,Occurred" bitfld.long 0x04 14. " CORRECTED_INT_ERR_MASK ,Corrected internal error mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " ADVISORY_NON_FATAL_ERR_MASK ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x04 12. " RPL_TIMER_TIMEOUT_MASK ,Replay timer timeout mask" "Not masked,Masked" textline " " bitfld.long 0x04 8. " RPL_NO_ROLLOVER_MASK ,Replay number rollover mask" "Not masked,Masked" bitfld.long 0x04 7. " BAD_DLLP_MASK ,Bad DLLP mask" "Not masked,Masked" textline " " bitfld.long 0x04 6. " BAD_TLP_MASK ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x04 0. " RX_ERR_MASK ,Receiver error mask" "Not masked,Masked" line.long 0x08 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register" rbitfld.long 0x08 10. " MULTIPLE_HEADER_EN ,Multiple header recording enable" "Disabled,Enabled" rbitfld.long 0x08 9. " MULTIPLE_HEADER_CAP ,Multiple header recording capable" "Not capable,Capable" textline " " bitfld.long 0x08 8. " ECRC_CHECK_EN ,ECRC check enable" "Disabled,Enabled" rbitfld.long 0x08 7. " ECRC_CHECK_CAP ,ECRC check capable" "Not capable,Capable" textline " " bitfld.long 0x08 6. " ECRC_GEN_EN ,ECRC generation enable" "Disabled,Enabled" textline " " rbitfld.long 0x08 5. " ECRC_GEN_CAP ,ECRC generation capable" "Not capable,Capable" rbitfld.long 0x08 0.--4. " FIRST_ERR_POINTER ,First error pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1C++0x0F line.long 0x00 "HDR_LOG_0_OFF,Header Log Register 0" hexmask.long.byte 0x00 24.--31. 1. " FIRST_DWORD_FOURTH_BYTE ,Byte 3 of header log register of first 32 bit data word" hexmask.long.byte 0x00 16.--23. 1. " FIRST_DWORD_THIRD_BYTE ,Byte 2 of header log register of first 32 bit data word" textline " " hexmask.long.byte 0x00 8.--15. 1. " FIRST_DWORD_SECOND_BYTE ,Byte 1 of header log register of first 32 bit data word" hexmask.long.byte 0x00 0.--7. 1. " FIRST_DWORD_FIRST_BYTE_BYTE ,Byte 0 of header log register of first 32 bit data word" line.long 0x04 "HDR_LOG_1_OFF,Header Log Register 1" hexmask.long.byte 0x04 24.--31. 1. " SECOND_DWORD_FOURTH_BYTE ,Byte 3 of header log register of second 32 bit data word" hexmask.long.byte 0x04 16.--23. 1. " SECOND_DWORD_THIRD_BYTE ,Byte 2 of header log register of second 32 bit data word" textline " " hexmask.long.byte 0x04 8.--15. 1. " SECOND_DWORD_SECOND_BYTE ,Byte 1 of header log register of second 32 bit data word" hexmask.long.byte 0x04 0.--7. 1. " SECOND_DWORD_FIRST_BYTE ,Byte 0 of header log register of second 32 bit data word" line.long 0x08 "HDR_LOG_2_OFF,Header Log Register 2" hexmask.long.byte 0x08 24.--31. 1. " THIRD_DWORD_FOURTH_BYTE ,Byte 3 of header log register of third 32 bit data word" hexmask.long.byte 0x08 16.--23. 1. " THIRD_DWORD_THIRD_BYTE ,Byte 2 of header log register of third 32 bit data word" textline " " hexmask.long.byte 0x08 8.--15. 1. " THIRD_DWORD_SECOND_BYTE ,Byte 1 of header log register of third 32 bit data word" hexmask.long.byte 0x08 0.--7. 1. " THIRD_DWORD_FIRST_BYTE ,Byte 0 of header log register of third 32 bit data word" line.long 0x0C "HDR_LOG_3_OFF,Header Log Register 3" hexmask.long.byte 0x0C 24.--31. 1. " FOURTH_DWORD_FOURTH_BYTE ,Byte 3 of header log register of fourth 32 bit data word" hexmask.long.byte 0x0C 16.--23. 1. " FOURTH_DWORD_THIRD_BYTE ,Byte 2 of header log register of fourth 32 bit data word" textline " " hexmask.long.byte 0x0C 8.--15. 1. " FOURTH_DWORD_SECOND_BYTE ,Byte 1 of header log register of fourth 32 bit data word" hexmask.long.byte 0x0C 0.--7. 1. " FOURTH_DWORD_FIRST_BYTE ,Byte 0 of header log register of fourth 32 bit data word" group.long 0x2C++0x03 line.long 0x00 "ROOT_ERR_CMD_OFF,Root Error Command Register" bitfld.long 0x00 2. " FATAL_ERR_REPORTING_EN ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NON_FATAL_ERR_REPORTING_EN ,Non-fatal error reporting enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CORR_ERR_REPORTING_EN ,Correctable error reporting enable" "Disabled,Enabled" if (((per.l(ad:0x33c00000+0x8B4))&0x01)==0x01) group.long 0x30++0x03 line.long 0x00 "ROOT_ERR_STATUS_OFF,Root Error Status Register" bitfld.long 0x00 27.--31. " ADV_ERR_INT_MSG_NUM ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x00 6. " FATAL_ERR_MSG_RX ,Fatal error messages received" "Not received,Received" textline " " eventfld.long 0x00 5. " NON_FATAL_ERR_MSG_RX ,Non-fatal error messages received" "Not received,Received" eventfld.long 0x00 4. " FIRST_UNCORR_FATAL ,First uncorrectable fatal" "Not received,Received" textline " " eventfld.long 0x00 3. " MUL_ERR_FATAL_NON_FATAL_RX ,Multiple fatal or non-fatal errors received" "Not received,Received" eventfld.long 0x00 2. " ERR_FATAL_NON_FATAL_RX ,Fatal or non-fatal errors received" "Not received,Received" textline " " eventfld.long 0x00 1. " MUL_ERR_COR_RX ,Multiple correctable errors received" "Not received,Received" eventfld.long 0x00 0. " ERR_COR_RX ,Correctable error received received" "Not received,Received" else group.long 0x30++0x03 line.long 0x00 "ROOT_ERR_STATUS_OFF,Root Error Status Register" rbitfld.long 0x00 27.--31. " ADV_ERR_INT_MSG_NUM ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x00 6. " FATAL_ERR_MSG_RX ,Fatal error messages received" "Not received,Received" textline " " eventfld.long 0x00 5. " NON_FATAL_ERR_MSG_RX ,Non-fatal error messages received" "Not received,Received" eventfld.long 0x00 4. " FIRST_UNCORR_FATAL ,First uncorrectable fatal" "Not received,Received" textline " " eventfld.long 0x00 3. " MUL_ERR_FATAL_NON_FATAL_RX ,Multiple fatal or non-fatal errors received" "Not received,Received" eventfld.long 0x00 2. " ERR_FATAL_NON_FATAL_RX ,Fatal or non-fatal errors received" "Not received,Received" textline " " eventfld.long 0x00 1. " MUL_ERR_COR_RX ,Multiple correctable errors received" "Not received,Received" eventfld.long 0x00 0. " ERR_COR_RX ,Correctable error received received" "Not received,Received" endif rgroup.long 0x34++0x13 line.long 0x00 "ERR_SRC_ID_OFF,Error Source Identification Register" hexmask.long.word 0x00 16.--31. 1. " ERR_FATAL_NON_FATAL_SOURCE_ID ,Source of fatal/non-fatal error" hexmask.long.word 0x00 0.--15. 1. " ERR_COR_SOURCE_ID ,Source of correctable error" line.long 0x04 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1" hexmask.long.byte 0x04 24.--31. 1. " CFG_TLP_PFX_LOG_1_FOURTH_BYTE ,Byte 3 of error TLP prefix log 1" hexmask.long.byte 0x04 16.--23. 1. " CFG_TLP_PFX_LOG_1_THIRD_BYTE ,Byte 2 of error TLP prefix log 1" textline " " hexmask.long.byte 0x04 8.--15. 1. " CFG_TLP_PFX_LOG_1_SECOND_BYTE ,Byte 1 of error TLP prefix log 1" hexmask.long.byte 0x04 0.--7. 1. " CFG_TLP_PFX_LOG_1_FIRST_BYTE ,Byte 0 of error TLP prefix log 1" line.long 0x08 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2" hexmask.long.byte 0x08 24.--31. 1. " CFG_TLP_PFX_LOG_2_FOURTH_BYTE ,Byte 3 of error TLP prefix log 2" hexmask.long.byte 0x08 16.--23. 1. " CFG_TLP_PFX_LOG_2_THIRD_BYTE ,Byte 2 of error TLP prefix log 2" textline " " hexmask.long.byte 0x08 8.--15. 1. " CFG_TLP_PFX_LOG_2_SECOND_BYTE ,Byte 1 of error TLP prefix log 2" hexmask.long.byte 0x08 0.--7. 1. " CFG_TLP_PFX_LOG_2_FIRST_BYTE ,Byte 0 of error TLP prefix log 2" line.long 0x0C "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3" hexmask.long.byte 0x0C 24.--31. 1. " CFG_TLP_PFX_LOG_3_FOURTH_BYTE ,Byte 3 of error TLP prefix log 3" hexmask.long.byte 0x0C 16.--23. 1. " CFG_TLP_PFX_LOG_3_THIRD_BYTE ,Byte 2 of error TLP prefix log 3" textline " " hexmask.long.byte 0x0C 8.--15. 1. " CFG_TLP_PFX_LOG_3_SECOND_BYTE ,Byte 1 of error TLP prefix log 3" hexmask.long.byte 0x0C 0.--7. 1. " CFG_TLP_PFX_LOG_3_FIRST_BYTE ,Byte 0 of error TLP prefix log 3" line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4" hexmask.long.byte 0x10 24.--31. 1. " CFG_TLP_PFX_LOG_4_FOURTH_BYTE ,Byte 3 of error TLP prefix log 4" hexmask.long.byte 0x10 16.--23. 1. " CFG_TLP_PFX_LOG_4_THIRD_BYTE ,Byte 2 of error TLP prefix log 4" textline " " hexmask.long.byte 0x10 8.--15. 1. " CFG_TLP_PFX_LOG_4_SECOND_BYTE ,Byte 1 of error TLP prefix log 4" hexmask.long.byte 0x10 0.--7. 1. " CFG_TLP_PFX_LOG_4_FIRST_BYTE ,Byte 0 of error TLP prefix log 4" base ad:0x33c00000+0x148 sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") if (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VERSION ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,L1SUB Extended capability ID" else rgroup.long 0x00++0x03 line.long 0x00 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VER ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " EX_CAP_ID ,Extended capability ID" endif group.long 0x04++0x0B line.long 0x00 "L1SUB_CAPABILITY_REG,L1 Substates Capability Header" bitfld.long 0x00 19.--23. " PWR_ON_VALUE_SUPPORT ,Port T power on value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " PWR_ON_SCALE_SUPPORT ,Port T power on scale" "2us,10us,100us,?..." textline " " hexmask.long.byte 0x00 8.--15. 1. " COME_MODE_SUPPORT ,Port common mode restore time" bitfld.long 0x00 4. " L1_PMSUB_SUPPORT ,L1 PM substates ECN supported" "Not supported,Supported" textline " " bitfld.long 0x00 3. " L1_1_ASPM_SUPPORT ,ASPM L11 supported" "Not supported,Supported" bitfld.long 0x00 2. " L1_2_ASPM_SUPPORT ,ASPM L12 supported" "Not supported,Supported" textline " " bitfld.long 0x00 1. " L1_1_PCI_PM_SUPPORT ,ASPM L11 supported" "Not supported,Supported" bitfld.long 0x00 0. " L1_2_PCI_PM_SUPPORT ,ASPM L12 supported" "Not supported,Supported" line.long 0x04 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register" bitfld.long 0x04 29.--31. " L1_2_TH_SCA ,LTR L12 Threshold Scale" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 16.--25. 1. " L1_2_TH_VAL ,LTR L12 Threshold Value" textline " " hexmask.long.byte 0x04 8.--15. 1. " T_COMMON_MODE ,Common mode restore time" bitfld.long 0x04 3. " L1_1_ASPM_EN ,ASPM L11 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " L1_2_ASPM_EN ,ASPM L12 Enable" "Disabled,Enabled" bitfld.long 0x04 1. " L1_1_PCIPM_EN ,PCI_PM L11 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " L1_2_PCIPM_EN ,PCI_PM L12 Enable" "Disabled,Enabled" line.long 0x08 "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register" bitfld.long 0x08 3.--7. " T_POWER_ON_VALUE ,T power on value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--1. " T_POWER_ON_SCALE ,T power on scale" "2us,10us,100us,?..." else rgroup.long 0x00++0x03 line.long 0x00 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VERSION ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,L1SUB Extended capability ID" group.long 0x04++0x07 line.long 0x00 "LINK_CONTROL3_REG,Link Control 3 Register" bitfld.long 0x00 1. " EQ_REQ_INT_EN ,Link equalization request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PERFORM_EQ ,Perform equalization" "Not performed,Performed" line.long 0x04 "LANE_ERR_STATUS_REG,Lane Error Status Register" eventfld.long 0x04 1. " LANE1_ERR_STATUS ,Lane 1 error status bit" "No error,Error" eventfld.long 0x04 0. " LANE0_ERR_STATUS ,Lane 0 error status bit" "No error,Error" rgroup.long 0x0C++0x03 line.long 0x00 "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register For Lanes 1 And 0" bitfld.long 0x00 28.--30. " USP_RX_PRESET_HINT1 ,Upstream port 8.0GT/s receiver preset hint 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--27. " USP_TX_PRESET1 ,Upstream port 8.0GT/s transmitter preset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--22. " DSP_RX_PRESET_HINT1 ,Downstream port 8.0GT/s receiver preset hint 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " DSP_TX_PRESET1 ,Downstream port 8.0GT/s transmitter preset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--14. " USP_RX_PRESET_HINT0 ,Upstream port 8.0GT/s receiver preset hint 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " USP_TX_PRESET0 ,Upstream port 8.0GT/s transmitter preset 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--6. " DSP_RX_PRESET_HINT0 ,Downstream port 8.0GT/s receiver preset hint 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " DSP_TX_PRESET0 ,Downstream port 8.0GT/s transmitter preset 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") base ad:0x33c00000+0x168 if (((per.l(ad:0x33c00000+0x8BC))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VERSION ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,L1SUB Extended capability ID" else rgroup.long 0x00++0x03 line.long 0x00 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VER ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " EX_CAP_ID ,Extended capability ID" endif group.long 0x04++0x0B line.long 0x00 "L1SUB_CAPABILITY_REG,L1 Substates Capability Header" bitfld.long 0x00 19.--23. " PWR_ON_VALUE_SUPPORT ,Port T power on value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " PWR_ON_SCALE_SUPPORT ,Port T power on scale" "2us,10us,100us,?..." textline " " hexmask.long.byte 0x00 8.--15. 1. " COME_MODE_SUPPORT ,Port common mode restore time" bitfld.long 0x00 4. " L1_PMSUB_SUPPORT ,L1 PM substates ECN supported" "Not supported,Supported" textline " " bitfld.long 0x00 3. " L1_1_ASPM_SUPPORT ,ASPM L11 supported" "Not supported,Supported" bitfld.long 0x00 2. " L1_2_ASPM_SUPPORT ,ASPM L12 supported" "Not supported,Supported" textline " " bitfld.long 0x00 1. " L1_1_PCI_PM_SUPPORT ,ASPM L11 supported" "Not supported,Supported" bitfld.long 0x00 0. " L1_2_PCI_PM_SUPPORT ,ASPM L12 supported" "Not supported,Supported" line.long 0x04 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register" bitfld.long 0x04 29.--31. " L1_2_TH_SCA ,LTR L12 Threshold Scale" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 16.--25. 1. " L1_2_TH_VAL ,LTR L12 Threshold Value" textline " " hexmask.long.byte 0x04 8.--15. 1. " T_COMMON_MODE ,Common mode restore time" bitfld.long 0x04 3. " L1_1_ASPM_EN ,ASPM L11 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " L1_2_ASPM_EN ,ASPM L12 Enable" "Disabled,Enabled" bitfld.long 0x04 1. " L1_1_PCIPM_EN ,PCI_PM L11 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " L1_2_PCIPM_EN ,PCI_PM L12 Enable" "Disabled,Enabled" line.long 0x08 "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register" bitfld.long 0x08 3.--7. " T_POWER_ON_VALUE ,T power on value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--1. " T_POWER_ON_SCALE ,T power on scale" "2us,10us,100us,?..." endif base ad:0x33c00000+0x700 group.long 0x00++0x27 line.long 0x00 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register" hexmask.long.word 0x00 16.--31. 1. " REPLAY_TIME_LIMIT ,Replay timer limit" hexmask.long.word 0x00 0.--15. 1. " ROUND_TRIP_LATENCY_TIME_LIMIT ,Ack latency timer limit" line.long 0x04 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register" line.long 0x08 "PORT_FORCE_OFF,Port Force Link Register" sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") hexmask.long.byte 0x08 24.--31. 1. " CPL_SENT_COUNT ,Low power entrance count" bitfld.long 0x08 16.--21. " LINK_STATE ,Forced LTSSM state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else bitfld.long 0x08 23. " DO_DESKEW_FOR_SRIS ,Use the transitions from TS2 to logical idle symbol" "0,1" bitfld.long 0x08 16.--21. " LINK_STATE ,Forced LTSSM state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif textline " " bitfld.long 0x08 15. " FORCE_EN ,Force link" "Disabled,Enabled" bitfld.long 0x08 8.--11. " FORCED_LTSSM ,Forced link command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x08 0.--7. 1. " LINK_NUM ,Link number" line.long 0x0C "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register" bitfld.long 0x0C 30. " ENTER_ASPM ,ASPM L1 entry control" "Not entered,Entered" bitfld.long 0x0C 27.--29. " L1_ENTRANCE_LAT ,L1 entrance latency" "1 us,2 us,4 us,8 us,16 us,32 us,64 us,64 us" textline " " bitfld.long 0x0C 24.--26. " L0S_ENTRANCE_LAT ,L0s entrance latency" "1 us,2 us,3 us,4 us,5 us,6 us,7 us,7 us" hexmask.long.byte 0x0C 16.--23. 1. " COMMON_CLK_N_FTS ,Common clock N_FTS" textline " " hexmask.long.byte 0x0C 8.--15. 1. " ACK_N_FTS ,Number of fast training sequence" hexmask.long.byte 0x0C 0.--7. 1. " ACK_FREQ ,Ack frequency" line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register" bitfld.long 0x10 16.--21. " LINK_CAPABLE ,Link mode enable" ",x1,,x2,,,,x4,,,,,,,,x8,,,,,,,,,,,,,,,,x16,?..." bitfld.long 0x10 7. " FAST_LINK_MODE ,Fast link mode" "No effect,Internal timers in fast mode" textline " " bitfld.long 0x10 5. " DLL_LINK_EN ,DLL link enable" "Disabled,Enabled" bitfld.long 0x10 3. " RST_ASSERT ,Reset assert" "No reset,Reset" textline " " bitfld.long 0x10 2. " LP_EN ,Loopback enable" "No reset,Reset" bitfld.long 0x10 1. " SCRAMBLE_DISABLE ,Scramble disable" "Enabled,Disabled" textline " " bitfld.long 0x10 0. " VENDOR_SPECIFIC_DLLP_REQ ,Vendor specific DLLP request" "Not requested,Requested" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x14 31. " DISABLE_LANE_TO_LANE_DESKEW ,Disable lane-to-lane deskew" "Enabled,Disabled" bitfld.long 0x14 27.--30. " IMPLEMENT_NUM_LANES ,Number of lanes" "1 lane,2 lane,,4 lane,,,,8 lane,,,,,,,,16 lane" textline " " bitfld.long 0x14 26. " GEN34_ELASTIC_BUFFER_MODE ,Select elasticity buffer operating mode in ge3 or gen4" "Half full,Empty" bitfld.long 0x14 25. " ACK_NAK_DISABLE ,Ack/nak disable" "Enabled,Disabled" else bitfld.long 0x14 31. " DISABLE_LANE_TO_LANE_DESKEW ,Disable lane-to-lane deskew" "Enabled,Disabled" bitfld.long 0x14 25. " ACK_NAK_DISABLE ,Ack/nak disable" "Enabled,Disabled" endif textline " " bitfld.long 0x14 24. " FLOW_CTRL_DISABLE ,Flow control disable" "Enabled,Disabled" hexmask.long.tbyte 0x14 0.--23. 1. " INSERT_LANE_SKEW ,Insert lane skew for transmit" line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register" bitfld.long 0x18 29.--30. " FAST_LINK_SCALING_FACTOR ,Fast link timer scaling factor" "1024,256,64,16" bitfld.long 0x18 19.--23. " TIMER_MOD_ACK_NAK ,Ack latency timer modifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x18 14.--18. " TIMER_MOD_REPLAY_TIMER ,Replay timer limit modifier" "Not modified,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x18 0.--7. 1. " MAX_FUNC_NUM ,Maximum function number" line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register" bitfld.long 0x1C 31. " CX_FLT_MASK_RC_CFG_DISCARD ,RC CFG discard mask" "Not masked,Masked" bitfld.long 0x1C 30. " CX_FLT_MASK_RC_IO_DISCARD ,RC IO discard mask" "Not masked,Masked" textline " " bitfld.long 0x1C 29. " CX_FLT_MASK_MSG_DROP ,Drop MSG TLP mask" "Not masked,Masked" bitfld.long 0x1C 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,Mask discarding completions with ECRC errors" "Not masked,Masked" textline " " bitfld.long 0x1C 27. " CX_FLT_MASK_ECRC_DISCARD ,Mask discarding TLPs with ECRC errors" "Not masked,Masked" bitfld.long 0x1C 26. " CX_FLT_MASK_CPL_LEN_MATCH ,Mask length match for completions" "Not masked,Masked" textline " " bitfld.long 0x1C 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,Mask attribute match for completions" "Not masked,Masked" bitfld.long 0x1C 24. " CX_FLT_MASK_CPL_TC_MATCH ,Mask traffic class match for completions" "Not masked,Masked" textline " " bitfld.long 0x1C 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,Mask function match for completions" "Not masked,Masked" bitfld.long 0x1C 22. " CX_FLT_MASK_CPL_REQID_MATCH ,Mask request ID match for completions" "Not masked,Masked" textline " " bitfld.long 0x1C 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,Mask tag error rules for completions" "Not masked,Masked" bitfld.long 0x1C 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,Mask treating locked read TLPs as UR for EP" "Not masked,Masked" textline " " bitfld.long 0x1C 19. " CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR ,Mask treating CFG type1 TLPs as UR for EP" "Not masked,Masked" bitfld.long 0x1C 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,Mask treating out-of-bar TLPs as UR" "Not masked,Masked" textline " " bitfld.long 0x1C 17. " CX_FLT_MASK_UR_POIS ,Mask treating poisoned TLPs as UR" "Not masked,Masked" bitfld.long 0x1C 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,Mask treating function mismatched TLPs as UR" "Not masked,Masked" textline " " sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") hexmask.long.word 0x1C 0.--10. 1. " SKP_INT_VAL ,SKP interval value" else bitfld.long 0x1C 15. " DISABLE_FCWD_TIMER ,Disable FX watchdog timer" "Enabled,Disabled" hexmask.long.word 0x1C 0.--10. 1. " SKP_INT_VAL ,SKP interval value" endif line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register" bitfld.long 0x20 7. " CX_FLT_MASK_PRS_DROP ,CX FLT mask PRS drop" "Not dropped,Dropped" bitfld.long 0x20 6. " CX_FLT_UNMASK_TD ,CX_FLT_UNMASK_TD" "Disabled,Enabled" textline " " bitfld.long 0x20 5. " CX_FLT_UNMASK_UR_POIS_TRGT0 ,CX_FLT_UNMASK_UR_POIS_TRGT0" "Disabled,Enabled" bitfld.long 0x20 4. " CX_FLT_MASK_LN_VENMSG1_DROP ,CX_FLT_MASK_LN_VENMSG1_DROP" "Not dropped,Dropped" textline " " bitfld.long 0x20 3. " CX_FLT_MASK_HANDLE_FLUSH ,Core filter enable" "Disabled,Enabled" bitfld.long 0x20 2. " CX_FLT_MASK_DABORT_4UCPL ,DLLP abort for unexpected completion enable" "Enabled,Disabled" textline " " bitfld.long 0x20 1. " CX_FLT_MASK_VENMSG1_DROP ,Vendor MSG Type 1 dropped silently" "Not dropped,Dropped" bitfld.long 0x20 0. " CX_FLT_MASK_VENMSG0_DROP ,Vendor MSG Type 0 dropped with UR error reporting" "Not dropped,Dropped" line.long 0x24 "AMBAMODNPSC,AMBA Multiple Outbound Decomposed NP SubRequests Control Register" bitfld.long 0x24 0. " OB_RD_SPLIT_BURST_EN ,Enable AMBA multiple outbound decomposed NP SubRequests" "Disabled,Enabled" rgroup.long 0x28++0x13 line.long 0x00 "PL_DEBUG0_OFF,Debug Register 0" line.long 0x04 "PL_DEBUG1_OFF,Debug Register 1" line.long 0x08 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.byte 0x08 12.--19. 1. " TX_P_HEADER_FC_CREDIT ,Transmit posted header FC credits" hexmask.long.word 0x08 0.--11. 1. " TX_P_DATA_FC_CREDIT ,Transmit posted data FC credits" line.long 0x0C "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status Register" hexmask.long.byte 0x0C 12.--19. 1. " TX_NP_HEADER_FC_CREDIT ,Transmit non-posted header FC credits" hexmask.long.word 0x0C 0.--11. 1. " TX_NP_DATA_FC_CREDIT ,Transmit non-posted data FC credits" line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status Register" hexmask.long.byte 0x10 12.--19. 1. " TX_CPL_HEADER_FC_CREDIT ,Transmit completion header FC credits" hexmask.long.word 0x10 0.--11. 1. " TX_CPL_DATA_FC_CREDIT ,Transmit completion data FC credits" group.long 0x3C++0x03 line.long 0x00 "QUEUE_STATUS_OFF,Queue Status Register" bitfld.long 0x00 31. " TIMER_MOD_FLOW_CONTROL_EN ,FC latency timer override enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--28. 1. " TIMER_MOD_FLOW_CONTROL ,FC latency timer override value" textline " " sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") eventfld.long 0x00 15. " RX_SERIALIZATION_Q_READ_ERR ,Received serialization read error" "No error,Error" eventfld.long 0x00 14. " RX_SERIALIZATION_Q_WRITE_ERR ,Received serialization queue write error" "No error,Error" textline " " rbitfld.long 0x00 13. " RX_SERIALIZATION_Q_NON_EMPTY ,Received serialization queue non empty" "Empty,Not empty" eventfld.long 0x00 3. " RX_QUEUE_OVERFLOW ,Received Credit queue overflow" "Not occurred,Occurred" textline " " endif rbitfld.long 0x00 2. " RX_QUEUE_NON_EMPTY ,Received queue not empty" "Not received,Received" rbitfld.long 0x00 1. " TX_RETRY_BUFFER_NE ,Transmit retry buffer not empty" "Not received,Received" textline " " rbitfld.long 0x00 0. " RX_TLP_FC_CRED_NON_RETURN ,Received TLP FC credits not returned" "Not received,Received" rgroup.long 0x40++0x07 line.long 0x00 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x00 24.--31. 1. " WRR_WEIGHT_VC_3 ,WRR weight for VC3" hexmask.long.byte 0x00 16.--23. 1. " WRR_WEIGHT_VC_2 ,WRR weight for VC2" textline " " hexmask.long.byte 0x00 8.--15. 1. " WRR_WEIGHT_VC_1 ,WRR weight for VC1" hexmask.long.byte 0x00 0.--7. 1. " WRR_WEIGHT_VC_0 ,WRR weight for VC0" line.long 0x04 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x04 24.--31. 1. " WRR_WEIGHT_VC_7 ,WRR weight for VC7" hexmask.long.byte 0x04 16.--23. 1. " WRR_WEIGHT_VC_6 ,WRR weight for VC6" textline " " hexmask.long.byte 0x04 8.--15. 1. " WRR_WEIGHT_VC_5 ,WRR weight for VC5" hexmask.long.byte 0x04 0.--7. 1. " WRR_WEIGHT_VC_4 ,WRR weight for VC4" group.long 0x48++0x0B line.long 0x00 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control" bitfld.long 0x00 31. " VC_ORDERING_RX_Q ,VC ordering for receive queues" "Round-robin,Strict" bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC0 ,TLP type ordering for VC0" "Strict,PCIe" textline " " sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 26.--27. " VC0_P_DATA_SCALE ,VC0 scale posted data credits" "0,1,2,3" bitfld.long 0x00 24.--25. " VC0_P_HDR_SCALE ,VC0 scale posted header credits" "0,1,2,3" textline " " endif hexmask.long.byte 0x00 12.--19. 1. " VC0_P_HEADER_CRED ,VC0 posted header credits" hexmask.long.word 0x00 0.--11. 1. " VC0_P_DATA_CRED ,VC0 posted data credits" line.long 0x04 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x04 26.--27. " VC0_NP_DATA_SCALE ,VC0 scale non-posted data credits" "0,1,2,3" bitfld.long 0x04 24.--25. " VC0_NP_HDR_SCALE ,VC0 scale non-posted header credits" "0,1,2,3" textline " " endif hexmask.long.byte 0x04 12.--19. 1. " VC0_NP_HEADER_CRED ,VC0 non-posted header credits" hexmask.long.word 0x04 0.--11. 1. " VC0_NP_DATA_CRED ,VC0 non-posted data credits" line.long 0x08 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x08 26.--27. " VC0_CPL_DATA_SCALE ,VC0 scale CPL data credits" "0,1,2,3" bitfld.long 0x08 24.--25. " VC0_CPL_HDR_SCALE ,VC0 scale CPL header credits" "0,1,2,3" textline " " endif hexmask.long.byte 0x08 12.--19. 1. " VC0_CPL_HEADER_CRED ,VC0 completion header credits" hexmask.long.word 0x08 0.--11. 1. " VC0_CPL_DATA_CRED ,VC0 completion data credits" group.long 0x10C++0x03 line.long 0x00 "GEN2_CTRL_OFF,Link Width and Speed Change Control Register" bitfld.long 0x00 21. " GEN1_EI_INFERENCE ,Electrical idle inference mode at Gen1 rate" "RxElecIdle,RxValid" bitfld.long 0x00 20. " SEL_DEEMPHASIS ,Select de-emphasis" "-6 dB,-3.5 dB" textline " " bitfld.long 0x00 19. " CONFIG_TX_COMP_RX ,Config Tx compliance receive bit" "No effect,LTSSM is signaled to transmit" bitfld.long 0x00 18. " CONFIG_PHY_TX_CHANGE ,Config PHY Tx swing" "Full,Low" textline " " bitfld.long 0x00 17. " DIRECT_SPEED_CHANGE ,Directed speed change" "No effect,Speed change to Gen2 or Gen3 initiated" bitfld.long 0x00 16. " AUTO_LANE_FLIP_CTRL_EN ,Enable auto flipping of the lanes" "Disabled,Enabled" textline " " bitfld.long 0x00 13.--15. " PRE_DET_LANE ,Predetermined lane for auto flip" "Phy L0,Phy L1,Phy L3,Phy L7,Phy L15,?..." bitfld.long 0x00 8.--12. " NUM_OF_LANES ,Predetermined number of lanes" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x00 0.--7. 1. " FAST_TRAIN_SEQ ,Number of fast training sequences" rgroup.long 0x110++0x03 line.long 0x00 "PHY_STATUS_OFF,PHY Status Register" group.long 0x114++0x03 line.long 0x00 "PHY_CONTROL_OFF,PHY Control Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") group.long 0x11C++0x03 line.long 0x00 "TRGT_MAP_CTRL_OFF,Programmable target map control register" bitfld.long 0x00 16.--20. " TARGET_MAP_INDEX ,The number of the PF function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " TARGET_MAP_ROM ,Target values for the ROM on the PF function" "0,1" textline " " bitfld.long 0x00 0.--5. " TARGET_MAP_PF ,Target values for each BAR on the PF function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x120++0x07 line.long 0x00 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register" line.long 0x04 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register" group.long 0x128++0x0B line.long 0x00 "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_0_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_0_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_0_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x134++0x0B line.long 0x00 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_1_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_1_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_1_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x140++0x0B line.long 0x00 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_2_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_2_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_2_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x14C++0x0B line.long 0x00 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_3_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_3_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_3_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x158++0x0B line.long 0x00 "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_4_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_4_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_4_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x164++0x0B line.long 0x00 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_5_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_5_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_5_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x170++0x0B line.long 0x00 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_6_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_6_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_6_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x17C++0x0B line.long 0x00 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register" bitfld.long 0x00 31. " MSI_CTRL_INT_7_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register" bitfld.long 0x04 31. " MSI_CTRL_INT_7_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" textline " " bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" textline " " bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" textline " " bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" textline " " bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" textline " " bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" textline " " bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" textline " " bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" textline " " bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" textline " " bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" textline " " bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" textline " " bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" textline " " bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" textline " " bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" textline " " bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" textline " " bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register" eventfld.long 0x08 31. " MSI_CTRL_INT_7_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" textline " " eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" textline " " eventfld.long 0x08 27. " [27] ,MSI interrupt 24 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" textline " " eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" textline " " eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" textline " " eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" textline " " eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" textline " " eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" textline " " eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" textline " " eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" textline " " eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" textline " " eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" textline " " eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" textline " " eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" textline " " eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" textline " " eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x188++0x03 line.long 0x00 "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") group.long 0x18C++0x03 line.long 0x00 "CLOCK_GATING_CTRL_OFF,RADM clock gating enable control register" bitfld.long 0x00 0. " RADM_CLK_GAITNG_EN ,Enable Radm clock gating features" "Disabled,Enabled" group.long 0x1B4++0x03 line.long 0x00 "ORDER_RULE_CTRL_OFF,Order Rule Control Register" hexmask.long.byte 0x00 8.--15. 1. " CPL_PASS_P ,Completion passing posted ordering rule control" hexmask.long.byte 0x00 0.--7. 1. " NP_PASS_P ,Non-posted passing posted ordering rule control" else group.long 0x190++0x03 line.long 0x00 "GEN3_RELATED_OFF,Gen3 Control Register" bitfld.long 0x00 23. " GEN3_EQ_INVREQ_EVAL_DIFF_DIS ,RxEqEval different time assertion disable" "Enabled,Disabled" bitfld.long 0x00 18. " GEN3_DC_BALANCE_DISABLE ,DC balance disable" "Enabled,Disabled" textline " " bitfld.long 0x00 17. " GEN3_DLLP_XMT_DELAY_DISABLE ,DLLP transmission delay disable" "Enabled,Disabled" bitfld.long 0x00 16. " GEN3_EQUALIZATION_DISABLE ,Equalization disable" "Enabled,Disabled" textline " " bitfld.long 0x00 13. " RXEQ_RGRDLESS_RXTS ,RxEqEval adaptation and evaluation" "After 1us,After 500ns" bitfld.long 0x00 12. " RXEQ_PH01_EN ,Rx equalization phase 0/1 hold enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " EQ_REDO ,Equalization redo disable" "Enabled,Disabled" bitfld.long 0x00 10. " EQ_EIEOS_CNT ,Equalization EIEOS count reset disable" "Enabled,Disabled" textline " " bitfld.long 0x00 9. " EQ_PHASE_2_3 ,Equalization phase 2/3 disable" "Enabled,Disabled" bitfld.long 0x00 8. " DISABLE_SCRAMBLER_GEN_3 ,Disable scrambler for gen3 and gen 4 data rate" "Enabled,Disabled" textline " " bitfld.long 0x00 0. " GEN3_ZRXDC_NONCOMPL ,Gen3 receiver impedance ZRX-DC not compliant" "Not compliant,Compliant" group.long 0x1A8++0x03 line.long 0x00 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register" bitfld.long 0x00 26. " GEN3_RSC_EIEOS_PSET_MAP ,Request core to send back-to-back EIEOS in RcvrLock state" "Not requested,Requested" bitfld.long 0x00 24. " GEN3_EQ_FOM_INC_INITIAL_EVAL ,Include initial FOM" "Not included,Included" textline " " hexmask.long.word 0x00 8.--23. 1. " GEN3_EQ_PSET_REQ_VEC ,Preset request vector" bitfld.long 0x00 5. " GEN3_EQ_EVAL_2MS_DISABLE ,Phase2_3 2ms timeout disable" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " GEN3_EQ_PHASE23_EXIT_MODE ,Behavior after 24ms timeout" "Recovery speed,Recovery equalization" bitfld.long 0x00 0.--3. " GEN3_EQ_FB_MODE ,Feedback mode" "Direction change,Figure out merit,?..." group.long 0x1B4++0x03 line.long 0x00 "ORDER_RULE_CTRL_OFF,Order Rule Control Register" hexmask.long.byte 0x00 8.--15. 1. " CPL_PASS_P ,Completion passing posted ordering rule control" hexmask.long.byte 0x00 0.--7. 1. " NP_PASS_P ,Non-posted passing posted ordering rule control" endif width 40. textline " " group.long 0x1B8++0x23 line.long 0x00 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register" bitfld.long 0x00 31. " PIPE_LOOPBACK ,PIPE loopback enable" "Disabled,Enabled" line.long 0x04 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x04 5. " ARI_DEVICE_NUMBER ,This field enables use of the device ID" "0,1" bitfld.long 0x04 3. " SIMPLIFIED_REPLAY_TIMER ,Enables Simplified Replay Timer" "24.000 to 31.000 Symbol Times,80.000 to 100.000 Symbol Times" textline " " bitfld.long 0x04 2. " UR_CA_MASK_4_TRGT1 ,UR CA mask 4 target 1" "No effect,Suppressed" bitfld.long 0x04 1. " DEFAULT_TARGET ,Default target" "Drop,Forward" textline " " bitfld.long 0x04 0. " DBI_RO_WR_EN ,Write to RO registers using DBI enable" "Disabled,Enabled" else bitfld.long 0x04 0. " DBI_RO_WR_EN ,Write to RO registers using DBI enable" "Disabled,Enabled" endif line.long 0x08 "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register" bitfld.long 0x08 7. " UPCONFIGURE_SUPPORT ,Upconfigure support" "0,1" bitfld.long 0x08 6. " DIRECT_LINK_WIDTH_CHANGE ,Directed link width change" "0,1" textline " " bitfld.long 0x08 0.--5. " TARGET_LINK_WIDTH ,Target link width" "No start,x1,x2,,x4,,,,x8,,,,,,,,x16,,,,,,,,,,,,,,,,x32,?..." line.long 0x0C "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x0C 10. " L1_CLK_SEL ,L1 clock control bit" "Requested,Not requested" bitfld.long 0x0C 9. " L1_NOWAIT_P1 ,L1 entry control bit" "Wait,No wait" textline " " bitfld.long 0x0C 8. " L1SUB_EXIT_MODE ,L1 exit control using phy_mac_pclkack_n" "Wait,Exit" hexmask.long.byte 0x0C 0.--6. 1. " RXSTANDBY_CONTROL ,RxStandby Control" else bitfld.long 0x0C 9. " L1_NOWAIT_P1 ,L1 entry control bit" "Wait,No wait" textline " " bitfld.long 0x0C 8. " L1SUB_EXIT_MODE ,L1 exit control using phy_mac_pclkack_n" "Wait,Exit" hexmask.long.byte 0x0C 0.--6. 1. " RXSTANDBY_CONTROL ,RxStandby Control" endif line.long 0x10 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control Register" eventfld.long 0x10 31. " DELETE_EN ,This is a one shot bit" "Not triggered,Triggered" hexmask.long 0x10 0.--30. 1. " LOOK_UP_ID ,This number selects one entry to delete of the TRGT_CPL_LUT" line.long 0x14 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register" bitfld.long 0x14 0. " AUTO_FLUSH_EN ,Enables automatic flushing" "Disabled,Enabled" line.long 0x18 "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register" bitfld.long 0x18 15. " AMBA_ERROR_RESPONSE_MAP[UR] ,AXI slave response error map - unsupported request" "DECERR,SLVERR" textline " " bitfld.long 0x18 14. " AMBA_ERROR_RESPONSE_MAP[CRS] ,AXI slave response error map - configuration retry status" "DECERR,SLVERR" bitfld.long 0x18 13. " AMBA_ERROR_RESPONSE_MAP[CA] ,AXI slave response error map - completer abort" "DECERR,SLVERR" textline " " bitfld.long 0x18 10. " AMBA_ERROR_RESPONSE_MAP[CT] ,AXI slave response error map - complete timeout" "DECERR,SLVERR" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x18 3.--4. " AMBA_ERROR_RESPONSE_CRS ,CRS slave error response mapping" "OKAY,OKAY with all FFFF_FFFF data,OKAY with FFFF_0001 data to vendor ID request adn FFFF_FFFF for others,DECERR/SLVERR" textline " " bitfld.long 0x18 2. " AMBA_ERROR_RESPONSE_VENDORID ,Vendor ID Non-existent slave error response mapping" "OKAY,ERROR AXI" bitfld.long 0x18 0. " AMBA_ERROR_RESPONSE_GLOBAL ,Global slave error response mapping" "OKAY,ERROR for normal link accesses" else bitfld.long 0x18 2. " AMBA_ERROR_RESPONSE_VEN_ID ,Vendor ID Non-existent slave error response mapping" "OKAY,ERROR AXI" textline " " bitfld.long 0x18 0. " AMBA_ERROR_RESPONSE_GLOBAL ,Global slave error response mapping" "OKAY,ERROR" endif line.long 0x1C "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register" bitfld.long 0x1C 8. " LINK_TIMEOUT_ENABLE_DFL ,Disable flush" "No effect,Enabled" hexmask.long.byte 0x1C 0.--7. 1. " LINK_TIMEOUT_PERIOD_DFL ,Timeout value (ms)" line.long 0x20 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x20 7. " AX_MSTR_ZEROLREAD_FW ,AXI master zero length read forward to he application" "DW PCIe AXI bridge master,Forward to the application" bitfld.long 0x20 3.--4. " AX_MSTR_ORDR_P_EVENT_SEL ,AXI master posted ordering event selector" "B'last,AW'last,W'last,?..." textline " " bitfld.long 0x20 1. " AX_SNP_EN ,AXI Serialize Non-Posted Requests Enable" "Disabled,Enabled" else bitfld.long 0x20 3.--4. " AX_MSTR_ORDR_P_EVENT_SEL ,AXI master posted ordering event selector" "B'last,AW'last,W'last,?..." bitfld.long 0x20 2. " AX_IB_CPL_PASS_P ,AXI inbound CPL must not pass P rule disable" "Enabled,Disabled" textline " " bitfld.long 0x20 1. " AX_SNP_EN ,AXI Serialize Non-Posted Requests Enable" "Disabled,Enabled" bitfld.long 0x20 0. " AX_MSTR_NP_PASS_P ,AXI master NP can pass P" "Disabled,Enabled" endif group.long 0x1E0++0x0B line.long 0x00 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BD_L_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VAL ,Memory type for the lower and upper parts of the address space select" "L:Periph UP:Mem,L:Mem UP:Periph" line.long 0x04 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" line.long 0x08 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" bitfld.long 0x08 27.--30. " CFG_MSTR_AWCACHE_VAL ,Master write CACHE signal value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 19.--22. " CFG_MSTR_ARCACHE_VAL ,Master read CACHE signal value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 11.--14. " CFG_MSTR_AWCACHE_MODE ,Master write CACHE signal behavior" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 3.--6. " CFG_MSTR_ARCACHE_MODE ,Master read CACHE signal behavior" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1F0++0x07 line.long 0x00 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to" hexmask.long.tbyte 0x00 12.--31. 1. " CFG_AXIMSTR_MSG_ADDR_LOW ,Lower 20 bits of the programmable AXI address for Messages" line.long 0x04 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") rgroup.long 0x1F8++0x07 line.long 0x00 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number" line.long 0x04 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type" group.long 0x440++0x07 line.long 0x00 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register" hexmask.long.word 0x00 0.--9. 1. " AUX_CLK_FREQ ,The aux_clk frequency in MHz" line.long 0x04 "L1_SUBSTATES_OFF,L1 Substates Timing Register" bitfld.long 0x04 6.--7. " L1SUB_T_PCLKACK ,Max delay" "0,1 us,2 us,3 us" bitfld.long 0x04 2.--5. " L1SUB_T_L1_2 ,Duration of L1.2" "0,1 us,2 us,3 us,4 us,5 us,6 us,7 us,8 us,9 us,10 us,11 us,12 us,13 us,14 us,15 us" textline " " bitfld.long 0x04 0.--1. " L1SUB_T_POWER_OFF ,Duration of L1.2.Entry" "0,1 us,2 us,3 us" endif sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") base ad:0x33c00000+0x80000000 else base ad:0x33c00000+0x904 group.long (0x00-0x04)++0x03 line.long 0x00 "IATU_VIEWPORT_OFF,IATU Index Register" bitfld.long 0x00 31. " REGION_DIR ,Region direction" "Outbound,Inbound" bitfld.long 0x00 0.--2. " REGIOX_INDEX ,Region index" "0,1,2,3,4,5,6,7" endif sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") group.long 0x0++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Maximum ATU region size - 4GB,Determined by CX_ATU_MAX_REGION_SIZE" textline " " bitfld.long 0x00 11. " IDO ,IDO" "0,1" bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" textline " " bitfld.long 0x00 8. " TD ,TD" "0,1" bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" textline " " bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Disabled,Enabled" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "0,1" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x04 8.--15. 1. " TAG ,TAG" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,iATU Upper Target Address Register" group.long (0x0+0x100)++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU Region size" "0,1" textline " " bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" textline " " bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID match mode,BAR/Accept/Vendor ID match mode (MSG/MSGD)" textline " " bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" textline " " bitfld.long 0x04 27. " Disabled ,Fuzzy type match mode" "Disabled,Enabled" bitfld.long 0x04 24.--25. " RESPONSE_CODE ,Response code" "Normal RADM filter response,Unsupported request,Completer abort," textline " " bitfld.long 0x04 23. " SINGLE_ADDR_LOC_TRANS_EN ,Single address location translate enable" "Disabled,Enabled" bitfld.long 0x04 21. " MSG_CODE_MATCH_EN ,message code match enable" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 16. " TAG_MATCH_EN ,ATTR match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " TD_MATCH_EN ,TD match enable" "Disabled,Enabled" bitfld.long 0x04 14. " TC_MATCH_EN ,TC match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " MSG_TYPE_MATCH_MODE ,Massage type match mode" "Disabled,Enabled" bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM," textline " " hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_0,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,iATU Upper Target Address Register" group.long 0x200++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_1,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Maximum ATU region size - 4GB,Determined by CX_ATU_MAX_REGION_SIZE" textline " " bitfld.long 0x00 11. " IDO ,IDO" "0,1" bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" textline " " bitfld.long 0x00 8. " TD ,TD" "0,1" bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_1,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" textline " " bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Disabled,Enabled" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "0,1" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x04 8.--15. 1. " TAG ,TAG" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_1,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1,iATU Upper Target Address Register" group.long (0x200+0x100)++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_1,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU Region size" "0,1" textline " " bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" textline " " bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_1,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID match mode,BAR/Accept/Vendor ID match mode (MSG/MSGD)" textline " " bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" textline " " bitfld.long 0x04 27. " Disabled ,Fuzzy type match mode" "Disabled,Enabled" bitfld.long 0x04 24.--25. " RESPONSE_CODE ,Response code" "Normal RADM filter response,Unsupported request,Completer abort," textline " " bitfld.long 0x04 23. " SINGLE_ADDR_LOC_TRANS_EN ,Single address location translate enable" "Disabled,Enabled" bitfld.long 0x04 21. " MSG_CODE_MATCH_EN ,message code match enable" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 16. " TAG_MATCH_EN ,ATTR match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " TD_MATCH_EN ,TD match enable" "Disabled,Enabled" bitfld.long 0x04 14. " TC_MATCH_EN ,TC match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " MSG_TYPE_MATCH_MODE ,Massage type match mode" "Disabled,Enabled" bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM," textline " " hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_1,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_1,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_1,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_1,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1,iATU Upper Target Address Register" group.long 0x400++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_2,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Maximum ATU region size - 4GB,Determined by CX_ATU_MAX_REGION_SIZE" textline " " bitfld.long 0x00 11. " IDO ,IDO" "0,1" bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" textline " " bitfld.long 0x00 8. " TD ,TD" "0,1" bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_2,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" textline " " bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Disabled,Enabled" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "0,1" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x04 8.--15. 1. " TAG ,TAG" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_2,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2,iATU Upper Target Address Register" group.long (0x400+0x100)++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_2,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU Region size" "0,1" textline " " bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" textline " " bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_2,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID match mode,BAR/Accept/Vendor ID match mode (MSG/MSGD)" textline " " bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" textline " " bitfld.long 0x04 27. " Disabled ,Fuzzy type match mode" "Disabled,Enabled" bitfld.long 0x04 24.--25. " RESPONSE_CODE ,Response code" "Normal RADM filter response,Unsupported request,Completer abort," textline " " bitfld.long 0x04 23. " SINGLE_ADDR_LOC_TRANS_EN ,Single address location translate enable" "Disabled,Enabled" bitfld.long 0x04 21. " MSG_CODE_MATCH_EN ,message code match enable" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 16. " TAG_MATCH_EN ,ATTR match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " TD_MATCH_EN ,TD match enable" "Disabled,Enabled" bitfld.long 0x04 14. " TC_MATCH_EN ,TC match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " MSG_TYPE_MATCH_MODE ,Massage type match mode" "Disabled,Enabled" bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM," textline " " hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_2,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_2,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_2,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_2,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2,iATU Upper Target Address Register" group.long 0x600++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_3,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Maximum ATU region size - 4GB,Determined by CX_ATU_MAX_REGION_SIZE" textline " " bitfld.long 0x00 11. " IDO ,IDO" "0,1" bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" textline " " bitfld.long 0x00 8. " TD ,TD" "0,1" bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_3,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" textline " " bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Disabled,Enabled" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "0,1" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x04 8.--15. 1. " TAG ,TAG" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_3,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3,iATU Upper Target Address Register" group.long (0x600+0x100)++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_3,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU Region size" "0,1" textline " " bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" textline " " bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_3,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID match mode,BAR/Accept/Vendor ID match mode (MSG/MSGD)" textline " " bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" textline " " bitfld.long 0x04 27. " Disabled ,Fuzzy type match mode" "Disabled,Enabled" bitfld.long 0x04 24.--25. " RESPONSE_CODE ,Response code" "Normal RADM filter response,Unsupported request,Completer abort," textline " " bitfld.long 0x04 23. " SINGLE_ADDR_LOC_TRANS_EN ,Single address location translate enable" "Disabled,Enabled" bitfld.long 0x04 21. " MSG_CODE_MATCH_EN ,message code match enable" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 16. " TAG_MATCH_EN ,ATTR match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " TD_MATCH_EN ,TD match enable" "Disabled,Enabled" bitfld.long 0x04 14. " TC_MATCH_EN ,TC match enable" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " MSG_TYPE_MATCH_MODE ,Massage type match mode" "Disabled,Enabled" bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM," textline " " hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_3,IATU Lower Base Address Register" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_3,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_3,IATU Limit Address Register" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_3,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3,iATU Upper Target Address Register" else group.long 0x00++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND,iATU Region Control 1 Register" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " AT ,AT" "0,1,2,3" textline " " bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "4GB,CX_ATU_MAX_REGION_SIZE" bitfld.long 0x00 11. " IDO ,IDO" "0,1" textline " " bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" textline " " bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" textline " " bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "ECAM not supported,ECAM supported" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Disabled,Enabled" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "0,1" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x04 8.--15. 1. " TAG ,TAG" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND,IATU Lower Base Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x08 0.--11. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$2,IATU Limit Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x10 0.--11. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND,iATU Lower Target Address Register" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$2,iATU Upper Target Address Register" endif sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") base ad:0x33c00000+0x80080000 else base ad:0x33c00000+0x970 endif group.long 0x00++0x03 line.long 0x00 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface" bitfld.long 0x00 9.--11. " RDBUFF_TRGT_WEIGHT ,DMA read channel MWr requests" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " RD_CTRL_TRGT_WEIGHT ,DMA Read channel MRd requests" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--5. " WR_CTRL_TRGT_WEIGHT ,DMA Write channel MRd requests" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " RTRGT1_WEIGHT ,Non-DMA Rx Requests" "0,1,2,3,4,5,6,7" group.long 0x08++0x0B line.long 0x00 "DMA_CTRL_OFF,DMA Number of Channels Register" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") bitfld.long 0x00 25. " DIS_C2W_CAC_HE_RD ,Disable DMA read Channels" "Enabled,Disabled" bitfld.long 0x00 24. " DIS_C2W_CAC_HE_WR ,Disable DMA write Channels" "Enabled,Disabled" textline " " bitfld.long 0x00 16.--19. " NUM_DMA_RD_CHAN ,Number of read channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NUM_DMA_WR_CHAN ,Number of write channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x00 16.--19. " NUM_DMA_RD_CHAN ,Number of read channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NUM_DMA_WR_CHAN ,Number of write channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.long 0x04 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register" bitfld.long 0x04 0. " DMA_WRITE_ENGINE ,DMA write engine enable" "Disabled,Enabled" line.long 0x08 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register" bitfld.long 0x08 31. " WR_STOP ,Stop" "Not stopped,Stopped" bitfld.long 0x08 0.--2. " WR_DOORBELL_NUM ,Doorbell number" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" group.long 0x18++0x07 line.long 0x00 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register" bitfld.long 0x00 15.--19. " WRITE_CHANNEL3_WEIGHT ,Channel 3 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " WRITE_CHANNEL2_WEIGHT ,Channel 2 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " WRITE_CHANNEL1_WEIGHT ,Channel 1 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " WRITE_CHANNEL0_WEIGHT ,Channel 0 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register" bitfld.long 0x04 15.--19. " WRITE_CHANNEL7_WEIGHT ,Channel 7 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 10.--14. " WRITE_CHANNEL6_WEIGHT ,Channel 6 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 5.--9. " WRITE_CHANNEL5_WEIGHT ,Channel 5 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " WRITE_CHANNEL4_WEIGHT ,Channel 4 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2C++0x07 line.long 0x00 "DMA_READ_ENGINE_EN_OFF ,DMA Read Engine Enable Register" bitfld.long 0x00 0. " DMA_READ_ENGINE ,DMA read engine enable" "Disabled,Enabled" line.long 0x04 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register" bitfld.long 0x04 31. " RD_STOP ,Stop" "Not stopped,Stopped" bitfld.long 0x04 0.--2. " WR_DOORBELL_NUM ,Doorbell number" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" group.long 0x38++0x07 line.long 0x00 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register" bitfld.long 0x00 15.--19. " READ_CHANNEL3_WEIGHT ,Channel 3 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " READ_CHANNEL2_WEIGHT ,Channel 2 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " READ_CHANNEL1_WEIGHT ,Channel 1 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " READ_CHANNEL0_WEIGHT ,Channel 0 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register" bitfld.long 0x04 15.--19. " READ_CHANNEL7_WEIGHT ,Channel 7 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 10.--14. " READ_CHANNEL6_WEIGHT ,Channel 6 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 5.--9. " READ_CHANNEL5_WEIGHT ,Channel 5 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " READ_CHANNEL4_WEIGHT ,Channel 4 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4C++0x03 line.long 0x00 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register" bitfld.long 0x00 23. " WR_ABORT_INT_STATUS[7] ,Abort interrupt status for channel 7" "Not aborted,Aborted" bitfld.long 0x00 22. " [6] ,Abort interrupt status for channel 6" "Not aborted,Aborted" textline " " bitfld.long 0x00 21. " [5] ,Abort interrupt status for channel 5" "Not aborted,Aborted" bitfld.long 0x00 20. " [4] ,Abort interrupt status for channel 4" "Not aborted,Aborted" textline " " bitfld.long 0x00 19. " [3] ,Abort interrupt status for channel 3" "Not aborted,Aborted" bitfld.long 0x00 18. " [2] ,Abort interrupt status for channel 2" "Not aborted,Aborted" textline " " bitfld.long 0x00 17. " [1] ,Abort interrupt status for channel 1" "Not aborted,Aborted" bitfld.long 0x00 16. " [0] ,Abort interrupt status for channel 0" "Not aborted,Aborted" textline " " bitfld.long 0x00 7. " WR_DONE_INT_STATUS[7] ,Done interrupt status for channel 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Done interrupt status for channel 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " [5] ,Done interrupt status for channel 5" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Done interrupt status for channel 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Done interrupt status for channel 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Done interrupt status for channel 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " [1] ,Done interrupt status for channel 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Done interrupt status for channel 0" "Not masked,Masked" group.long 0x54++0x07 line.long 0x00 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register" bitfld.long 0x00 16. " WR_ABORT_INT_MASK ,Abort interrupt mask for channel 0" "Not aborted,Aborted" bitfld.long 0x00 0. " WR_DONE_INT_MASK ,Done interrupt mask for channel 0" "Not done,Done" line.long 0x04 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register" bitfld.long 0x04 23. " WR_ABORT_INT_CLEAR[7] ,Abort interrupt clear for channel 7" "Not interrupted,Interrupted" bitfld.long 0x04 22. " [6] ,Abort interrupt clear for channel 6" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 21. " [5] ,Abort interrupt clear for channel 5" "Not interrupted,Interrupted" bitfld.long 0x04 20. " [4] ,Abort interrupt clear for channel 4" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 19. " [3] ,Abort interrupt clear for channel 3" "Not interrupted,Interrupted" bitfld.long 0x04 18. " [2] ,Abort interrupt clear for channel 2" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 17. " [1] ,Abort interrupt clear for channel 1" "Not interrupted,Interrupted" bitfld.long 0x04 16. " [0] ,Abort interrupt clear for channel 0" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 7. " WR_DONE_INT_CLEAR[7] ,Done interrupt clear for channel 7" "Not interrupted,Interrupted" bitfld.long 0x04 6. " [6] ,Done interrupt clear for channel 6" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 5. " [5] ,Done interrupt clear for channel 5" "Not interrupted,Interrupted" bitfld.long 0x04 4. " [4] ,Done interrupt clear for channel 4" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 3. " [3] ,Done interrupt clear for channel 3" "Not interrupted,Interrupted" bitfld.long 0x04 2. " [2] ,Done interrupt clear for channel 2" "Not interrupted,Interrupted" textline " " bitfld.long 0x04 1. " [1] ,Done interrupt clear for channel 1" "Not interrupted,Interrupted" bitfld.long 0x04 0. " [0] ,Done interrupt clear for channel 0" "Not interrupted,Interrupted" rgroup.long 0x5C++0x03 line.long 0x00 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" bitfld.long 0x00 23. " LINKLIST_ELEMENT_FETCH_ERR_DETECT[7] ,Linked list element fetch error detected for channel 7" "Not occurred,Occurred" bitfld.long 0x00 22. " [6] ,Linked list element fetch error detected for channel 6" "Not occurred,Occurred" textline " " bitfld.long 0x00 21. " [5] ,Linked list element fetch error detected for channel 5" "Not occurred,Occurred" bitfld.long 0x00 20. " [4] ,Linked list element fetch error detected for channel 4" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [3] ,Linked list element fetch error detected for channel 3" "Not occurred,Occurred" bitfld.long 0x00 18. " [2] ,Linked list element fetch error detected for channel 2" "Not occurred,Occurred" textline " " bitfld.long 0x00 17. " [1] ,Linked list element fetch error detected for channel 1" "Not occurred,Occurred" bitfld.long 0x00 16. " [0] ,Linked list element fetch error detected for channel 0" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " APP_READ_ERR_DETECT[7] ,Application read error detected for channel 7" "Not occurred,Occurred" bitfld.long 0x00 6. " [6] ,Application read error detected for channel 6" "Not occurred,Occurred" textline " " bitfld.long 0x00 5. " [5] ,Application read error detected for channel 5" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Application read error detected for channel 4" "Not occurred,Occurred" textline " " bitfld.long 0x00 3. " [3] ,Application read error detected for channel 3" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Application read error detected for channel 2" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " [1] ,Application read error detected for channel 1" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Application read error detected for channel 0" "Not occurred,Occurred" group.long 0x60++0x1F line.long 0x00 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register" line.long 0x04 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register" line.long 0x08 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register" line.long 0x0C "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register" hexmask.long.word 0x10 16.--31. 1. " WR_CHANNEL_1_DATA ,Write channel 1 data" hexmask.long.word 0x10 0.--15. 1. " WR_CHANNEL_0_DATA ,Write channel 0 data" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register" hexmask.long.word 0x14 16.--31. 1. " WR_CHANNEL_3_DATA ,Write channel 3 data" hexmask.long.word 0x14 0.--15. 1. " WR_CHANNEL_2_DATA ,Write channel 2 data" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register" hexmask.long.word 0x18 16.--31. 1. " WR_CHANNEL_5_DATA ,Write channel 5 data" hexmask.long.word 0x18 0.--15. 1. " WR_CHANNEL_4_DATA ,Write channel 4 data" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register" hexmask.long.word 0x1C 16.--31. 1. " WR_CHANNEL_7_DATA ,Write channel 7 data" hexmask.long.word 0x1C 0.--15. 1. " WR_CHANNEL_6_DATA ,Write channel 6 data" if (((per.l(ad:0x33c00000+0x370+0x700))&0x200)==0x200) group.long 0x90++0x03 line.long 0x00 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register" bitfld.long 0x00 16. " WR_CHANNEL_LLLAIE ,Write channel LL local abort interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " WR_CHANNEL_LLRAIE ,Write channel LL remote abort interrupt enable" "Disabled,Enabled" else hgroup.long 0x90++0x03 hide.long 0x00 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register" endif group.long (0x00+0xA0)++0x03 line.long 0x00 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register" bitfld.long 0x00 23. " RD_ABORT_INT_STATUS[7] ,Abort interrupt status for channel 7" "Not aborted,Aborted" bitfld.long 0x00 22. " [6] ,Abort interrupt status for channel 6" "Not aborted,Aborted" textline " " bitfld.long 0x00 21. " [5] ,Abort interrupt status for channel 5" "Not aborted,Aborted" bitfld.long 0x00 20. " [4] ,Abort interrupt status for channel 4" "Not aborted,Aborted" textline " " bitfld.long 0x00 19. " [3] ,Abort interrupt status for channel 3" "Not aborted,Aborted" bitfld.long 0x00 18. " [2] ,Abort interrupt status for channel 2" "Not aborted,Aborted" textline " " bitfld.long 0x00 17. " [1] ,Abort interrupt status for channel 1" "Not aborted,Aborted" bitfld.long 0x00 16. " [0] ,Abort interrupt status for channel 0" "Not aborted,Aborted" textline " " bitfld.long 0x00 7. " RD_DONE_INT_STATUS[7] ,Done interrupt status for channel 7" "Not done,Done" bitfld.long 0x00 6. " [6] ,Done interrupt status for channel 6" "Not done,Done" textline " " bitfld.long 0x00 5. " [5] ,Done interrupt status for channel 5" "Not done,Done" bitfld.long 0x00 4. " [4] ,Done interrupt status for channel 4" "Not done,Done" textline " " bitfld.long 0x00 3. " [3] ,Done interrupt status for channel 3" "Not done,Done" bitfld.long 0x00 2. " [2] ,Done interrupt status for channel 2" "Not done,Done" textline " " bitfld.long 0x00 1. " [1] ,Done interrupt status for channel 1" "Not done,Done" bitfld.long 0x00 0. " [0] ,Done interrupt status for channel 0" "Not done,Done" group.long (0x00+0xA8)++0x03 line.long 0x00 "DMA_READ_INT_MASK_OFF,DMA read interrupt mask register" bitfld.long 0x00 16. " RD_ABORT_INT_MASK ,Abort interrupt mask" "Not aborted,Aborted" bitfld.long 0x00 0. " RD_DONE_INT_MASK ,Done interrupt mask" "Not done,Done" wgroup.long (0x00+0xAC)++0x03 line.long 0x00 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register" bitfld.long 0x00 23. " RD_ABORT_INT_CLEAR[7] ,Abort interrupt clear for channel 7" "Not aborted,Aborted" bitfld.long 0x00 22. " [6] ,Abort interrupt clear for channel 6" "Not aborted,Aborted" textline " " bitfld.long 0x00 21. " [5] ,Abort interrupt clear for channel 5" "Not aborted,Aborted" bitfld.long 0x00 20. " [4] ,Abort interrupt clear for channel 4" "Not aborted,Aborted" textline " " bitfld.long 0x00 19. " [3] ,Abort interrupt clear for channel 3" "Not aborted,Aborted" bitfld.long 0x00 18. " [2] ,Abort interrupt clear for channel 2" "Not aborted,Aborted" textline " " bitfld.long 0x00 17. " [1] ,Abort interrupt clear for channel 1" "Not aborted,Aborted" bitfld.long 0x00 16. " [0] ,Abort interrupt clear for channel 0" "Not aborted,Aborted" textline " " bitfld.long 0x00 7. " RD_DONE_INT_CLEAR[7] ,Done interrupt clear for channel 7" "Not done,Done" bitfld.long 0x00 6. " [6] ,Done interrupt clear for channel 6" "Not done,Done" textline " " bitfld.long 0x00 5. " [5] ,Done interrupt clear for channel 5" "Not done,Done" bitfld.long 0x00 4. " [4] ,Done interrupt clear for channel 4" "Not done,Done" textline " " bitfld.long 0x00 3. " [3] ,Done interrupt clear for channel 3" "Not done,Done" bitfld.long 0x00 2. " [2] ,Done interrupt clear for channel 2" "Not done,Done" textline " " bitfld.long 0x00 1. " [1] ,Done interrupt clear for channel 1" "Not done,Done" bitfld.long 0x00 0. " [0] ,Done interrupt clear for channel 0" "Not done,Done" rgroup.long (0x00+0xB4)++0x07 line.long 0x00 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register" bitfld.long 0x00 23. " LINK_LIST_ELEMENT_FETCH_ERR_DETECT[7] ,Linked list element fetch error detected for channel 7" "Not detected,Detected" bitfld.long 0x00 22. " [6] ,Linked list element fetch error detected for channel 6" "Not detected,Detected" textline " " bitfld.long 0x00 21. " [5] ,Linked list element fetch error detected for channel 5" "Not detected,Detected" bitfld.long 0x00 20. " [4] ,Linked list element fetch error detected for channel 4" "Not detected,Detected" textline " " bitfld.long 0x00 19. " [3] ,Linked list element fetch error detected for channel 3" "Not detected,Detected" bitfld.long 0x00 18. " [2] ,Linked list element fetch error detected for channel 2" "Not detected,Detected" textline " " bitfld.long 0x00 17. " [1] ,Linked list element fetch error detected for channel 1" "Not detected,Detected" bitfld.long 0x00 16. " [0] ,Linked list element fetch error detected for channel 0" "Not detected,Detected" textline " " bitfld.long 0x00 7. " APP_WR_ERR_DETECT[7] ,Application write error detected for channel 7" "Not detected,Detected" bitfld.long 0x00 6. " [6] ,Application write error detected for channel 6" "Not detected,Detected" textline " " bitfld.long 0x00 5. " [5] ,Application write error detected for channel 5" "Not detected,Detected" bitfld.long 0x00 4. " [4] ,Application write error detected for channel 4" "Not detected,Detected" textline " " bitfld.long 0x00 3. " [3] ,Application write error detected for channel 3" "Not detected,Detected" bitfld.long 0x00 2. " [2] ,Application write error detected for channel 2" "Not detected,Detected" textline " " bitfld.long 0x00 1. " [1] ,Application write error detected for channel 1" "Not detected,Detected" bitfld.long 0x00 0. " [0] ,Application write error detected for channel 0" "Not detected,Detected" line.long 0x04 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register" bitfld.long 0x04 31. " DATA_POISIONING[7] ,Data poisoning for channel 7" "Disabled,Enabled" bitfld.long 0x04 30. " [6] ,Data poisoning for channel 6" "Disabled,Enabled" textline " " bitfld.long 0x04 29. " [5] ,Data poisoning for channel 5" "Disabled,Enabled" bitfld.long 0x04 28. " [4] ,Data poisoning for channel 4" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " [3] ,Data poisoning for channel 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Data poisoning for channel 2" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " [1] ,Data poisoning for channel 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Data poisoning for channel 0" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " CPL_TIMEOUT[7] ,Completion time out for channel 7" "Disabled,Enabled" bitfld.long 0x04 22. " [6] ,Completion time out for channel 6" "Disabled,Enabled" textline " " bitfld.long 0x04 21. " [5] ,Completion time out for channel 5" "Disabled,Enabled" bitfld.long 0x04 20. " [4] ,Completion time out for channel 4" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " [3] ,Completion time out for channel 3" "Disabled,Enabled" bitfld.long 0x04 18. " [2] ,Completion time out for channel 2" "Disabled,Enabled" textline " " bitfld.long 0x04 17. " [1] ,Completion time out for channel 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Completion time out for channel 0" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " CPL_ABORT[7] ,Completer abort for channel 7" "Not Received,Received" bitfld.long 0x04 14. " [6] ,Completer abort for channel 6" "Not Received,Received" textline " " bitfld.long 0x04 13. " [5] ,Completer abort for channel 5" "Not Received,Received" bitfld.long 0x04 12. " [4] ,Completer abort for channel 4" "Not Received,Received" textline " " bitfld.long 0x04 11. " [3] ,Completer abort for channel 3" "Not Received,Received" bitfld.long 0x04 10. " [2] ,Completer abort for channel 2" "Not Received,Received" textline " " bitfld.long 0x04 9. " [1] ,Completer abort for channel 1" "Not Received,Received" bitfld.long 0x04 8. " [0] ,Completer abort for channel 0" "Not Received,Received" textline " " bitfld.long 0x04 7. " UNSUPPORTED_REQ[7] ,Unsupported request for channel 7" "Not Received,Received" bitfld.long 0x04 6. " [6] ,Unsupported request for channel 6" "Not Received,Received" textline " " bitfld.long 0x04 5. " [5] ,Unsupported request for channel 5" "Not Received,Received" bitfld.long 0x04 4. " [4] ,Unsupported request for channel 4" "Not Received,Received" textline " " bitfld.long 0x04 3. " [3] ,Unsupported request for channel 3" "Not Received,Received" bitfld.long 0x04 2. " [2] ,Unsupported request for channel 2" "Not Received,Received" textline " " bitfld.long 0x04 1. " [1] ,Unsupported request for channel 1" "Not Received,Received" bitfld.long 0x04 0. " [0] ,Unsupported request for channel 0" "Not Received,Received" if (((per.l(ad:0x33c00000+0x370+0x700))&0x200)==0x200) group.long 0xC4++0x03 line.long 0x00 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register" bitfld.long 0x00 16. " RD_CHANNEL_LLLAIE ,Read channel LL local abort interrupt enable" "Enabled,Disabled" bitfld.long 0x00 0. " RD_CHANNEL_LLRAIE ,Read channel LL remote abort interrupt enable" "Enabled,Disabled" else hgroup.long 0xC4++0x03 hide.long 0x00 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register" endif group.long (0x00+0xCC)++0x1F line.long 0x00 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register" line.long 0x04 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register" line.long 0x08 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register" line.long 0x0C "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register" hexmask.long.word 0x10 16.--31. 1. " RD_CHANNEL_1_DATA , Read channel 1 data" hexmask.long.word 0x10 0.--15. 1. " RD_CHANNEL_0_DATA , Read channel 0 data" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register" hexmask.long.word 0x14 16.--31. 1. " RD_CHANNEL_3_DATA , Read channel 3 data" hexmask.long.word 0x14 0.--15. 1. " RD_CHANNEL_2_DATA , Read channel 2 data" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register" hexmask.long.word 0x18 16.--31. 1. " RD_CHANNEL_5_DATA , Read channel 5 data" hexmask.long.word 0x18 0.--15. 1. " RD_CHANNEL_4_DATA , Read channel 4 data" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register" hexmask.long.word 0x1C 16.--31. 1. " RD_CHANNEL_7_DATA , Read channel 7 data" hexmask.long.word 0x1C 0.--15. 1. " RD_CHANNEL_6_DATA , Read channel 6 data" sif !cpuis("IMX8Q")&&!cpuis("IMX8Q*")&&!cpuis("IMX8QM*")&&!cpuis("IMX8QP*") if (((per.l(ad:0x33c00000+0x80080200))&0x200)==0x200) group.long 0x80200++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" textline " " bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCS ,Consumer cycle state" "0,1" textline " " rbitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " LLP ,Load link pointer" "0,1" textline " " bitfld.long 0x00 1. " TCB ,Toggle cycle bit" "0,1" bitfld.long 0x00 0. " CB ,Cycle bit" "0,1" else group.long 0x80200++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" textline " " bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" endif group.long 0x80208++0x1B line.long 0x00 "DMA_TRANSFER_SIZE_OFF_WRCH_0,DMA Write Transfer Size Register" line.long 0x04 "DMA_SAR_LOW_OFF_WRCH_0,DMA Write SAR Low Register" line.long 0x08 "DMA_SAR_HIGH_OFF_WRCH_0,DMA Write SAR High Register" line.long 0x0C "DMA_DAR_LOW_OFF_WRCH_0,DMA Write DAR Low Register" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_0,DMA Write DAR High Register" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_0,DMA Write Linked List Pointer Low Register" line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_0,DMA Write Linked List Pointer High Register" if (((per.l(ad:0x33c00000+0x80080300))&0x200)==0x200) group.long 0x80300++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" textline " " bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCS ,Consumer cycle state" "0,1" textline " " rbitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " LLP ,Load link pointer" "0,1" textline " " bitfld.long 0x00 1. " TCB ,Toggle cycle bit" "0,1" bitfld.long 0x00 0. " CB ,Cycle bit" "0,1" else group.long 0x80300++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" textline " " bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" endif group.long 0x80308++0x1B line.long 0x00 "DMA_TRANSFER_SIZE_OFF_WRCH_0,DMA Write Transfer Size Register" line.long 0x04 "DMA_SAR_LOW_OFF_WRCH_0,DMA Write SAR Low Register" line.long 0x08 "DMA_SAR_HIGH_OFF_WRCH_0,DMA Write SAR High Register" line.long 0x0C "DMA_DAR_LOW_OFF_WRCH_0,DMA Write DAR Low Register" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_0,DMA Write DAR High Register" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_0,DMA Write Linked List Pointer Low Register" line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_0,DMA Write Linked List Pointer High Register" else group.long 0xFC++0x03 line.long 0x00 "DMA_VIEWPORT_SEL_OFF,DMA Channel Context Index Register" bitfld.long 0x00 31. " CHANNEL_DIR ,Channel direction" "Write,Read" bitfld.long 0x00 0.--2. " CHANNEL_NUM ,Channel index" "Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7" if (((per.l(ad:0x33c00000+0x370+0x700))&0x200)==0x200) group.long 0x100++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" textline " " bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCS ,Consumer cycle state" "0,1" textline " " rbitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " LLP ,Load link pointer" "0,1" textline " " bitfld.long 0x00 1. " TCB ,Toggle cycle bit" "0,1" bitfld.long 0x00 0. " CB ,Cycle bit" "0,1" else group.long 0x100++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" textline " " bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" endif group.long 0x108++0x1B line.long 0x00 "DMA_TRANSFER_SIZE_OFF_WRCH_0,DMA Write Transfer Size Register" line.long 0x04 "DMA_SAR_LOW_OFF_WRCH_0,DMA Write SAR Low Register" line.long 0x08 "DMA_SAR_HIGH_OFF_WRCH_0,DMA Write SAR High Register" line.long 0x0C "DMA_DAR_LOW_OFF_WRCH_0,DMA Write DAR Low Register" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_0,DMA Write DAR High Register" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_0,DMA Write Linked List Pointer Low Register" line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_0,DMA Write Linked List Pointer High Register" group.long 0x1D0++0x03 line.long 0x00 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register" hexmask.long.word 0x00 0.--9. 1. " AUX_CLK_FREQ ,The auxiliary clock frequency in MHz" group.long 0x1D4++0x03 line.long 0x00 "L1_SUBSTATER_OFF,L1 Substates Timing Register" bitfld.long 0x00 6.--7. " L1SUB_T_PCLKACK ,Max delay between a MAC remove request and a PHY response" "0,1,2,3,?..." bitfld.long 0x00 2.--5. " L1SUB_T_L1_2 ,Duration of L1.2" "0,1us,2us,3us,4us,5us,6us,7us,8us,9us,10us,11us,12us,13us,14us,15us" textline " " bitfld.long 0x00 0.--1. " L1SUB_T_POWER_OFF ,Duration of L1.2 entry" "0us,1us,2us,3us" endif width 0x0B tree.end tree.end tree "ENET (Ethernet MAC)" base ad:0x30BE0000 width 9. group.long 0x04++0x07 line.long 0x00 "EIR,Interrupt Event Register" eventfld.long 0x00 30. " BABR ,Babbling receive error" "No error,Error" eventfld.long 0x00 29. " BABT ,Babbling transmit error" "No error,Error" eventfld.long 0x00 28. " GRA ,Graceful stop complete" "Not completed,Completed" textline " " eventfld.long 0x00 27. " TXF ,Transmit frame interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " TXB ,Transmit buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " RXF ,Receive frame interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 24. " RXB ,Receive buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " MII ,MII interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " EBERR ,Ethernet bus error" "No error,Error" textline " " eventfld.long 0x00 21. " LC ,Late collision occur" "Not occurred,Occurred" eventfld.long 0x00 20. " RL ,Collision retry limit occur" "Not occurred,Occurred" eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "No underrun,Underrun" textline " " eventfld.long 0x00 18. " PLR ,Payload receive error" "No error,Error" eventfld.long 0x00 17. " WAKEUP ,Node wakeup request indication" "Not detected,Detected" eventfld.long 0x00 16. " TS_AVAIL ,Transmit timestamp available" "Not available,Available" textline " " eventfld.long 0x00 15. " TS_TIMER ,Timestamp timer reached period event" "Not reached,Reached" eventfld.long 0x00 14. " RXFLUSH_2 ,RX DMA ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 13. " RXFLUSH_1 ,RX DMA ring 1 flush indication" "Not flushed,Flushed" textline " " eventfld.long 0x00 12. " RXFLUSH_0 ,RX DMA ring 0 flush indication" "Not flushed,Flushed" eventfld.long 0x00 7. " TXF2 ,Transmit frame interrupt, class 2" "No interrupt,Interrupt" eventfld.long 0x00 6. " TXB2 ,Transmit buffer interrupt, class 2" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " RXF2 ,Receive frame interrupt, class 2" "No interrupt,Interrupt" eventfld.long 0x00 4. " RXB2 ,Receive buffer interrupt, class 2" "No interrupt,Interrupt" eventfld.long 0x00 3. " TXF1 ,Transmit frame interrupt, class 1" "No interrupt,Interrupt" textline " " eventfld.long 0x00 2. " TXB1 ,Transmit buffer interrupt, class 1" "No interrupt,Interrupt" eventfld.long 0x00 1. " RXF1 ,Receive frame interrupt, class 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " RXB1 ,Receive buffer interrupt, class 1" "No interrupt,Interrupt" line.long 0x04 "EIMR,Interrupt Mask Register" bitfld.long 0x04 30. " BABR ,BABR interrupt mask" "Masked,Not masked" bitfld.long 0x04 29. " BABT ,BABT interrupt mask" "Masked,Not masked" bitfld.long 0x04 28. " GRA ,GRA interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 27. " TXF ,TXF interrupt mask" "Masked,Not masked" bitfld.long 0x04 26. " TXB ,TXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 25. " RXF ,RXF interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 24. " RXB ,RXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 23. " MII ,MII interrupt mask" "Masked,Not masked" bitfld.long 0x04 22. " EBERR ,EBERR interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 21. " LC ,LC interrupt mask" "Masked,Not masked" bitfld.long 0x04 20. " RL ,RL interrupt mask" "Masked,Not masked" bitfld.long 0x04 19. " UN ,UN interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 18. " PLR ,PLR interrupt mask" "Masked,Not masked" bitfld.long 0x04 17. " WAKEUP ,WAKEUP interrupt mask" "Masked,Not masked" bitfld.long 0x04 16. " TS_AVAIL ,TS_AVAIL interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 15. " TS_TIMER ,TS_TIMER interrupt mask" "Masked,Not masked" bitfld.long 0x04 14. " RXFLUSH_2 ,RXFLUSH_2 interrupt mask" "Masked,Not masked" bitfld.long 0x04 13. " RXFLUSH_1 ,RXFLUSH_1 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 12. " RXFLUSH_0 ,RXFLUSH_0 interrupt mask" "Masked,Not masked" bitfld.long 0x04 7. " TXF2 ,TXF2 interrupt mask" "Masked,Not masked" bitfld.long 0x04 6. " TXB2 ,TXB2 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 5. " RXF2 ,RXF2 interrupt mask" "Masked,Not masked" bitfld.long 0x04 4. " RXB2 ,RXB2 interrupt mask" "Masked,Not masked" bitfld.long 0x04 3. " TXF1 ,TXF1 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 2. " TXB1 ,TXB1 interrupt mask" "Masked,Not masked" bitfld.long 0x04 1. " RXF1 ,RXF1 interrupt mask" "Masked,Not masked" bitfld.long 0x04 0. " RXB1 ,RXB1 interrupt mask" "Masked,Not masked" group.long 0x10++0x07 line.long 0x00 "RDAR ,Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "TDAR ,Transmit Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" if (((per.l(ad:0x30BE0000+0x24)&0x08)==0x08)) group.long 0x24++0x03 line.long 0x00 "ECR,Ethernet Control Register" bitfld.long 0x00 11. " SVLANDBL ,S-VLAN double tag require" "Not required,Required" bitfld.long 0x00 10. " VLANUSE2ND ,VLAN use second tag" "Not used,Used" bitfld.long 0x00 9. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " DBSWP ,Descriptor byte swapping enable" "Not swapped,Swapped" bitfld.long 0x00 6. " DBGEN ,Enter hardware freeze mode while device enters debug mode" "Debug mode only,Freeze mode in debug mode" bitfld.long 0x00 5. " SPEED ,Select between 10/100-Mbit/s and 1000-Mbit/s modes of operation" "10/100-Mbit/s,1000-Mbit/s" textline " " bitfld.long 0x00 4. " EN1588 ,Enhanced functionality of the MAC select" "Legacy FEC buffer,Enhanced frame time-stamping" bitfld.long 0x00 3. " SLEEP ,Sleep mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " MAGICEN ,Magic packet detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ETHEREN ,Enable the ethernet MAC" "Disabled,Enabled" bitfld.long 0x00 0. " RESET ,Ethernet MAC reset" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "ECR,Ethernet Control Register" bitfld.long 0x00 11. " SVLANDBL ,S-VLAN double tag require" "Not required,Required" bitfld.long 0x00 10. " VLANUSE2ND ,VLAN use second tag" "Not used,Used" bitfld.long 0x00 9. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " DBSWP ,Descriptor byte swapping enable" "Not swapped,Swapped" bitfld.long 0x00 6. " DBGEN ,Enter hardware freeze mode while device enters debug mode" "Debug mode only,Freeze mode in debug mode" bitfld.long 0x00 5. " SPEED ,Select between 10/100-Mbit/s and 1000-Mbit/s modes of operation" "10/100-Mbit/s,1000-Mbit/s" textline " " bitfld.long 0x00 4. " EN1588 ,Enhanced functionality of the MAC select" "Legacy FEC buffer,Enhanced frame time-stamping" bitfld.long 0x00 3. " SLEEP ,Sleep mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " ETHEREN ,Enable the ethernet MAC" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RESET ,Ethernet MAC reset" "Disabled,Enabled" endif group.long 0x40++0x07 line.long 0x00 "MMFR,MII Management Frame Register" bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "Extended MDIO,Standard MDIO,?..." bitfld.long 0x00 28.--29. " OP ,Operation code" "Address write,Write operation,Read inc operation,Read operation" hexmask.long.byte 0x00 23.--27. 0x80 " PA ,PHY address" textline " " hexmask.long.byte 0x00 18.--22. 0x04 " RA ,Register address" bitfld.long 0x00 16.--17. " TA ,Turn around" ",,Enabled,?..." hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data" line.long 0x04 "MSCR,MII Speed Control Register" bitfld.long 0x04 8.--10. " HOLDTIME ,Hold time On MDIO Output [internal module clock cycle]" "1,2,3,,,,,8" bitfld.long 0x04 7. " DIS_PRE ,Disable preamble" "No,Yes" bitfld.long 0x04 1.--6. " MII_SPEED ,MII speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x64++0x03 line.long 0x00 "MIBC,MIB Control Register" bitfld.long 0x00 31. " MIB_DIS ,Disable MIB logic" "No,Yes" rbitfld.long 0x00 30. " MIB_IDLE ,MIB block updating/not updating(idle) counters mode" "Updating,Idle" bitfld.long 0x00 29. " MIB_CLEAR ,MIB clear (reset statistic counters)" "No effect,Clear" if (((per.l(ad:0x30BE0000+0x84)&0x1000)==0x00)) if (((per.l(ad:0x30BE0000+0x84)&0x100)==0x100)) group.long 0x84++0x03 line.long 0x00 "RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stop" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Enables/disables a payload length check" "Disabled,Enabled" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" textline " " bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" bitfld.long 0x00 14. " CRCFWD ,CRC field of received frames were transmitted/stripped" "Transmitted,Stripped" bitfld.long 0x00 13. " PAUFWD ,Terminate/Forward pause frames" "Terminated,Forwarded" textline " " bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Disabled,Enabled" bitfld.long 0x00 9. " RMII_10T ,100-Mbits/10-Mbits mode of the RMII or RGMII" "100-Mbit/s,10-Mbit/s" bitfld.long 0x00 8. " RMII_MODE ,MAC MII/RMII mode enable" "MII,RMII" textline " " bitfld.long 0x00 6. " RGMII_EN ,RGMII mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected" textline " " bitfld.long 0x00 3. " PROM ,Promiscuous mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",RMII" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" textline " " bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" else group.long 0x84++0x03 line.long 0x00 "RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stop" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Enables/disables a payload length check" "Disabled,Enabled" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" textline " " bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" bitfld.long 0x00 14. " CRCFWD ,CRC field of received frames were transmitted/stripped" "Transmitted,Stripped" bitfld.long 0x00 13. " PAUFWD ,Terminate/Forward pause frames" "Terminated,Forwarded" textline " " bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Disabled,Enabled" bitfld.long 0x00 9. " RMII_10T ,100-Mbits/10-Mbits mode of the RMII or RGMII" "100-Mbit/s,10-Mbit/s" bitfld.long 0x00 8. " RMII_MODE ,MAC MII/RMII mode enable" "MII,RMII" textline " " bitfld.long 0x00 6. " RGMII_EN ,RGMII mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected" textline " " bitfld.long 0x00 3. " PROM ,Promiscuous mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",MII" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" textline " " bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" endif else if (((per.l(ad:0x30BE0000+0x84)&0x100)==0x100)) group.long 0x84++0x03 line.long 0x00 "RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stop" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Enables/disables a payload length check" "Disabled,Enabled" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" textline " " bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" bitfld.long 0x00 13. " PAUFWD ,Terminate/Forward pause frames" "Terminated,Forwarded" bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMII_10T ,100-Mbits/10-Mbits mode of the RMII or RGMII" "100-Mbit/s,10-Mbit/s" bitfld.long 0x00 8. " RMII_MODE ,MAC MII/RMII mode enable" "MII,RMII" bitfld.long 0x00 6. " RGMII_EN ,RGMII mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected" bitfld.long 0x00 3. " PROM ,Promiscuous mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",RMII" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" else group.long 0x84++0x03 line.long 0x00 "RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stop" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Enables/disables a payload length check" "Disabled,Enabled" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" textline " " bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" bitfld.long 0x00 13. " PAUFWD ,Terminate/Forward pause frames" "Terminated,Forwarded" bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMII_10T ,100-Mbits/10-Mbits mode of the RMII or RGMII" "100-Mbit/s,10-Mbit/s" bitfld.long 0x00 8. " RMII_MODE ,MAC MII/RMII mode enable" "MII,RMII" bitfld.long 0x00 6. " RGMII_EN ,RGMII mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected" bitfld.long 0x00 3. " PROM ,Promiscuous mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",MII" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" endif endif if (((per.l(ad:0x30BE0000+0x24)&0x02)==0x00)) group.long 0xC4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Without CRC,With CRC" bitfld.long 0x00 8. " ADDINS ,Modify MAC address on transmit" "Not modified,Modified" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "Node MAC on PADDR1/2,?..." textline " " rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not paused,Paused" bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not paused,Paused" rbitfld.long 0x00 2. " FDEN ,Full-duplex enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped" else group.long 0xC4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Without CRC,With CRC" bitfld.long 0x00 8. " ADDINS ,Modify MAC address on transmit" "Not modified,Modified" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "Node MAC on PADDR1/2,?..." textline " " rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not paused,Paused" bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not paused,Paused" bitfld.long 0x00 2. " FDEN ,Full-duplex enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped" endif group.long 0xE4++0x0F line.long 0x00 "PALR ,Physical Address Lower Register" line.long 0x04 "PAUR ,Physical Address Upper Register" hexmask.long.byte 0x04 24.--31. 0x01 " PADDR2[1] ,4 byte of the 6-byte individual address used for exact match" hexmask.long.byte 0x04 16.--23. 0x01 " PADDR2[0] ,5 byte of the 6-byte individual address used for exact match" hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames" line.long 0x08 "OPD,Opcode/Pause Duration Register ENET_OPD" hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause duration" line.long 0x0C "TXIC,Transmit Interrupt Coalescing Register" bitfld.long 0x0C 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x0C 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET system" hexmask.long.byte 0x0C 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" textline " " hexmask.long.word 0x0C 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x100++0x03 line.long 0x00 "RXIC,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET system" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" textline " " hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x118++0x0F line.long 0x00 "IAUR,Descriptor Individual Upper Address Register" line.long 0x04 "IALR,Descriptor Individual Lower Address Register" line.long 0x08 "GAUR,Descriptor Group Upper Address Register" line.long 0x0C "GALR,Descriptor Group Lower Address Register" group.long 0x144++0x03 line.long 0x00 "TFWR,Transmit FIFO Watermark Register" bitfld.long 0x00 8. " STRFWD ,Store and forward enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " TFWR ,Transmit FIFO write" "64 bytes,64 bytes,128 bytes,192 bytes,256 bytes,320 bytes,384 bytes,448 bytes,512 bytes,576 bytes,640 bytes,704 bytes,768 bytes,832 bytes,896 bytes,960 bytes,1024 bytes,1088 bytes,1152 bytes,1216 bytes,1280 bytes,1344 bytes,1408 bytes,1472 bytes,1536 bytes,1600 bytes,1664 bytes,1728 bytes,1792 bytes,1856 bytes,1920 bytes,1984 bytes,2048 bytes,2112 bytes,2176 bytes,2240 bytes,2304 bytes,2368 bytes,2432 bytes,2496 bytes,2560 bytes,2624 bytes,2688 bytes,2752 bytes,2816 bytes,2880 bytes,2944 bytes,3008 bytes,3072 bytes,3136 bytes,3200 bytes,3264 bytes,3328 bytes,3392 bytes,3456 bytes,3520 bytes,3584 bytes,3648 bytes,3712 bytes,3776 bytes,3840 bytes,3904 bytes,3968 bytes,4032 bytes" group.long 0x160++0x0B line.long 0x00 "RDSR1,Receive Descriptor Ring 1 Start Register" hexmask.long 0x00 3.--31. 1. " R_DES_START ,Pointer to the beginning of the receive buffer descriptor queue 1" line.long 0x04 "TDSR1,Transmit Buffer Descriptor Ring 1 Start Register" hexmask.long 0x04 3.--31. 1. " X_DES_START ,Pointer to the beginning of the transmit buffer descriptor queue 1" line.long 0x08 "MRBR1,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x16C++0x0B line.long 0x00 "RDSR2,Receive Descriptor Ring 2 Start Register" hexmask.long 0x00 3.--31. 1. " R_DES_START ,Pointer to the beginning of the receive buffer descriptor queue 2" line.long 0x04 "TDSR2,Transmit Buffer Descriptor Ring 2 Start Register" hexmask.long 0x04 3.--31. 1. " X_DES_START ,Pointer to the beginning of the transmit buffer descriptor queue 2" line.long 0x08 "MRBR2,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x180++0x0B line.long 0x00 "RDSR,Receive Descriptor Ring 0 Start Register" hexmask.long 0x00 3.--31. 1. " R_DES_START ,Pointer to the beginning of the receive buffer descriptor queue $2" line.long 0x04 "TDSR,Transmit Buffer Descriptor Ring 0 Start Register" hexmask.long 0x04 3.--31. 1. " X_DES_START ,Pointer to the beginning of the transmit buffer descriptor queue $2" line.long 0x08 "MRBR,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x190++0x23 line.long 0x00 "RSFL,Receive FIFO Section Full Threshold" hexmask.long.word 0x00 0.--9. 1. " RX_SECTION_FULL ,Value of receive FIFO section full threshold" line.long 0x04 "RSEM,Receive FIFO Section Empty Threshold" bitfld.long 0x04 16.--20. " STAT_SECTION_EMPTY ,RX status FIFO section empty threshold" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--9. 1. " RX_SECTION_EMPTY ,Value of the receive FIFO section empty threshold" line.long 0x08 "RAEM,Receive FIFO Almost Empty Threshold" hexmask.long.word 0x08 0.--9. 1. " RX_ALMOST_EMPTY ,Value of the receive FIFO almost empty threshold" line.long 0x0C "RAFL,Receive FIFO Almost Full Threshold" hexmask.long.word 0x0C 0.--9. 1. " RX_ALMOST_FULL ,Value of the receive FIFO almost full threshold" line.long 0x10 "TSEM,Transmit FIFO Section Empty Threshold" hexmask.long.word 0x10 0.--9. 1. " TX_SECTION_EMPTY ,Value of the transmit FIFO section empty threshold" line.long 0x14 "TAEM,Transmit FIFO Almost Empty Threshold" hexmask.long.word 0x14 0.--9. 1. " TX_ALMOST_EMPTY ,Value of transmit FIFO almost empty threshold" line.long 0x18 "TAFL,Transmit FIFO Almost Full Threshold" hexmask.long.word 0x18 0.--9. 1. " TX_ALMOST_FULL ,Value of the transmit FIFO almost full threshold" line.long 0x1C "TIPG,Transmit Inter-Packet Gap" bitfld.long 0x1C 0.--4. " IPG ,Transmit inter-packet gap" "12,12,12,12,12,12,12,12,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,12,12,12,12,12" line.long 0x20 "FTRL,Frame Truncation Length" hexmask.long.word 0x20 0.--13. 1. " TRUNC_FL ,Frame truncation length" group.long 0x1C0++0x07 line.long 0x00 "TACC,Transmit Accelerator Function Configuration" bitfld.long 0x00 4. " PROCHK ,Enables insertion of protocol checksum" "Not inserted,Inserted" bitfld.long 0x00 3. " IPCHK ,Enables insertion of IP header checksum" "Not inserted,Inserted" bitfld.long 0x00 0. " SHIFT16 ,TX FIFO shift-16 enable" "Disabled,Enabled" line.long 0x04 "RACC,Receive Accelerator Function Configuration" bitfld.long 0x04 7. " SHIFT16 ,RX FIFO shift-16 enable" "Disabled,Enabled" bitfld.long 0x04 6. " LINEDIS ,Enable discard of frames with MAC layer errors" "Disabled,Enabled" bitfld.long 0x04 2. " PRODIS ,Enable discard of frames with wrong protocol checksum" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " IPDIS ,Enable discard of frames with wrong IPv4 header checksum" "Disabled,Enabled" bitfld.long 0x04 0. " PADREM ,Enable padding removal for short IP frames" "Disabled,Enabled" group.long 0x1C8++0x03 line.long 0x00 "RCMR0,Receive Classification Match Register For Class 0" bitfld.long 0x00 16. " MATCHEN ,Match enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long (0x1C8+0x10)++0x03 line.long 0x00 "DMA0CFG,DMA Class Based Configuration 0" bitfld.long 0x00 17. " CALC_NOIPG ,Disable inclusion of IPG bytes for bandwidth calculations" "No,Yes" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,Idle slope" group.long 0x1CC++0x03 line.long 0x00 "RCMR1,Receive Classification Match Register For Class 1" bitfld.long 0x00 16. " MATCHEN ,Match enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long (0x1CC+0x10)++0x03 line.long 0x00 "DMA1CFG,DMA Class Based Configuration 1" bitfld.long 0x00 17. " CALC_NOIPG ,Disable inclusion of IPG bytes for bandwidth calculations" "No,Yes" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,Idle slope" group.long 0x1E0++0x07 line.long 0x00 "RDAR0,Receive Descriptor Active Register - Ring 0" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "TDAR0,Transmit Descriptor Active Register - Ring 0" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" group.long 0x1E8++0x07 line.long 0x00 "RDAR1,Receive Descriptor Active Register - Ring 1" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "TDAR1,Transmit Descriptor Active Register - Ring 1" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" group.long 0x1F0++0x03 line.long 0x00 "QOS,QOS Scheme" bitfld.long 0x00 5. " RX_FLUSH2 ,Enable/disable RX flush for ring 2" "Disabled,Enabled" bitfld.long 0x00 4. " RX_FLUSH1 ,Enable/disable RX flush for ring 1" "Disabled,Enabled" bitfld.long 0x00 3. " RX_FLUSH1 ,Enable/disable RX flush for ring 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--2. " TX_SCHEME ,TX scheme configuration" "Credit-based scheme,Round-robin scheme,?..." textline " " width 20. rgroup.long 0x204++0x43 line.long 0x00 "RMON_T_PACKETS,Tx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " TXPKTS ,Transmit packet count" line.long 0x04 "RMON_T_BC_PKT,Tx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " TXPKTS ,Broadcast packets" line.long 0x08 "RMON_T_MC_PKT,Tx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " TXPKTS ,Multicast packets" line.long 0x0C "RMON_T_CRC_ALIGN,Tx Packets With CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " TXPKTS ,Packets with CRC/align error" line.long 0x10 "RMON_T_UNDERSIZE,Tx Packets Less Than Bytes And Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " TXPKTS ,Number of transmit packets less than 64 bytes with good CRC" line.long 0x14 "RMON_T_OVERSIZE,Tx Packets GT MAX_FL Bytes And Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes with good CRC" line.long 0x18 "RMON_T_FRAG,Tx Packets Less Than 64 Bytes And Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " TXPKTS ,Number of packets less than 64 bytes with bad CRC" line.long 0x1C "RMON_T_JAB,Tx Packets Greater Than MAX_FL Bytes And Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes and bad CRC" line.long 0x20 "RMON_T_COL,Tx Collision Count Statistic Register" hexmask.long.word 0x20 0.--15. 1. " TXPKTS ,Number of transmit collisions" line.long 0x24 "RMON_T_P64,Tx 64-Byte Packets Statistic Register" hexmask.long.word 0x24 0.--15. 1. " TXPKTS ,Number of 64-byte transmit packets" line.long 0x28 "RMON_T_P65TO127,Tx 65- to 127-byte Packets Statistic Register" hexmask.long.word 0x28 0.--15. 1. " TXPKTS ,Number of 65- to 127-byte transmit packets" line.long 0x2C "RMON_T_P128TO255,Tx 128- to 255-byte Packets Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " TXPKTS ,Number of 128- to 255-byte transmit packets" line.long 0x30 "RMON_T_P256TO511,Tx 256- to 511-byte Packets Statistic Register" hexmask.long.word 0x30 0.--15. 1. " TXPKTS ,Number of 256- to 511-byte transmit packets" line.long 0x34 "RMON_T_P512TO1023,Tx 512- to 1023-byte Packets Statistic Register" hexmask.long.word 0x34 0.--15. 1. " TXPKTS ,Number of 512- to 1023-byte transmit packets" line.long 0x38 "RMON_T_P1024TO2047,Tx 1024- to 2047-byte Packets Statistic Register" hexmask.long.word 0x38 0.--15. 1. " TXPKTS ,Number of 1024- to 2047-byte transmit packets" line.long 0x3C "RMON_T_P_GTE2048,Tx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x3C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than 2048 bytes" line.long 0x40 "RMON_T_OCTETS,Tx Octets Statistic Register" rgroup.long 0x24C++0x1F line.long 0x00 "IEEE_T_FRAME_OK,Frames Transmitted OK Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of frames transmitted OK" line.long 0x04 "IEEE_T_1COL,Frames Transmitted With Single Collision Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of frames transmitted with one collision" line.long 0x08 "IEEE_T_MCOL,Frames Transmitted With Multiple Collisions Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of frames transmitted with multiple collisions" line.long 0x0C "IEEE_T_DEF,Frames Transmitted After Deferral Delay Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of frames transmitted with deferral delay" line.long 0x10 "IEEE_T_LCOL,Frames Transmitted With Late Collision Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of frames transmitted with late collision" line.long 0x14 "IEEE_T_EXCOL,Frames Transmitted With Excessive Collisions Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of frames transmitted with excessive collisions" line.long 0x18 "IEEE_T_MACERR,Frames Transmitted With Tx FIFO Underrun Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of frames transmitted with transmit FIFO underrun" line.long 0x1C "IEEE_T_CSERR,Frames Transmitted With Carrier Sense Error Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of frames transmitted with carrier sense error" rgroup.long 0x270++0x07 line.long 0x00 "IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of flow-control pause frames transmitted" line.long 0x04 "IEEE_T_OCTETS_OK,Octet Count For Frames Transmitted w/o Error Statistic Register" rgroup.long 0x284++0x1F line.long 0x00 "RMON_R_PACKETS,Rx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of packets received" line.long 0x04 "RMON_R_BC_PKT,Rx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of receive broadcast packets" line.long 0x08 "RMON_R_MC_PKT,Rx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of receive multicast packets" line.long 0x0C "RMON_R_CRC_ALIGN ,Rx Packets With CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of receive packets with CRC or align error" line.long 0x10 "RMON_R_UNDERSIZE ,Rx Packets With Less Than 64 Bytes and Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and good CRC" line.long 0x14 "RMON_R_OVERSIZE ,Rx Packets Greater Than MAX_FL and Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and good CRC" line.long 0x18 "RMON_R_FRAG ,Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and bad CRC" line.long 0x1C "RMON_R_JAB ,Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and bad CRC" rgroup.long 0x2A8++0x3B line.long 0x00 "RMON_R_P64,Rx 64-Byte Packets Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of 64-byte receive packets" line.long 0x04 "RMON_R_P65TO127,Rx 65- To 127-Byte Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of 65- to 127-byte recieve packets" line.long 0x08 "RMON_R_P128TO255,Rx 128- To 255-Byte Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of 128- to 255-byte recieve packets" line.long 0x0C "RMON_R_P256TO511,Rx 256- To 511-Byte Packets Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of 256- to 511-byte recieve packets" line.long 0x10 "RMON_R_P512TO1023,Rx 512- To 1023-Byte Packets Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of 512- to 1023-byte recieve packets" line.long 0x14 "RMON_R_P1024TO2047,Rx 1024- To 2047-Byte Packets Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of 1024- to 2047-byte recieve packets" line.long 0x18 "RMON_R_P_GTE2048,Rx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of greater-than-2048-byte recieve packets" line.long 0x1C "RMON_R_OCTETS,Rx Octets Statistic Register" line.long 0x20 "IEEE_R_DROP,Frames Not Counted Correctly Statistic Register" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Frame count" line.long 0x24 "IEEE_R_FRAME_OK,Frames Received OK Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of frames received OK" line.long 0x28 "IEEE_R_CRC,Frames Received With CRC Error Statistic Register" hexmask.long.word 0x28 0.--15. 1. " COUNT ,Number of frames received with CRC error" line.long 0x2C "IEEE_R_ALIGN,Frames Received With Alignment Error Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " COUNT ,Number of frames received with alignment error" line.long 0x30 "IEEE_R_MACERR,Receive FIFO Overflow Count Statistic Register" hexmask.long.word 0x30 0.--15. 1. " COUNT ,Receive FIFO overflow count" line.long 0x34 "IEEE_R_FDXFC,Flow Control Pause Frames Received Statistic Register" hexmask.long.word 0x34 0.--15. 1. " COUNT ,Number of flow-control pause frames received" line.long 0x38 "IEEE_R_OCTETS_OK,Octet Count For Frames Received Without Error Statistic Register" group.long 0x400++0x17 line.long 0x00 "ATCR,Adjustable Timer Control Register" bitfld.long 0x00 13. " SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture current time" "No effect,Time captured" bitfld.long 0x00 9. " RESTART ,Reset timer" "No reset,Reset" textline " " bitfld.long 0x00 7. " PINPER ,Enables event signal output assertion on period event" "Disabled,Enabled" bitfld.long 0x00 4. " PEREN ,Enable periodical event" "Disabled,Enabled" bitfld.long 0x00 3. " OFFRST ,Reset timer on offset event" "No reset,Reset" textline " " bitfld.long 0x00 2. " OFFEN ,Enable one-shot offset event" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable timer" "Disabled,Enabled" line.long 0x04 "ATVR,Timer Value Register" line.long 0x08 "ATOFF,Timer Offset Register" line.long 0x0C "ATPER,Timer Period Register" line.long 0x10 "ATCOR,Timer Correction Register" hexmask.long 0x10 0.--30. 1. " COR ,Correction counter wrap-around value" line.long 0x14 "ATINC,Time-Stamping Clock Period Register" hexmask.long.byte 0x14 8.--14. 1. " INC_CORR ,Correction increment value" hexmask.long.byte 0x14 0.--6. 1. " INC ,Clock period of the timestamping clock in nanoseconds" rgroup.long 0x418++0x03 line.long 0x00 "ATSTMP,Timestamp of Last Transmitted Frame" group.long 0x604++0x03 line.long 0x00 "TGSR,Timer Global Status Register" eventfld.long 0x00 3. " TF3 ,Copy of timer flag for channel 3" "Clear,Set" eventfld.long 0x00 2. " TF2 ,Copy of timer flag for channel 2" "Clear,Set" eventfld.long 0x00 1. " TF1 ,Copy of timer flag for channel 1" "Clear,Set" textline " " eventfld.long 0x00 0. " TF0 ,Copy of timer flag for channel 0" "Clear,Set" group.long 0x608++0x07 line.long 0x00 "TCSR0,Timer Control Status Register" eventfld.long 0x00 7. " TF ,Timer flag occur" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Rising edge,Falling edge,Both edges,Software only,Toggle output on compare,Clear output on compare,Set output on compare,,Set output on compare,Clear output on compare,Set output on compare,,,Pulse output low,Pulse output high" textline " " bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR0,Timer Compare Capture Register" group.long 0x610++0x07 line.long 0x00 "TCSR1,Timer Control Status Register" eventfld.long 0x00 7. " TF ,Timer flag occur" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Rising edge,Falling edge,Both edges,Software only,Toggle output on compare,Clear output on compare,Set output on compare,,Set output on compare,Clear output on compare,Set output on compare,,,Pulse output low,Pulse output high" textline " " bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR1,Timer Compare Capture Register" group.long 0x618++0x07 line.long 0x00 "TCSR2,Timer Control Status Register" eventfld.long 0x00 7. " TF ,Timer flag occur" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Rising edge,Falling edge,Both edges,Software only,Toggle output on compare,Clear output on compare,Set output on compare,,Set output on compare,Clear output on compare,Set output on compare,,,Pulse output low,Pulse output high" textline " " bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR2,Timer Compare Capture Register" group.long 0x620++0x07 line.long 0x00 "TCSR3,Timer Control Status Register" eventfld.long 0x00 7. " TF ,Timer flag occur" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Rising edge,Falling edge,Both edges,Software only,Toggle output on compare,Clear output on compare,Set output on compare,,Set output on compare,Clear output on compare,Set output on compare,,,Pulse output low,Pulse output high" textline " " bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR3,Timer Compare Capture Register" width 0x0B tree.end tree.end tree.open "Timers" tree "GPT (General Purpose Timer)" tree "GPT1" base ad:0x302D0000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" textline " " bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" textline " " bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." textline " " bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" textline " " eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT2" base ad:0x302E0000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" textline " " bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" textline " " bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." textline " " bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" textline " " eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT3" base ad:0x302F0000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" textline " " bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" textline " " bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." textline " " bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" textline " " eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT4" base ad:0x30700000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" textline " " bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" textline " " bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." textline " " bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" textline " " eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT5" base ad:0x306F0000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" textline " " bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" textline " " bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." textline " " bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" textline " " eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT6" base ad:0x306E0000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" textline " " bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" textline " " bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." textline " " bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" textline " " eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree.end tree.open "PWM (Pulse Width Modulation)" tree "PWM1" base ad:0x30660000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration [rollover/comparison}" "Set/cleared,Cleared/set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select clock source" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Above mark,Below mark" textline " " rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM2" base ad:0x30670000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration [rollover/comparison}" "Set/cleared,Cleared/set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select clock source" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Above mark,Below mark" textline " " rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM3" base ad:0x30680000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration [rollover/comparison}" "Set/cleared,Cleared/set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select clock source" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Above mark,Below mark" textline " " rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM4" base ad:0x30690000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration [rollover/comparison}" "Set/cleared,Cleared/set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select clock source" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Above mark,Below mark" textline " " rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree.end tree.end tree.open "Multimedia" tree "eLCDIF (Enhanced LCD Interface)" base ad:0x30320000 width 16. sif !cpuis("IMX8MQ")&&!cpuis("IMX8MQ-CM4") if (((per.l(ad:0x30320000)&0x300)==0x00)) group.long 0x0++0x3 line.long 0x00 "CTRL,eLCDIF General Control Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST_SET/CLR ,Disable normal operation of the eLCDIF" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Disable normal operation" "No,Yes" textline " " setclrfld.long 0x00 26. 0x04 26. 0x08 26. " DATA_SHIFT_DIR_SET/CLR ,Direction of shift of transmit data" "Left,Right" bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " BYPASS_COUNT_SET/CLR ,Bypass block operation" "Not bypassed,Bypassed" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DOTCLK_MODE_SET/CLR ,DOTCLK mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ENABLE_PXP_HANDSHAKE_SET/CLR ,PXP handshake enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " MASTER_SET/CLR ,eLCDIF act as a bus master" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DATA_FORMAT_16_BIT_SET/CLR ,16 bit data format" "RGB565,ARGB555" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_SET/CLR ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" elif (((per.l(ad:0x30320000)&0x300)==0x200)) group.long 0x0++0x3 line.long 0x00 "CTRL,eLCDIF General Control Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST_SET/CLR ,Disable normal operation of the eLCDIF" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Disable normal operation" "No,Yes" textline " " setclrfld.long 0x00 26. 0x04 26. 0x08 26. " DATA_SHIFT_DIR_SET/CLR ,Direction of shift of transmit data" "Left,Right" bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " BYPASS_COUNT_SET/CLR ,Bypass block operation" "Not bypassed,Bypassed" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DOTCLK_MODE_SET/CLR ,Dotclk mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ENABLE_PXP_HANDSHAKE_SET/CLR ,PXP handshake enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " MASTER_SET/CLR ,eLCDIF act as a bus master" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DATA_FORMAT_18_BIT_SET/CLR ,Lower/upper data bits validation" "Lower 18 bits,Upper 18 bits" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_SET/CLR ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" elif (((per.l(ad:0x30320000)&0x300)==0x300)) group.long 0x0++0x3 line.long 0x00 "CTRL,eLCDIF General Control Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST_SET/CLR ,Disable normal operation of the eLCDIF" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Disable normal operation" "No,Yes" textline " " setclrfld.long 0x00 26. 0x04 26. 0x08 26. " DATA_SHIFT_DIR_SET/CLR ,Direction of shift of transmit data" "Left,Right" bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " BYPASS_COUNT_SET/CLR ,Bypass block operation" "Not bypassed,Bypassed" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DOTCLK_MODE_SET/CLR ,Dotclk mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ENABLE_PXP_HANDSHAKE_SET/CLR ,PXP handshake enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " MASTER_SET/CLR ,eLCDIF act as a bus master" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x00 1. " DATA_FORMAT_24_BIT_SET/CLR ,24 bit data format" "24 bits valid,Drop upper 2 bits per byte" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_SET/CLR ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0x0++0x3 line.long 0x00 "CTRL,eLCDIF General Control Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST_SET/CLR ,Disable normal operation of the eLCDIF" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Disable normal operation" "No,Yes" textline " " setclrfld.long 0x00 26. 0x04 26. 0x08 26. " DATA_SHIFT_DIR_SET/CLR ,Direction of shift of transmit data" "Left,Right" bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " BYPASS_COUNT_SET/CLR ,Bypass block operation" "Not bypassed,Bypassed" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DOTCLK_MODE_SET/CLR ,Dotclk mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ENABLE_PXP_HANDSHAKE_SET/CLR ,PXP handshake enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " MASTER_SET/CLR ,eLCDIF act as a bus master" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_SET/CLR ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif else if (((per.l(ad:0x30320000)&0x300)==0x00)) if (((per.l(ad:0x30320000)&0x40000)==0x40000)) group.long 0x0++0x3 line.long 0x00 "CTRL,eLCDIF General Control Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST_SET/CLR ,Disable normal operation of the eLCDIF" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Disable normal operation" "No,Yes" textline " " setclrfld.long 0x00 29. 0x04 29. 0x08 29. " YCBCR422_INPUT_SET/CLR ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " READ_WRITEB_SET/CLR ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " WAIT_FOR_VSYNC_EDGE_SET/CLR ,Hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "No wait,Wait" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " DATA_SHIFT_DIR_SET/CLR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " DVI_MODE_SET/CLR ,DVI mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " BYPASS_COUNT_SET/CLR ,Bypass block operation" "Not bypassed,Bypassed" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " VSYNC_MODE_SET/CLR ,VSYNC mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DOTCLK_MODE_SET/CLR ,DOTCLK mode enable" "Disabled,Enabled" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA_SELECT_SET/CLR ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " RGB_TO_YCBCR422_CSC_SET/CLR ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ENABLE_PXP_HANDSHAKE_SET/CLR ,PXP handshake enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " MASTER_SET/CLR ,Enable LCDIF act as a bus master" "Disabled,Enabled" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DATA_FORMAT_16_BIT_SET/CLR ,16 bit data format" "RGB565,ARGB555" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_SET/CLR ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0x0++0x3 line.long 0x00 "CTRL,eLCDIF General Control Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST_SET/CLR ,Disable normal operation of the eLCDIF" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Disable normal operation" "No,Yes" textline " " setclrfld.long 0x00 29. 0x04 29. 0x08 29. " YCBCR422_INPUT_SET/CLR ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " READ_WRITEB_SET/CLR ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 26. 0x04 26. 0x08 26. " DATA_SHIFT_DIR_SET/CLR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " DVI_MODE_SET/CLR ,DVI mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " BYPASS_COUNT_SET/CLR ,Bypass block operation" "Not bypassed,Bypassed" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " VSYNC_MODE_SET/CLR ,VSYNC mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DOTCLK_MODE_SET/CLR ,DOTCLK mode enable" "Disabled,Enabled" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA_SELECT_SET/CLR ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " RGB_TO_YCBCR422_CSC_SET/CLR ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ENABLE_PXP_HANDSHAKE_SET/CLR ,PXP handshake enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " MASTER_SET/CLR ,Enable LCDIF act as a bus master" "Disabled,Enabled" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DATA_FORMAT_16_BIT_SET/CLR ,16 bit data format" "RGB565,ARGB555" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_SET/CLR ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif elif (((per.l(ad:0x30320000)&0x300)==0x200)) if (((per.l(ad:0x30320000)&0x40000)==0x40000)) group.long 0x0++0x3 line.long 0x00 "CTRL,eLCDIF General Control Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST_SET/CLR ,Disable normal operation of the eLCDIF" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Disable normal operation" "No,Yes" textline " " setclrfld.long 0x00 29. 0x04 29. 0x08 29. " YCBCR422_INPUT_SET/CLR ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " READ_WRITEB_SET/CLR ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " WAIT_FOR_VSYNC_EDGE_SET/CLR ,Hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "No wait,Wait" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " DATA_SHIFT_DIR_SET/CLR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " DVI_MODE_SET/CLR ,DVI mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " BYPASS_COUNT_SET/CLR ,Bypass block operation" "Not bypassed,Bypassed" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " VSYNC_MODE_SET/CLR ,VSYNC mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DOTCLK_MODE_SET/CLR ,DOTCLK mode enable" "Disabled,Enabled" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA_SELECT_SET/CLR ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " RGB_TO_YCBCR422_CSC_SET/CLR ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ENABLE_PXP_HANDSHAKE_SET/CLR ,PXP handshake enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " MASTER_SET/CLR ,Enable LCDIF act as a bus master" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DATA_FORMAT_18_BIT_SET/CLR ,Lower/upper data bits validation" "Lower 18 bits,Upper 18 bits" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_SET/CLR ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0x0++0x3 line.long 0x00 "CTRL,eLCDIF General Control Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST_SET/CLR ,Disable normal operation of the eLCDIF" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Disable normal operation" "No,Yes" textline " " setclrfld.long 0x00 29. 0x04 29. 0x08 29. " YCBCR422_INPUT_SET/CLR ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " READ_WRITEB_SET/CLR ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 26. 0x04 26. 0x08 26. " DATA_SHIFT_DIR_SET/CLR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " DVI_MODE_SET/CLR ,DVI mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " BYPASS_COUNT_SET/CLR ,Bypass block operation" "Not bypassed,Bypassed" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " VSYNC_MODE_SET/CLR ,VSYNC mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DOTCLK_MODE_SET/CLR ,DOTCLK mode enable" "Disabled,Enabled" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA_SELECT_SET/CLR ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " RGB_TO_YCBCR422_CSC_SET/CLR ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ENABLE_PXP_HANDSHAKE_SET/CLR ,PXP handshake enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " MASTER_SET/CLR ,Enable LCDIF act as a bus master" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DATA_FORMAT_18_BIT_SET/CLR ,Lower/upper data bits validation" "Lower 18 bits,Upper 18 bits" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_SET/CLR ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif elif (((per.l(ad:0x30320000)&0x300)==0x300)) if (((per.l(ad:0x30320000)&0x40000)==0x40000)) group.long 0x0++0x3 line.long 0x00 "CTRL,eLCDIF General Control Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST_SET/CLR ,Disable normal operation of the eLCDIF" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Disable normal operation" "No,Yes" textline " " setclrfld.long 0x00 29. 0x04 29. 0x08 29. " YCBCR422_INPUT_SET/CLR ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " READ_WRITEB_SET/CLR ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " WAIT_FOR_VSYNC_EDGE_SET/CLR ,Hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "No wait,Wait" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " DATA_SHIFT_DIR_SET/CLR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " DVI_MODE_SET/CLR ,DVI mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " BYPASS_COUNT_SET/CLR ,Bypass block operation" "Not bypassed,Bypassed" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " VSYNC_MODE_SET/CLR ,VSYNC mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DOTCLK_MODE_SET/CLR ,DOTCLK mode enable" "Disabled,Enabled" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA_SELECT_SET/CLR ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " RGB_TO_YCBCR422_CSC_SET/CLR ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ENABLE_PXP_HANDSHAKE_SET/CLR ,PXP handshake enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " MASTER_SET/CLR ,Enable LCDIF act as a bus master" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x00 1. " DATA_FORMAT_24_BIT_SET/CLR ,24 bit data format" "24 bits valid,Drop upper 2 bits per byte" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_SET/CLR ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0x0++0x3 line.long 0x00 "CTRL,eLCDIF General Control Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST_SET/CLR ,Disable normal operation of the eLCDIF" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Disable normal operation" "No,Yes" textline " " setclrfld.long 0x00 29. 0x04 29. 0x08 29. " YCBCR422_INPUT_SET/CLR ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " READ_WRITEB_SET/CLR ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 26. 0x04 26. 0x08 26. " DATA_SHIFT_DIR_SET/CLR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " DVI_MODE_SET/CLR ,DVI mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " BYPASS_COUNT_SET/CLR ,Bypass block operation" "Not bypassed,Bypassed" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " VSYNC_MODE_SET/CLR ,VSYNC mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DOTCLK_MODE_SET/CLR ,DOTCLK mode enable" "Disabled,Enabled" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA_SELECT_SET/CLR ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " RGB_TO_YCBCR422_CSC_SET/CLR ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ENABLE_PXP_HANDSHAKE_SET/CLR ,PXP handshake enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " MASTER_SET/CLR ,Enable LCDIF act as a bus master" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x00 1. " DATA_FORMAT_24_BIT_SET/CLR ,24 bit data format" "24 bits valid,Drop upper 2 bits per byte" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_SET/CLR ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif else if (((per.l(ad:0x30320000)&0x40000)==0x40000)) group.long 0x0++0x3 line.long 0x00 "CTRL,eLCDIF General Control Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST_SET/CLR ,Disable normal operation of the eLCDIF" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Disable normal operation" "No,Yes" textline " " setclrfld.long 0x00 29. 0x04 29. 0x08 29. " YCBCR422_INPUT_SET/CLR ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " READ_WRITEB_SET/CLR ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " WAIT_FOR_VSYNC_EDGE_SET/CLR ,Hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "No wait,Wait" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " DATA_SHIFT_DIR_SET/CLR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " DVI_MODE_SET/CLR ,DVI mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " BYPASS_COUNT_SET/CLR ,Bypass block operation" "Not bypassed,Bypassed" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " VSYNC_MODE_SET/CLR ,VSYNC mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DOTCLK_MODE_SET/CLR ,DOTCLK mode enable" "Disabled,Enabled" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA_SELECT_SET/CLR ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " RGB_TO_YCBCR422_CSC_SET/CLR ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ENABLE_PXP_HANDSHAKE_SET/CLR ,PXP handshake enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " MASTER_SET/CLR ,Enable LCDIF act as a bus master" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_SET/CLR ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0x0++0x3 line.long 0x00 "CTRL,eLCDIF General Control Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST_SET/CLR ,Disable normal operation of the eLCDIF" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Disable normal operation" "No,Yes" textline " " setclrfld.long 0x00 29. 0x04 29. 0x08 29. " YCBCR422_INPUT_SET/CLR ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " READ_WRITEB_SET/CLR ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 26. 0x04 26. 0x08 26. " DATA_SHIFT_DIR_SET/CLR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " DVI_MODE_SET/CLR ,DVI mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " BYPASS_COUNT_SET/CLR ,Bypass block operation" "Not bypassed,Bypassed" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " VSYNC_MODE_SET/CLR ,VSYNC mode enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DOTCLK_MODE_SET/CLR ,DOTCLK mode enable" "Disabled,Enabled" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA_SELECT_SET/CLR ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap/Little endian,Big endian swap/Swap all bytes,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " RGB_TO_YCBCR422_CSC_SET/CLR ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ENABLE_PXP_HANDSHAKE_SET/CLR ,PXP handshake enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " MASTER_SET/CLR ,Enable LCDIF act as a bus master" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_SET/CLR ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif endif endif group.long 0x4++0x07 line.long 0x00 "CTRL_SET,eLCDIF General Control Register" bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" line.long 0x04 "CTRL_CLR,eLCDIF General Control Register" bitfld.long 0x04 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x04 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x04 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x04 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" sif !cpuis("IMX8MQ")&&!cpuis("IMX8MQ-CM4") if (((per.l(ad:0x30320000+0x0C)&0x300)==0x00)) group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 17. " DOTCLK_MODE ,Dotclk mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,eLCDIF act as a bus master" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16 bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" elif (((per.l(ad:0x30320000+0x0C)&0x300)==0x200)) group.long 0xC++0x3 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 17. " DOTCLK_MODE ,Dotclk mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,eLCDIF act as a bus master" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,Lower/upper data bits validation" "Lower 18 bits,Upper 18 bits" bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" elif (((per.l(ad:0x30320000+0x0C)&0x300)==0x300)) group.long 0xC++0x3 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 17. " DOTCLK_MODE ,Dotclk mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,eLCDIF act as a bus master" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24 bit data format" "24 bits valid,Drop upper 2 bits per byte" bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0xC++0x3 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 17. " DOTCLK_MODE ,Dotclk mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,eLCDIF act as a bus master" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif else if (((per.l(ad:0x30320000+0x0C)&0x300)==0x00)) if (((per.l(ad:0x30320000+0x0C)&0x40000)==0x40000)) if (((per.l(ad:0x30320000+0x0C)&0x01)==0x00)) group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "No wait,Wait" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16 bit data format" "RGB565,ARGB555" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "No wait,Wait" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16 bit data format" "RGB565,ARGB555" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif else if (((per.l(ad:0x30320000+0x0C)&0x01)==0x00)) group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16 bit data format" "RGB565,ARGB555" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16 bit data format" "RGB565,ARGB555" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif endif elif (((per.l(ad:0x30320000+0x0C)&0x300)==0x200)) if (((per.l(ad:0x30320000+0x0C)&0x40000)==0x40000)) if (((per.l(ad:0x30320000+0x0C)&0x01)==0x00)) group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "No wait,Wait" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,Lower/upper data bits validation" "Lower 18 bits,Upper 18 bits" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "No wait,Wait" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,Lower/upper data bits validation" "Lower 18 bits,Upper 18 bits" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif else if (((per.l(ad:0x30320000+0x0C)&0x01)==0x00)) group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,Lower/upper data bits validation" "Lower 18 bits,Upper 18 bits" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,Lower/upper data bits validation" "Lower 18 bits,Upper 18 bits" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif endif elif (((per.l(ad:0x30320000+0x0C)&0x300)==0x300)) if (((per.l(ad:0x30320000+0x0C)&0x40000)==0x40000)) if (((per.l(ad:0x30320000+0x0C)&0x01)==0x00)) group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "No wait,Wait" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24 bit data format" "24 bits valid,Drop upper 2 bits per byte" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "No wait,Wait" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24 bit data format" "24 bits valid,Drop upper 2 bits per byte" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif else if (((per.l(ad:0x30320000+0x0C)&0x01)==0x00)) group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24 bit data format" "24 bits valid,Drop upper 2 bits per byte" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24 bit data format" "24 bits valid,Drop upper 2 bits per byte" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif endif else if (((per.l(ad:0x30320000+0x0C)&0x40000)==0x40000)) if (((per.l(ad:0x30320000+0x0C)&0x01)==0x00)) group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "No wait,Wait" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "No wait,Wait" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif else if (((per.l(ad:0x30320000+0x0C)&0x01)==0x00)) group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Disable normal operation of the eLCDIF" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Disable normal operation" "No,Yes" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,RGB/YCbCr 4:2:2 input data selection" "RGB,YCBCR422" bitfld.long 0x00 28. " READ_WRITEB ,6800/8080 MPU read mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,Number of data to be transmitted shifted left or right" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,DVI mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass block operation" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "CMD_MODE,DATA_MODE" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swap the bytes mode fetched by the bus master interface" "No swap,Big endian swap,HWD swap,HWD byte swap" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swap the bytes mode after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian swap,HWD swap,HWD byte swap" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,PXP handshake enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,Enable LCDIF act as a bus master" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RUN ,eLCDIF begin transferring data between the SoC and the display" "Disabled,Enabled" endif endif endif endif textline " " group.long 0x10++0x0F line.long 0x00 "CTRL1,eLCDIF General Control1 Register" sif !cpuis("IMX8MQ")&&!cpuis("IMX8MQ-CM4") setclrfld.long 0x00 31. 0x04 31. 0x08 31. " IMAGE_DATA_SELECT_SET/CLR ,Command Mode MIPI image data select bit" "0,1" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CS_OUT_SELECT_SET/CLR ,CS0/CS1 valid select signals" "CS0,CS1" textline " " endif sif cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4") setclrfld.long 0x00 27. 0x04 27. 0x08 27. " COMBINE_MPU_WR_STRB_SET/CLR ,Enable write strobe of both the 6800 and 8080 modes drive only on the LCD_WR_RWn pin" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 26. 0x04 26. 0x08 26. " BM_ERROR_IRQ_EN_SET/CLR ,Enable bus master error interrupt in the eLCDIF master mode" "Disabled,Enabled" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " BM_ERROR_IRQ_SET/CLR ,Interrupt requested by the eLCDIF block" "Not requested,Requested" textline " " setclrfld.long 0x00 24. 0x04 24. 0x08 24. " RECOVER_ON_UNDERFLOW_SET/CLR ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " INTERLACE_FIELDS_SET/CLR ,eLCDIF block fetches odd lines in one field and even lines in the other field" "Not fetched,Fetched" textline " " setclrfld.long 0x00 22. 0x04 22. 0x08 22. " START_INTERLACE_FROM_SECOND_FIELD_SET/CLR ,Grab even lines first and then the odd lines" "Disabled,Enabled" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " FIFO_CLEAR_SET/CLR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No clear,Clear" textline " " setclrfld.long 0x00 20. 0x04 20. 0x08 20. " IRQ_ON_ALTERNATE_FIELDS_SET/CLR ,Select when eLCDIF block will assert the cur_frame_done interrupt" "Both fields,Alternate fields" bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,Data bytes in a 32-bit word which are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " setclrfld.long 0x00 15. 0x04 15. 0x08 15. " OVERFLOW_IRQ_EN_SET/CLR ,Enable an overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " UNDERFLOW_IRQ_EN_SET/CLR ,Enable an underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x04 13. 0x08 13. " CUR_FRAME_DONE_IRQ_EN_SET/CLR ,Enable an interrupt every time the hardware enters in the vertical blanking state" "No interrupt,Interrupt" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " VSYNC_EDGE_IRQ_EN_SET/CLR ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " OVERFLOW_IRQ_SET/CLR ,Interrupt is requested by the eLCDIF block" "Not requested,Requested" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " UNDERFLOW_IRQ_SET/CLR ,Interrupt is requested by the eLCDIF block" "Not requested,Requested" textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CUR_FRAME_DONE_IRQ_SET/CLR ,Interrupt is requested by the eLCDIF block" "Not requested,Requested" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " VSYNC_EDGE_IRQ_SET/CLR ,Interrupt is requested by the eLCDIF block" "Not requested,Requested" sif cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4") textline " " setclrfld.long 0x00 2. 0x04 2. 0x08 2. " BUSY_ENABLE_SET/CLR ,Busy signal input enable" "Disabled,Enabled" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " MODE86_SET/CLR ,Select 8080/6800 series of microprocessor mode" "8080,6800" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RESET_SET/CLR ,Reset bit for the external LCD controller" "No reset,Reset" endif line.long 0x04 "CTRL1_SET,eLCDIF General Control1 Register" bitfld.long 0x04 16.--19. " BYTE_PACKING_FORMAT ,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CTRL1_CLR,eLCDIF General Control1 Register" bitfld.long 0x08 16.--19. " BYTE_PACKING_FORMAT ,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "CTRL1_TOG,eLCDIF General Control1 Register" sif !cpuis("IMX8MQ")&&!cpuis("IMX8MQ-CM4") bitfld.long 0x0C 31. " IMAGE_DATA_SELECT ,Command Mode MIPI image data select bit" "0,1" bitfld.long 0x0C 30. " CS_OUT_SELECT ,CS0/CS1 valid select signals" "CS0,CS1" textline " " endif sif cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4") bitfld.long 0x0C 27. " COMBINE_MPU_WR_STRB ,Enable write strobe of both the 6800 and 8080 modes drive only on the LCD_WR_RWn pin" "Disabled,Enabled" textline " " endif bitfld.long 0x0C 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the eLCDIF master mode" "Disabled,Enabled" bitfld.long 0x0C 25. " BM_ERROR_IRQ ,Interrupt requested by the eLCDIF block" "Not requested,Requested" textline " " bitfld.long 0x0C 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x0C 23. " INTERLACE_FIELDS ,eLCDIF block fetches odd lines in one field and even lines in the other field" "Not fetched,Fetched" textline " " bitfld.long 0x0C 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab even lines first and then the odd lines" "Disabled,Enabled" bitfld.long 0x0C 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No clear,Clear" textline " " bitfld.long 0x0C 20. " IRQ_ON_ALTERNATE_FIELDS ,Select when eLCDIF block will assert the cur_frame_done interrupt" "Both fields,Alternate fields" bitfld.long 0x0C 16.--19. " BYTE_PACKING_FORMAT ,Data bytes in a 32-bit word which are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0C 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x0C 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" textline " " bitfld.long 0x0C 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "No interrupt,Interrupt" bitfld.long 0x0C 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "No interrupt,Interrupt" textline " " bitfld.long 0x0C 11. " OVERFLOW_IRQ ,Interrupt is requested by the eLCDIF block" "Not requested,Requested" bitfld.long 0x0C 10. " UNDERFLOW_IRQ ,Interrupt is requested by the eLCDIF block" "Not requested,Requested" textline " " bitfld.long 0x0C 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the eLCDIF block" "Not requested,Requested" bitfld.long 0x0C 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the eLCDIF block" "Not requested,Requested" sif cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4") textline " " bitfld.long 0x0C 2. " BUSY_ENABLE ,Busy signal input enable" "Disabled,Enabled" bitfld.long 0x0C 1. " MODE86 ,Select 8080/6800 series of microprocessor mode" "8080,6800" textline " " bitfld.long 0x0C 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" endif sif !cpuis("IMX8MQ")&&!cpuis("IMX8MQ-CM4") if (((per.l(ad:0x30320000)&0x20)==0x20)) group.long 0x20++0x3 line.long 0x00 "CTRL2,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." setclrfld.long 0x00 20. 0x04 20. 0x08 20. " BURST_LEN_8_SET/CLR ,Issue AXI bursts of length 16" "Not issued,Issued" textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." else group.long 0x20++0x3 line.long 0x00 "CTRL2,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." endif else if (((per.l(ad:0x30320000)&0x20)==0x20)) if (((per.l(ad:0x30320000)&0xC00)==0x400)) group.long 0x20++0x3 line.long 0x00 "CTRL2,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." setclrfld.long 0x00 20. 0x04 20. 0x08 20. " BURST_LEN_8_SET/CLR ,Issue AXI bursts of length 16" "Not issued,Issued" textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " setclrfld.long 0x00 10. 0x04 10. 0x08 10. " READ_PACK_DIR_SET/CLR ,Little endian/Big endian data stored format" "Little endian,Big endian" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " READ_MODE_6_BIT_INPUT_SET/CLR ,Indicates that input data is 6 bits wide and exists on D5-D0" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" elif (((per.l(ad:0x30320000)&0xC00)==0x00)) group.long 0x20++0x3 line.long 0x00 "CTRL2,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." setclrfld.long 0x00 20. 0x04 20. 0x08 20. " BURST_LEN_8_SET/CLR ,Issue AXI bursts of length 16" "Not issued,Issued" textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT_SET/CLR ,Enable the LCDIF to convert the incoming data to the RGB format" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " READ_MODE_6_BIT_INPUT_SET/CLR ,Indicates that input data is 6 bits wide and exists on D5-D0" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 16-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" else group.long 0x20++0x3 line.long 0x00 "CTRL2,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." setclrfld.long 0x00 20. 0x04 20. 0x08 20. " BURST_LEN_8_SET/CLR ,Issue AXI bursts of length 16" "Not issued,Issued" textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT_SET/CLR ,Enable the LCDIF to convert the incoming data to the RGB format" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " READ_MODE_6_BIT_INPUT_SET/CLR ,Indicates that input data is 6 bits wide and exists on D5-D0" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 16-bit subwords that will be packed into the 32-bit word in read mode" "0,1,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" endif else if (((per.l(ad:0x30320000)&0xC00)==0x400)) group.long 0x20++0x3 line.long 0x00 "CTRL2,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " setclrfld.long 0x00 10. 0x04 10. 0x08 10. " READ_PACK_DIR_SET/CLR ,Little endian/Big endian data stored format" "Little endian,Big endian" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " READ_MODE_6_BIT_INPUT_SET/CLR ,Indicates that input data is 6 bits wide and exists on D5-D0" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" elif (((per.l(ad:0x30320000)&0xC00)==0x00)) group.long 0x20++0x3 line.long 0x00 "CTRL2,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT_SET/CLR ,Enable the LCDIF to convert the incoming data to the RGB format" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " READ_MODE_6_BIT_INPUT_SET/CLR ,Indicates that input data is 6 bits wide and exists on D5-D0" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 16-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" else group.long 0x20++0x3 line.long 0x00 "CTRL2,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT_SET/CLR ,Enable the LCDIF to convert the incoming data to the RGB format" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " READ_MODE_6_BIT_INPUT_SET/CLR ,Indicates that input data is 6 bits wide and exists on D5-D0" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 16-bit subwords that will be packed into the 32-bit word in read mode" "0,1,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" endif endif endif sif !cpuis("IMX8MQ")&&!cpuis("IMX8MQ-CM4") group.long 0x24++0x07 line.long 0x00 "CTRL2_SET,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5," "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6," "RGB,RBG,GBR,GRB,BRG,BGR,?..." line.long 0x04 "CTRL2_CLR,eLCDIF General Control2 Register" bitfld.long 0x04 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x04 16.--18. " ODD_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5," "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x04 12.--14. " EVEN_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6," "RGB,RBG,GBR,GRB,BRG,BGR,?..." else if (((per.l(ad:0x30320000)&0xC00)==0x400)) group.long 0x24++0x07 line.long 0x00 "CTRL2_SET,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." textline " " bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x04 "CTRL2_CLR,eLCDIF General Control2 Register" bitfld.long 0x04 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x04 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x04 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x04 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." textline " " bitfld.long 0x04 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" elif (((per.l(ad:0x30320000)&0xC00)==0x00)) group.long 0x24++0x07 line.long 0x00 "CTRL2_SET,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 16-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,?..." textline " " bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x04 "CTRL2_CLR,eLCDIF General Control2 Register" bitfld.long 0x04 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x04 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x04 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x04 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." textline " " bitfld.long 0x04 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" else group.long 0x24++0x07 line.long 0x00 "CTRL2_SET,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 16-bit subwords that will be packed into the 32-bit word in read mode" "0,1,?..." textline " " bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x04 "CTRL2_CLR,eLCDIF General Control2 Register" bitfld.long 0x04 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x04 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x04 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x04 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." textline " " bitfld.long 0x04 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" endif endif sif !cpuis("IMX8MQ")&&!cpuis("IMX8MQ-CM4") if (((per.l(ad:0x30320000)&0x20)==0x20)) group.long 0x2C++0x3 line.long 0x00 "CTRL2_TOG,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,Issue AXI bursts of length 16" "Not issued,Issued" textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." else group.long 0x2C++0x3 line.long 0x00 "CTRL2_TOG,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." endif else if (((per.l(ad:0x30320000)&0x20)==0x20)) if (((per.l(ad:0x30320000)&0xC00)==0x400)) group.long 0x2C++0x03 line.long 0x00 "CTRL2_TOG,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,Issue AXI bursts of length 16" "Not issued,Issued" textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x00 10. " READ_PACK_DIR ,Little endian/Big endian data stored format" "Little endian,Big endian" bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Indicates that input data is 6 bits wide and exists on D5-D0" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" elif (((per.l(ad:0x30320000)&0xC00)==0x00)) group.long 0x2C++0x03 line.long 0x00 "CTRL2_TOG,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,Issue AXI bursts of length 16" "Not issued,Issued" textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the LCDIF to convert the incoming data to the RGB format" "Disabled,Enabled" bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Indicates that input data is 6 bits wide and exists on D5-D0" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 16-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" else group.long 0x2C++0x03 line.long 0x00 "CTRL2_TOG,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,Issue AXI bursts of length 16" "Not issued,Issued" textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the LCDIF to convert the incoming data to the RGB format" "Disabled,Enabled" bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Indicates that input data is 6 bits wide and exists on D5-D0" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 16-bit subwords that will be packed into the 32-bit word in read mode" "0,1,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" endif else if (((per.l(ad:0x30320000)&0xC00)==0x400)) group.long 0x2C++0x03 line.long 0x00 "CTRL2_TOG,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x00 10. " READ_PACK_DIR ,Little endian/Big endian data stored format" "Little endian,Big endian" bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Indicates that input data is 6 bits wide and exists on D5-D0" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" elif (((per.l(ad:0x30320000)&0xC00)==0x00)) group.long 0x2C++0x03 line.long 0x00 "CTRL2_TOG,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the LCDIF to convert the incoming data to the RGB format" "Disabled,Enabled" bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Indicates that input data is 6 bits wide and exists on D5-D0" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 16-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" else group.long 0x2C++0x03 line.long 0x00 "CTRL2_TOG,eLCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the LCDIF to convert the incoming data to the RGB format" "Disabled,Enabled" bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Indicates that input data is 6 bits wide and exists on D5-D0" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 16-bit subwords that will be packed into the 32-bit word in read mode" "0,1,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" endif endif endif group.long 0x30++0x3 line.long 0x00 "TRANSFER_COUNT,eLCDIF Horizontal and Vertical Valid Data Count Register" hexmask.long.word 0x00 16.--31. 1. " V_COUNT ,Number of horizontal lines per frame which contain valid data" hexmask.long.word 0x00 0.--15. 1. " H_COUNT ,Total valid data (pixels) in each horizontal line" group.long 0x40++0x3 line.long 0x00 "CUR_BUF,LCD Interface Current Buffer Address Register" group.long 0x50++0x3 line.long 0x00 "NEXT_BUF,LCD Interface Next Buffer Address Register" sif cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4") group.long 0x60++0x3 line.long 0x00 "TIMING,LCD Interface Timing Register" hexmask.long.byte 0x00 24.--31. 1. " CMD_HOLD ,Number of DISPLAY CLOCK (pix_clk) cycles that the LCD_RS signal is active after LCD_CS is deasserted" hexmask.long.byte 0x00 16.--23. 1. " CMD_SETUP ,Number of DISPLAY CLOCK (pix_clk) cycles that the LCD_RS signal is active before LCD_CS is asserted" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_HOLD ,Data bus hold time in DISPLAY CLOCK (pix_clk) cycles" hexmask.long.byte 0x00 0.--7. 1. " DATA_SETUP ,Data bus setup time in DISPLAY CLOCK (pix_clk) cycles" endif sif cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4") if (((per.l(ad:0x30320000)&0x60000)==0x20000)) group.long 0x70++0x0F line.long 0x00 "VDCTRL0,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " VSYNC_OEB_SET/CLR ,VSYNC output/input indicator" "VSYNC_OUTPUT,VSYNC_INPUT" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " ENABLE_PRESENT_SET/CLR ,Enable signal in DOTCLK mode" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " VSYNC_POL_SET/CLR ,VSYNC polarity invert" "Not inverted,Inverted" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " HSYNC_POL_SET/CLR ,HSYNC polarity invert" "Not inverted,Inverted" textline " " setclrfld.long 0x00 25. 0x04 25. 0x08 25. " DOTCLK_POL_SET/CLR ,DOTCLK polarity invert" "Not inverted,Inverted" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " ENABLE_POL_SET/CLR ,Enable polarity" "Low,High" textline " " setclrfld.long 0x00 21. 0x04 21. 0x08 21. " VSYNC_PERIOD_UNIT_SET/CLR ,VSYNC period unit" "Display clock,Complete horizontal lines" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " VSYNC_PULSE_WIDTH_UNIT_SET/CLR ,VSYNC pulse width unit" "Display clock,Complete horizontal lines" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " HALF_LINE_SET/CLR ,Total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field enable" "Disabled,Enabled" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " HALF_LINE_MODE_SET/CLR ,Enable all fields end with half a horizontal line" "Disabled,Enabled" textline " " hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x04 "VDCTRL0_SET,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" hexmask.long.tbyte 0x04 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x08 "VDCTRL0_CLR,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" hexmask.long.tbyte 0x08 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x0C "VDCTRL0_TOG,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" bitfld.long 0x0C 29. " VSYNC_OEB ,VSYNC output/input indicator" "VSYNC_OUTPUT,VSYNC_INPUT" bitfld.long 0x0C 28. " ENABLE_PRESENT ,Enable signal in DOTCLK mode" "Disabled,Enabled" textline " " bitfld.long 0x0C 27. " VSYNC_POL ,VSYNC polarity invert" "Not inverted,Inverted" bitfld.long 0x0C 26. " HSYNC_POL ,HSYNC polarity invert" "Not inverted,Inverted" textline " " bitfld.long 0x0C 25. " DOTCLK_POL ,DOTCLK polarity invert" "Not inverted,Inverted" bitfld.long 0x0C 24. " ENABLE_POL ,Enable polarity" "Low,High" textline " " bitfld.long 0x0C 21. " VSYNC_PERIOD_UNIT ,VSYNC period unit" "Display clock,Complete horizontal lines" bitfld.long 0x0C 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC pulse width unit" "Display clock,Complete horizontal lines" textline " " bitfld.long 0x0C 19. " HALF_LINE ,Total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field enable" "Disabled,Enabled" bitfld.long 0x0C 18. " HALF_LINE_MODE ,Enable all fields end with half a horizontal line" "Disabled,Enabled" textline " " hexmask.long.tbyte 0x0C 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" else group.long 0x70++0x0F line.long 0x00 "VDCTRL0,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " VSYNC_OEB_SET/CLR ,VSYNC output/input indicator" "VSYNC_OUTPUT,VSYNC_INPUT" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " ENABLE_PRESENT_SET/CLR ,Enable signal in DOTCLK mode" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " VSYNC_POL_SET/CLR ,VSYNC polarity invert" "Not inverted,Inverted" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " HSYNC_POL_SET/CLR ,HSYNC polarity invert" "Not inverted,Inverted" textline " " setclrfld.long 0x00 25. 0x04 25. 0x08 25. " DOTCLK_POL_SET/CLR ,DOTCLK polarity invert" "Not inverted,Inverted" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " ENABLE_POL_SET/CLR ,Enable polarity" "Low,High" textline " " setclrfld.long 0x00 21. 0x04 21. 0x08 21. " VSYNC_PERIOD_UNIT_SET/CLR ,VSYNC period unit" "Display clock,Complete horizontal lines" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " VSYNC_PULSE_WIDTH_UNIT_SET/CLR ,VSYNC pulse width unit" "Display clock,Complete horizontal lines" textline " " setclrfld.long 0x00 18. 0x04 18. 0x08 18. " HALF_LINE_MODE_SET/CLR ,Enable all fields end with half a horizontal line" "Disabled,Enabled" textline " " hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x04 "VDCTRL0_SET,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" hexmask.long.tbyte 0x04 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x08 "VDCTRL0_CLR,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" hexmask.long.tbyte 0x08 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x0C "VDCTRL0_TOG,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" bitfld.long 0x0C 29. " VSYNC_OEB ,VSYNC output/input indicator" "VSYNC_OUTPUT,VSYNC_INPUT" bitfld.long 0x0C 28. " ENABLE_PRESENT ,Enable signal in DOTCLK mode" "Disabled,Enabled" textline " " bitfld.long 0x0C 27. " VSYNC_POL ,VSYNC polarity invert" "Not inverted,Inverted" bitfld.long 0x0C 26. " HSYNC_POL ,HSYNC polarity invert" "Not inverted,Inverted" textline " " bitfld.long 0x0C 25. " DOTCLK_POL ,DOTCLK polarity invert" "Not inverted,Inverted" bitfld.long 0x0C 24. " ENABLE_POL ,Enable polarity" "Low,High" textline " " bitfld.long 0x0C 21. " VSYNC_PERIOD_UNIT ,VSYNC period unit" "Display clock,Complete horizontal lines" bitfld.long 0x0C 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC pulse width unit" "Display clock,Complete horizontal lines" textline " " bitfld.long 0x0C 18. " HALF_LINE_MODE ,Enable all fields end with half a horizontal line" "Disabled,Enabled" textline " " hexmask.long.tbyte 0x0C 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" endif else if (((per.l(ad:0x30320000)&0x20000)==0x20000)) group.long 0x70++0x0F line.long 0x00 "VDCTRL0,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " ENABLE_PRESENT_SET/CLR ,Enable signal in DOTCLK mode" "Disabled,Enabled" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " VSYNC_POL_SET/CLR ,VSYNC polarity invert" "Not inverted,Inverted" textline " " setclrfld.long 0x00 26. 0x04 26. 0x08 26. " HSYNC_POL_SET/CLR ,HSYNC polarity invert" "Not inverted,Inverted" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " DOTCLK_POL_SET/CLR ,DOTCLK polarity invert" "Not inverted,Inverted" textline " " setclrfld.long 0x00 24. 0x04 24. 0x08 24. " ENABLE_POL_SET/CLR ,Enable polarity" "Low,High" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " VSYNC_PERIOD_UNIT_SET/CLR ,VSYNC period unit" "Display clock,Complete horizontal lines" textline " " setclrfld.long 0x00 20. 0x04 20. 0x08 20. " VSYNC_PULSE_WIDTH_UNIT_SET/CLR ,VSYNC pulse width unit" "Display clock,Complete horizontal lines" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " HALF_LINE_SET/CLR ,Total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 18. 0x04 18. 0x08 18. " HALF_LINE_MODE_SET/CLR ,Enable all fields end with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x04 "VDCTRL0_SET,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" hexmask.long.tbyte 0x04 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x08 "VDCTRL0_CLR,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" hexmask.long.tbyte 0x08 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x0C "VDCTRL0_TOG,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" bitfld.long 0x0C 28. " ENABLE_PRESENT ,Enable signal in DOTCLK mode" "Disabled,Enabled" bitfld.long 0x0C 27. " VSYNC_POL ,VSYNC polarity invert" "Not inverted,Inverted" textline " " bitfld.long 0x0C 26. " HSYNC_POL ,HSYNC polarity invert" "Not inverted,Inverted" bitfld.long 0x0C 25. " DOTCLK_POL ,DOTCLK polarity invert" "Not inverted,Inverted" textline " " bitfld.long 0x0C 24. " ENABLE_POL ,Enable polarity" "Low,High" bitfld.long 0x0C 21. " VSYNC_PERIOD_UNIT ,VSYNC period unit" "Display clock,Complete horizontal lines" textline " " bitfld.long 0x0C 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC pulse width unit" "Display clock,Complete horizontal lines" bitfld.long 0x0C 19. " HALF_LINE ,Total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 18. " HALF_LINE_MODE ,Enable all fields end with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x0C 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" else group.long 0x70++0x0F line.long 0x00 "VDCTRL0,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " ENABLE_PRESENT_SET/CLR ,Enable signal in DOTCLK mode" "Disabled,Enabled" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " VSYNC_POL_SET/CLR ,VSYNC polarity invert" "Not inverted,Inverted" textline " " setclrfld.long 0x00 26. 0x04 26. 0x08 26. " HSYNC_POL_SET/CLR ,HSYNC polarity invert" "Not inverted,Inverted" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " DOTCLK_POL_SET/CLR ,DOTCLK polarity invert" "Not inverted,Inverted" textline " " setclrfld.long 0x00 24. 0x04 24. 0x08 24. " ENABLE_POL_SET/CLR ,Enable polarity" "Low,High" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " VSYNC_PERIOD_UNIT_SET/CLR ,VSYNC period unit" "Display clock,Complete horizontal lines" textline " " setclrfld.long 0x00 20. 0x04 20. 0x08 20. " VSYNC_PULSE_WIDTH_UNIT_SET/CLR ,VSYNC pulse width unit" "Display clock,Complete horizontal lines" textline " " setclrfld.long 0x00 18. 0x04 18. 0x08 18. " HALF_LINE_MODE_SET/CLR ,Enable all fields end with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x04 "VDCTRL0_SET,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" hexmask.long.tbyte 0x04 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x08 "VDCTRL0_CLR,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" hexmask.long.tbyte 0x08 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x0C "VDCTRL0_TOG,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" bitfld.long 0x0C 28. " ENABLE_PRESENT ,Enable signal in DOTCLK mode" "Disabled,Enabled" bitfld.long 0x0C 27. " VSYNC_POL ,VSYNC polarity invert" "Not inverted,Inverted" textline " " bitfld.long 0x0C 26. " HSYNC_POL ,HSYNC polarity invert" "Not inverted,Inverted" bitfld.long 0x0C 25. " DOTCLK_POL ,DOTCLK polarity invert" "Not inverted,Inverted" textline " " bitfld.long 0x0C 24. " ENABLE_POL ,Enable polarity" "Low,High" bitfld.long 0x0C 21. " VSYNC_PERIOD_UNIT ,VSYNC period unit" "Display clock,Complete horizontal lines" textline " " bitfld.long 0x0C 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC pulse width unit" "Display clock,Complete horizontal lines" textline " " bitfld.long 0x0C 18. " HALF_LINE_MODE ,Enable all fields end with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x0C 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" endif endif group.long 0x80++0x03 line.long 0x00 "VDCTRL1,eLCDIF VSYNC Mode and Dotclk Mode Control Register 1" group.long 0x90++0x03 line.long 0x00 "VDCTRL2,LCDIF VSYNC Mode and Dotclk Mode Control Register 2" hexmask.long.word 0x00 18.--31. 1. " HSYNC_PULSE_WIDTH ,Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active" hexmask.long.tbyte 0x00 0.--17. 1. " HSYNC_PERIOD ,Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal" if (((per.l(ad:0x30320000)&0x60000)==0x20000)) group.long 0xA0++0x3 line.long 0x00 "VDCTRL3,LCDIF VSYNC Mode and Dotclk Mode Control Register 3" bitfld.long 0x00 29. " MUX_SYNC_SIGNALS ,Mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12" "Not muxed,Muxed" textline " " hexmask.long.word 0x00 16.--27. 1. " HORIZONTAL_WAIT_CNT ,Number of clocks from falling edge of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins" hexmask.long.word 0x00 0.--15. 1. " VERTICAL_WAIT_CNT ,Vertical back porch lines plus the number of horizontal lines before the moving picture begins" else group.long 0xA0++0x3 line.long 0x00 "VDCTRL3,LCDIF VSYNC Mode and Dotclk Mode Control Register 3" bitfld.long 0x00 29. " MUX_SYNC_SIGNALS ,Mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12" "Not muxed,Muxed" bitfld.long 0x00 28. " VSYNC_ONLY ,VSYNC only" ",1" textline " " hexmask.long.word 0x00 16.--27. 1. " HORIZONTAL_WAIT_CNT ,Number of clocks from falling edge of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins" hexmask.long.word 0x00 0.--15. 1. " VERTICAL_WAIT_CNT ,Wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions" endif group.long 0xB0++0x3 line.long 0x00 "VDCTRL4,eLCDIF VSYNC Mode and Dotclk Mode Control Register 4" bitfld.long 0x00 29.--31. " DOTCLK_DLY_SEL ,Amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin" "2ns,4ns,6ns,8ns,?..." bitfld.long 0x00 18. " SYNC_SIGNALS_ON ,VSYNC or VSYNC/HSYNC/DOTCLK control signals active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end" "Disabled,Enabled" textline " " hexmask.long.tbyte 0x00 0.--17. 1. " DOTCLK_H_VALID_DATA_CNT ,Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode" textline " " width 21. sif cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4") group.long 0xC0++0x03 line.long 0x00 "DVICTRL0,Digital Video Interface Control 0 Register" hexmask.long.word 0x00 16.--27. 1. " H_ACTIVE_CNT ,Number of active video samples to be transmitted" hexmask.long.word 0x00 0.--11. 1. " H_BLANKING_CNT ,Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval" group.long 0xD0++0x03 line.long 0x00 "DVICTRL1,Digital Video Interface Control 1 Register" hexmask.long.word 0x00 20.--29. 1. " F1_START_LINE ,Vertical line number from which field 1 begins" hexmask.long.word 0x00 10.--19. 1. " F1_END_LINE ,Vertical line number at which field 1 ends" textline " " hexmask.long.word 0x00 0.--9. 1. " F2_START_LINE ,Vertical line number from which field 2 begins" group.long 0xE0++0x03 line.long 0x00 "DVICTRL2,Digital Video Interface Control 2 Register" hexmask.long.word 0x00 20.--29. 1. " F2_END_LINE ,Vertical line number at which field 2 ends" hexmask.long.word 0x00 10.--19. 1. " V1_BLANK_START_LINE ,Vertical line number towards the end of field 1 where first vertical blanking interval starts" textline " " hexmask.long.word 0x00 0.--9. 1. " V1_BLANK_END_LINE ,Vertical line number in the beginning part of field 2 where first vertical blanking interval ends" group.long 0xF0++0x03 line.long 0x00 "DVICTRL3,Digital Video Interface Control 3 Register" hexmask.long.word 0x00 20.--29. 1. " V2_BLANK_START_LINE ,Vertical line number towards the end of field 2 where second vertical blanking interval starts" hexmask.long.word 0x00 10.--19. 1. " V2_BLANK_END_LINE ,Vertical line number in the beginning part of field 1 where second vertical blanking interval ends" textline " " hexmask.long.word 0x00 0.--9. 1. " V_LINES_CNT ,Total number of vertical lines per frame" group.long 0x100++0x03 line.long 0x00 "DVICTRL4,Digital Video Interface Control 4 Register" hexmask.long.byte 0x00 24.--31. 1. " Y_FILL_VALUE ,Value of Y component of filler data" hexmask.long.byte 0x00 16.--23. 1. " CB_FILL_VALUE ,Value of CB component of filler data" textline " " hexmask.long.byte 0x00 8.--15. 1. " CR_FILL_VALUE ,Value of CR component of filler data" hexmask.long.byte 0x00 0.--7. 1. " H_FILL_CNT ,Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval" group.long 0x110++0x03 line.long 0x00 "CSC_COEFF0,RGB to YCbCr 4:2:2 CSC Coefficient 0 Register" hexmask.long.word 0x00 16.--25. 1. " C0 ,Twos complement red multiplier coefficient for Y" bitfld.long 0x00 0.--1. " CSC_SUBSAMPLE_FILTER ,Filtering and subsampling scheme" "SAMPLE_AND_HOLD,,INTERSTITIAL,COSITED" group.long 0x120++0x03 line.long 0x00 "CSC_COEFF1,RGB to YCbCr 4:2:2 CSC Coefficient 1 Register" hexmask.long.word 0x00 16.--25. 1. " C0 ,Twos complement red multiplier coefficient for Y" hexmask.long.word 0x00 0.--9. 1. " C1 ,Twos complement green multiplier coefficient for Y" group.long 0x130++0x03 line.long 0x00 "CSC_COEFF2,RGB to YCbCr 4:2:2 CSC Coefficient 2 Register" hexmask.long.word 0x00 16.--25. 1. " C4 ,Twos complement green multiplier coefficient for Cb" hexmask.long.word 0x00 0.--9. 1. " C3 ,Twos complement red multiplier coefficient for Cb" group.long 0x140++0x03 line.long 0x00 "CSC_COEFF3,RGB to YCbCr 4:2:2 CSC Coefficient 3 Register" hexmask.long.word 0x00 16.--25. 1. " C6 ,Twos complement red multiplier coefficient for Cr" hexmask.long.word 0x00 0.--9. 1. " C5 ,Twos complement blue multiplier coefficient for Cb" group.long 0x150++0x03 line.long 0x00 "CSC_COEFF4,RGB to YCbCr 4:2:2 CSC Coefficient 4 Register" hexmask.long.word 0x00 16.--25. 1. " C8 ,Twos complement blue multiplier coefficient for Cr" hexmask.long.word 0x00 0.--9. 1. " C7 ,Twos complement green multiplier coefficient for Cr" group.long 0x160++0x03 line.long 0x00 "CSC_OFFSET,RGB to YCbCr 4:2:2 CSC Offset Register" hexmask.long.word 0x00 16.--24. 0x01 " CBCR_OFFSET ,Twos complement offset for the Cb and Cr components" hexmask.long.word 0x00 0.--8. 0x01 " Y_OFFSET ,Twos complement offset for the Y components" group.long 0x170++0x03 line.long 0x00 "CSC_LIMIT,RGB to YCbCr 4:2:2 CSC Limit Register" hexmask.long.byte 0x00 24.--31. 1. " CBCR_MIN ,Lower limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion" hexmask.long.byte 0x00 16.--23. 1. " CBCR_MAX ,Upper limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion" textline " " hexmask.long.byte 0x00 8.--15. 1. " Y_MIN ,Lower limit of Y after RGB to 4:2:2 YCbCr conversion" hexmask.long.byte 0x00 0.--7. 1. " Y_MAX ,Upper limit of Y after RGB to 4:2:2 YCbCr conversion" group.long 0x180++0x03 line.long 0x00 "DATA,LCD Interface Data Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_THREE ,Byte 3 (most significant byte) of data written to LCDIF" hexmask.long.byte 0x00 16.--23. 1. " DATA_TWO ,Byte 2 of data written to LCDIF" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_ONE ,Byte 1 of data written to LCDIF" hexmask.long.byte 0x00 0.--7. 1. " DATA_ZERO ,Byte 0 (least significant byte) of data written to LCDIF" endif group.long 0x190++0x03 line.long 0x00 "BM_ERROR_STAT,Bus Master Error Status Register" group.long 0x1A0++0x03 line.long 0x00 "CRC_STAT,CRC Status Register" rgroup.long 0x1B0++0x3 line.long 0x00 "STAT,LCD Interface Status Register" bitfld.long 0x00 31. " PRESENT ,eLCDIF present" "Not preset,Present" textline " " sif !cpuis("IMX8MQ")&&!cpuis("IMX8MQ-CM4") bitfld.long 0x00 30. " DMA_REQ ,Current state of the DMA request line for the eLCDIF" "Not requested,Requested" textline " " endif bitfld.long 0x00 29. " LFIFO_FULL ,LCD LFIFO is full" "Not full,Full" bitfld.long 0x00 28. " LFIFO_EMPTY ,LCD LFIFO is empty" "Not empty,Empty" textline " " bitfld.long 0x00 27. " TXFIFO_FULL ,LCD TXFIFO is full" "Not full,Full" bitfld.long 0x00 26. " TXFIFO_EMPTY ,LCD TXFIFO is empty" "Not empty,Empty" textline " " sif cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4") bitfld.long 0x00 25. " BUSY ,Busy signal from the external LCD controller" "Not busy,Busy" bitfld.long 0x00 24. " DVI_CURRENT_FIELD ,Current field being transmitted" "Field 1,Field 2" textline " " endif hexmask.long.word 0x00 0.--8. 1. " LFIFO_COUNT ,Current count in latency buffer (LFIFO)" group.long 0x200++0x03 line.long 0x00 "THRES,eLCDIF Threshold Register" hexmask.long.word 0x00 16.--24. 1. " FASTCLOCK ,Value of pixels from 0 to 511" hexmask.long.word 0x00 0.--8. 1. " PANIC ,Internal panic control output" sif cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4") group.long 0x210++0x03 line.long 0x00 "AS_CTRL,LCDIF AS Buffer Control Register" bitfld.long 0x00 31. " CSI_VSYNC_ENABLE ,Enable LCDIF work as sync mode with CSI input" "Disabled,Enabled" bitfld.long 0x00 30. " CSI_VSYNC_POL ,CSI VSYNC polarity invert" "Not inverted,Inverted" textline " " bitfld.long 0x00 29. " CSI_VSYNC_MODE ,VSYNC generate mode" "INT_SYNC_MODE,EXT_SYNC_MODE" bitfld.long 0x00 28. " CSI_SYNC_ON_IRQ_EN ,Enable an interrupt when LCDIF lock with CSI vsync input" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " CSI_SYNC_ON_IRQ ,VSYNC generate mode" "INT_SYNC_MODE,EXT_SYNC_MODE" bitfld.long 0x00 23. " PS_DISABLE ,LCDIF PS buffer data disable" "No,Yes" textline " " bitfld.long 0x00 21.--22. " INPUT_DATA_SWIZZLE ,Swap mode bytes either in the HW_LCDIF_DATA register or those fetched by the AXI master part of LCDIF" "No swap,Swap all bytes,HWD swap,HWD byte swap" bitfld.long 0x00 20. " ALPHA_INVERT ,Invert the alpha value" "Not inverted,Inverted" textline " " bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "MASKAS,MASKNOTAS,MASKASNOT,MERGEAS,MERGENOTAS,MERGEASNOT,NOTCOPYAS,NOT,NOTMASKAS,NOTMERGEAS,XORAS,NOTXORAS,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL[ALPHA_CTRL]" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for AS" "ARGB8888,,,,RGB888,,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this alpha surface" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CTRL ,Construct mode of alpha value for this alpha surface" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " AS_ENABLE ,Enable fetching AS buffer data in bus master mode and combine it with another buffer" "Disabled,Enabled" group.long 0x220++0x03 line.long 0x00 "AS_BUF,Alpha Surface Buffer Pointer Register" group.long 0x230++0x03 line.long 0x00 "AS_NEXT_BUF,AS Next Buffer Register" group.long 0x240++0x03 line.long 0x00 "AS_CLRKEYLOW,LCDIF Overlay Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to AS buffer" group.long 0x250++0x03 line.long 0x00 "AS_CLRKEYHIGH,LCDIF Overlay Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to AS buffer" group.long 0x260++0x03 line.long 0x00 "SYNC_DELAY,LCD Working Insync Mode With CSI For VSYNC Delay" hexmask.long.word 0x00 16.--31. 1. " V_COUNT_DELAY ,LCDIF VSYNC delayed counter for CSI_VSYNC" hexmask.long.word 0x00 0.--15. 1. " H_COUNT_DELAY ,LCDIF VSYNC delayed counter for CSI_VSYNC" else group.long 0x380++0x23 line.long 0x00 "PIGEONCTRL0,LCDIF Pigeon Mode Control 0 Register" hexmask.long.word 0x00 16.--27. 1. " LD_PERIOD ,Period of pclk counter during LD phase" hexmask.long.word 0x00 0.--11. 1. " FD_PERIOD ,Period of line counter during FD phase" line.long 0x04 "PIGEONCTRL0_SET,LCDIF Pigeon Mode Control 0 Register" hexmask.long.word 0x04 16.--27. 1. " LD_PERIOD ,Period of pclk counter during LD phase" hexmask.long.word 0x04 0.--11. 1. " FD_PERIOD ,Period of line counter during FD phase" line.long 0x08 "PIGEONCTRL0_CLR,LCDIF Pigeon Mode Control0 Register" hexmask.long.word 0x08 16.--27. 1. " LD_PERIOD ,Period of pclk counter during LD phase" hexmask.long.word 0x08 0.--11. 1. " FD_PERIOD ,Period of line counter during FD phase" line.long 0x0C "PIGEONCTRL0_TOG,LCDIF Pigeon Mode Control0 Register" hexmask.long.word 0x0C 16.--27. 1. " LD_PERIOD ,Period of pclk counter during LD phase" hexmask.long.word 0x0C 0.--11. 1. " FD_PERIOD ,Period of line counter during FD phase" line.long 0x10 "PIGEONCTRL1,LCDIF Pigeon Mode Control1 Register" hexmask.long.word 0x10 16.--27. 1. " FRAME_CNT_CYCLES ,Max cycles of frame counter" hexmask.long.word 0x10 0.--11. 1. " FRAME_CNT_PERIOD ,Period of frame counter" line.long 0x14 "PIGEONCTRL1_SET,LCDIF Pigeon Mode Control1 Register" hexmask.long.word 0x14 16.--27. 1. " FRAME_CNT_CYCLES ,Max cycles of frame counter" hexmask.long.word 0x14 0.--11. 1. " FRAME_CNT_PERIOD ,Period of frame counter" line.long 0x18 "PIGEONCTRL1_CLR,LCDIF Pigeon Mode Control1 Register" hexmask.long.word 0x18 16.--27. 1. " FRAME_CNT_CYCLES ,Max cycles of frame counter" hexmask.long.word 0x18 0.--11. 1. " FRAME_CNT_PERIOD ,Period of frame counter" line.long 0x1C "PIGEONCTRL1_TOG,LCDIF Pigeon Mode Control1 Register" hexmask.long.word 0x1C 16.--27. 1. " FRAME_CNT_CYCLES ,Max cycles of frame counter" hexmask.long.word 0x1C 0.--11. 1. " FRAME_CNT_PERIOD ,Period of frame counter" line.long 0x20 "PIGEONCTRL2_SET/CLR,LCDIF Pigeon Mode Control2 Register" setclrfld.long 0x20 1. 0x24 1. 0x28 1. " PIGEON_CLK_GATE ,Pigeon mode dot clock gate enable" "Disabled,Enabled" setclrfld.long 0x20 0. 0x24 0. 0x28 0. " PIGEON_DATA_EN ,Pigeon mode data enable" "Disabled,Enabled" group.long 0x3AC++0x3 line.long 0x00 "PIGEONCTRL2_TOG,LCDIF Pigeon Mode Control2 Register" bitfld.long 0x00 1. " PIGEON_CLK_GATE ,Pigeon mode dot clock gate enable" "Disabled,Enabled" bitfld.long 0x00 0. " PIGEON_DATA_EN ,Pigeon mode data enable" "Disabled,Enabled" group.long 0x800++0x3 line.long 0x00 "PIGEON_0_0,Panel Interface Signal Generator Register" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,State mask" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,Mask counter" textline " " bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Global counters as mask condition select" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F" textline " " bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" textline " " bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x800+0x10)++0x3 line.long 0x00 "PIGEON_0_1,Panel Interface Signal Generator Register" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x800+0x20)++0x3 line.long 0x00 "PIGEON_0_2,Panel Interface Signal Generator Register" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "CLEAR_USING_MASK,?..." bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "DIS,AND,OR,MASK,?..." group.long 0x840++0x3 line.long 0x00 "PIGEON_1_0,Panel Interface Signal Generator Register" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,State mask" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,Mask counter" textline " " bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Global counters as mask condition select" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F" textline " " bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" textline " " bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x840+0x10)++0x3 line.long 0x00 "PIGEON_1_1,Panel Interface Signal Generator Register" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x840+0x20)++0x3 line.long 0x00 "PIGEON_1_2,Panel Interface Signal Generator Register" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "CLEAR_USING_MASK,?..." bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "DIS,AND,OR,MASK,?..." group.long 0x880++0x3 line.long 0x00 "PIGEON_2_0,Panel Interface Signal Generator Register" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,State mask" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,Mask counter" textline " " bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Global counters as mask condition select" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F" textline " " bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" textline " " bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x880+0x10)++0x3 line.long 0x00 "PIGEON_2_1,Panel Interface Signal Generator Register" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x880+0x20)++0x3 line.long 0x00 "PIGEON_2_2,Panel Interface Signal Generator Register" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "CLEAR_USING_MASK,?..." bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "DIS,AND,OR,MASK,?..." group.long 0x8C0++0x3 line.long 0x00 "PIGEON_3_0,Panel Interface Signal Generator Register" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,State mask" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,Mask counter" textline " " bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Global counters as mask condition select" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F" textline " " bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" textline " " bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x8C0+0x10)++0x3 line.long 0x00 "PIGEON_3_1,Panel Interface Signal Generator Register" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x8C0+0x20)++0x3 line.long 0x00 "PIGEON_3_2,Panel Interface Signal Generator Register" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "CLEAR_USING_MASK,?..." bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "DIS,AND,OR,MASK,?..." group.long 0x900++0x3 line.long 0x00 "PIGEON_4_0,Panel Interface Signal Generator Register" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,State mask" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,Mask counter" textline " " bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Global counters as mask condition select" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F" textline " " bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" textline " " bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x900+0x10)++0x3 line.long 0x00 "PIGEON_4_1,Panel Interface Signal Generator Register" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x900+0x20)++0x3 line.long 0x00 "PIGEON_4_2,Panel Interface Signal Generator Register" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "CLEAR_USING_MASK,?..." bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "DIS,AND,OR,MASK,?..." group.long 0x940++0x3 line.long 0x00 "PIGEON_5_0,Panel Interface Signal Generator Register" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,State mask" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,Mask counter" textline " " bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Global counters as mask condition select" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F" textline " " bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" textline " " bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x940+0x10)++0x3 line.long 0x00 "PIGEON_5_1,Panel Interface Signal Generator Register" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x940+0x20)++0x3 line.long 0x00 "PIGEON_5_2,Panel Interface Signal Generator Register" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "CLEAR_USING_MASK,?..." bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "DIS,AND,OR,MASK,?..." group.long 0x980++0x3 line.long 0x00 "PIGEON_6_0,Panel Interface Signal Generator Register" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,State mask" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,Mask counter" textline " " bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Global counters as mask condition select" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F" textline " " bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" textline " " bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x980+0x10)++0x3 line.long 0x00 "PIGEON_6_1,Panel Interface Signal Generator Register" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x980+0x20)++0x3 line.long 0x00 "PIGEON_6_2,Panel Interface Signal Generator Register" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "CLEAR_USING_MASK,?..." bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "DIS,AND,OR,MASK,?..." group.long 0x9C0++0x3 line.long 0x00 "PIGEON_7_0,Panel Interface Signal Generator Register" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,State mask" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,Mask counter" textline " " bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Global counters as mask condition select" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F" textline " " bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" textline " " bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x9C0+0x10)++0x3 line.long 0x00 "PIGEON_7_1,Panel Interface Signal Generator Register" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x9C0+0x20)++0x3 line.long 0x00 "PIGEON_7_2,Panel Interface Signal Generator Register" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "CLEAR_USING_MASK,?..." bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "DIS,AND,OR,MASK,?..." group.long 0xA00++0x3 line.long 0x00 "PIGEON_8_0,Panel Interface Signal Generator Register" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,State mask" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,Mask counter" textline " " bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Global counters as mask condition select" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F" textline " " bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" textline " " bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xA00+0x10)++0x3 line.long 0x00 "PIGEON_8_1,Panel Interface Signal Generator Register" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xA00+0x20)++0x3 line.long 0x00 "PIGEON_8_2,Panel Interface Signal Generator Register" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "CLEAR_USING_MASK,?..." bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "DIS,AND,OR,MASK,?..." group.long 0xA40++0x3 line.long 0x00 "PIGEON_9_0,Panel Interface Signal Generator Register" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,State mask" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,Mask counter" textline " " bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Global counters as mask condition select" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F" textline " " bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" textline " " bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xA40+0x10)++0x3 line.long 0x00 "PIGEON_9_1,Panel Interface Signal Generator Register" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xA40+0x20)++0x3 line.long 0x00 "PIGEON_9_2,Panel Interface Signal Generator Register" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "CLEAR_USING_MASK,?..." bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "DIS,AND,OR,MASK,?..." group.long 0xA80++0x3 line.long 0x00 "PIGEON_10_0,Panel Interface Signal Generator Register" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,State mask" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,Mask counter" textline " " bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Global counters as mask condition select" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F" textline " " bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" textline " " bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xA80+0x10)++0x3 line.long 0x00 "PIGEON_10_1,Panel Interface Signal Generator Register" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xA80+0x20)++0x3 line.long 0x00 "PIGEON_10_2,Panel Interface Signal Generator Register" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "CLEAR_USING_MASK,?..." bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "DIS,AND,OR,MASK,?..." group.long 0xAC0++0x3 line.long 0x00 "PIGEON_11_0,Panel Interface Signal Generator Register" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,State mask" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,Mask counter" textline " " bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Global counters as mask condition select" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F" textline " " bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" textline " " bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xAC0+0x10)++0x3 line.long 0x00 "PIGEON_11_1,Panel Interface Signal Generator Register" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xAC0+0x20)++0x3 line.long 0x00 "PIGEON_11_2,Panel Interface Signal Generator Register" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "CLEAR_USING_MASK,?..." bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "DIS,AND,OR,MASK,?..." group.long 0xB00++0x3 line.long 0x00 "LUT_CTRL,Lookup Table Data Register" bitfld.long 0x00 0. " LUT_BYPASS ,Pixels enter the CSC2 unit get converted or not" "Converted,Not converted" group.long 0xB10++0x3 line.long 0x00 "LUT0_ADDR,Lookup Table Control Register" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,LUT indexed address pointer" group.long 0xB20++0x3 line.long 0x00 "LUT0_DATA,Lookup Table Data Register" group.long 0xB30++0x3 line.long 0x00 "LUT1_ADDR,Lookup Table Control Register" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,LUT indexed address pointer" group.long 0xB40++0x3 line.long 0x00 "LUT1_DATA,Lookup Table Data Register" endif width 0x0B tree.end tree "HDMI TX (HD Display Transmitter Controller)" base ad:0x00000000 width 29. group.long 0x00++0x07 line.long 0x00 "APB_CTRL,APB Control Register" bitfld.long 0x00 2. " APB_IRAM_PATH ,Enable APB to R/W the IRAM" "Disabled,Enabled" bitfld.long 0x00 1. " APB_DRAM_PATH ,Enable APB to R/W the DRAM" "Disabled,Enabled" bitfld.long 0x00 0. " APB_XT_RESET ,APB control on the CPU reset active high" "No reset,Reset" line.long 0x04 "XT_INT_CTRL,XT Interrupt Control Register" bitfld.long 0x04 0.--1. " XT_INT_POLARITY ,Xt interrupt polarity" "0,1,2,3" rgroup.long 0x08++0x07 line.long 0x00 "MAILBOX_FULL_ADDR,Mailbox Full Address Register" bitfld.long 0x00 0. " MAILBOX_FULL ,Mailboxes full indication" "Not full,Full" line.long 0x04 "MAILBOX_EMPTY_ADDR,Mailbox Empty Address" bitfld.long 0x04 0. " MAILBOX_EMPTY ,Mailboxes empty indication" "Not empty,Empty" group.long 0x10++0x03 line.long 0x00 "MAILBOX0_WR_DATA,Mailbox0 Write Data Register" hexmask.long.byte 0x00 0.--7. 1. " MAILBOX0_WR_DATA ,Write data to mailbox" rgroup.long 0x14++0x1F line.long 0x00 "MAILBOX0_RD_DATA,Mailbox0 Read Data Register" hexmask.long.byte 0x00 0.--7. 1. " MAILBOX0_RD_DATA ,Mailbox read data" line.long 0x04 "KEEP_ALIVE,Keep Alive Register" hexmask.long.byte 0x04 0.--7. 1. " KEEP_ALIVE_CNT ,Software keep alive counter" line.long 0x08 "VER_L,VER L Register" hexmask.long.byte 0x08 0.--7. 1. " VER_LSB ,Software version LSB" line.long 0x0C "VER_H,VER H Register" hexmask.long.byte 0x0C 0.--7. 1. " VER_MSB ,Software version MSB" line.long 0x10 "VER_LIB_L_ADDR,VER LIB L Address Register" hexmask.long.byte 0x10 0.--7. 1. " SW_LIB_VER_L ,Software lib version written by CPU" line.long 0x14 "VER_LIB_H_ADDR,VER LIB H Address Register" hexmask.long.byte 0x14 0.--7. 1. " SW_LIB_VER_H ,Software lib version written by CPU" line.long 0x18 "SW_DEBUG_L,SW Debug L Register" hexmask.long.byte 0x18 0.--7. 1. " SW_DEBUG_7_0 ,Sw debug 7_0" line.long 0x1C "SW_DEBUG_H,SW Debug H Register" hexmask.long.byte 0x1C 0.--7. 1. " SW_DEBUG_15_8 ,Sw debug 15_8" group.long 0x34++0x03 line.long 0x00 "MAILBOX_INT_MASK,Mailbox Interrupt Mask Register" bitfld.long 0x00 1. " MAILBOX_INT_MASK[1] ,Mailbox interrupt mask (empty)" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Mailbox interrupt mask (full)" "Not masked,Masked" rgroup.long 0x38++0x03 line.long 0x00 "MAILBOX_INT_STATUS,Mailbox Interrupt Status Register" bitfld.long 0x00 1. " MAILBOX_INT_MASK[1] ,Mailbox interrupt status (empty)" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Mailbox interrupt status (full)" "No interrupt,Interrupt" group.long 0x3C++0x07 line.long 0x00 "SW_CLK_L,SW Clock L Register" hexmask.long.byte 0x00 0.--7. 1. " SW_CLOCK_VAL_L ,Fractional of the clock decimal value" line.long 0x04 "SW_CLK_H,SW Clock H Register" hexmask.long.byte 0x04 0.--7. 1. " SW_CLOCK_VAL_H ,Clock frequency in decimal values" rgroup.long 0x44++0x0F line.long 0x00 "SW_EVENTS0,SW Events 0 Register" hexmask.long.byte 0x00 0.--7. 1. " SW_EVENTS7_0 ,Sw events 7_0" line.long 0x04 "SW_EVENTS1,SW Events 1 Register" hexmask.long.byte 0x04 0.--7. 1. " SW_EVENTS15_8 ,Sw events 15_8" line.long 0x08 "SW_EVENTS2,SW Events 2 Register" hexmask.long.byte 0x08 0.--7. 1. " SW_EVENTS23_16 ,Sw events 23_16" line.long 0x0C "SW_EVENTS3,SW Events 3 Register" hexmask.long.byte 0x0C 0.--7. 1. " SW_EVENTS31_24 ,Sw events 31_24" group.long 0x60++0x03 line.long 0x00 "XT_OCD_CTRL,XT OCD Control Register" bitfld.long 0x00 1. " XT_OCDHALTONRESET ,Xtensa halt on reget configuration register" "Not halted,halted" bitfld.long 0x00 0. " XT_DRESET ,Xtensa reset control register" "No reset,Reset" rgroup.long 0x64++0x03 line.long 0x00 "XT_OCD_CTRL_RO,XT OCD Control RO Register" bitfld.long 0x00 0. " XT_XOCDMODE ,Xtensa OCD mode configuration" "0,1" group.long 0x6C++0x03 line.long 0x00 "APB_INT_MASK,APB Interrupt Mask Register" bitfld.long 0x00 2. " APB_INTR_MASK[2] ,Mailbox interrupt" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,PIF interrupt" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,CEC interrupt" "Not masked,Masked" rgroup.long 0x70++0x03 line.long 0x00 "APB_STATUS_MASK,APB Status Mask Register" bitfld.long 0x00 2. " APB_INTR_STATUS[2] ,Mailbox interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,PIF interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,CEC interrupt" "No interrupt,Interrupt" textline " " group.long 0x30000++0x4F line.long 0x00 "AUDIO_SRC_CNTL,Audio SRC Control Register" bitfld.long 0x00 6. " VALID_ALL ,Valid bit for all samples" "Not valid,Valid" bitfld.long 0x00 5. " VALID_BITS_FORCE ,Force valid bits of the channels" "Not forced,Forced" textline " " bitfld.long 0x00 4. " I2S_TS_EN ,Enable I2S time stamp when decoders are disabled" "Disabled,Enabled" bitfld.long 0x00 3. " SPDIF_TS_EN ,Enable SPDIF time stamp when decoders are disabled" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " I2S_BLOCK_START_FORCE ,Force a block start in the audio stream" "Not forced,Forced" bitfld.long 0x00 1. " I2S_DEC_START ,When high source decoder starts" "Not started,Started" textline " " bitfld.long 0x00 0. " SW_RST ,Software reset" "No reset,Reset" line.long 0x04 "AUDIO_SRC_CNFG,Audio SRC Configuration Register" bitfld.long 0x04 17.--20. " I2S_DEC_PORT_EN ,Enable the I2S decoder ports [Ports enabled]" ",0,,0;1,,,,,,,,,,,,0;1;2;3" bitfld.long 0x04 13.--16. " AUDIO_CHANNEL_TYPE ,Transmission type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 11.--12. " TRANS_SMPL_WIDTH ,Decoder word select width" "16-bit,24-bit,32-bit,?..." bitfld.long 0x04 9.--10. " AUDIO_SAMPLE_WIDTH ,Decoder sample width" "16-bit,24-bit,32-bit,?..." textline " " bitfld.long 0x04 7.--8. " AUDIO_SAMPLE_JUST ,Data justification setting" "Left justified,Right justified,?..." bitfld.long 0x04 2.--6. " AUDIO_CH_NUM ,Number of channels to decode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 1. " WS_POLARITY ,Word select polarity" "Normal,Inverted" bitfld.long 0x04 0. " LOW_INDEX_MSB ,Low index MSB/LSB" "MSB first,LSB first" textline " " line.long 0x08 "COM_CH_STTS_BITS,COM CH Status Bits Register" bitfld.long 0x08 24.--27. " ORIGINAL_SAMP_FREQ ,Original sampling freq. of transmitted channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 20.--23. " CLOCK_ACCURACY ,Clock accuracy of transmitted channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 16.--19. " SAMPLING_FREQ ,Sampling frequency of transmitted channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x08 8.--15. 1. " CATEGORY_CODE ,Category code of transmitted channel" hexmask.long.byte 0x08 0.--7. 1. " BYTE0 ,Byte 0 of transmitted channel" line.long 0x0C "STTS_BIT_CH01,Status Bit Channel 0 && 1 Register" bitfld.long 0x0C 24.--25. " VALID_BITS1_0 ,Valid bits for channel 1 and 0" "0,1,2,3" bitfld.long 0x0C 20.--23. " WORD_LENGTH_CH1 ,Channel 1 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 16.--19. " CHANNEL_NUM_CH1 ,Channel 1 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0C 12.--15. " SOURCE_NUM_CH1 ,Channel 1 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 8.--11. " WORD_LENGTH_CH0 ,Channel 0 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " CHANNEL_NUM_CH0 ,Channel 0 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0C 0.--3. " SOURCE_NUM_CH0 ,Channel 0 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "STTS_BIT_CH23,Status Bit Channel 2 && 3 Register" bitfld.long 0x10 24.--25. " VALID_BITS3_2 ,Valid bits for channel 3 and 2" "0,1,2,3" bitfld.long 0x10 20.--23. " WORD_LENGTH_CH3 ,Channel 3 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 16.--19. " CHANNEL_NUM_CH3 ,Channel 3 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 12.--15. " SOURCE_NUM_CH3 ,Channel 3 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. " WORD_LENGTH_CH2 ,Channel 2 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 4.--7. " CHANNEL_NUM_CH2 ,Channel 2 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 0.--3. " SOURCE_NUM_CH2 ,Channel 2 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "STTS_BIT_CH45,Status Bit Channel 4 && 5 Register" bitfld.long 0x14 24.--25. " VALID_BITS5_4 ,Valid bits for channel 5 and 4" "0,1,2,3" bitfld.long 0x14 20.--23. " WORD_LENGTH_CH5 ,Channel 5 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 16.--19. " CHANNEL_NUM_CH5 ,Channel 5 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x14 12.--15. " SOURCE_NUM_CH5 ,Channel 5 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 8.--11. " WORD_LENGTH_CH4 ,Channel 4 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 4.--7. " CHANNEL_NUM_CH4 ,Channel 4 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x14 0.--3. " SOURCE_NUM_CH4 ,Channel 4 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "STTS_BIT_CH67,Status Bit Channel 6 && 7 Register" bitfld.long 0x18 24.--25. " VALID_BITS7_6 ,Valid bits for channel 7 and 6" "0,1,2,3" bitfld.long 0x18 20.--23. " WORD_LENGTH_CH7 ,Channel 7 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 16.--19. " CHANNEL_NUM_CH7 ,Channel 7 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x18 12.--15. " SOURCE_NUM_CH7 ,Channel 7 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 8.--11. " WORD_LENGTH_CH6 ,Channel 6 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 4.--7. " CHANNEL_NUM_CH6 ,Channel 6 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x18 0.--3. " SOURCE_NUM_CH6 ,Channel 6 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "STTS_BIT_CH89,Status Bit Channel 8 && 9 Register" bitfld.long 0x1C 24.--25. " VALID_BITS9_8 ,Valid bits for channel 9 and 8" "0,1,2,3" bitfld.long 0x1C 20.--23. " WORD_LENGTH_CH9 ,Channel 9 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " CHANNEL_NUM_CH9 ,Channel 9 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x1C 12.--15. " SOURCE_NUM_CH9 ,Channel 9 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 8.--11. " WORD_LENGTH_CH8 ,Channel 8 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 4.--7. " CHANNEL_NUM_CH8 ,Channel 8 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x1C 0.--3. " SOURCE_NUM_CH8 ,Channel 8 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "STTS_BIT_CH1011,Status Bit Channel 10 && 11 Register" bitfld.long 0x20 24.--25. " VALID_BITS11_10 ,Valid bits for channel 11 and 10" "0,1,2,3" bitfld.long 0x20 20.--23. " WORD_LENGTH_CH11 ,Channel 11 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x20 16.--19. " CHANNEL_NUM_CH11 ,Channel 11 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x20 12.--15. " SOURCE_NUM_CH11 ,Channel 11 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x20 8.--11. " WORD_LENGTH_CH10 ,Channel 10 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x20 4.--7. " CHANNEL_NUM_CH10 ,Channel 10 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x20 0.--3. " SOURCE_NUM_CH10 ,Channel 10 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x24 "STTS_BIT_CH1213,Status Bit Channel 12 && 13 Register" bitfld.long 0x24 24.--25. " VALID_BITS13_12 ,Valid bits for channel 13 and 12" "0,1,2,3" bitfld.long 0x24 20.--23. " WORD_LENGTH_CH13 ,Channel 13 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x24 16.--19. " CHANNEL_NUM_CH13 ,Channel 13 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x24 12.--15. " SOURCE_NUM_CH13 ,Channel 13 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x24 8.--11. " WORD_LENGTH_CH12 ,Channel 12 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x24 4.--7. " CHANNEL_NUM_CH12 ,Channel 12 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x24 0.--3. " SOURCE_NUM_CH12 ,Channel 12 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x28 "STTS_BIT_CH1415,Status Bit Channel 14 && 15 Register" bitfld.long 0x28 24.--25. " VALID_BITS15_14 ,Valid bits for channel 15 and 14" "0,1,2,3" bitfld.long 0x28 20.--23. " WORD_LENGTH_CH15 ,Channel 15 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x28 16.--19. " CHANNEL_NUM_CH15 ,Channel 15 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x28 12.--15. " SOURCE_NUM_CH15 ,Channel 15 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x28 8.--11. " WORD_LENGTH_CH14 ,Channel 14 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x28 4.--7. " CHANNEL_NUM_CH14 ,Channel 14 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x28 0.--3. " SOURCE_NUM_CH14 ,Channel 14 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "STTS_BIT_CH1617,Status Bit Channel 16 && 17 Register" bitfld.long 0x2C 24.--25. " VALID_BITS17_16 ,Valid bits for channel 17 and 16" "0,1,2,3" bitfld.long 0x2C 20.--23. " WORD_LENGTH_CH17 ,Channel 17 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x2C 16.--19. " CHANNEL_NUM_CH17 ,Channel 17 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x2C 12.--15. " SOURCE_NUM_CH17 ,Channel 17 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x2C 8.--11. " WORD_LENGTH_CH16 ,Channel 16 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x2C 4.--7. " CHANNEL_NUM_CH16 ,Channel 16 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x2C 0.--3. " SOURCE_NUM_CH16 ,Channel 16 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x30 "STTS_BIT_CH1819,Status Bit Channel 18 && 19 Register" bitfld.long 0x30 24.--25. " VALID_BITS19_18 ,Valid bits for channel 19 and 18" "0,1,2,3" bitfld.long 0x30 20.--23. " WORD_LENGTH_CH19 ,Channel 19 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x30 16.--19. " CHANNEL_NUM_CH19 ,Channel 19 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x30 12.--15. " SOURCE_NUM_CH19 ,Channel 19 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x30 8.--11. " WORD_LENGTH_CH18 ,Channel 18 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x30 4.--7. " CHANNEL_NUM_CH18 ,Channel 18 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x30 0.--3. " SOURCE_NUM_CH18 ,Channel 18 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x34 "STTS_BIT_CH2021,Status Bit Channel 20 && 21 Register" bitfld.long 0x34 24.--25. " VALID_BITS21_20 ,Valid bits for channel 21 and 20" "0,1,2,3" bitfld.long 0x34 20.--23. " WORD_LENGTH_CH21 ,Channel 21 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x34 16.--19. " CHANNEL_NUM_CH21 ,Channel 21 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x34 12.--15. " SOURCE_NUM_CH21 ,Channel 21 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x34 8.--11. " WORD_LENGTH_CH20 ,Channel 20 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x34 4.--7. " CHANNEL_NUM_CH20 ,Channel 20 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x34 0.--3. " SOURCE_NUM_CH20 ,Channel 20 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x38 "STTS_BIT_CH2223,Status Bit Channel 22 && 23 Register" bitfld.long 0x38 24.--25. " VALID_BITS23_22 ,Valid bits for channel 23 and 22" "0,1,2,3" bitfld.long 0x38 20.--23. " WORD_LENGTH_CH23 ,Channel 23 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x38 16.--19. " CHANNEL_NUM_CH23 ,Channel 23 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x38 12.--15. " SOURCE_NUM_CH23 ,Channel 23 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x38 8.--11. " WORD_LENGTH_CH22 ,Channel 22 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x38 4.--7. " CHANNEL_NUM_CH22 ,Channel 22 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x38 0.--3. " SOURCE_NUM_CH22 ,Channel 22 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x3C "STTS_BIT_CH2425,Status Bit Channel 24 && 25 Register" bitfld.long 0x3C 24.--25. " VALID_BITS25_24 ,Valid bits for channel 25 and 24" "0,1,2,3" bitfld.long 0x3C 20.--23. " WORD_LENGTH_CH25 ,Channel 25 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x3C 16.--19. " CHANNEL_NUM_CH25 ,Channel 25 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x3C 12.--15. " SOURCE_NUM_CH25 ,Channel 25 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x3C 8.--11. " WORD_LENGTH_CH24 ,Channel 24 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x3C 4.--7. " CHANNEL_NUM_CH24 ,Channel 24 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x3C 0.--3. " SOURCE_NUM_CH24 ,Channel 24 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x40 "STTS_BIT_CH2627,Status Bit Channel 27 && 26 Register" bitfld.long 0x40 24.--25. " VALID_BITS27_26 ,Valid bits for channel 27 and 26" "0,1,2,3" bitfld.long 0x40 20.--23. " WORD_LENGTH_CH27 ,Channel 27 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 16.--19. " CHANNEL_NUM_CH27 ,Channel 27 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x40 12.--15. " SOURCE_NUM_CH27 ,Channel 27 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 8.--11. " WORD_LENGTH_CH26 ,Channel 26 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 4.--7. " CHANNEL_NUM_CH26 ,Channel 26 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x40 0.--3. " SOURCE_NUM_CH26 ,Channel 26 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x44 "STTS_BIT_CH2829,Status Bit Channel 28 && 29 Register" bitfld.long 0x44 24.--25. " VALID_BITS29_28 ,Valid bits for channel 29 and 28" "0,1,2,3" bitfld.long 0x44 20.--23. " WORD_LENGTH_CH29 ,Channel 29 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x44 16.--19. " CHANNEL_NUM_CH29 ,Channel 29 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x44 12.--15. " SOURCE_NUM_CH29 ,Channel 29 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x44 8.--11. " WORD_LENGTH_CH28 ,Channel 28 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x44 4.--7. " CHANNEL_NUM_CH28 ,Channel 28 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x44 0.--3. " SOURCE_NUM_CH28 ,Channel 28 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x48 "STTS_BIT_CH3031,Status Bit Channel 30 && 31 Register" bitfld.long 0x48 24.--25. " VALID_BITS31_30 ,Valid bits for channel 31 and 30" "0,1,2,3" bitfld.long 0x48 20.--23. " WORD_LENGTH_CH31 ,Channel 31 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x48 16.--19. " CHANNEL_NUM_CH31 ,Channel 31 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x48 12.--15. " SOURCE_NUM_CH31 ,Channel 31 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x48 8.--11. " WORD_LENGTH_CH30 ,Channel 30 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x48 4.--7. " CHANNEL_NUM_CH30 ,Channel 30 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x48 0.--3. " SOURCE_NUM_CH30 ,Channel 30 source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x4C "SPDIF_CTRL_ADDR,SPDIF Control Address Register" rbitfld.long 0x4C 22.--25. " SPDIF_JITTER_STATUS ,SPDIF jitter status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x4C 21. " SPDIF_ENABLE ,SPDIF enable" "Disabled,Enabled" bitfld.long 0x4C 20. " SPDIF_AVG_SEL ,SPDIF average select" "Not selected,Selected" textline " " bitfld.long 0x4C 19. " SPDIF_JITTER_BYPASS ,SPDIF jitter bypass" "Not bypassed,Bypassed" hexmask.long.word 0x4C 11.--18. 1. " SPDIF_FIFO_MID_RANGE ,SPDIF FIFO mid range" hexmask.long.word 0x4C 3.--10. 1. " SPDIF_JITTER_THRSH ,SPDIF jitter threshold" textline " " bitfld.long 0x4C 0.--2. " SPDIF_JITTER_AVG_WIN ,SPDIF jitter AVG window" "0,1,2,3,4,5,6,7" textline " " rgroup.long 0x30050++0x2F line.long 0x00 "SPDIF_CH1_CS_3100_ADDR,SPDIF Channel 1 CS 3100 Address Register" line.long 0x04 "SPDIF_CH1_CS_6332_ADDR,SPDIF Channel 1 CS 6332 Address Register" line.long 0x08 "SPDIF_CH1_CS_9564_ADDR,SPDIF Channel 1 CS 9564 Address Register" line.long 0x0C "SPDIF_CH1_CS_12796_ADDR,SPDIF Channel 1 CS 12796 Address Register" line.long 0x10 "SPDIF_CH1_CS_159128_ADDR,SPDIF Channel 1 CS 159128 Address Register" line.long 0x14 "SPDIF_CH1_CS_191160_ADDR,SPDIF Channel 1 CS 191160 Address Register" line.long 0x18 "SPDIF_CH2_CS_3100_ADDR,SPDIF Channel 2 CS 3100 Address Register" line.long 0x1C "SPDIF_CH2_CS_6332_ADDR,SPDIF Channel 2 CS 6332 Address Register" line.long 0x20 "SPDIF_CH2_CS_9564_ADDR,SPDIF Channel 2 CS 9564 Address Register" line.long 0x24 "SPDIF_CH2_CS_12796_ADDR,SPDIF Channel 2 CS 12796 Address Register" line.long 0x28 "SPDIF_CH2_CS_159128_ADDR,SPDIF Channel 2 CS 159128 Address Register" line.long 0x2C "SPDIF_CH2_CS_191160_ADDR,SPDIF Channel 2 CS 191160 Address Register" group.long 0x30080++0x0B line.long 0x00 "SMPL2PKT_CNTL,SMPL2PKT Control Register" bitfld.long 0x00 1. " SMPL2PKT_EN ,Start sample to packets block" "Disabled,Enabled" bitfld.long 0x00 0. " SW_RST ,Software reset" "No reset,Reset" line.long 0x04 "SMPL2PKT_CNFG,SMPL2PKT Configuration Register" bitfld.long 0x04 20. " CFG_SAMPLE_PRESENT_FORCE ,Force sample present bits" "Not forced,Forced" bitfld.long 0x04 16.--19. " CFG_SAMPLE_PRESENT ,Sample present bits if force them is active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 15. " CFG_EN_AUTO_SUB_PCKT_NUM ,Enable automatics sub packet number" "Disabled,Enabled" bitfld.long 0x04 14. " CFG_BLOCK_LPCM_FIRST_PKT ,First lpcm audio packet is sent" "No,Yes" textline " " bitfld.long 0x04 11.--13. " CFG_SUB_PCKT_NUM ,Number of sub-packets in HDMI audio 2-ch packet" "1-SP,2-SP,3-SP,4-SP,?..." bitfld.long 0x04 7.--10. " AUDIO_TYPE ,Audio type setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 5.--6. " NUM_OF_I2S_PORTS ,Number of active I2S ports" "1 port,2 ports,4 ports,?..." bitfld.long 0x04 0.--4. " MAX_NUM_CH ,Number of channels to decode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x08 "FIFO_CNTL,FIFO Control Register" bitfld.long 0x08 4. " CFG_DIS_PORT3 ,Configuration disable PORT3" "No,Yes" bitfld.long 0x08 3. " FIFO_EMPTY_CALC ,FIFO empty calc" "Read address,BASE read address" textline " " bitfld.long 0x08 2. " FIFO_DIR ,FIFO direction" "Smpl2pkt,Pkt2smpl" bitfld.long 0x08 1. " SYNC_WR_TO_CH_ZERO ,Last channel index synchronizes the write addresses" "No synchronization,Synchronization" textline " " bitfld.long 0x08 0. " FIFO_SW_RST ,FIFO write and read pointers reset" "No reset,Reset" rgroup.long 0x3008C++0x03 line.long 0x00 "FIFO_STTS,FIFO Status Register" bitfld.long 0x00 3. " UNDERRUN ,FIFO under run error has occurred" "Not occurred,Occurred" bitfld.long 0x00 2. " OVERRUN ,FIFO overrun error has occurred" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " REMPTY ,Indicates FIFO empty" "Not empty,Empty" bitfld.long 0x00 0. " WFULL ,Indicates FIFO full" "Not full,Full" group.long 0x30090++0x03 line.long 0x00 "SUB_PCKT_THRSH,SUB Packet Threshold Register" hexmask.long.byte 0x00 16.--23. 1. " CFG_MEM_FIFO_THRSH3 ,Configuration memory FIFO threshold 3 sub packet" hexmask.long.byte 0x00 8.--15. 1. " CFG_MEM_FIFO_THRSH2 ,Configuration memory FIFO threshold 2 sub packet" textline " " hexmask.long.byte 0x00 0.--7. 1. " CFG_MEM_FIFO_THRSH1 ,Configuration memory FIFO threshold 1 sub packet" group.long 0x30800++0x13 line.long 0x00 "SOURCE_PIF_WR_ADDR,Source PIF Write Address Register" bitfld.long 0x00 0.--3. " WR_ADDR ,4 MSB of the packet memory address in which the data is written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SOURCE_PIF_WR_REQ,Source PIF Write Request Register" bitfld.long 0x04 0. " HOST_WR ,Write request bit for the host write transaction" "Not requested,Requested" line.long 0x08 "SOURCE_PIF_RD_ADDR,Source PIF Read Address Register" bitfld.long 0x08 0.--3. " RD_ADDR ,4 MSB of the packet memory address in which the data is read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SOURCE_PIF_RD_REQ,Source PIF Read Request Register" bitfld.long 0x0C 0. " HOST_RD ,Read request bit for the host write transaction" "Not requested,Requested" line.long 0x10 "SOURCE_PIF_DATA_WR,Source PIF Data Write Register" rgroup.long 0x30814++0x03 line.long 0x00 "SOURCE_PIF_DATA_RD,Source PIF Data Read Register" group.long 0x30818++0x07 line.long 0x00 "SOURCE_PIF_FIFO1_FLUSH,Source PIF FIFO1 Flush Register" bitfld.long 0x00 0. " FIFO1_FLUSH ,FIFO1 flush bit" "0,1" line.long 0x04 "SOURCE_PIF_FIFO2_FLUSH,Source PIF FIFO2 Flush Register" bitfld.long 0x04 0. " FIFO2_FLUSH ,FIFO2 flush bit" "0,1" rgroup.long 0x30820++0x07 line.long 0x00 "SOURCE_PIF_STATUS,Source PIF Status Register" bitfld.long 0x00 3. " FIFO2_EMPTY ,FIFO2 empty indication" "Not empty,Empty" bitfld.long 0x00 2. " FIFO1_FULL ,FIFO1 full indication" "Not full,Full" textline " " bitfld.long 0x00 0.--1. " SOURCE_PKT_MEM_CTRL_FSM_STATE ,State of the FSM that controls packet memory transactions" "0,1,2,3" line.long 0x04 "SOURCE_PIF_INTERRUPT_SOURCE,Source PIF Interrupt Source Register" bitfld.long 0x04 9. " FIFO2_UNDERFLOW ,FIFO2 underflow indication" "No underflow,Underflow" bitfld.long 0x04 8. " FIFO2_OVERFLOW ,FIFO2 overflow indication" "No overflow,Overflow" textline " " bitfld.long 0x04 7. " FIFO1_UNDERFLOW ,FIFO1 underflow indication" "No underflow,Underflow" bitfld.long 0x04 6. " FIFO1_OVERFLOW ,FIFO1 overflow indication" "No overflow,Overflow" textline " " bitfld.long 0x04 5. " ALLOC_WR_ERROR ,Invalid write to the allocation table error" "No error,Error" bitfld.long 0x04 4. " ALLOC_WR_DONE ,Successful write to the allocation table" "Not written,Written" textline " " bitfld.long 0x04 3. " PSLVERR ,APB slave error interrupt" "No interrupt,Interrupt" bitfld.long 0x04 2. " NONVALID_TYPE_REQUESTED_INT ,Non valid type of packet is requested by the packet interface" "Not requested,Requested" textline " " bitfld.long 0x04 1. " HOST_RD_DONE_INT ,Host read transaction finished" "Not finished,Finished" bitfld.long 0x04 0. " HOST_WR_DONE_INT ,Host write transaction finished" "Not finished,Finished" group.long 0x30828++0x0F line.long 0x00 "SOURCE_PIF_INTERRUPT_MASK,Source PIF Interrupt Mask" bitfld.long 0x00 9. " FIFO2_UNDERFLOW_MASK ,FIFO2 underflow interrupt mask" "Not masked,Masked" bitfld.long 0x00 8. " FIFO2_OVERFLOW_MASK ,FIFO2 overflow interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 7. " FIFO1_UNDERFLOW_MASK ,FIFO1 underflow interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " FIFO1_OVERFLOW_MASK ,FIFO1 overflow interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " ALLOC_WR_ERROR_MASK ,Invalid write to the allocation table error interrupt mask" "Not masked,Masked" bitfld.long 0x00 4. " ALLOC_WR_DONE_MASK ,Successful write to the allocation table interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 3. " PSLVERR_MASK ,APB slave error interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " NONVALID_TYPE_REQUESTED_INT_MASK ,Non valid type of packet is requested by the packet interface interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 1. " HOST_RD_DONE_INT_MASK ,Host read transaction finished interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. " HOST_WR_DONE_INT_MASK ,Host write transaction finished interrupt mask" "Not masked,Masked" line.long 0x04 "SOURCE_PIF_PKT_ALLOC_REG,Source PIF Packet Allocation Register" bitfld.long 0x04 17. " ACTIVE_IDLE_TYPE ,Active idle type" "0,1" bitfld.long 0x04 16. " TYPE_VALID ,Type valid" "Invalid,Valid" textline " " hexmask.long.byte 0x04 8.--15. 1. " PACKET_TYPE ,Type of packet" hexmask.long.byte 0x04 0.--3. 0x01 " PKT_ALLOC_ADDRESS ,Address of the register in the source allocation table" line.long 0x08 "SOURCE_PIF_PKT_ALLOC_WR_EN,Source PIF Packet Allocation Write Enable" bitfld.long 0x08 0. " PKT_ALLOC_WR_EN ,Writing to the allocation table enable" "Disabled,Enabled" line.long 0x0C "SOURCE_PIF_SW_RESET,Source PIF SW Reset" bitfld.long 0x0C 0. " SW_RST ,Software reset" "No reset,Reset" tree "HDMI_TX_PHY" base ad:0x00080000 width 40. rgroup.word 0x00++0x1B line.word 0x00 "CMN_PID_TYPE,Product Type ID Register" line.word 0x02 "CMN_PID_NUM12,Product Number 1 2 ID Register" line.word 0x04 "CMN_PID_NUM34,Product Number 3 4 ID Register" line.word 0x06 "CMN_PID_NUM56,Product Number 5 6 ID Register" line.word 0x08 "CMN_PID_NUM78,Product Number 7 8 ID Register" line.word 0x0A "CMN_PID_NUM910,Product Number 9 10 ID Register" line.word 0x0C "CMN_PID_NUM1112,Product Number 11 12 ID Register" line.word 0x0E "CMN_PID_REV,Product Revision ID Register" line.word 0x10 "CMN_PID_MFG,Product Technology Manufacturer ID Register" line.word 0x12 "CMN_PID_NODE,Product Technology Process Node ID Register" line.word 0x14 "CMN_PID_FLV0,Product Technology Process Flavor ID Register 0" line.word 0x16 "CMN_PID_FLV1,Product Technology Process Flavor ID Register 1" line.word 0x18 "CMN_PID_IOV,Product I/O Voltage ID Register" line.word 0x1A "CMN_PID_LANES,Product SerDes Lanes ID Register" hexmask.word.byte 0x1A 8.--15. 1. " CMN_PID_LANES_15_8 ,Product SerDes lanes left of common" hexmask.word.byte 0x1A 0.--7. 1. " CMN_PID_LANES_0_7 ,Product SerDes lanes right of common" rgroup.word 0x20++0x09 line.word 0x00 "CMN_PID_METAL0,Product Metal Layers ID Register 0" bitfld.word 0x00 12.--15. " CMN_PID_METAL0_15_12 ,Product X metal layers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 8.--11. " CMN_PID_METAL0_11_8 ,Product Y metal layers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x00 4.--7. " CMN_PID_METAL0_7_4 ,Product Z metal layers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " CMN_PID_METAL0_3_0 ,Product R/U metal layers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "CMN_PID_METAL1,Product Metal Layers ID Register 1" line.word 0x04 "CMN_PID_METAL2,Product Metal Layers ID register 2" line.word 0x06 "CMN_PID_METAL3,Product Metal Layers ID register 3" line.word 0x08 "CMN_PID_METALD,Product Metal Layer Direction ID Register" group.word 0x40++0x05 line.word 0x00 "CMN_SSM_SM_CTRL,Startup State Machine Control Register" bitfld.word 0x00 7. " CMN_SSM_SM_CTRL_7 ,Bandgap enable override enable" "Disabled,Enabled" bitfld.word 0x00 6. " CMN_SSM_SM_CTRL_6 ,Bandgap enable override" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " CMN_SSM_SM_CTRL_5 ,Bias enable override enable" "Disabled,Enabled" bitfld.word 0x00 4. " CMN_SSM_SM_CTRL_4 ,Bias enable override" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CMN_SSM_SM_CTRL_1 ,Skip post bandgap enable re-calibration" "Disabled,Enabled" bitfld.word 0x00 0. " CMN_SSM_SM_CTRL_1 ,Skip post bandgap re-calibration" "Disabled,Enabled" line.word 0x02 "CMN_SSM_BANDGAP_TMR,Bandgap Enable Timer Register" hexmask.word 0x02 0.--9. 1. " CMN_SSM_BANDGAP_TMR_9_0 ,Bandgap enable state timer value" line.word 0x04 "CMN_SSM_BIAS_TMR,Bias Enable Timer Register" hexmask.word 0x04 0.--9. 1. " CMN_SSM_BANDGAP_BIAS_9_0 ,Bias enable state timer value" group.word 0x4E++0x0D line.word 0x00 "CMN_SSM_USER_DEF_CTRL,Startup State Machine User Defined Control Register" bitfld.word 0x00 7. " CMN_SSM_USER_DEF_CTRL_7 ,Analog reference clock enable override enable" "Disabled,Enabled" bitfld.word 0x00 6. " CMN_SSM_USER_DEF_CTRL_6 ,Analog reference clock enable override" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " CMN_SSM_USER_DEF_CTRL_5 ,Calibration iconst enable override enable" "Disabled,Enabled" bitfld.word 0x00 4. " CMN_SSM_USER_DEF_CTRL_4 ,Calibration iconst enable override" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CMN_SSM_USER_DEF_CTRL_3 ,Calibration power enable override enable" "Disabled,Enabled" bitfld.word 0x00 2. " CMN_SSM_USER_DEF_CTRL_2 ,Calibration power enable override" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CMN_SSM_USER_DEF_CTRL_1 ,Bandgap enable override enable" "Disabled,Enabled" bitfld.word 0x00 0. " CMN_SSM_USER_DEF_CTRL_0 ,Bandgap enable override" "Disabled,Enabled" line.word 0x02 "CMN_PLLSM0_SM_CTRL,PLL 0 Control State Machine Control Register" bitfld.word 0x02 9. " CMN_PLLSM0_SM_CTRL_9 ,PLL enable override enable" "Disabled,Enabled" bitfld.word 0x02 8. " CMN_PLLSM0_SM_CTRL_8 ,PLL enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 7. " CMN_PLLSM0_SM_CTRL_7 ,PLL VCO LDO reference override enable" "Disabled,Enabled" bitfld.word 0x02 6. " CMN_PLLSM0_SM_CTRL_6 ,PLL VCO LDO reference override" "Disabled,Enabled" textline " " bitfld.word 0x02 5. " CMN_PLLSM0_SM_CTRL_5 ,PLL VCO LDO reference charge pulse override enable" "Disabled,Enabled" bitfld.word 0x02 4. " CMN_PLLSM0_SM_CTRL_4 ,PLL VCO LDO reference charge pulse override" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " CMN_PLLSM0_SM_CTRL_0 ,Skip PLL re-calibration" "Not skipped,Skipped" line.word 0x04 "CMN_PLLSM0_PLLEN_TMR,PLL 0 Enable Timer Register" hexmask.word 0x04 0.--9. 1. " CMN_PLLSM0_PLLEN_TMR_9_0 ,PLL enable state timer value" line.word 0x06 "CMN_PLLSM0_PLLPRE_TMR,PLL 0 Pre-Charge Timer Register" hexmask.word 0x06 0.--9. 1. " CMN_PLLSM0_PLLPRE_TMR_9_0 ,PLL pre-charge state timer value" line.word 0x08 "CMN_PLLSM0_PLLVREF_TMR,PLL 0 VREF Delay Timer Register" hexmask.word 0x08 0.--9. 1. " CMN_PLLSM0_PLLVREF_TMR_9_0 ,PLL VREF delay state timer value" line.word 0x0A "CMN_PLLSM0_PLLLOCK_TMR,PLL 0 Lock Delay Timer Register" hexmask.word 0x0A 0.--9. 1. " CMN_PLLSM0_PLLLOCK_TMR_9_0 ,PLL lock delay state timer value" line.word 0x0C "CMN_PLLSM0_PLLCLKDIS_TMR,PLL 0 Clock Disable Delay Timer Register" hexmask.word 0x0C 0.--9. 1. " CMN_PLLSM0_PLLCLKDIS_TMR_9_0 ,PLL clock disable delay state timer value" group.word 0x5E++0x0D line.word 0x00 "CMN_PLLSM0_USER_DEF_CTRL,PLL 0 Control State Machine User Defined Control Register" bitfld.word 0x00 12. " CMN_PLLSM0_USER_DEF_CTRL_12 ,PLL oscillator ring select" "0,1" bitfld.word 0x00 5. " CMN_PLLSM0_USER_DEF_CTRL_5 ,PLL bias enable override enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " CMN_PLLSM0_USER_DEF_CTRL_4 ,PLL bias enable override" "Disabled,Enabled" bitfld.word 0x00 3. " CMN_PLLSM0_USER_DEF_CTRL_3 ,PLL 0 start loop override enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " CMN_PLLSM0_USER_DEF_CTRL_2 ,PLL 0 start loop enable override" "Disabled,Enabled" bitfld.word 0x00 1. " CMN_PLLSM0_USER_DEF_CTRL_1 ,PLL 0 VCO LDO enable override enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CMN_PLLSM0_USER_DEF_CTRL_0 ,PLL 0 VCO LDO enable override" "Disabled,Enabled" line.word 0x02 "CMN_PLLSM1_SM_CTRL,PLL 1 Control State Machine Control Register" bitfld.word 0x02 9. " CMN_PLLSM1_SM_CTRL_9 ,PLL enable override enable" "Disabled,Enabled" bitfld.word 0x02 8. " CMN_PLLSM1_SM_CTRL_8 ,PLL enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 7. " CMN_PLLSM1_SM_CTRL_7 ,PLL VCO LDO reference override enable" "Disabled,Enabled" bitfld.word 0x02 6. " CMN_PLLSM1_SM_CTRL_6 ,PLL VCO LDO reference override" "Disabled,Enabled" textline " " bitfld.word 0x02 5. " CMN_PLLSM1_SM_CTRL_5 ,PLL VCO LDO reference charge pulse override enable" "Disabled,Enabled" bitfld.word 0x02 4. " CMN_PLLSM1_SM_CTRL_4 ,PLL VCO LDO reference charge pulse override" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " CMN_PLLSM1_SM_CTRL_0 ,Skip PLL re-calibration" "Not skipped,Skipped" line.word 0x04 "CMN_PLLSM1_PLLEN_TMR,PLL 1 Enable Timer Register" hexmask.word 0x04 0.--9. 1. " CMN_PLLSM1_PLLEN_TMR_9_0 ,PLL enable state timer value" line.word 0x06 "CMN_PLLSM1_PLLPRE_TMR,PLL 1 Pre-Charge Timer Register" hexmask.word 0x06 0.--9. 1. " CMN_PLLSM1_PLLPRE_TMR_9_0 ,PLL pre-charge state timer value" line.word 0x08 "CMN_PLLSM1_PLLVREF_TMR,PLL 1 VREF Delay Timer Register" hexmask.word 0x08 0.--9. 1. " CMN_PLLSM1_PLLVREF_TMR_9_0 ,PLL VREF delay state timer value" line.word 0x0A "CMN_PLLSM1_PLLLOCK_TMR,PLL 1 Lock Delay Timer Register" hexmask.word 0x0A 0.--9. 1. " CMN_PLLSM1_PLLLOCK_TMR_9_0 ,PLL lock delay state timer value" line.word 0x0C "CMN_PLLSM1_PLLCLKDIS_TMR,PLL 1 Clock Disable Delay Timer Register" hexmask.word 0x0C 0.--9. 1. " CMN_PLLSM1_PLLCLKDIS_TMR_9_0 ,PLL clock disable delay state timer value" group.word 0x6E++0x01 line.word 0x00 "CMN_PLLSM1_USER_DEF_CTRL,PLL 1 Control State Machine User Defined Control Register" bitfld.word 0x00 12. " CMN_PLLSM1_USER_DEF_CTRL_12 ,PLL oscillator ring select" "0,1" bitfld.word 0x00 5. " CMN_PLLSM1_USER_DEF_CTRL_5 ,PLL bias enable override enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " CMN_PLLSM1_USER_DEF_CTRL_4 ,PLL bias enable override" "Disabled,Enabled" bitfld.word 0x00 3. " CMN_PLLSM1_USER_DEF_CTRL_3 ,PLL 1 start loop override enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " CMN_PLLSM1_USER_DEF_CTRL_2 ,PLL 1 start loop enable override" "Disabled,Enabled" bitfld.word 0x00 1. " CMN_PLLSM1_USER_DEF_CTRL_1 ,PLL 1 VCO LDO enable override enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CMN_PLLSM1_USER_DEF_CTRL_0 ,PLL 1 VCO LDO enable override" "Disabled,Enabled" group.word 0xC0++0x05 line.word 0x00 "CMN_CDIAG_PWR_CTRL,Common Control Power Island Control Register" bitfld.word 0x00 15. " CMN_CDIAG_PWR_CTRL_15 ,Startup state machine auto calibration power down disable" "No,Yes" bitfld.word 0x00 14. " CMN_CDIAG_PWR_CTRL_14 ,PLL Control 1 state machine auto calibration power down disable" "No,Yes" textline " " bitfld.word 0x00 13. " CMN_CDIAG_PWR_CTRL_13 ,PLL control 0 state machine auto calibration power down disable" "No,Yes" bitfld.word 0x00 4.--6. " CMN_CDIAG_PWR_CTRL_6_4 ,Power enable phase 2 timer value" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 0.--2. " CMN_CDIAG_PWR_CTRL_2_0 ,Power enable phase 1 timer value" "0,1,2,3,4,5,6,7" line.word 0x02 "CMN_PSM_CLK_CTRL,Common PSM Clock Control Register" bitfld.word 0x02 4. " CMN_PSM_CLK_CTRL_4 ,PSM clock select" "0,1" bitfld.word 0x02 0.--3. " CMN_PSM_CLK_CTRL_3_0 ,PLL clock divider value for PSM clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "CMN_CDIAG_REFCLK_CTRL,Reference Clock Receiver Control Register" bitfld.word 0x04 12.--14. " CMN_CDIAG_REFCLK_CTRL_14_12 ,Digital reference clock divider scaler" "0,1,2,3,4,5,6,7" bitfld.word 0x04 10. " CMN_CDIAG_REFCLK_CTRL_10 ,Reference clock analog clock test mode" "Disabled,Enabled" textline " " bitfld.word 0x04 9. " CMN_CDIAG_REFCLK_CTRL_9 ,Reference clock digital clock test mode" "Disabled,Enabled" bitfld.word 0x04 8. " CMN_CDIAG_REFCLK_CTRL_8 ,Reference clock hysteresis enable" "Disabled,Enabled" textline " " bitfld.word 0x04 7. " CMN_CDIAG_REFCLK_CTRL_7 ,Reference clock termination enable override enable" "Disabled,Enabled" bitfld.word 0x04 6. " CMN_CDIAG_REFCLK_CTRL_6 ,Reference clock termination enable override" "Disabled,Enabled" textline " " bitfld.word 0x04 0.--4. " CMN_CDIAG_REFCLK_CTRL_4_0 ,Reference clock termination code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0xC8++0x01 line.word 0x00 "CMN_CDIAG_CDB_DIAG,Common Control CDB Diagnostic Register" bitfld.word 0x00 1. " CMN_CDIAG_CDB_DIAG_1 ,Force clear of the CDB first access detected register bit" "No force,Force" rbitfld.word 0x00 0. " CMN_CDIAG_CDB_DIAG_0 ,CDB bus error" "No error,Error" rgroup.word 0xCC++0x01 line.word 0x00 "CMN_CDIAG_RST_DIAG,Common Control reset Diagnostic Register" bitfld.word 0x00 1. " CMN_CDIAG_RST_DIAG_1 ,Current state of the macro_pwr_reset_sync_n reset" "No reset,Reset" bitfld.word 0x00 0. " CMN_CDIAG_RST_DIAG_0 ,Current state of the cmn_reset_sync_n reset" "No reset,Reset" group.word 0xFE++0x0F line.word 0x00 "CMN_CDIAG_DCYA,Common Control Cover Your Alternatives Register" line.word 0x02 "CMN_PLL0_VCOCAL_CTRL,PLL 0 VCO Calibration Control Register" bitfld.word 0x02 15. " CMN_PLL0_VCOCAL_CTRL_15 ,Start VCO calibration" "Not started,Started" rbitfld.word 0x02 14. " CMN_PLL0_VCOCAL_CTRL_14 ,VCO calibration process done" "Not done,Done" textline " " hexmask.word 0x02 0.--8. 1. " CMN_PLL0_VCOCAL_CTRL_8_0 ,VCO calibration code" line.word 0x04 "CMN_PLL0_VCOCAL_START,PLL 0 VCO Calibration Start Point Register" bitfld.word 0x04 12.--14. " CMN_PLL0_VCOCAL_START_14_12 ,VCO calibration initial step size control" "0,1,2,3,4,5,6,7" hexmask.word 0x04 0.--8. 1. " CMN_PLL0_VCOCAL_START_8_0 ,VCO calibration code starting point value" line.word 0x06 "CMN_PLL0_VCOCAL_TCTRL,PLL 0 VCO Calibration Timer Control Register" bitfld.word 0x06 0.--2. " CMN_PLL0_VCOCAL_TCTRL_2_0 ,VCO calibration initial time scale control" "0,1,2,3,4,5,6,7" line.word 0x08 "CMN_PLL0_VCOCAL_OVRD,PLL 0 VCO Calibration Override Register" bitfld.word 0x08 15. " CMN_PLL0_VCOCAL_OVRD_15 ,VCO calibration code override enable" "Disabled,Enabled" hexmask.word 0x08 0.--8. 1. " CMN_PLL0_VCOCAL_OVRD_8_0 ,VCO calibration code override value" line.word 0x0A "CMN_PLL0_VCOCAL_INIT_TMR,PLL 0 VCO Calibration Initialization Timer Register" hexmask.word 0x0A 0.--13. 1. " CMN_PLL0_VCOCAL_INIT_TMR_13_0 ,Initialization wait timer value" line.word 0x0C "CMN_PLL0_VCOCAL_ITER_TMR,PLL 0 VCO Calibration Iteration Timer Register" hexmask.word 0x0C 0.--13. 1. " CMN_PLL0_VCOCAL_ITER_TMR_13_0 ,Iteration wait timer value" line.word 0x0E "CMN_PLL0_VCOCAL_REFTIM_START,PLL 0 VCO Calibration Reference Clock Timer Start Value Register" hexmask.word 0x0E 0.--13. 1. " CMN_PLL0_VCOCAL_REFTIM_START_13_0 ,PLL VCO calibration reference clock timer start value" group.word 0x110++0x01 line.word 0x00 "CMN_PLL0_VCOCAL_PLLCNT_START,PLL 0 VCO Calibration PLL Clock Counter Start Value Register" hexmask.word 0x00 0.--13. 1. " CMN_PLL0_VCOCAL_PLLCNT_START_13_0 ,PLL VCO calibration PLL clock counter start value" group.word 0x120++0x13 line.word 0x00 "CMN_PLL0_LOCK_REFCNT_START,PLL 0 Lock Reference Counter Start Value Register" hexmask.word 0x00 0.--11. 1. " CMN_PLL0_LOCK_REFCNT_START_11_0 ,PLL lock reference counter start value" line.word 0x02 "CMN_PLL0_LOCK_REFCNT_IDLE,PLL 0 Lock Reference Counter Idle Value Register" hexmask.word 0x02 0.--11. 1. " CMN_PLL0_LOCK_REFCNT_IDLE_11_0 ,PLL lock reference counter idle value" line.word 0x04 "CMN_PLL0_LOCK_PLLCNT_START,PLL 0 Lock PLL Counter Start Value Register" hexmask.word 0x04 0.--11. 1. " CMN_PLL0_LOCK_PLLCNT_START_11_0 ,PLL lock PLL counter start value" line.word 0x06 "CMN_PLL0_LOCK_PLLCNT_THR,PLL 0 Lock PLL Counter Threshold Value Register" hexmask.word 0x06 0.--11. 1. " CMN_PLL0_LOCK_PLLCNT_THR_11_0 ,PLL lock counter threshold value" line.word 0x08 "CMN_PLL0_INTDIV,PLL 0 Feedback Divider Integer Register" hexmask.word 0x08 0.--9. 1. " CMN_PLL0_INTDIV_9_0 ,Value of the pll_fb_div_integer signal" line.word 0x0A "CMN_PLL0_FRACDIV,PLL 0 Feedback Divider Fractional Register" line.word 0x0C "CMN_PLL0_HIGH_THR,PLL 0 Feedback Divider High Threshold Register" hexmask.word 0x0C 0.--9. 1. " CMN_PLL0_HIGH_THR_9_0 ,Value of the pll_fb_div_high_threshold signal" line.word 0x0E "CMN_PLL0_DSM_DIAG,PLL 0 Delta Sigma Modulator Diagnostics Register" bitfld.word 0x0E 15. " CMN_PLL0_DSM_DIAG_15 ,Delta sigma bypass enable" "Disabled,Enabled" bitfld.word 0x0E 4.--7. " CMN_PLL0_DSM_DIAG_7_4 ,PLL feedback divider latency adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x10 "CMN_PLL0_SS_CTRL1,PLL 0 Spread Spectrum Control Register 1" bitfld.word 0x10 15. " CMN_PLL0_SS_CTRL1_15 ,Spread spectrum waveform generator disable" "No,Yes" bitfld.word 0x10 14. " CMN_PLL0_SS_CTRL1_14 ,Spread spectrum enable during VCO calibration" "Disabled,Enabled" textline " " hexmask.word 0x10 0.--11. 1. " CMN_PLL0_SS_CTRL1_11_0 ,Amplitude step size" line.word 0x12 "CMN_PLL0_SS_CTRL2,PLL 0 Spread Spectrum Control Register 2" hexmask.word.byte 0x12 8.--14. 1. " CMN_PLL0_SS_CTRL2_14_8 ,Number of steps" hexmask.word.byte 0x12 0.--6. 1. " CMN_PLL0_SS_CTRL2_6_0 ,Time step size" group.word 0x138++0x01 line.word 0x00 "CMN_PLL0_VCOCAL_V2I_CTRL,PLL 0 VCO Calibration V2I Control Register" rbitfld.word 0x00 15. " CMN_PLL0_VCOCAL_V2I_CTRL_15 ,VCO calibration code for voltage to current DAC override enable" "Disabled,Enabled" bitfld.word 0x00 8.--11. " CMN_PLL0_VCOCAL_V2I_CTRL_11_8 ,VCO calibration code for voltage to current DAC override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x00 0.--1. " CMN_PLL0_VCOCAL_V2I_CTRL_1_0 ,VCO calibration code for voltage to current DAC scaling factor" "0,1,2,3" group.word 0x140++0x0D line.word 0x00 "CMN_PLL1_VCOCAL_CTRL,PLL 1 VCO Calibration Control Register" bitfld.word 0x00 15. " CMN_PLL1_VCOCAL_CTRL_15 ,Start VCO calibration" "Not started,Started" rbitfld.word 0x00 14. " CMN_PLL1_VCOCAL_CTRL_14 ,VCO calibration process done" "Not done,Done" textline " " hexmask.word 0x00 0.--8. 1. " CMN_PLL1_VCOCAL_CTRL_8_0 ,VCO calibration code" line.word 0x02 "CMN_PLL1_VCOCAL_START,PLL 1 VCO Calibration Start Point Register" bitfld.word 0x02 12.--14. " CMN_PLL1_VCOCAL_START_14_12 ,VCO calibration initial step size control" "0,1,2,3,4,5,6,7" hexmask.word 0x02 0.--8. 1. " CMN_PLL1_VCOCAL_START_8_0 ,VCO calibration code starting point value" line.word 0x04 "CMN_PLL1_VCOCAL_TCTRL,PLL 1 VCO Calibration Timer Control Register" bitfld.word 0x04 0.--2. " CMN_PLL1_VCOCAL_TCTRL_2_0 ,VCO calibration initial time scale control" "0,1,2,3,4,5,6,7" line.word 0x06 "CMN_PLL1_VCOCAL_OVRD,PLL 1 VCO Calibration Override Register" bitfld.word 0x06 15. " CMN_PLL1_VCOCAL_OVRD_15 ,VCO calibration code override enable" "Disabled,Enabled" hexmask.word 0x06 0.--8. 1. " CMN_PLL1_VCOCAL_OVRD_8_0 ,VCO calibration code override value" line.word 0x08 "CMN_PLL1_VCOCAL_INIT_TMR,PLL 1 VCO Calibration Initialization Timer Register" hexmask.word 0x08 0.--13. 1. " CMN_PLL1_VCOCAL_INIT_TMR_13_0 ,Initialization wait timer value" line.word 0x0A "CMN_PLL1_VCOCAL_ITER_TMR,PLL 1 VCO Calibration Iteration Timer Register" hexmask.word 0x0A 0.--13. 1. " CMN_PLL1_VCOCAL_ITER_TMR_13_0 ,Iteration wait timer value" line.word 0x0C "CMN_PLL1_VCOCAL_REFTIM_START,PLL 1 VCO Calibration Reference Clock Timer Start Value Register" hexmask.word 0x0C 0.--13. 1. " CMN_PLL1_VCOCAL_REFTIM_START_13_0 ,PLL VCO calibration reference clock timer start value" group.word 0x150++0x01 line.word 0x00 "CMN_PLL1_VCOCAL_PLLCNT_START,PLL 1 VCO Calibration PLL Clock Counter Start Value Register" hexmask.word 0x00 0.--13. 1. " CMN_PLL1_VCOCAL_PLLCNT_START_13_0 ,PLL VCO calibration PLL clock counter start value" group.word 0x160++0x13 line.word 0x00 "CMN_PLL1_LOCK_REFCNT_START,PLL 1 Lock Reference Counter Start Value Register" hexmask.word 0x00 0.--11. 1. " CMN_PLL1_LOCK_REFCNT_START_11_0 ,PLL lock reference counter start value" line.word 0x02 "CMN_PLL1_LOCK_REFCNT_IDLE,PLL 1 Lock Reference Counter Idle Value Register" hexmask.word 0x02 0.--11. 1. " CMN_PLL1_LOCK_REFCNT_IDLE_11_0 ,PLL lock reference counter idle value" line.word 0x04 "CMN_PLL1_LOCK_PLLCNT_START,PLL 1 Lock PLL Counter Start Value Register" hexmask.word 0x04 0.--11. 1. " CMN_PLL1_LOCK_PLLCNT_START_11_0 ,PLL lock PLL counter start value" line.word 0x06 "CMN_PLL1_LOCK_PLLCNT_THR,PLL 1 Lock PLL Counter Threshold Value Register" hexmask.word 0x06 0.--11. 1. " CMN_PLL1_LOCK_PLLCNT_THR_11_0 ,PLL lock counter threshold value" line.word 0x08 "CMN_PLL1_INTDIV,PLL 1 Feedback Divider Integer Register" hexmask.word 0x08 0.--9. 1. " CMN_PLL1_INTDIV_9_0 ,Value of the pll_fb_div_integer signal" line.word 0x0A "CMN_PLL1_FRACDIV,PLL 1 Feedback Divider Fractional Register" line.word 0x0C "CMN_PLL1_HIGH_THR,PLL 1 Feedback Divider High Threshold Register" hexmask.word 0x0C 0.--9. 1. " CMN_PLL1_HIGH_THR_9_0 ,Value of the pll_fb_div_high_threshold signal" line.word 0x0E "CMN_PLL1_DSM_DIAG,PLL 1 Delta Sigma Modulator Diagnostics Register" bitfld.word 0x0E 15. " CMN_PLL1_DSM_DIAG_15 ,Delta sigma bypass enable" "Disabled,Enabled" bitfld.word 0x0E 4.--7. " CMN_PLL1_DSM_DIAG_7_4 ,PLL feedback divider latency adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x10 "CMN_PLL1_SS_CTRL1,PLL 1 Spread Spectrum Control Register 1" bitfld.word 0x10 15. " CMN_PLL1_SS_CTRL1_15 ,Spread spectrum waveform generator disable" "No,Yes" bitfld.word 0x10 14. " CMN_PLL1_SS_CTRL1_14 ,Spread spectrum enable during VCO calibration" "Disabled,Enabled" textline " " hexmask.word 0x10 0.--11. 1. " CMN_PLL1_SS_CTRL1_11_0 ,Value of the amplitude_step_size pin on the spread spectrum waveform generator" line.word 0x12 "CMN_PLL1_SS_CTRL2,PLL 1 Spread Spectrum Control Register 2" hexmask.word.byte 0x12 8.--14. 1. " CMN_PLL1_SS_CTRL2_14_8 ,Value of the num_steps pin on the spread spectrum waveform generator" hexmask.word.byte 0x12 0.--6. 1. " CMN_PLL1_SS_CTRL2_6_0 ,Value for the time_step_size pin on the spread spectrum waveform generator" group.word 0x178++0x01 line.word 0x00 "CMN_PLL1_VCOCAL_V2I_CTRL,PLL 1 VCO Calibration V2I Control Register" rbitfld.word 0x00 15. " CMN_PLL1_VCOCAL_V2I_CTRL_15 ,VCO calibration code for voltage to current DAC override enable" "Disabled,Enabled" bitfld.word 0x00 8.--11. " CMN_PLL1_VCOCAL_V2I_CTRL_11_8 ,VCO calibration code for voltage to current DAC override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x00 0.--1. " CMN_PLL1_VCOCAL_V2I_CTRL_1_0 ,VCO calibration code for voltage to current DAC scaling factor" "0,1,2,3" group.word 0x180++0x0B line.word 0x00 "CMN_ICAL_CTRL,Current Calibration Control Register" bitfld.word 0x00 15. " CMN_ICAL_CTRL_15 ,Start current calibration" "Not started,Started" rbitfld.word 0x00 14. " CMN_ICAL_CTRL_14 ,Current calibration process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " CMN_ICAL_CTRL_13 ,No analog calibration response" "No response,Response" rbitfld.word 0x00 12. " CMN_ICAL_CTRL_12 ,Current analog comparator response" "No response,Response" textline " " rbitfld.word 0x00 0.--5. " CMN_ICAL_CTRL_5_0 ,Current calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "CMN_ICAL_OVRD,Current Calibration Override Register" bitfld.word 0x02 15. " CMN_ICAL_OVRD_15 ,Current code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " CMN_ICAL_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " rbitfld.word 0x02 0.--5. " CMN_ICAL_OVRD_5_0 ,Current code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "CMN_ICAL_START,Current Calibration Start Register" bitfld.word 0x04 15. " CMN_ICAL_START_15 ,Current calibration direction" "Disabled,Enabled" bitfld.word 0x04 0.--5. " CMN_ICAL_START_5_0 ,Start current calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x06 "CMN_ICAL_TUNE,Current Calibration Tune Register" bitfld.word 0x06 0.--5. " CMN_ICAL_TUNE_5_0 ,Current calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "CMN_ICAL_INIT_TMR,Current Calibration Initialization Timer Register" hexmask.word.byte 0x08 0.--7. 1. " CMN_ICAL_INIT_TMR_7_0 ,Initialization wait timer value" line.word 0x0A "CMN_ICAL_ITER_TMR,Current Calibration Iteration Timer Register" hexmask.word.byte 0x0A 0.--7. 1. " CMN_ICAL_ITER_TMR_7_0 ,Iteration wait timer value" group.word 0x1A0++0x0B line.word 0x00 "CMN_RXCAL_CTRL,RX Resistor Calibration Control Register" bitfld.word 0x00 15. " CMN_RXCAL_CTRL_15 ,Start resistor calibration" "Not started,Started" rbitfld.word 0x00 14. " CMN_RXCAL_CTRL_14 ,Resistor calibration process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " CMN_RXCAL_CTRL_13 ,No analog calibration response" "No response,Response" rbitfld.word 0x00 12. " CMN_RXCAL_CTRL_12 ,Current analog comparator response" "No response,Response" textline " " rbitfld.word 0x00 0.--4. " CMN_RXCAL_CTRL_4_0 ,Resistor calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x02 "CMN_RXCAL_OVRD,RX Resistor Calibration Override Register" bitfld.word 0x02 15. " CMN_RXCAL_OVRD_15 ,Resistor code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " CMN_RXCAL_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " rbitfld.word 0x02 0.--4. " CMN_RXCAL_OVRD_4_0 ,Resistor code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "CMN_RXCAL_START,RX Resistor Calibration Start Register" bitfld.word 0x04 15. " CMN_RXCAL_START_15 ,Resistor calibration direction" "0,1" bitfld.word 0x04 0.--4. " CMN_RXCAL_START_4_0 ,Start resistor calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "CMN_RXCAL_TUNE,RX Resistor Calibration Tune Register" bitfld.word 0x06 0.--4. " CMN_RXCAL_TUNE_4_0 ,Resistor calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "CMN_RXCAL_INIT_TMR,RX Resistor Calibration Initialization Timer Register" bitfld.word 0x08 0.--5. " CMN_RXCAL_INIT_TMR_5_0 ,Initialization wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0A "CMN_RXCAL_ITER_TMR,RX Resistor Calibration Iteration Timer Register" bitfld.word 0x0A 0.--5. " CMN_RXCAL_ITER_TMR_5_0 ,Iteration wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x1C0++0x0B line.word 0x00 "CMN_TXPUCAL_CTRL,TX Pull-Up Resistor Calibration Control Register" bitfld.word 0x00 15. " CMN_TXPUCAL_CTRL_15 ,Start resistor calibration" "Not started,Started" rbitfld.word 0x00 14. " CMN_TXPUCAL_CTRL_14 ,Resistor calibration process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " CMN_TXPUCAL_CTRL_13 ,No analog calibration response" "No response,Response" rbitfld.word 0x00 12. " CMN_TXPUCAL_CTRL_12 ,Current analog comparator response" "No response,Response" textline " " hexmask.word.byte 0x00 0.--6. 1. " CMN_TXPUCAL_CTRL_6_0 ,Resistor calibration code" line.word 0x02 "CMN_TXPUCAL_OVRD,TX Pull-Up Resistor Calibration Override Register" bitfld.word 0x02 15. " CMN_TXPUCAL_OVRD_15 ,Resistor code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " CMN_TXPUCAL_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " hexmask.word.byte 0x02 0.--6. 1. " CMN_TXPUCAL_OVRD_6_0 ,Resistor code override value" line.word 0x04 "CMN_TXPUCAL_START,TX Pull-Up Resistor Calibration Start Register" bitfld.word 0x04 15. " CMN_TXPUCAL_START_15 ,Resistor calibration direction" "0,1" hexmask.word.byte 0x04 0.--6. 1. " CMN_TXPUCAL_START_6_0 ,Start resistor calibration code" line.word 0x06 "CMN_TXPUCAL_TUNE,TX Pull-Up Resistor Calibration Tune Register" hexmask.word.byte 0x06 0.--6. 1. " CMN_TXPUCAL_TUNE_6_0 ,Resistor calibration tune value" line.word 0x08 "CMN_TXPUCAL_INIT_TMR,TX Pull-Up Resistor Calibration Initialization Timer Register" bitfld.word 0x08 0.--5. " CMN_TXPUCAL_INIT_TMR_5_0 ,Initialization wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0A "CMN_TXPUCAL_ITER_TMR,TX Pull-Up Resistor Calibration Iteration Timer Register" bitfld.word 0x0A 0.--5. " CMN_TXPUCAL_ITER_TMR_5_0 ,Iteration wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x1E0++0x0B line.word 0x00 "CMN_TXPDCAL_CTRL,TX Pull-Down Resistor Calibration Control Register" bitfld.word 0x00 15. " CMN_TXPDCAL_CTRL_15 ,Start resistor calibration" "Not started,Started" rbitfld.word 0x00 14. " CMN_TXPDCAL_CTRL_14 ,Resistor calibration process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " CMN_TXPDCAL_CTRL_13 ,No analog calibration response" "No response,Response" rbitfld.word 0x00 12. " CMN_TXPDCAL_CTRL_12 ,Current analog comparator response" "No response,Response" textline " " hexmask.word.byte 0x00 0.--6. 1. " CMN_TXPDCAL_CTRL_6_0 ,Resistor calibration code" line.word 0x02 "CMN_TXPDCAL_OVRD,TX Pull-Down Resistor Calibration Override Register" bitfld.word 0x02 15. " CMN_TXPDCAL_OVRD_15 ,Resistor code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " CMN_TXPDCAL_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " hexmask.word.byte 0x02 0.--6. 1. " CMN_TXPDCAL_OVRD_6_0 ,Resistor code override value" line.word 0x04 "CMN_TXPDCAL_START,TX Pull-Down Resistor Calibration Start Register" bitfld.word 0x04 15. " CMN_TXPDCAL_START_15 ,Resistor calibration direction" "0,1" hexmask.word.byte 0x04 0.--6. 1. " CMN_TXPDCAL_START_6_0 ,Start resistor calibration code" line.word 0x06 "CMN_TXPDCAL_TUNE,TX Pull-Down Resistor Calibration Tune Register" hexmask.word.byte 0x06 0.--6. 1. " CMN_TXPDCAL_TUNE_6_0 ,Resistor calibration tune value" line.word 0x08 "CMN_TXPDCAL_INIT_TMR,TX Pull-Down Resistor Calibration Initialization Timer Register" bitfld.word 0x08 0.--5. " CMN_TXPDCAL_INIT_TMR_5_0 ,Initialization wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0A "CMN_TXPDCAL_ITER_TMR,TX Pull-Down Resistor Calibration Iteration Timer Register" bitfld.word 0x0A 0.--5. " CMN_TXPDCAL_ITER_TMR_5_0 ,Iteration wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x200++0x1F line.word 0x00 "CMN_ICAL_ADJ_CTRL,Current Calibration Adjust Control Register" bitfld.word 0x00 15. " CMN_ICAL_ADJ_CTRL_15 ,Start calibration adjust" "Not started,Started" rbitfld.word 0x00 14. " CMN_ICAL_ADJ_CTRL_14 ,Calibration adjust process done" "Not done,Done" textline " " bitfld.word 0x00 13. " CMN_ICAL_ADJ_CTRL_13 ,Calibration adjust direction" "0,1" bitfld.word 0x00 0.--5. " CMN_ICAL_ADJ_CTRL_5_0 ,Calibration adjust code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "CMN_ICAL_ADJ_CNT,Current Calibration Adjust Count Register" bitfld.word 0x02 0. " CMN_ICAL_ADJ_CNT_0 ,Calibration adjust count value" "0,1" line.word 0x04 "CMN_ICAL_ADJ_INIT_TMR,Current Calibration Adjust Initialization Timer Register" bitfld.word 0x04 0.--5. " CMN_ICAL_ADJ_INIT_TMR_5_0 ,Initialization wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x06 "CMN_ICAL_ADJ_ITER_TMR,Current Calibration Adjust Iteration Timer Register" bitfld.word 0x06 0.--5. " CMN_ICAL_ADJ_ITER_TMR_5_0 ,Iteration wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "CMN_RX_ADJ_CTRL,RX Resistor Calibration Adjust Control Register" bitfld.word 0x08 15. " CMN_RX_ADJ_CTRL_15 ,Start calibration adjust" "Not started,Started" rbitfld.word 0x08 14. " CMN_RX_ADJ_CTRL_14 ,Calibration adjust process done" "Not done,Done" textline " " bitfld.word 0x08 13. " CMN_RX_ADJ_CTRL_13 ,Calibration adjust direction" "No response,Response" rbitfld.word 0x08 0.--4. " CMN_RX_ADJ_CTRL_4_0 ,Calibration adjust code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0A "CMN_RX_ADJ_CNT,RX Resistor Calibration Adjust Count Register" bitfld.word 0x0A 0. " CMN_RX_ADJ_CNT_0 ,Calibration adjust count value" "0,1" line.word 0x0C "CMN_RX_ADJ_INIT_TMR,RX Resistor Calibration Adjust Initialization Timer Register" bitfld.word 0x0C 0.--5. " CMN_RX_ADJ_INIT_TMR_5_0 ,Initialization wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0E "CMN_RX_ADJ_ITER_TMR,RX Resistor Calibration Adjust Iteration Timer Register" bitfld.word 0x0E 0.--5. " CMN_RX_ADJ_ITER_TMR_5_0 ,Iteration wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x10 "CMN_TXPU_ADJ_CTRL,TX Pull Up Resistor Calibration Adjust Control Register" bitfld.word 0x10 15. " CMN_TXPU_ADJ_CTRL_15 ,Start calibration adjust" "Not started,Started" rbitfld.word 0x10 14. " CMN_TXPU_ADJ_CTRL_14 ,Calibration adjust process done" "Not done,Done" textline " " bitfld.word 0x10 13. " CMN_TXPU_ADJ_CTRL_13 ,Calibration adjust direction" "0,1" hexmask.word.byte 0x10 0.--6. 1. " CMN_TXPU_ADJ_CTRL_6_0 ,Calibration adjust code" line.word 0x12 "CMN_TXPU_ADJ_CNT,TX Pull Up Resistor Calibration Adjust Count Register" bitfld.word 0x12 0. " CMN_TXPU_ADJ_CNT_0 ,Calibration adjust count value" "0,1" line.word 0x14 "CMN_TXPU_ADJ_INIT_TMR,TX Pull Up Resistor Calibration Adjust Initialization Timer Register" bitfld.word 0x14 0.--5. " CMN_TXPU_ADJ_INIT_TMR_5_0 ,Initialization wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x16 "CMN_TXPU_ADJ_ITER_TMR,TX Pull Up Resistor Calibration Adjust Iteration Timer Register" bitfld.word 0x16 0.--5. " CMN_TXPU_ADJ_ITER_TMR_5_0 ,Iteration wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x18 "CMN_TXPD_ADJ_CTRL,TX Pull Down Resistor Calibration Adjust Control Register" bitfld.word 0x18 15. " CMN_TXPD_ADJ_CTRL_15 ,Start calibration adjust" "Not started,Started" rbitfld.word 0x18 14. " CMN_TXPD_ADJ_CTRL_14 ,Calibration adjust process done" "Not done,Done" textline " " bitfld.word 0x18 13. " CMN_TXPD_ADJ_CTRL_13 ,Calibration adjust direction" "0,1" hexmask.word.byte 0x18 0.--6. 1. " CMN_TXPD_ADJ_CTRL_6_0 ,Calibration adjust code" line.word 0x1A "CMN_TXPD_ADJ_CNT,TX Pull Down Resistor Calibration Adjust Count Register" bitfld.word 0x1A 0. " CMN_TXPD_ADJ_CNT_0 ,Calibration adjust count value" "0,1" line.word 0x1C "CMN_TXPD_ADJ_INIT_TMR,TX Pull Down Resistor Calibration Adjust Initialization Timer Register" bitfld.word 0x1C 0.--5. " CMN_TXPD_ADJ_INIT_TMR_5_0 ,Initialization wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x1E "CMN_TXPD_ADJ_ITER_TMR,TX Pull Down Resistor Calibration Adjust Iteration Timer Register" bitfld.word 0x1E 0.--5. " CMN_TXPD_ADJ_ITER_TMR_5_0 ,Iteration wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x340++0x05 line.word 0x00 "CMN_CMSMT_CLK_FREQ_MSMT_CTRL,Clock Frequency Measurement Control Register" bitfld.word 0x00 15. " CMN_CMSMT_CLK_FREQ_MSMT_CTRL_15 ,Run test clock measurement" "Not started,Started" rbitfld.word 0x00 14. " CMN_CMSMT_CLK_FREQ_MSMT_CTRL_14 ,Test clock measurement done" "Not done,Done" line.word 0x02 "CMN_CMSMT_TEST_CLK_SEL,Test Clock Selection Register" bitfld.word 0x02 0.--2. " CMN_CMSMT_TEST_CLK_SEL_2_0 ,Test clock select" "0,1,2,3,4,5,6,7" line.word 0x04 "CMN_CMSMT_REF_CLK_TMR_VALUE,Reference Clock Timer Value Register" hexmask.word 0x04 0.--11. 1. " CMN_CMSMT_REF_CLK_TMR_VALUE_11_0 ,Reference clock timer value" rgroup.word 0x346++0x01 line.word 0x00 "CMN_CMSMT_TEST_CLK_CNT_VALUE,Test Clock Counter Value Register" hexmask.word 0x00 0.--11. 1. " CMN_CMSMT_TEST_CLK_CNT_VALUE_11_0 ,Test clock counter value" group.word 0x380++0x15 line.word 0x00 "CMN_DIAG_PLL0_FBH_OVRD,PLL 0 Feedback Divider Value High Override Register" bitfld.word 0x00 15. " CMN_DIAG_PLL0_FBH_OVRD_15 ,PLL feedback divider high override enable" "Disabled,Enabled" hexmask.word 0x00 0.--9. 1. " CMN_DIAG_PLL0_FBH_OVRD_9_0 ,PLL feedback divider high override value" line.word 0x02 "CMN_DIAG_PLL0_FBL_OVRD,PLL 0 Feedback Divider Value Low Override Register" bitfld.word 0x02 15. " CMN_DIAG_PLL0_FBL_OVRD_15 ,PLL feedback divider low override enable" "Disabled,Enabled" hexmask.word 0x02 0.--9. 1. " CMN_DIAG_PLL0_FBL_OVRD_9_0 ,PLL feedback divider low override value" line.word 0x04 "CMN_DIAG_PLL0_OVRD,PLL 0 Override Register" bitfld.word 0x04 6. " CMN_DIAG_PLL0_OVRD_6 ,PLL lock override" "No override,Override" bitfld.word 0x04 4. " CMN_DIAG_PLL0_OVRD_4 ,PLL PCIe mode" "0,1" textline " " bitfld.word 0x04 3. " CMN_DIAG_PLL0_OVRD_3 ,PLL VCO calibration enable override enable" "Disabled,Enabled" bitfld.word 0x04 2. " CMN_DIAG_PLL0_OVRD_2 ,PLL VCO calibration enable override" "Disabled,Enabled" line.word 0x06 "CMN_DIAG_PLL0_LDO_CTRL,PLL 0 LDO Control Register" bitfld.word 0x06 4.--5. " CMN_DIAG_PLL0_LDO_CTRL_5_4 ,PLL 0 LDO output bypass selection" "0,1,2,3" bitfld.word 0x06 0.--3. " CMN_DIAG_PLL0_LDO_CTRL_3_0 ,PLL 0 LDO nominal output voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "CMN_DIAG_PLL0_TEST_MODE,PLL 0 Test Mode Register" bitfld.word 0x08 8.--9. " CMN_DIAG_PLL0_TEST_MODE_9_8 ,PLL 0 secondary loop bandwidth control" "0,1,2,3" bitfld.word 0x08 5. " CMN_DIAG_PLL0_TEST_MODE_5 ,PLL 0 VCO clock divider test mode select" "Not selected,Selected" textline " " bitfld.word 0x08 4. " CMN_DIAG_PLL0_TEST_MODE_4 ,PLL 0 secondary loop bypass" "Not bypassed,Bypassed" bitfld.word 0x08 3. " CMN_DIAG_PLL0_TEST_MODE_3 ,PLL 0 high speed ripple divider select" "Not selected,Selected" textline " " bitfld.word 0x08 2. " CMN_DIAG_PLL0_TEST_MODE_2 ,PLL 0 secondary loop amp bypass enable" "Disabled,Enabled" bitfld.word 0x08 1. " CMN_DIAG_PLL0_TEST_MODE_1 ,PLL 0 secondary loop gain control" "0,1" textline " " bitfld.word 0x08 0. " CMN_DIAG_PLL0_TEST_MODE_0 ,PLL 0 test mode charge pump current select" "0,1" line.word 0x0A "CMN_DIAG_PLL0_V2I_TUNE,PLL 0 Voltage To Current Unit Tuning Register" bitfld.word 0x0A 4.--5. " CMN_DIAG_PLL0_V2I_TUNE_5_4 ,PLL 0 voltage to current program code" "0,1,2,3" bitfld.word 0x0A 0.--2. " CMN_DIAG_PLL0_V2I_TUNE_2_0 ,PLL 0 voltage to current coarse program code" "0,1,2,3,4,5,6,7" line.word 0x0C "CMN_DIAG_PLL0_CP_TUNE,PLL 0 Charge Pump Tuning Register" hexmask.word 0x0C 0.--8. 1. " CMN_DIAG_PLL0_CP_TUNE_8_0 ,PLL 0 charge pump gain" line.word 0x0E "CMN_DIAG_PLL0_LF_PROG,PLL 0 Loop Filter Programmability Register" hexmask.word.byte 0x0E 0.--7. 1. " CMN_DIAG_PLL0_LF_PROG_7_0 ,PLL 0 loop filter programmability" line.word 0x10 "CMN_DIAG_PLL0_PTATIS_TUNE1,PLL 0 PTAT Current Slope Tuning Register 1" bitfld.word 0x10 8.--11. " CMN_DIAG_PLL0_PTATIS_TUNE1_11_8 ,PLL 0 NDAC control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word.byte 0x10 0.--7. 1. " CMN_DIAG_PLL0_PTATIS_TUNE1_7_0 ,PLL 0 PMOS control" line.word 0x12 "CMN_DIAG_PLL0_PTATIS_TUNE2,PLL 0 PTAT Current Slope Tuning Register 2" bitfld.word 0x12 0.--5. " CMN_DIAG_PLL0_PTATIS_TUNE2_5_0 ,PLL 0 PTAT NDAC control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x14 "CMN_DIAG_PLL0_INCLK_CTRL,PLL 0 Input Clock Control Register" bitfld.word 0x14 8.--9. " CMN_DIAG_PLL0_INCLK_CTRL_9_8 ,PLL 0 low speed output clock divider control" "0,1,2,3" hexmask.word.byte 0x14 0.--7. 1. " CMN_DIAG_PLL0_INCLK_CTRL_7_0 ,PLL 0 input clock divider control" group.word 0x3A0++0x15 line.word 0x00 "CMN_DIAG_PLL1_FBH_OVRD,PLL 1 Feedback Divider Value High Override Register" bitfld.word 0x00 15. " CMN_DIAG_PLL1_FBH_OVRD_15 ,PLL feedback divider high override enable" "Disabled,Enabled" hexmask.word 0x00 0.--9. 1. " CMN_DIAG_PLL1_FBH_OVRD_9_0 ,PLL feedback divider high override value" line.word 0x02 "CMN_DIAG_PLL1_FBL_OVRD,PLL 1 Feedback Divider Value Low Override Register" bitfld.word 0x02 15. " CMN_DIAG_PLL1_FBL_OVRD_15 ,PLL feedback divider low override enable" "Disabled,Enabled" hexmask.word 0x02 0.--9. 1. " CMN_DIAG_PLL1_FBL_OVRD_9_0 ,PLL feedback divider low override value" line.word 0x04 "CMN_DIAG_PLL1_OVRD,PLL 1 Override Register" bitfld.word 0x04 6. " CMN_DIAG_PLL1_OVRD_6 ,PLL lock override" "No override,Override" bitfld.word 0x04 4. " CMN_DIAG_PLL1_OVRD_4 ,PLL PCIe mode" "0,1" textline " " bitfld.word 0x04 3. " CMN_DIAG_PLL1_OVRD_3 ,PLL VCO calibration enable override enable" "Disabled,Enabled" bitfld.word 0x04 2. " CMN_DIAG_PLL1_OVRD_2 ,PLL VCO calibration enable override" "Disabled,Enabled" line.word 0x06 "CMN_DIAG_PLL0_LD1_CTRL,PLL 1 LDO Control Register" bitfld.word 0x06 4.--5. " CMN_DIAG_PLL0_LD1_CTRL_5_4 ,PLL 1 LDO output bypass selection" "0,1,2,3" bitfld.word 0x06 0.--3. " CMN_DIAG_PLL0_LD1_CTRL_3_0 ,PLL 1 LDO nominal output voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "CMN_DIAG_PLL1_TEST_MODE,PLL 1 Test Mode Register" bitfld.word 0x08 8.--9. " CMN_DIAG_PLL1_TEST_MODE_9_8 ,PLL 1 secondary loop bandwidth control" "0,1,2,3" bitfld.word 0x08 5. " CMN_DIAG_PLL1_TEST_MODE_5 ,PLL 1 VCO clock divider test mode select" "Not selected,Selected" textline " " bitfld.word 0x08 4. " CMN_DIAG_PLL1_TEST_MODE_4 ,PLL 1 secondary loop bypass" "Not bypassed,Bypassed" bitfld.word 0x08 3. " CMN_DIAG_PLL1_TEST_MODE_3 ,PLL 1 high speed ripple divider select" "Not selected,Selected" textline " " bitfld.word 0x08 2. " CMN_DIAG_PLL1_TEST_MODE_2 ,PLL 1 secondary loop amp bypass enable" "Disabled,Enabled" bitfld.word 0x08 1. " CMN_DIAG_PLL1_TEST_MODE_1 ,PLL 1 secondary loop gain control" "0,1" textline " " bitfld.word 0x08 0. " CMN_DIAG_PLL1_TEST_MODE_0 ,PLL 1 test mode charge pump current select" "0,1" line.word 0x0A "CMN_DIAG_PLL1_V2I_TUNE,PLL 1 Voltage To Current Unit Tuning Register" bitfld.word 0x0A 4.--5. " CMN_DIAG_PLL1_V2I_TUNE_5_4 ,PLL 1 voltage to current program code" "0,1,2,3" bitfld.word 0x0A 0.--2. " CMN_DIAG_PLL1_V2I_TUNE_2_0 ,PLL 1 voltage to current coarse program code" "0,1,2,3,4,5,6,7" line.word 0x0C "CMN_DIAG_PLL1_CP_TUNE,PLL 1 Charge Pump Tuning Register" hexmask.word 0x0C 0.--8. 1. " CMN_DIAG_PLL1_CP_TUNE_8_0 ,PLL 1 charge pump gain" line.word 0x0E "CMN_DIAG_PLL1_LF_PROG,PLL 1 Loop Filter Programmability Register" hexmask.word.byte 0x0E 0.--7. 1. " CMN_DIAG_PLL1_LF_PROG_7_0 ,PLL 1 loop filter programmability" line.word 0x10 "CMN_DIAG_PLL1_PTATIS_TUNE1,PLL 1 PTAT Current Slope Tuning Register 1" bitfld.word 0x10 8.--11. " CMN_DIAG_PLL1_PTATIS_TUNE1_11_8 ,PLL 1 NDAC control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word.byte 0x10 0.--7. 1. " CMN_DIAG_PLL1_PTATIS_TUNE1_7_0 ,PLL 1 PMOS control" line.word 0x12 "CMN_DIAG_PLL1_PTATIS_TUNE2,PLL 1 PTAT Current Slope Tuning Register 2" bitfld.word 0x12 0.--5. " CMN_DIAG_PLL1_PTATIS_TUNE2_5_0 ,PLL 1 PTAT NDAC control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x14 "CMN_DIAG_PLL1_INCLK_CTRL,PLL 1 Input Clock Control Register" bitfld.word 0x14 8.--9. " CMN_DIAG_PLL1_INCLK_CTRL_9_8 ,PLL 1 low speed output clock divider control" "0,1,2,3" hexmask.word.byte 0x14 0.--7. 1. " CMN_DIAG_PLL1_INCLK_CTRL_7_0 ,PLL 1 input clock divider control" group.word 0x3C0++0x05 line.word 0x00 "CMN_DIAG_HSCLK_SEL,Common High Speed Clock Select Register" bitfld.word 0x00 4.--5. " CMN_DIAG_HSCLK_SEL_5_4 ,High speed clock 1 select" "0,1,2,3" bitfld.word 0x00 0.--1. " CMN_DIAG_HSCLK_SEL_5_4 ,High speed clock 0 select" "0,1,2,3" line.word 0x02 "CMN_DIAG_CALCLK_CTRL,Common Calibration Clock Control Register" bitfld.word 0x02 0.--2. " CMN_DIAG_CALCLK_CTRL_2_0 ,Calibration clock divider select" "0,1,2,3,4,5,6,7" line.word 0x04 "CMN_DIAG_HSRRSM_CTRL,Common High Speed Reset Release State Machine Control Register" bitfld.word 0x04 0.--2. " CMN_DIAG_HSRRSM_CTRL_2_0 ,Transmitter reset delay" "0,1,2,3,4,5,6,7" rgroup.word 0x3C6++0x01 line.word 0x00 "CMN_DIAG_RST_DIAG,Common Functions Reset Diagnostic Register" bitfld.word 0x00 12. " CMN_DIAG_RST_DIAG_12 ,Current state of the ssmac_power_reset_n reset" "No reset,Reset" bitfld.word 0x00 9. " CMN_DIAG_RST_DIAG_9 ,Current state of the cmn_pll1_dsm_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 8. " CMN_DIAG_RST_DIAG_8 ,Current state of the cmn_pll0_dsm_reset_n reset" "No reset,Reset" bitfld.word 0x00 7. " CMN_DIAG_RST_DIAG_7 ,Current state of the cmn_pll1_vco_cal_fbdiv_clk_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 6. " CMN_DIAG_RST_DIAG_6 ,Current state of the cmn_pll1_lock_det_fbdiv_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 5. " CMN_DIAG_RST_DIAG_5 ,Current state of the cmn_pll1_vco_cal_ref_clk_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 4. " CMN_DIAG_RST_DIAG_4 ,Current state of the cmn_pll1_lock_det_ref_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 3. " CMN_DIAG_RST_DIAG_4 ,Current state of the cmn_pll0_vco_cal_fbdiv_clk_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 2. " CMN_DIAG_RST_DIAG_2 ,Current state of the cmn_pll0_lock_det_fbdiv_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 1. " CMN_DIAG_RST_DIAG_1 ,Current state of the cmn_pll0_vco_cal_ref_clk_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 0. " CMN_DIAG_RST_DIAG_0 ,Current state of the cmn_pll0_lock_det_ref_clk_reset_n reset" "No reset,Reset" group.word 0x3D0++0x03 line.word 0x00 "CMN_DIAG_BANDGAP_OVRD,Bandgap Override Register" bitfld.word 0x00 3. " CMN_DIAG_BANDGAP_OVRD_3 ,Bandgap reference current increase" "Not increased,Increased" bitfld.word 0x00 2. " CMN_DIAG_BANDGAP_OVRD_2 ,Bandgap reference current decrease" "Not decreased,Decreased" textline " " bitfld.word 0x00 1. " CMN_DIAG_BANDGAP_OVRD_1 ,Bandgap startup force on" "Disabled,Enabled" bitfld.word 0x00 0. " CMN_DIAG_BANDGAP_OVRD_0 ,Bandgap startup force off" "No,Yes" line.word 0x02 "CMN_DIAG_BIAS_OVRD,Bias Override Register" bitfld.word 0x02 4.--6. " CMN_DIAG_BIAS_OVRD_6_4 ,Receiver resistor calibration current adjust" "0,1,2,3,4,5,6,7" bitfld.word 0x02 0.--2. " CMN_DIAG_BIAS_OVRD_2_0 ,Transmitter resistor calibration current adjust" "0,1,2,3,4,5,6,7" group.word 0x3D8++0x03 line.word 0x00 "CMN_DIAG_PER_CAL_ADJ,Common Periodic Calibration Adjust Control Register" bitfld.word 0x00 15. " CMN_DIAG_PER_CAL_ADJ_15 ,Calibration latch enable override enable" "Disabled,Enabled" bitfld.word 0x00 14. " CMN_DIAG_PER_CAL_ADJ_14 ,Calibration latch enable override" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CMN_DIAG_PER_CAL_ADJ_12 ,Transmitter termination pull up calibration adjust enable" "Disabled,Enabled" bitfld.word 0x00 11. " CMN_DIAG_PER_CAL_ADJ_11 ,Transmitter termination pull down calibration adjust enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " CMN_DIAG_PER_CAL_ADJ_10 ,Receiver termination calibration adjust enable" "Disabled,Enabled" bitfld.word 0x00 9. " CMN_DIAG_PER_CAL_ADJ_9 ,Current calibration adjust enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " CMN_DIAG_PER_CAL_ADJ_8 ,Periodic calibration adjust enable" "Disabled,Enabled" hexmask.word.byte 0x00 0.--7. 1. " CMN_DIAG_PER_CAL_ADJ_7_0 ,Periodic calibration timer value" line.word 0x02 "CMN_DIAG_CAL_CTRL,Common Calibration Control Register" bitfld.word 0x02 0. " CMN_DIAG_CAL_CTRL_0 ,Resistor calibration low swing select" "Not selected,Selected" group.word 0x3E0++0x03 line.word 0x00 "CMN_DIAG_ATB_CTRL1,ATB Control Register 1" bitfld.word 0x00 1. " CMN_DIAG_ATB_CTRL1_1 ,ATB source select" "0,1" bitfld.word 0x00 0. " CMN_DIAG_ATB_CTRL1_0 ,ATB enable" "Disabled,Enabled" line.word 0x02 "CMN_DIAG_ATB_CTRL2,ATB Control Register 2" bitfld.word 0x02 11.--12. " CMN_DIAG_ATB_CTRL2_12_11 ,ATB component type select" "0,1,2,3" hexmask.word.byte 0x02 6.--10. 0x40 " CMN_DIAG_ATB_CTRL2_10_6 ,ATB component sub address" textline " " hexmask.word.byte 0x02 0.--5. 0x01 " CMN_DIAG_ATB_CTRL2_5_0 ,ATB test point address" group.word 0x3E8++0x09 line.word 0x00 "CMN_DIAG_BGI_PTAT_CTRL,Common Bandgap PTAT current Control Register" bitfld.word 0x00 15. " CMN_DIAG_BGI_PTAT_CTRL_15 ,Bandgap PTAT current base unit enable" "Disabled,Enabled" bitfld.word 0x00 2.--3. " CMN_DIAG_BGI_PTAT_CTRL_3_2 ,Current programmability on the bandgap PTAT current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x00 0.--1. " CMN_DIAG_BGI_PTAT_CTRL_1_0 ,Current programmability on the bandgap PTAT current supplying block xxx" "0,1,2,3" line.word 0x02 "CMN_DIAG_BGI_CTRL1,Common Bandgap Current Control Register 1" bitfld.word 0x02 14.--15. " CMN_DIAG_BGI_CTRL1_15_14 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" bitfld.word 0x02 12.--13. " CMN_DIAG_BGI_CTRL1_13_12 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 10.--11. " CMN_DIAG_BGI_CTRL1_11_10 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" bitfld.word 0x02 8.--9. " CMN_DIAG_BGI_CTRL1_9_8 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 6.--7. " CMN_DIAG_BGI_CTRL1_7_6 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" bitfld.word 0x02 4.--5. " CMN_DIAG_BGI_CTRL1_5_4 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 2.--3. " CMN_DIAG_BGI_CTRL1_3_2 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" bitfld.word 0x02 0.--1. " CMN_DIAG_BGI_CTRL1_1_0 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" line.word 0x04 "CMN_DIAG_BGI_CTRL2,Common Bandgap Current Control Register 2" bitfld.word 0x04 15. " CMN_DIAG_BGI_CTRL2_15 ,Bandgap normal current base unit enable" "Disabled,Enabled" bitfld.word 0x04 10.--11. " CMN_DIAG_BGI_CTRL2_11_10 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 8.--9. " CMN_DIAG_BGI_CTRL2_9_8 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" bitfld.word 0x04 6.--7. " CMN_DIAG_BGI_CTRL2_7_6 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 4.--5. " CMN_DIAG_BGI_CTRL2_5_4 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" bitfld.word 0x04 2.--3. " CMN_DIAG_BGI_CTRL2_3_2 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 0.--1. " CMN_DIAG_BGI_CTRL2_1_0 ,Current programmability on the bandgap normal current supplying block xxx" "0,1,2,3" line.word 0x06 "CMN_DIAG_CTRLI_CTRL1,Common Control Current Control Register 1" bitfld.word 0x06 14.--15. " CMN_DIAG_CTRLI_CTRL1_15_14 ,Current programmability on the constant current from the calibration block supplying block xxx" "0,1,2,3" bitfld.word 0x06 12.--13. " CMN_DIAG_CTRLI_CTRL1_13_12 ,Current programmability on the constant current from the calibration block supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 10.--11. " CMN_DIAG_CTRLI_CTRL1_11_10 ,Current programmability on the constant current from the calibration block supplying block xxx" "0,1,2,3" bitfld.word 0x06 8.--9. " CMN_DIAG_CTRLI_CTRL1_9_8 ,Current programmability on the constant current from the calibration block supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 6.--7. " CMN_DIAG_CTRLI_CTRL1_7_6 ,Current programmability on the constant current from the calibration block supplying block xxx" "0,1,2,3" bitfld.word 0x06 4.--5. " CMN_DIAG_CTRLI_CTRL1_5_4 ,Current programmability on the constant current from the calibration block supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 2.--3. " CMN_DIAG_CTRLI_CTRL1_3_2 ,Current programmability on the constant current from the calibration block supplying block xxx" "0,1,2,3" bitfld.word 0x06 0.--1. " CMN_DIAG_CTRLI_CTRL1_1_0 ,Current programmability on the constant current from the calibration block supplying block xxx" "0,1,2,3" line.word 0x08 "CMN_DIAG_CTRLI_CTRL2,Common Control Current Control Register 2" bitfld.word 0x08 15. " CMN_DIAG_CTRLI_CTRL2_15 ,Constant current base unit enable" "Disabled,Enabled" bitfld.word 0x08 4.--5. " CMN_DIAG_CTRLI_CTRL2_5_4 ,Current programmability on the constant current from the calibration block supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x08 2.--3. " CMN_DIAG_CTRLI_CTRL2_3_2 ,Current programmability on the constant current from the calibration block supplying block xxx" "0,1,2,3" bitfld.word 0x08 0.--1. " CMN_DIAG_CTRLI_CTRL2_1_0 ,Current programmability on the constant current from the calibration block supplying block xxx" "0,1,2,3" textline " " group.word 0x4000++0x21 line.word 0x00 "LANE0_XCVR_PSM_CTRL,Power State Machine Control Register Lane 0" bitfld.word 0x00 14. " XCVR_PSM_CTRL_14 ,Bypass A0 in delay from PSM ready" "Not bypassed,Bypassed" bitfld.word 0x00 13. " XCVR_PSM_CTRL_13 ,Bypass A0 in delay from A5" "Not bypassed,Bypassed" textline " " bitfld.word 0x00 12. " XCVR_PSM_CTRL_12 ,Bypass A0 in delay from A4" "Not bypassed,Bypassed" bitfld.word 0x00 11. " XCVR_PSM_CTRL_11 ,Bypass A0 in delay from A3" "Not bypassed,Bypassed" textline " " bitfld.word 0x00 10. " XCVR_PSM_CTRL_10 ,Bypass A0 in delay from A2" "Not bypassed,Bypassed" bitfld.word 0x00 9. " XCVR_PSM_CTRL_9 ,Bypass A0 in delay from A1" "Not bypassed,Bypassed" textline " " bitfld.word 0x00 0. " XCVR_PSM_CTRL_0 ,Skip lane re-calibration" "Not skipped,Skipped" line.word 0x02 "LANE0_XCVR_PSM_RCTRL,Power State Machine Reset Control Register Lane 0" bitfld.word 0x02 15. " XCVR_PSM_RCTRL_15 ,RX reset active ready" "No reset,Reset" bitfld.word 0x02 14. " XCVR_PSM_RCTRL_14 ,RX reset active calibration" "No reset,Reset" textline " " bitfld.word 0x02 13. " XCVR_PSM_RCTRL_13 ,RX reset active A5" "No reset,Reset" bitfld.word 0x02 12. " XCVR_PSM_RCTRL_12 ,RX reset active A4" "No reset,Reset" textline " " bitfld.word 0x02 11. " XCVR_PSM_RCTRL_11 ,RX reset active A3" "No reset,Reset" bitfld.word 0x02 10. " XCVR_PSM_RCTRL_10 ,RX reset active A2" "No reset,Reset" textline " " bitfld.word 0x02 9. " XCVR_PSM_RCTRL_9 ,RX reset active A1" "No reset,Reset" bitfld.word 0x02 8. " XCVR_PSM_RCTRL_8 ,RX reset active A0" "No reset,Reset" textline " " bitfld.word 0x02 7. " XCVR_PSM_RCTRL_7 ,TX reset active ready" "No reset,Reset" bitfld.word 0x02 6. " XCVR_PSM_RCTRL_6 ,TX reset active calibration" "No reset,Reset" textline " " bitfld.word 0x02 5. " XCVR_PSM_RCTRL_5 ,TX reset active A5" "No reset,Reset" bitfld.word 0x02 4. " XCVR_PSM_RCTRL_4 ,TX reset active A4" "No reset,Reset" textline " " bitfld.word 0x02 3. " XCVR_PSM_RCTRL_3 ,TX reset active A3" "No reset,Reset" bitfld.word 0x02 2. " XCVR_PSM_RCTRL_2 ,TX reset active A2" "No reset,Reset" textline " " bitfld.word 0x02 1. " XCVR_PSM_RCTRL_1 ,TX reset active A1" "No reset,Reset" bitfld.word 0x02 0. " XCVR_PSM_RCTRL_0 ,TX reset active A0" "No reset,Reset" line.word 0x04 "LANE0_XCVR_PSM_CAL_TMR,PSM Calibration Delay Timer Register Lane 0" hexmask.word 0x04 0.--9. 1. " XCVR_PSM_CAL_TMR_9_0 ,PSM calibration delay state timer value" line.word 0x06 "LANE0_XCVR_PSM_A0IN_TMR,A0 In Delay Timer Register Lane 0" hexmask.word 0x06 0.--9. 1. " XCVR_PSM_A0IN_TMR_9_0 ,A0 in delay state timer value" line.word 0x08 "LANE0_XCVR_PSM_A0BYP_TMR,A0 In Bypass Timer Register Lane 0" bitfld.word 0x08 0.--4. " XCVR_PSM_A0BYP_TMR_4_0 ,A0 in delay state bypass timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0A "LANE0_XCVR_PSM_A1IN_TMR,A1 In Delay Timer Register Lane 0" bitfld.word 0x0A 0.--4. " XCVR_PSM_A1IN_TMR_4_0 ,A1 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "LANE0_XCVR_PSM_A2IN_TMR,A2 In Delay Timer Register Lane 0" bitfld.word 0x0C 0.--4. " XCVR_PSM_A2IN_TMR_4_0 ,A2 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0E "LANE0_XCVR_PSM_A3IN_TMR,A3 In Delay Timer Register Lane 0" bitfld.word 0x0E 0.--4. " XCVR_PSM_A3IN_TMR_4_0 ,A3 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "LANE0_XCVR_PSM_A4IN_TMR,A4 In Delay Timer Register Lane 0" bitfld.word 0x10 0.--4. " XCVR_PSM_A4IN_TMR_4_0 ,A4 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x12 "LANE0_XCVR_PSM_A5IN_TMR,A5 In Delay Timer Register Lane 0" bitfld.word 0x12 0.--4. " XCVR_PSM_A5IN_TMR_4_0 ,A5 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "LANE0_XCVR_PSM_A0OUT_TMR,A0 Out Delay Timer Register Lane 0" bitfld.word 0x14 0.--4. " XCVR_PSM_A0OUT_TMR_4_0 ,A0 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x16 "LANE0_XCVR_PSM_A1OUT_TMR,A1 Out Delay Timer Register Lane 0" bitfld.word 0x16 0.--4. " XCVR_PSM_A1OUT_TMR_4_0 ,A1 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x18 "LANE0_XCVR_PSM_A2OUT_TMR,A2 Out Delay Timer Register Lane 0" bitfld.word 0x18 0.--4. " XCVR_PSM_A2OUT_TMR_4_0 ,A2 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x1A "LANE0_XCVR_PSM_A3OUT_TMR,A3 Out Delay Timer Register Lane 0" bitfld.word 0x1A 0.--4. " XCVR_PSM_A3OUT_TMR_4_0 ,A3 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x1C "LANE0_XCVR_PSM_A4OUT_TMR,A4 Out Delay Timer Register Lane 0" bitfld.word 0x1C 0.--4. " XCVR_PSM_A4OUT_TMR_4_0 ,A4 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x1E "LANE0_XCVR_PSM_A5OUT_TMR,A5 Out Delay Timer Register Lane 0" bitfld.word 0x1E 0.--4. " XCVR_PSM_A5OUT_TMR_4_0 ,A5 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x20 "LANE0_XCVR_PSM_DIAG,Power State Machine Diagnostic Register Lane 0" bitfld.word 0x20 13. " XCVR_PSM_DIAG_13 ,Force A5 exit acknowledge" "Not forced,Forced" bitfld.word 0x20 12. " XCVR_PSM_DIAG_12 ,Force A4 exit acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 11. " XCVR_PSM_DIAG_11 ,Force A3 exit acknowledge" "Not forced,Forced" bitfld.word 0x20 10. " XCVR_PSM_DIAG_10 ,Force A2 exit acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 9. " XCVR_PSM_DIAG_9 ,Force A1 exit acknowledge" "Not forced,Forced" bitfld.word 0x20 8. " XCVR_PSM_DIAG_8 ,Force A0 exit acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 5. " XCVR_PSM_DIAG_5 ,Force A5 entry acknowledge" "Not forced,Forced" bitfld.word 0x20 4. " XCVR_PSM_DIAG_4 ,Force A4 entry acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 3. " XCVR_PSM_DIAG_3 ,Force A3 entry acknowledge" "Not forced,Forced" bitfld.word 0x20 2. " XCVR_PSM_DIAG_2 ,Force A2 entry acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 1. " XCVR_PSM_DIAG_1 ,Force A1 entry acknowledge" "Not forced,Forced" bitfld.word 0x20 0. " XCVR_PSM_DIAG_0 ,Force A0 entry acknowledge" "Not forced,Forced" group.word (0x4000+0x3E)++0x01 line.word 0x00 "LANE0_XCVR_PSM_USER_DEF_CTRL,Power State Machine User Defined Control Register Lane 0" bitfld.word 0x00 1. " XCVR_PSM_USER_DEF_CTRL_1 ,Disable PSM clock gating" "No,Yes" bitfld.word 0x00 0. " XCVR_PSM_USER_DEF_CTRL_0 ,Disable early A0 acknowledge response" "No,Yes" group.word (0x4000+0x82)++0x05 line.word 0x00 "LANE0_TX_TXCC_PRE_OVRD,TX Pre-Cursor Override Register Lane 0" bitfld.word 0x00 8. " TX_TXCC_PRE_OVRD_8 ,Pre-cursor override enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " TX_TXCC_PRE_OVRD_5_0 ,Pre-cursor override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE0_TX_TXCC_MAIN_OVRD,TX Main-Cursor Override Register Lane 0" bitfld.word 0x02 8. " TX_TXCC_MAIN_OVRD_8 ,Main-cursor override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " TX_TXCC_MAIN_OVRD_5_0 ,Main-cursor override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE0_TX_TXCC_POST_OVRD,TX Post-Cursor Override Register Lane 0" bitfld.word 0x04 8. " TX_TXCC_POST_OVRD_8 ,Post-cursor override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " TX_TXCC_POST_OVRD_5_0 ,Post-cursor override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.word (0x4000+0x88)++0x05 line.word 0x00 "LANE0_TX_TXCC_PRE_CVAL,TX Pre-Cursor Current Value Register 0" bitfld.word 0x00 0.--5. " TX_TXCC_PRE_CVAL_5_0 ,Pre-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE0_TX_TXCC_MAIN_CVAL,TX Main-Cursor Current Value Register 0" bitfld.word 0x02 0.--5. " TX_TXCC_MAIN_CVAL_5_0 ,Main-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE0_TX_TXCC_POST_CVAL,TX Post-Cursor Current Value Register 0" bitfld.word 0x04 0.--5. " TX_TXCC_POST_CVAL_5_0 ,Post-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x4000+0x8E)++0x31 line.word 0x00 "LANE0_TX_TXCC_CAL_SCLR_MULT,Resistor Calibration Code Scaler Multiplier Value Register Lane 0" bitfld.word 0x00 8. " TX_TXCC_CAL_SCLR_MULT_8 ,Scaled resistor calibration code add" "0,1" hexmask.word.byte 0x00 0.--7. 1. " TX_TXCC_CAL_SCLR_MULT_7_0 ,Resistor calibration multiplier value" line.word 0x02 "LANE0_TX_TXCC_CPRE_MULT_00,Calculated Pre Emphasis Multiplier Value 00 Register Lane 0" hexmask.word.byte 0x02 0.--7. 1. " TX_TXCC_CPRE_MULT_00_7_0 ,Calculated pre emphasis multiplier value 00" line.word 0x04 "LANE0_TX_TXCC_CPRE_MULT_01,Calculated Pre Emphasis Multiplier Value 01 Register Lane 0" hexmask.word.byte 0x04 0.--7. 1. " TX_TXCC_CPRE_MULT_01_7_0 ,Calculated pre emphasis multiplier value 01" line.word 0x06 "LANE0_TX_TXCC_CPRE_MULT_10,Calculated Pre Emphasis Multiplier Value 10 Register Lane 0" hexmask.word.byte 0x06 0.--7. 1. " TX_TXCC_CPRE_MULT_10_7_0 ,Calculated pre emphasis multiplier value 10" line.word 0x08 "LANE0_TX_TXCC_CPRE_MULT_11,Calculated Pre Emphasis Multiplier Value 11 Register Lane 0" hexmask.word.byte 0x08 0.--7. 1. " TX_TXCC_CPRE_MULT_11_7_0 ,Calculated pre emphasis multiplier value 11" line.word 0x0A "LANE0_TX_TXCC_CPOST_MULT_00,Calculated Post Emphasis Multiplier Value 00 Register Lane 0" hexmask.word.byte 0x0A 0.--7. 1. " TX_TXCC_CPOST_MULT_00_7_0 ,Calculated post emphasis multiplier value 00" line.word 0x0C "LANE0_TX_TXCC_CPOST_MULT_01,Calculated Post Emphasis Multiplier Value 01 Register Lane 0" hexmask.word.byte 0x0C 0.--7. 1. " TX_TXCC_CPOST_MULT_01_7_0 ,Calculated post emphasis multiplier value 01" line.word 0x0E "LANE0_TX_TXCC_CPOST_MULT_10,Calculated Post Emphasis Multiplier Value 10 Register Lane 0" hexmask.word.byte 0x0E 0.--7. 1. " TX_TXCC_CPOST_MULT_10_7_0 ,Calculated post emphasis multiplier value 10" line.word 0x10 "LANE0_TX_TXCC_CPOST_MULT_11,Calculated Post Emphasis Multiplier Value 11 Register Lane 0" hexmask.word.byte 0x10 0.--7. 1. " TX_TXCC_CPOST_MULT_11_7_0 ,Calculated post emphasis multiplier value 11" line.word 0x12 "LANE0_TX_TXCC_MGNFS_MULT_000,Margin Full Swing Multiplier Value 000 Register Lane 0" hexmask.word.byte 0x12 0.--7. 1. " TX_TXCC_MGNFS_MULT_000_7_0 ,Margin full swing multiplier value 000" line.word 0x14 "LANE0_TX_TXCC_MGNFS_MULT_001,Margin Full Swing Multiplier Value 001 Register Lane 0" hexmask.word.byte 0x14 0.--7. 1. " TX_TXCC_MGNFS_MULT_001_7_0 ,Margin full swing multiplier value 001" line.word 0x16 "LANE0_TX_TXCC_MGNFS_MULT_010,Margin Full Swing Multiplier Value 010 Register Lane 0" hexmask.word.byte 0x16 0.--7. 1. " TX_TXCC_MGNFS_MULT_010_7_0 ,Margin full swing multiplier value 010" line.word 0x18 "LANE0_TX_TXCC_MGNFS_MULT_011,Margin Full Swing Multiplier Value 011 Register Lane 0" hexmask.word.byte 0x18 0.--7. 1. " TX_TXCC_MGNFS_MULT_011_7_0 ,Margin full swing multiplier value 011" line.word 0x1A "LANE0_TX_TXCC_MGNFS_MULT_100,Margin Full Swing Multiplier Value 100 Register Lane 0" hexmask.word.byte 0x1A 0.--7. 1. " TX_TXCC_MGNFS_MULT_100_7_0 ,Margin full swing multiplier value 100" line.word 0x1C "LANE0_TX_TXCC_MGNFS_MULT_101,Margin Full Swing Multiplier Value 101 Register Lane 0" hexmask.word.byte 0x1C 0.--7. 1. " TX_TXCC_MGNFS_MULT_101_7_0 ,Margin full swing multiplier value 101" line.word 0x1E "LANE0_TX_TXCC_MGNFS_MULT_110,Margin Full Swing Multiplier Value 110 Register Lane 0" hexmask.word.byte 0x1E 0.--7. 1. " TX_TXCC_MGNFS_MULT_110_7_0 ,Margin full swing multiplier value 110" line.word 0x20 "LANE0_TX_TXCC_MGNFS_MULT_111,Margin Full Swing Multiplier Value 111 Register Lane 0" hexmask.word.byte 0x20 0.--7. 1. " TX_TXCC_MGNFS_MULT_111_7_0 ,Margin full swing multiplier value 111" line.word 0x22 "LANE0_TX_TXCC_MGNLS_MULT_000,Margin Half Swing Multiplier Value 000 Register Lane 0" hexmask.word.byte 0x22 0.--7. 1. " TX_TXCC_MGNLS_MULT_000_7_0 ,Margin half swing multiplier value 000" line.word 0x24 "LANE0_TX_TXCC_MGNLS_MULT_001,Margin Half Swing Multiplier Value 001 Register Lane 0" hexmask.word.byte 0x24 0.--7. 1. " TX_TXCC_MGNLS_MULT_001_7_0 ,Margin half swing multiplier value 001" line.word 0x26 "LANE0_TX_TXCC_MGNLS_MULT_010,Margin Half Swing Multiplier Value 010 Register Lane 0" hexmask.word.byte 0x26 0.--7. 1. " TX_TXCC_MGNLS_MULT_010_7_0 ,Margin half swing multiplier value 010" line.word 0x28 "LANE0_TX_TXCC_MGNLS_MULT_011,Margin Half Swing Multiplier Value 011 Register Lane 0" hexmask.word.byte 0x28 0.--7. 1. " TX_TXCC_MGNLS_MULT_011_7_0 ,Margin half swing multiplier value 011" line.word 0x2A "LANE0_TX_TXCC_MGNLS_MULT_100,Margin Half Swing Multiplier Value 100 Register Lane 0" hexmask.word.byte 0x2A 0.--7. 1. " TX_TXCC_MGNLS_MULT_100_7_0 ,Margin half swing multiplier value 100" line.word 0x2C "LANE0_TX_TXCC_MGNLS_MULT_101,Margin Half Swing Multiplier Value 101 Register Lane 0" hexmask.word.byte 0x2C 0.--7. 1. " TX_TXCC_MGNLS_MULT_101_7_0 ,Margin half swing multiplier value 101" line.word 0x2E "LANE0_TX_TXCC_MGNLS_MULT_110,Margin Half Swing Multiplier Value 110 Register Lane 0" hexmask.word.byte 0x2E 0.--7. 1. " TX_TXCC_MGNLS_MULT_110_7_0 ,Margin half swing multiplier value 110" line.word 0x30 "LANE0_TX_TXCC_MGNLS_MULT_111,Margin Half Swing Multiplier Value 111 Register Lane 0" hexmask.word.byte 0x30 0.--7. 1. " TX_TXCC_MGNLS_MULT_111_7_0 ,Margin half swing multiplier value 111" group.word (0x4000+0x1C0)++0x07 line.word 0x00 "LANE0_XCVR_DIAG_PLLDRC_CTRL,Transceiver PLL Data Rate Clock Control Register Lane 0" bitfld.word 0x00 14. " XCVR_DIAG_PLLDRC_CTRL_14 ,Digital PLL clock select standard mode 3" "Not selected,Selected" bitfld.word 0x00 12.--13. " XCVR_DIAG_PLLDRC_CTRL_13_12 ,Digital PLL data rate divider standard mode 3 value" "0,1,2,3" textline " " bitfld.word 0x00 10. " XCVR_DIAG_PLLDRC_CTRL_10 ,Digital PLL clock select standard mode 2" "Not selected,Selected" bitfld.word 0x00 8.--9. " XCVR_DIAG_PLLDRC_CTRL_9_8 ,Digital PLL data rate divider standard mode 2 value" "0,1,2,3" textline " " bitfld.word 0x00 6. " XCVR_DIAG_PLLDRC_CTRL_6 ,Digital PLL clock select standard mode 1" "Not selected,Selected" bitfld.word 0x00 4.--5. " XCVR_DIAG_PLLDRC_CTRL_5_4 ,Digital PLL data rate divider standard mode 1 value" "0,1,2,3" textline " " bitfld.word 0x00 2. " XCVR_DIAG_PLLDRC_CTRL_2 ,Digital PLL clock select standard mode 0" "Not selected,Selected" bitfld.word 0x00 0.--1. " XCVR_DIAG_PLLDRC_CTRL_0_1 ,Digital PLL data rate divider standard mode 0 value" "0,1,2,3" line.word 0x02 "LANE0_XCVR_DIAG_HSCLK_SEL,Transceiver High Speed Clock Select Register Lane 0" bitfld.word 0x02 12.--13. " XCVR_DIAG_HSCLK_SEL_13_12 ,High speed clock select standard mode 3" "0,1,2,3" bitfld.word 0x02 8.--9. " XCVR_DIAG_HSCLK_SEL_9_8 ,High speed clock select standard mode 2" "0,1,2,3" textline " " bitfld.word 0x02 4.--5. " XCVR_DIAG_HSCLK_SEL_5_4 ,High speed clock select standard mode 1" "0,1,2,3" bitfld.word 0x02 0.--1. " XCVR_DIAG_HSCLK_SEL_5_4 ,High speed clock select standard mode 0" "0,1,2,3" line.word 0x04 "LANE0_XCVR_DIAG_HSCLKA_DCTRL,Transceiver High Speed Clock A Divider Control Register Lane 0" bitfld.word 0x04 12.--13. " XCVR_DIAG_HSCLKA_DCTRL_13_12 ,Transceiver clock A (transmitter) divider control standard mode 3" "0,1,2,3" bitfld.word 0x04 8.--9. " XCVR_DIAG_HSCLKA_DCTRL_9_8 ,Transceiver clock A (transmitter) divider control standard mode 2" "0,1,2,3" textline " " bitfld.word 0x04 4.--5. " XCVR_DIAG_HSCLKA_DCTRL_5_4 ,Transceiver clock A (transmitter) divider control standard mode 1" "0,1,2,3" bitfld.word 0x04 0.--1. " XCVR_DIAG_HSCLKA_DCTRL_1_0 ,Transceiver clock A (transmitter) divider control standard mode 0" "0,1,2,3" line.word 0x06 "LANE0_XCVR_DIAG_HSCLKB_DCTRL,Transceiver High Speed Clock B Divider Control Register Lane 0" bitfld.word 0x06 12.--13. " XCVR_DIAG_HSCLKB_DCTRL_13_12 ,Transceiver clock B (transmitter) divider control standard mode 3" "0,1,2,3" bitfld.word 0x06 8.--9. " XCVR_DIAG_HSCLKB_DCTRL_9_8 ,Transceiver clock B (transmitter) divider control standard mode 2" "0,1,2,3" textline " " bitfld.word 0x06 4.--5. " XCVR_DIAG_HSCLKB_DCTRL_5_4 ,Transceiver clock B (transmitter) divider control standard mode 1" "0,1,2,3" bitfld.word 0x06 0.--1. " XCVR_DIAG_HSCLKB_DCTRL_1_0 ,Transceiver clock B (transmitter) divider control standard mode 0" "0,1,2,3" rgroup.word (0x4000+0x1CE)++0x01 line.word 0x00 "LANE0_XCVR_DIAG_RST_DIAG,Transceiver Control Reset Diagnostic Register Lane 0" bitfld.word 0x00 1. " XCVR_DIAG_RST_DIAG_1 ,Current state of the xcvr_psm_reset_n reset" "No reset,Reset" bitfld.word 0x00 0. " XCVR_DIAG_RST_DIAG_0 ,Current state of the xcvr_ref_clk_reset_n reset" "No reset,Reset" group.word (0x4000+0x1D0)++0x05 line.word 0x00 "LANE0_XCVR_DIAG_BIDI_CTRL,Transceiver Bidirectional Control Register Lane 0" bitfld.word 0x00 7. " XCVR_DIAG_BIDI_CTRL_7 ,Receiver enable standard mode 3" "Disabled,Enabled" bitfld.word 0x00 6. " XCVR_DIAG_BIDI_CTRL_6 ,Receiver enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " XCVR_DIAG_BIDI_CTRL_5 ,Receiver enable standard mode 1" "Disabled,Enabled" bitfld.word 0x00 4. " XCVR_DIAG_BIDI_CTRL_4 ,Receiver enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " XCVR_DIAG_BIDI_CTRL_3 ,Transmitter enable standard mode 3" "Disabled,Enabled" bitfld.word 0x00 2. " XCVR_DIAG_BIDI_CTRL_2 ,Transmitter enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " XCVR_DIAG_BIDI_CTRL_1 ,Transmitter enable standard mode 1" "Disabled,Enabled" bitfld.word 0x00 0. " XCVR_DIAG_BIDI_CTRL_0 ,Transmitter enable standard mode 0" "Disabled,Enabled" line.word 0x02 "LANE0_XCVR_DIAG_PWR_CTRL,Transceiver Power Island Control Register Lane 0" bitfld.word 0x02 15. " XCVR_DIAG_PWR_CTRL_15 ,Transceiver dsync power down disable" "No,Yes" bitfld.word 0x02 14. " XCVR_DIAG_PWR_CTRL_14 ,Transceiver calibration one time power down disable" "No,Yes" textline " " bitfld.word 0x02 13. " XCVR_DIAG_PWR_CTRL_13 ,Transceiver calibration multiples time power down disable" "No,Yes" bitfld.word 0x02 11. " XCVR_DIAG_PWR_CTRL_11 ,Transceiver test functions power enable" "Disabled,Enabled" line.word 0x04 "LANE0_XCVR_DIAG_RX_LANE_CAL_RST_TMR,RX Lane Calibration Reset Timer Register Lane 0" hexmask.word 0x04 0.--9. 1. " XCVR_DIAG_RX_LANE_CAL_RST_TMR_9_0 ,Lane calibration receiver reset timer value" group.word (0x4000+0x1E0)++0x07 line.word 0x00 "LANE0_XCVR_DIAG_LANE_FCM_EN_TO,Lane Fast Common Mode Enable Timeout Register Lane 0" hexmask.word 0x00 0.--11. 1. " XCVR_DIAG_LANE_FCM_EN_TO_11_0 ,Lane fast common mode enable timeout value" line.word 0x02 "LANE0_XCVR_DIAG_LANE_FCM_EN_SWAIT_TMR,Lane Fast Common Mode Enable Sample Wait Timer Register Lane 0" bitfld.word 0x02 0.--3. " XCVR_DIAG_LANE_FCM_EN_SWAIT_TMR_3_0 ,Lane fast common mode enable sample wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "LANE0_XCVR_DIAG_LANE_FCM_EN_MGN_TMR,Lane Fast Common Mode Enable Margin Timer Register Lane 0" hexmask.word 0x04 0.--11. 1. " XCVR_DIAG_LANE_FCM_EN_MGN_TMR_11_0 ,Lane fast common mode enable margin timer value" line.word 0x06 "LANE0_XCVR_DIAG_LANE_FCM_EN_TUNE,Lane Fast Common Mode Enable Tuning Register Lane 0" bitfld.word 0x06 8.--9. " XCVR_DIAG_LANE_FCM_EN_TUNE_9_8 ,Common mode sense reference DAC voltage initial test" "0,1,2,3" bitfld.word 0x06 4.--5. " XCVR_DIAG_LANE_FCM_EN_TUNE_5_4 ,Common mode sense reference DAC voltage high test" "0,1,2,3" textline " " bitfld.word 0x06 0.--1. " XCVR_DIAG_LANE_FCM_EN_TUNE_1_0 ,Common mode sense reference DAC voltage low test" "0,1,2,3" group.word (0x4000+0x200)++0x0F line.word 0x00 "LANE0_TX_PSC_A0,Transmitter A0 Power State Definition Register Lane 0" bitfld.word 0x00 14. " TX_PSC_A0_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x00 13. " TX_PSC_A0_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TX_PSC_A0_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x00 11. " TX_PSC_A0_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " TX_PSC_A0_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x00 9. " TX_PSC_A0_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " TX_PSC_A0_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x00 7. " TX_PSC_A0_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TX_PSC_A0_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x00 5. " TX_PSC_A0_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TX_PSC_A0_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x00 3. " TX_PSC_A0_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TX_PSC_A0_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x00 1. " TX_PSC_A0_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TX_PSC_A0_0 ,TX driver enable" "Disabled,Enabled" line.word 0x02 "LANE0_TX_PSC_A1,Transmitter A1 Power State Definition Register Lane 0" bitfld.word 0x02 14. " TX_PSC_A1_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x02 13. " TX_PSC_A1_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " TX_PSC_A1_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x02 11. " TX_PSC_A1_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x02 10. " TX_PSC_A1_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x02 9. " TX_PSC_A1_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x02 8. " TX_PSC_A1_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x02 7. " TX_PSC_A1_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " TX_PSC_A1_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x02 5. " TX_PSC_A1_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x02 4. " TX_PSC_A1_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x02 3. " TX_PSC_A1_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x02 2. " TX_PSC_A1_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x02 1. " TX_PSC_A1_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " TX_PSC_A1_0 ,TX driver enable" "Disabled,Enabled" line.word 0x04 "LANE0_TX_PSC_A2,Transmitter A2 Power State Definition Register Lane 0" bitfld.word 0x04 14. " TX_PSC_A2_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x04 13. " TX_PSC_A2_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x04 12. " TX_PSC_A2_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x04 11. " TX_PSC_A2_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x04 10. " TX_PSC_A2_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x04 9. " TX_PSC_A2_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x04 8. " TX_PSC_A2_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x04 7. " TX_PSC_A2_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " TX_PSC_A2_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x04 5. " TX_PSC_A2_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x04 4. " TX_PSC_A2_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x04 3. " TX_PSC_A2_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x04 2. " TX_PSC_A2_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x04 1. " TX_PSC_A2_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x04 0. " TX_PSC_A2_0 ,TX driver enable" "Disabled,Enabled" line.word 0x06 "LANE0_TX_PSC_A3,Transmitter A3 Power State Definition Register Lane 0" bitfld.word 0x06 14. " TX_PSC_A3_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x06 13. " TX_PSC_A3_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x06 12. " TX_PSC_A3_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x06 11. " TX_PSC_A3_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x06 10. " TX_PSC_A3_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x06 9. " TX_PSC_A3_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x06 8. " TX_PSC_A3_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x06 7. " TX_PSC_A3_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " TX_PSC_A3_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x06 5. " TX_PSC_A3_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " TX_PSC_A3_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x06 3. " TX_PSC_A3_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x06 2. " TX_PSC_A3_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x06 1. " TX_PSC_A3_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " TX_PSC_A3_0 ,TX driver enable" "Disabled,Enabled" line.word 0x08 "LANE0_TX_PSC_A4,Transmitter A4 Power State Definition Register Lane 0" bitfld.word 0x08 14. " TX_PSC_A4_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x08 13. " TX_PSC_A4_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x08 12. " TX_PSC_A4_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x08 11. " TX_PSC_A4_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x08 10. " TX_PSC_A4_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x08 9. " TX_PSC_A4_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x08 8. " TX_PSC_A4_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x08 7. " TX_PSC_A4_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " TX_PSC_A4_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x08 5. " TX_PSC_A4_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x08 4. " TX_PSC_A4_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x08 3. " TX_PSC_A4_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x08 2. " TX_PSC_A4_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x08 1. " TX_PSC_A4_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " TX_PSC_A4_0 ,TX driver enable" "Disabled,Enabled" line.word 0x0A "LANE0_TX_PSC_A5,Transmitter A5 Power State Definition Register Lane 0" bitfld.word 0x0A 14. " TX_PSC_A5_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x0A 13. " TX_PSC_A5_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 12. " TX_PSC_A5_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x0A 11. " TX_PSC_A5_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 10. " TX_PSC_A5_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x0A 9. " TX_PSC_A5_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 8. " TX_PSC_A5_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x0A 7. " TX_PSC_A5_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x0A 6. " TX_PSC_A5_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x0A 5. " TX_PSC_A5_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x0A 4. " TX_PSC_A5_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x0A 3. " TX_PSC_A5_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 2. " TX_PSC_A5_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x0A 1. " TX_PSC_A5_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 0. " TX_PSC_A5_0 ,TX driver enable" "Disabled,Enabled" line.word 0x0C "LANE0_TX_PSC_CAL,Transmitter Calibration Power State Definition Register Lane 0" bitfld.word 0x0C 14. " TX_PSC_CAL_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x0C 13. " TX_PSC_CAL_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 12. " TX_PSC_CAL_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x0C 11. " TX_PSC_CAL_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 10. " TX_PSC_CAL_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x0C 9. " TX_PSC_CAL_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 8. " TX_PSC_CAL_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x0C 7. " TX_PSC_CAL_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " TX_PSC_CAL_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x0C 5. " TX_PSC_CAL_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x0C 4. " TX_PSC_CAL_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x0C 3. " TX_PSC_CAL_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 2. " TX_PSC_CAL_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x0C 1. " TX_PSC_CAL_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 0. " TX_PSC_CAL_0 ,TX driver enable" "Disabled,Enabled" line.word 0x0E "LANE0_TX_PSC_RDY,Transmitter Ready Power State Definition Register Lane 0" bitfld.word 0x0E 14. " TX_PSC_RDY_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x0E 13. " TX_PSC_RDY_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 12. " TX_PSC_RDY_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x0E 11. " TX_PSC_RDY_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 10. " TX_PSC_RDY_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x0E 9. " TX_PSC_RDY_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 8. " TX_PSC_RDY_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x0E 7. " TX_PSC_RDY_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x0E 6. " TX_PSC_RDY_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x0E 5. " TX_PSC_RDY_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x0E 4. " TX_PSC_RDY_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x0E 3. " TX_PSC_RDY_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 2. " TX_PSC_RDY_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x0E 1. " TX_PSC_RDY_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 0. " TX_PSC_RDY_0 ,TX driver enable" "Disabled,Enabled" group.word (0x4000+0x240)++0x07 line.word 0x00 "LANE0_TX_RCVDET_CTRL,Transmit Receiver Detect Control Register Lane 0" bitfld.word 0x00 15. " TX_RCVDET_CTRL_15 ,Start receiver detect" "Not started,Started" rbitfld.word 0x00 14. " TX_RCVDET_CTRL_14 ,Receiver detect process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " TX_RCVDET_CTRL_13 ,Receiver detected" "Not detected,Detected" line.word 0x02 "LANE0_TX_RCVDET_OVRD,Transmit Receiver Detect Override Register Lane 0" bitfld.word 0x02 15. " TX_RCVDET_OVRD_15 ,Receiver detect override enable" "Disabled,Enabled" bitfld.word 0x02 14. " TX_RCVDET_OVRD_14 ,Receiver detect override" "No override,Override" line.word 0x04 "LANE0_TX_RCVDET_EN_TMR,Transmit Receiver Detect Enable Timer Register Lane 0" hexmask.word 0x04 0.--11. 1. " TX_RCVDET_EN_TMR_11_0 ,Enable wait time value" line.word 0x06 "LANE0_TX_RCVDET_ST_TMR,Transmit Receiver Detect Start Timer Register Lane 0" hexmask.word 0x06 0.--11. 1. " TX_RCVDET_ST_TMR_11_0 ,Start wait time value" group.word (0x4000+0x280)++0x01 line.word 0x00 "LANE0_TX_BIST_CTRL,Transmit BIST Control Register Lane 0" bitfld.word 0x00 8.--11. " TX_BIST_CTRL_11_8 ,Transmitter BIST mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4. " TX_BIST_CTRL_4 ,Transmitter BIST force error" "Not forced,Forced" textline " " bitfld.word 0x00 1. " TX_BIST_CTRL_1 ,Transmitter BIST user defined data FIFO clear" "No clear,Clear" bitfld.word 0x00 0. " TX_BIST_CTRL_0 ,Transmitter BIST enable" "Disabled,Enabled" wgroup.word (0x4000+0x282)++0x01 line.word 0x00 "LANE0_TX_BIST_UDDWR,Transmit BIST User Defined Data Write Register Lane 0" hexmask.word 0x00 0.--9. 1. " TX_BIST_UDDWR_9_0 ,Transmitter BIST user defined data" group.word (0x4000+0x284)++0x03 line.word 0x00 "LANE0_TX_BIST_SEED0,Transmit BIST PRBS Seed 0 Register Lane 0" line.word 0x02 "LANE0_TX_BIST_SEED1,Transmit BIST PRBS Seed 1 Register Lane 0" hexmask.word 0x02 0.--14. 1. " TX_BIST_SEED1_14_0 ,Transmitter BIST PRBS seed (30:16)" group.word (0x4000+0x3C0)++0x0B line.word 0x00 "LANE0_TX_DIAG_TX_CTRL,TX Control Register Lane 0" bitfld.word 0x00 15. " TX_DIAG_TX_CTRL_15 ,TX serializer clock invert" "Not inverted,Inverted" bitfld.word 0x00 6.--7. " TX_DIAG_TX_CTRL_7_6 ,TX interface sub-rate standard mode 3" "0,1,2,3" textline " " bitfld.word 0x00 4.--5. " TX_DIAG_TX_CTRL_7_6 ,TX interface sub-rate standard mode 2" "0,1,2,3" bitfld.word 0x00 2.--3. " TX_DIAG_TX_CTRL_3_2 ,TX interface sub-rate standard mode 1" "0,1,2,3" textline " " bitfld.word 0x00 0.--1. " TX_DIAG_TX_CTRL_1_0 ,TX interface sub-rate standard mode 0" "0,1,2,3" line.word 0x02 "LANE0_TX_DIAG_TX_DRV,TX Driver Control Register Lane 0" bitfld.word 0x02 13. " TX_DIAG_TX_DRV_13 ,Transmitter reset pull down override enable" "Disabled,Enabled" bitfld.word 0x02 12. " TX_DIAG_TX_DRV_12 ,Transmitter reset pull down override" "Disabled,Enabled" textline " " bitfld.word 0x02 10. " TX_DIAG_TX_DRV_10 ,TX driver programmable boost enable" "Disabled,Enabled" bitfld.word 0x02 8.--9. " TX_DIAG_TX_DRV_9_8 ,TX driver programmable boost level" "0,1,2,3" textline " " bitfld.word 0x02 7. " TX_DIAG_TX_DRV_7 ,TX driver LDO bandgap dependent feedback reference enable" "Disabled,Enabled" bitfld.word 0x02 6. " TX_DIAG_TX_DRV_6 ,TX driver LDO bandgap dependent reference enable" "Disabled,Enabled" textline " " bitfld.word 0x02 5. " TX_DIAG_TX_DRV_5 ,TX driver LDO VDD dependent feedback reference enable" "Disabled,Enabled" bitfld.word 0x02 4. " TX_DIAG_TX_DRV_4 ,TX driver LDO VDD dependent reference enable" "Disabled,Enabled" textline " " bitfld.word 0x02 2. " TX_DIAG_TX_DRV_2 ,TD driver polarity control" "Low,High" bitfld.word 0x02 1. " TX_DIAG_TX_DRV_1 ,TX pre-driver pull up control" "0,1" textline " " bitfld.word 0x02 0. " TX_DIAG_TX_DRV_0 ,TX driver margin type" "0,1" line.word 0x04 "LANE0_TX_DIAG_ELEC_IDLE,TX Electrical Idle Diagnostic Register Lane 0" bitfld.word 0x04 4.--7. " TX_DIAG_ELEC_IDLE_7_4 ,TX electrical idle exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x04 0.--3. " TX_DIAG_ELEC_IDLE_3_0 ,TX electrical idle entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x06 "LANE0_TX_DIAG_SFIFO_CTRL,TX Sync FIFO Diagnostic Control Register Lane 0" bitfld.word 0x06 4. " TX_DIAG_SFIFO_CTRL_4 ,FIFO enqueue pointer bump" "Not decremented,Decremented" rbitfld.word 0x06 3. " TX_DIAG_SFIFO_CTRL_3 ,FIFO alignment error" "No error,Error" textline " " rbitfld.word 0x06 2. " TX_DIAG_SFIFO_CTRL_2 ,FIFO alignment acknowledge" "Not acknowledged,Acknowledged" bitfld.word 0x06 1. " TX_DIAG_SFIFO_CTRL_1 ,FIFO alignment enable override enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " TX_DIAG_SFIFO_CTRL_0 ,FIFO alignment enable override" "Disabled,Enabled" line.word 0x08 "LANE0_TX_DIAG_SFIFO_TMR,TX Sync FIFO Diagnostic Timer Register Lane 0" bitfld.word 0x08 8.--13. " TX_DIAG_SFIFO_TMR_13_8 ,FIFO alignment settle delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x08 0.--5. " TX_DIAG_SFIFO_TMR_5_0 ,FIFO alignment detect delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0A "LANE0_TX_DIAG_RDVDET_TUNE,TX Receiver Detect Tuning Register Lane 0" bitfld.word 0x0A 0.--1. " TX_DIAG_RDVDET_TUNE_1_0 ,Receiver detect reference DAC voltage" "0,1,2,3" rgroup.word (0x4000+0x3CC)++0x01 line.word 0x00 "LANE0_TX_DIAG_RST_DIAG,Transmitter Control Reset Diagnostic Register Lane 0" bitfld.word 0x00 8. " TX_DIAG_RST_DIAG_8 ,Current state of the dsync_power_reset_n reset" "No reset,Reset" bitfld.word 0x00 7. " TX_DIAG_RST_DIAG_7 ,Current state of the tfunc_power_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 6. " TX_DIAG_RST_DIAG_6 ,Current state of the xcal1_power_reset_n reset" "No reset,Reset" bitfld.word 0x00 5. " TX_DIAG_RST_DIAG_5 ,Current state of the xcaln_power_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 4. " TX_DIAG_RST_DIAG_4 ,Current state of the txda_tx_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 3. " TX_DIAG_RST_DIAG_3 ,Current state of the tx_dig_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 2. " TX_DIAG_RST_DIAG_2 ,Current state of the tx_sync_fifo_deq_rst_n reset" "No reset,Reset" bitfld.word 0x00 1. " TX_DIAG_RST_DIAG_1 ,Current state of the tx_sync_fifo_enq_rst_n reset" "No reset,Reset" textline " " bitfld.word 0x00 0. " TX_DIAG_RST_DIAG_0 ,Current state of the tx_lfps_reset_n reset" "No reset,Reset" group.word (0x4000+0x3CE)++0x05 line.word 0x00 "LANE0_TX_DIAG_BGREF_PREDRV_DELAY,TX Bandgap Reference And Pre-Drive Enable Delay Register Lane 0" hexmask.word.byte 0x00 0.--7. 1. " TX_DIAG_BGREF_PREDRV_DELAY_7_0 ,TX bandgap reference and pre-drive enable delay" line.word 0x02 "LANE0_TX_DIAG_MPHY_CTRL1,TX MPHY Control Register 1 Lane0" bitfld.word 0x02 8.--11. " TX_DIAG_MPHY_CTRL1_11_8 ,Register definition to be provided by the analog team" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x02 4. " TX_DIAG_MPHY_CTRL1_4 ,MPHY small amplitude mode" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " TX_DIAG_MPHY_CTRL1_3 ,AUX bias current enable" "Disabled,Enabled" bitfld.word 0x02 2. " TX_DIAG_MPHY_CTRL1_2 ,LDO no-load current reduce" "Not reduced,Reduced" textline " " bitfld.word 0x02 1. " TX_DIAG_MPHY_CTRL1_1 ,Register definition to be provided by the analog team" "0,1" bitfld.word 0x02 0. " TX_DIAG_MPHY_CTRL1_0 ,MPHY high load current mode enable" "Disabled,Enabled" line.word 0x04 "LANE0_TX_DIAG_MPHY_CTRL2,TX MPHY Control Register 2 Lane 0" bitfld.word 0x04 8.--11. " TX_DIAG_MPHY_CTRL2_11_8 ,Register definition to be provided by the analog team" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word.byte 0x04 0.--7. 1. " TX_DIAG_MPHY_CTRL2_7_0 ,MPHY slew rate control" group.word (0x4000+0x3E8)++0x03 line.word 0x00 "LANE0_TX_DIAG_DRV_LDO_PROG,TX Driver LDO Programming Register Lane 0" line.word 0x02 "LANE0_TX_DIAG_ECTRL_OVRD,TX Extra Enable Control Override Register Lane 0" bitfld.word 0x02 3. " TX_DIAG_ECTRL_OVRD_3 ,Driver pre-drive enable override enable" "Disabled,Enabled" bitfld.word 0x02 2. " TX_DIAG_ECTRL_OVRD_2 ,Driver pre-drive enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 1. " TX_DIAG_ECTRL_OVRD_1 ,Bandgap reference enable override enable" "Disabled,Enabled" bitfld.word 0x02 0. " TX_DIAG_ECTRL_OVRD_0 ,Bandgap reference enable override" "Disabled,Enabled" group.word 0x4400++0x21 line.word 0x00 "LANE1_XCVR_PSM_CTRL,Power State Machine Control Register Lane 1" bitfld.word 0x00 14. " XCVR_PSM_CTRL_14 ,Bypass A0 in delay from PSM ready" "Not bypassed,Bypassed" bitfld.word 0x00 13. " XCVR_PSM_CTRL_13 ,Bypass A0 in delay from A5" "Not bypassed,Bypassed" textline " " bitfld.word 0x00 12. " XCVR_PSM_CTRL_12 ,Bypass A0 in delay from A4" "Not bypassed,Bypassed" bitfld.word 0x00 11. " XCVR_PSM_CTRL_11 ,Bypass A0 in delay from A3" "Not bypassed,Bypassed" textline " " bitfld.word 0x00 10. " XCVR_PSM_CTRL_10 ,Bypass A0 in delay from A2" "Not bypassed,Bypassed" bitfld.word 0x00 9. " XCVR_PSM_CTRL_9 ,Bypass A0 in delay from A1" "Not bypassed,Bypassed" textline " " bitfld.word 0x00 0. " XCVR_PSM_CTRL_0 ,Skip lane re-calibration" "Not skipped,Skipped" line.word 0x02 "LANE1_XCVR_PSM_RCTRL,Power State Machine Reset Control Register Lane 1" bitfld.word 0x02 15. " XCVR_PSM_RCTRL_15 ,RX reset active ready" "No reset,Reset" bitfld.word 0x02 14. " XCVR_PSM_RCTRL_14 ,RX reset active calibration" "No reset,Reset" textline " " bitfld.word 0x02 13. " XCVR_PSM_RCTRL_13 ,RX reset active A5" "No reset,Reset" bitfld.word 0x02 12. " XCVR_PSM_RCTRL_12 ,RX reset active A4" "No reset,Reset" textline " " bitfld.word 0x02 11. " XCVR_PSM_RCTRL_11 ,RX reset active A3" "No reset,Reset" bitfld.word 0x02 10. " XCVR_PSM_RCTRL_10 ,RX reset active A2" "No reset,Reset" textline " " bitfld.word 0x02 9. " XCVR_PSM_RCTRL_9 ,RX reset active A1" "No reset,Reset" bitfld.word 0x02 8. " XCVR_PSM_RCTRL_8 ,RX reset active A0" "No reset,Reset" textline " " bitfld.word 0x02 7. " XCVR_PSM_RCTRL_7 ,TX reset active ready" "No reset,Reset" bitfld.word 0x02 6. " XCVR_PSM_RCTRL_6 ,TX reset active calibration" "No reset,Reset" textline " " bitfld.word 0x02 5. " XCVR_PSM_RCTRL_5 ,TX reset active A5" "No reset,Reset" bitfld.word 0x02 4. " XCVR_PSM_RCTRL_4 ,TX reset active A4" "No reset,Reset" textline " " bitfld.word 0x02 3. " XCVR_PSM_RCTRL_3 ,TX reset active A3" "No reset,Reset" bitfld.word 0x02 2. " XCVR_PSM_RCTRL_2 ,TX reset active A2" "No reset,Reset" textline " " bitfld.word 0x02 1. " XCVR_PSM_RCTRL_1 ,TX reset active A1" "No reset,Reset" bitfld.word 0x02 0. " XCVR_PSM_RCTRL_0 ,TX reset active A0" "No reset,Reset" line.word 0x04 "LANE1_XCVR_PSM_CAL_TMR,PSM Calibration Delay Timer Register Lane 1" hexmask.word 0x04 0.--9. 1. " XCVR_PSM_CAL_TMR_9_0 ,PSM calibration delay state timer value" line.word 0x06 "LANE1_XCVR_PSM_A0IN_TMR,A0 In Delay Timer Register Lane 1" hexmask.word 0x06 0.--9. 1. " XCVR_PSM_A0IN_TMR_9_0 ,A0 in delay state timer value" line.word 0x08 "LANE1_XCVR_PSM_A0BYP_TMR,A0 In Bypass Timer Register Lane 1" bitfld.word 0x08 0.--4. " XCVR_PSM_A0BYP_TMR_4_0 ,A0 in delay state bypass timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0A "LANE1_XCVR_PSM_A1IN_TMR,A1 In Delay Timer Register Lane 1" bitfld.word 0x0A 0.--4. " XCVR_PSM_A1IN_TMR_4_0 ,A1 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "LANE1_XCVR_PSM_A2IN_TMR,A2 In Delay Timer Register Lane 1" bitfld.word 0x0C 0.--4. " XCVR_PSM_A2IN_TMR_4_0 ,A2 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0E "LANE1_XCVR_PSM_A3IN_TMR,A3 In Delay Timer Register Lane 1" bitfld.word 0x0E 0.--4. " XCVR_PSM_A3IN_TMR_4_0 ,A3 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "LANE1_XCVR_PSM_A4IN_TMR,A4 In Delay Timer Register Lane 1" bitfld.word 0x10 0.--4. " XCVR_PSM_A4IN_TMR_4_0 ,A4 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x12 "LANE1_XCVR_PSM_A5IN_TMR,A5 In Delay Timer Register Lane 1" bitfld.word 0x12 0.--4. " XCVR_PSM_A5IN_TMR_4_0 ,A5 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "LANE1_XCVR_PSM_A0OUT_TMR,A0 Out Delay Timer Register Lane 1" bitfld.word 0x14 0.--4. " XCVR_PSM_A0OUT_TMR_4_0 ,A0 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x16 "LANE1_XCVR_PSM_A1OUT_TMR,A1 Out Delay Timer Register Lane 1" bitfld.word 0x16 0.--4. " XCVR_PSM_A1OUT_TMR_4_0 ,A1 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x18 "LANE1_XCVR_PSM_A2OUT_TMR,A2 Out Delay Timer Register Lane 1" bitfld.word 0x18 0.--4. " XCVR_PSM_A2OUT_TMR_4_0 ,A2 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x1A "LANE1_XCVR_PSM_A3OUT_TMR,A3 Out Delay Timer Register Lane 1" bitfld.word 0x1A 0.--4. " XCVR_PSM_A3OUT_TMR_4_0 ,A3 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x1C "LANE1_XCVR_PSM_A4OUT_TMR,A4 Out Delay Timer Register Lane 1" bitfld.word 0x1C 0.--4. " XCVR_PSM_A4OUT_TMR_4_0 ,A4 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x1E "LANE1_XCVR_PSM_A5OUT_TMR,A5 Out Delay Timer Register Lane 1" bitfld.word 0x1E 0.--4. " XCVR_PSM_A5OUT_TMR_4_0 ,A5 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x20 "LANE1_XCVR_PSM_DIAG,Power State Machine Diagnostic Register Lane 1" bitfld.word 0x20 13. " XCVR_PSM_DIAG_13 ,Force A5 exit acknowledge" "Not forced,Forced" bitfld.word 0x20 12. " XCVR_PSM_DIAG_12 ,Force A4 exit acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 11. " XCVR_PSM_DIAG_11 ,Force A3 exit acknowledge" "Not forced,Forced" bitfld.word 0x20 10. " XCVR_PSM_DIAG_10 ,Force A2 exit acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 9. " XCVR_PSM_DIAG_9 ,Force A1 exit acknowledge" "Not forced,Forced" bitfld.word 0x20 8. " XCVR_PSM_DIAG_8 ,Force A0 exit acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 5. " XCVR_PSM_DIAG_5 ,Force A5 entry acknowledge" "Not forced,Forced" bitfld.word 0x20 4. " XCVR_PSM_DIAG_4 ,Force A4 entry acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 3. " XCVR_PSM_DIAG_3 ,Force A3 entry acknowledge" "Not forced,Forced" bitfld.word 0x20 2. " XCVR_PSM_DIAG_2 ,Force A2 entry acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 1. " XCVR_PSM_DIAG_1 ,Force A1 entry acknowledge" "Not forced,Forced" bitfld.word 0x20 0. " XCVR_PSM_DIAG_0 ,Force A0 entry acknowledge" "Not forced,Forced" group.word (0x4400+0x3E)++0x01 line.word 0x00 "LANE1_XCVR_PSM_USER_DEF_CTRL,Power State Machine User Defined Control Register Lane 1" bitfld.word 0x00 1. " XCVR_PSM_USER_DEF_CTRL_1 ,Disable PSM clock gating" "No,Yes" bitfld.word 0x00 0. " XCVR_PSM_USER_DEF_CTRL_0 ,Disable early A0 acknowledge response" "No,Yes" group.word (0x4400+0x82)++0x05 line.word 0x00 "LANE1_TX_TXCC_PRE_OVRD,TX Pre-Cursor Override Register Lane 1" bitfld.word 0x00 8. " TX_TXCC_PRE_OVRD_8 ,Pre-cursor override enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " TX_TXCC_PRE_OVRD_5_0 ,Pre-cursor override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE1_TX_TXCC_MAIN_OVRD,TX Main-Cursor Override Register Lane 1" bitfld.word 0x02 8. " TX_TXCC_MAIN_OVRD_8 ,Main-cursor override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " TX_TXCC_MAIN_OVRD_5_0 ,Main-cursor override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE1_TX_TXCC_POST_OVRD,TX Post-Cursor Override Register Lane 1" bitfld.word 0x04 8. " TX_TXCC_POST_OVRD_8 ,Post-cursor override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " TX_TXCC_POST_OVRD_5_0 ,Post-cursor override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.word (0x4400+0x88)++0x05 line.word 0x00 "LANE1_TX_TXCC_PRE_CVAL,TX Pre-Cursor Current Value Register 1" bitfld.word 0x00 0.--5. " TX_TXCC_PRE_CVAL_5_0 ,Pre-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE1_TX_TXCC_MAIN_CVAL,TX Main-Cursor Current Value Register 1" bitfld.word 0x02 0.--5. " TX_TXCC_MAIN_CVAL_5_0 ,Main-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE1_TX_TXCC_POST_CVAL,TX Post-Cursor Current Value Register 1" bitfld.word 0x04 0.--5. " TX_TXCC_POST_CVAL_5_0 ,Post-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x4400+0x8E)++0x31 line.word 0x00 "LANE1_TX_TXCC_CAL_SCLR_MULT,Resistor Calibration Code Scaler Multiplier Value Register Lane 1" bitfld.word 0x00 8. " TX_TXCC_CAL_SCLR_MULT_8 ,Scaled resistor calibration code add" "0,1" hexmask.word.byte 0x00 0.--7. 1. " TX_TXCC_CAL_SCLR_MULT_7_0 ,Resistor calibration multiplier value" line.word 0x02 "LANE1_TX_TXCC_CPRE_MULT_00,Calculated Pre Emphasis Multiplier Value 00 Register Lane 1" hexmask.word.byte 0x02 0.--7. 1. " TX_TXCC_CPRE_MULT_00_7_0 ,Calculated pre emphasis multiplier value 00" line.word 0x04 "LANE1_TX_TXCC_CPRE_MULT_01,Calculated Pre Emphasis Multiplier Value 01 Register Lane 1" hexmask.word.byte 0x04 0.--7. 1. " TX_TXCC_CPRE_MULT_01_7_0 ,Calculated pre emphasis multiplier value 01" line.word 0x06 "LANE1_TX_TXCC_CPRE_MULT_10,Calculated Pre Emphasis Multiplier Value 10 Register Lane 1" hexmask.word.byte 0x06 0.--7. 1. " TX_TXCC_CPRE_MULT_10_7_0 ,Calculated pre emphasis multiplier value 10" line.word 0x08 "LANE1_TX_TXCC_CPRE_MULT_11,Calculated Pre Emphasis Multiplier Value 11 Register Lane 1" hexmask.word.byte 0x08 0.--7. 1. " TX_TXCC_CPRE_MULT_11_7_0 ,Calculated pre emphasis multiplier value 11" line.word 0x0A "LANE1_TX_TXCC_CPOST_MULT_00,Calculated Post Emphasis Multiplier Value 00 Register Lane 1" hexmask.word.byte 0x0A 0.--7. 1. " TX_TXCC_CPOST_MULT_00_7_0 ,Calculated post emphasis multiplier value 00" line.word 0x0C "LANE1_TX_TXCC_CPOST_MULT_01,Calculated Post Emphasis Multiplier Value 01 Register Lane 1" hexmask.word.byte 0x0C 0.--7. 1. " TX_TXCC_CPOST_MULT_01_7_0 ,Calculated post emphasis multiplier value 01" line.word 0x0E "LANE1_TX_TXCC_CPOST_MULT_10,Calculated Post Emphasis Multiplier Value 10 Register Lane 1" hexmask.word.byte 0x0E 0.--7. 1. " TX_TXCC_CPOST_MULT_10_7_0 ,Calculated post emphasis multiplier value 10" line.word 0x10 "LANE1_TX_TXCC_CPOST_MULT_11,Calculated Post Emphasis Multiplier Value 11 Register Lane 1" hexmask.word.byte 0x10 0.--7. 1. " TX_TXCC_CPOST_MULT_11_7_0 ,Calculated post emphasis multiplier value 11" line.word 0x12 "LANE1_TX_TXCC_MGNFS_MULT_000,Margin Full Swing Multiplier Value 000 Register Lane 1" hexmask.word.byte 0x12 0.--7. 1. " TX_TXCC_MGNFS_MULT_000_7_0 ,Margin full swing multiplier value 000" line.word 0x14 "LANE1_TX_TXCC_MGNFS_MULT_001,Margin Full Swing Multiplier Value 001 Register Lane 1" hexmask.word.byte 0x14 0.--7. 1. " TX_TXCC_MGNFS_MULT_001_7_0 ,Margin full swing multiplier value 001" line.word 0x16 "LANE1_TX_TXCC_MGNFS_MULT_010,Margin Full Swing Multiplier Value 010 Register Lane 1" hexmask.word.byte 0x16 0.--7. 1. " TX_TXCC_MGNFS_MULT_010_7_0 ,Margin full swing multiplier value 010" line.word 0x18 "LANE1_TX_TXCC_MGNFS_MULT_011,Margin Full Swing Multiplier Value 011 Register Lane 1" hexmask.word.byte 0x18 0.--7. 1. " TX_TXCC_MGNFS_MULT_011_7_0 ,Margin full swing multiplier value 011" line.word 0x1A "LANE1_TX_TXCC_MGNFS_MULT_100,Margin Full Swing Multiplier Value 100 Register Lane 1" hexmask.word.byte 0x1A 0.--7. 1. " TX_TXCC_MGNFS_MULT_100_7_0 ,Margin full swing multiplier value 100" line.word 0x1C "LANE1_TX_TXCC_MGNFS_MULT_101,Margin Full Swing Multiplier Value 101 Register Lane 1" hexmask.word.byte 0x1C 0.--7. 1. " TX_TXCC_MGNFS_MULT_101_7_0 ,Margin full swing multiplier value 101" line.word 0x1E "LANE1_TX_TXCC_MGNFS_MULT_110,Margin Full Swing Multiplier Value 110 Register Lane 1" hexmask.word.byte 0x1E 0.--7. 1. " TX_TXCC_MGNFS_MULT_110_7_0 ,Margin full swing multiplier value 110" line.word 0x20 "LANE1_TX_TXCC_MGNFS_MULT_111,Margin Full Swing Multiplier Value 111 Register Lane 1" hexmask.word.byte 0x20 0.--7. 1. " TX_TXCC_MGNFS_MULT_111_7_0 ,Margin full swing multiplier value 111" line.word 0x22 "LANE1_TX_TXCC_MGNLS_MULT_000,Margin Half Swing Multiplier Value 000 Register Lane 1" hexmask.word.byte 0x22 0.--7. 1. " TX_TXCC_MGNLS_MULT_000_7_0 ,Margin half swing multiplier value 000" line.word 0x24 "LANE1_TX_TXCC_MGNLS_MULT_001,Margin Half Swing Multiplier Value 001 Register Lane 1" hexmask.word.byte 0x24 0.--7. 1. " TX_TXCC_MGNLS_MULT_001_7_0 ,Margin half swing multiplier value 001" line.word 0x26 "LANE1_TX_TXCC_MGNLS_MULT_010,Margin Half Swing Multiplier Value 010 Register Lane 1" hexmask.word.byte 0x26 0.--7. 1. " TX_TXCC_MGNLS_MULT_010_7_0 ,Margin half swing multiplier value 010" line.word 0x28 "LANE1_TX_TXCC_MGNLS_MULT_011,Margin Half Swing Multiplier Value 011 Register Lane 1" hexmask.word.byte 0x28 0.--7. 1. " TX_TXCC_MGNLS_MULT_011_7_0 ,Margin half swing multiplier value 011" line.word 0x2A "LANE1_TX_TXCC_MGNLS_MULT_100,Margin Half Swing Multiplier Value 100 Register Lane 1" hexmask.word.byte 0x2A 0.--7. 1. " TX_TXCC_MGNLS_MULT_100_7_0 ,Margin half swing multiplier value 100" line.word 0x2C "LANE1_TX_TXCC_MGNLS_MULT_101,Margin Half Swing Multiplier Value 101 Register Lane 1" hexmask.word.byte 0x2C 0.--7. 1. " TX_TXCC_MGNLS_MULT_101_7_0 ,Margin half swing multiplier value 101" line.word 0x2E "LANE1_TX_TXCC_MGNLS_MULT_110,Margin Half Swing Multiplier Value 110 Register Lane 1" hexmask.word.byte 0x2E 0.--7. 1. " TX_TXCC_MGNLS_MULT_110_7_0 ,Margin half swing multiplier value 110" line.word 0x30 "LANE1_TX_TXCC_MGNLS_MULT_111,Margin Half Swing Multiplier Value 111 Register Lane 1" hexmask.word.byte 0x30 0.--7. 1. " TX_TXCC_MGNLS_MULT_111_7_0 ,Margin half swing multiplier value 111" group.word (0x4400+0x1C0)++0x07 line.word 0x00 "LANE1_XCVR_DIAG_PLLDRC_CTRL,Transceiver PLL Data Rate Clock Control Register Lane 1" bitfld.word 0x00 14. " XCVR_DIAG_PLLDRC_CTRL_14 ,Digital PLL clock select standard mode 3" "Not selected,Selected" bitfld.word 0x00 12.--13. " XCVR_DIAG_PLLDRC_CTRL_13_12 ,Digital PLL data rate divider standard mode 3 value" "0,1,2,3" textline " " bitfld.word 0x00 10. " XCVR_DIAG_PLLDRC_CTRL_10 ,Digital PLL clock select standard mode 2" "Not selected,Selected" bitfld.word 0x00 8.--9. " XCVR_DIAG_PLLDRC_CTRL_9_8 ,Digital PLL data rate divider standard mode 2 value" "0,1,2,3" textline " " bitfld.word 0x00 6. " XCVR_DIAG_PLLDRC_CTRL_6 ,Digital PLL clock select standard mode 1" "Not selected,Selected" bitfld.word 0x00 4.--5. " XCVR_DIAG_PLLDRC_CTRL_5_4 ,Digital PLL data rate divider standard mode 1 value" "0,1,2,3" textline " " bitfld.word 0x00 2. " XCVR_DIAG_PLLDRC_CTRL_2 ,Digital PLL clock select standard mode 0" "Not selected,Selected" bitfld.word 0x00 0.--1. " XCVR_DIAG_PLLDRC_CTRL_0_1 ,Digital PLL data rate divider standard mode 0 value" "0,1,2,3" line.word 0x02 "LANE1_XCVR_DIAG_HSCLK_SEL,Transceiver High Speed Clock Select Register Lane 1" bitfld.word 0x02 12.--13. " XCVR_DIAG_HSCLK_SEL_13_12 ,High speed clock select standard mode 3" "0,1,2,3" bitfld.word 0x02 8.--9. " XCVR_DIAG_HSCLK_SEL_9_8 ,High speed clock select standard mode 2" "0,1,2,3" textline " " bitfld.word 0x02 4.--5. " XCVR_DIAG_HSCLK_SEL_5_4 ,High speed clock select standard mode 1" "0,1,2,3" bitfld.word 0x02 0.--1. " XCVR_DIAG_HSCLK_SEL_5_4 ,High speed clock select standard mode 0" "0,1,2,3" line.word 0x04 "LANE1_XCVR_DIAG_HSCLKA_DCTRL,Transceiver High Speed Clock A Divider Control Register Lane 1" bitfld.word 0x04 12.--13. " XCVR_DIAG_HSCLKA_DCTRL_13_12 ,Transceiver clock A (transmitter) divider control standard mode 3" "0,1,2,3" bitfld.word 0x04 8.--9. " XCVR_DIAG_HSCLKA_DCTRL_9_8 ,Transceiver clock A (transmitter) divider control standard mode 2" "0,1,2,3" textline " " bitfld.word 0x04 4.--5. " XCVR_DIAG_HSCLKA_DCTRL_5_4 ,Transceiver clock A (transmitter) divider control standard mode 1" "0,1,2,3" bitfld.word 0x04 0.--1. " XCVR_DIAG_HSCLKA_DCTRL_1_0 ,Transceiver clock A (transmitter) divider control standard mode 0" "0,1,2,3" line.word 0x06 "LANE1_XCVR_DIAG_HSCLKB_DCTRL,Transceiver High Speed Clock B Divider Control Register Lane 1" bitfld.word 0x06 12.--13. " XCVR_DIAG_HSCLKB_DCTRL_13_12 ,Transceiver clock B (transmitter) divider control standard mode 3" "0,1,2,3" bitfld.word 0x06 8.--9. " XCVR_DIAG_HSCLKB_DCTRL_9_8 ,Transceiver clock B (transmitter) divider control standard mode 2" "0,1,2,3" textline " " bitfld.word 0x06 4.--5. " XCVR_DIAG_HSCLKB_DCTRL_5_4 ,Transceiver clock B (transmitter) divider control standard mode 1" "0,1,2,3" bitfld.word 0x06 0.--1. " XCVR_DIAG_HSCLKB_DCTRL_1_0 ,Transceiver clock B (transmitter) divider control standard mode 0" "0,1,2,3" rgroup.word (0x4400+0x1CE)++0x01 line.word 0x00 "LANE1_XCVR_DIAG_RST_DIAG,Transceiver Control Reset Diagnostic Register Lane 1" bitfld.word 0x00 1. " XCVR_DIAG_RST_DIAG_1 ,Current state of the xcvr_psm_reset_n reset" "No reset,Reset" bitfld.word 0x00 0. " XCVR_DIAG_RST_DIAG_0 ,Current state of the xcvr_ref_clk_reset_n reset" "No reset,Reset" group.word (0x4400+0x1D0)++0x05 line.word 0x00 "LANE1_XCVR_DIAG_BIDI_CTRL,Transceiver Bidirectional Control Register Lane 1" bitfld.word 0x00 7. " XCVR_DIAG_BIDI_CTRL_7 ,Receiver enable standard mode 3" "Disabled,Enabled" bitfld.word 0x00 6. " XCVR_DIAG_BIDI_CTRL_6 ,Receiver enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " XCVR_DIAG_BIDI_CTRL_5 ,Receiver enable standard mode 1" "Disabled,Enabled" bitfld.word 0x00 4. " XCVR_DIAG_BIDI_CTRL_4 ,Receiver enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " XCVR_DIAG_BIDI_CTRL_3 ,Transmitter enable standard mode 3" "Disabled,Enabled" bitfld.word 0x00 2. " XCVR_DIAG_BIDI_CTRL_2 ,Transmitter enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " XCVR_DIAG_BIDI_CTRL_1 ,Transmitter enable standard mode 1" "Disabled,Enabled" bitfld.word 0x00 0. " XCVR_DIAG_BIDI_CTRL_0 ,Transmitter enable standard mode 0" "Disabled,Enabled" line.word 0x02 "LANE1_XCVR_DIAG_PWR_CTRL,Transceiver Power Island Control Register Lane 1" bitfld.word 0x02 15. " XCVR_DIAG_PWR_CTRL_15 ,Transceiver dsync power down disable" "No,Yes" bitfld.word 0x02 14. " XCVR_DIAG_PWR_CTRL_14 ,Transceiver calibration one time power down disable" "No,Yes" textline " " bitfld.word 0x02 13. " XCVR_DIAG_PWR_CTRL_13 ,Transceiver calibration multiples time power down disable" "No,Yes" bitfld.word 0x02 11. " XCVR_DIAG_PWR_CTRL_11 ,Transceiver test functions power enable" "Disabled,Enabled" line.word 0x04 "LANE1_XCVR_DIAG_RX_LANE_CAL_RST_TMR,RX Lane Calibration Reset Timer Register Lane 1" hexmask.word 0x04 0.--9. 1. " XCVR_DIAG_RX_LANE_CAL_RST_TMR_9_0 ,Lane calibration receiver reset timer value" group.word (0x4400+0x1E0)++0x07 line.word 0x00 "LANE1_XCVR_DIAG_LANE_FCM_EN_TO,Lane Fast Common Mode Enable Timeout Register Lane 1" hexmask.word 0x00 0.--11. 1. " XCVR_DIAG_LANE_FCM_EN_TO_11_0 ,Lane fast common mode enable timeout value" line.word 0x02 "LANE1_XCVR_DIAG_LANE_FCM_EN_SWAIT_TMR,Lane Fast Common Mode Enable Sample Wait Timer Register Lane 1" bitfld.word 0x02 0.--3. " XCVR_DIAG_LANE_FCM_EN_SWAIT_TMR_3_0 ,Lane fast common mode enable sample wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "LANE1_XCVR_DIAG_LANE_FCM_EN_MGN_TMR,Lane Fast Common Mode Enable Margin Timer Register Lane 1" hexmask.word 0x04 0.--11. 1. " XCVR_DIAG_LANE_FCM_EN_MGN_TMR_11_0 ,Lane fast common mode enable margin timer value" line.word 0x06 "LANE1_XCVR_DIAG_LANE_FCM_EN_TUNE,Lane Fast Common Mode Enable Tuning Register Lane 1" bitfld.word 0x06 8.--9. " XCVR_DIAG_LANE_FCM_EN_TUNE_9_8 ,Common mode sense reference DAC voltage initial test" "0,1,2,3" bitfld.word 0x06 4.--5. " XCVR_DIAG_LANE_FCM_EN_TUNE_5_4 ,Common mode sense reference DAC voltage high test" "0,1,2,3" textline " " bitfld.word 0x06 0.--1. " XCVR_DIAG_LANE_FCM_EN_TUNE_1_0 ,Common mode sense reference DAC voltage low test" "0,1,2,3" group.word (0x4400+0x200)++0x0F line.word 0x00 "LANE1_TX_PSC_A0,Transmitter A0 Power State Definition Register Lane 1" bitfld.word 0x00 14. " TX_PSC_A0_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x00 13. " TX_PSC_A0_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TX_PSC_A0_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x00 11. " TX_PSC_A0_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " TX_PSC_A0_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x00 9. " TX_PSC_A0_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " TX_PSC_A0_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x00 7. " TX_PSC_A0_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TX_PSC_A0_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x00 5. " TX_PSC_A0_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TX_PSC_A0_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x00 3. " TX_PSC_A0_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TX_PSC_A0_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x00 1. " TX_PSC_A0_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TX_PSC_A0_0 ,TX driver enable" "Disabled,Enabled" line.word 0x02 "LANE1_TX_PSC_A1,Transmitter A1 Power State Definition Register Lane 1" bitfld.word 0x02 14. " TX_PSC_A1_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x02 13. " TX_PSC_A1_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " TX_PSC_A1_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x02 11. " TX_PSC_A1_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x02 10. " TX_PSC_A1_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x02 9. " TX_PSC_A1_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x02 8. " TX_PSC_A1_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x02 7. " TX_PSC_A1_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " TX_PSC_A1_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x02 5. " TX_PSC_A1_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x02 4. " TX_PSC_A1_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x02 3. " TX_PSC_A1_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x02 2. " TX_PSC_A1_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x02 1. " TX_PSC_A1_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " TX_PSC_A1_0 ,TX driver enable" "Disabled,Enabled" line.word 0x04 "LANE1_TX_PSC_A2,Transmitter A2 Power State Definition Register Lane 1" bitfld.word 0x04 14. " TX_PSC_A2_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x04 13. " TX_PSC_A2_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x04 12. " TX_PSC_A2_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x04 11. " TX_PSC_A2_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x04 10. " TX_PSC_A2_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x04 9. " TX_PSC_A2_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x04 8. " TX_PSC_A2_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x04 7. " TX_PSC_A2_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " TX_PSC_A2_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x04 5. " TX_PSC_A2_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x04 4. " TX_PSC_A2_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x04 3. " TX_PSC_A2_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x04 2. " TX_PSC_A2_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x04 1. " TX_PSC_A2_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x04 0. " TX_PSC_A2_0 ,TX driver enable" "Disabled,Enabled" line.word 0x06 "LANE1_TX_PSC_A3,Transmitter A3 Power State Definition Register Lane 1" bitfld.word 0x06 14. " TX_PSC_A3_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x06 13. " TX_PSC_A3_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x06 12. " TX_PSC_A3_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x06 11. " TX_PSC_A3_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x06 10. " TX_PSC_A3_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x06 9. " TX_PSC_A3_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x06 8. " TX_PSC_A3_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x06 7. " TX_PSC_A3_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " TX_PSC_A3_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x06 5. " TX_PSC_A3_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " TX_PSC_A3_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x06 3. " TX_PSC_A3_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x06 2. " TX_PSC_A3_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x06 1. " TX_PSC_A3_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " TX_PSC_A3_0 ,TX driver enable" "Disabled,Enabled" line.word 0x08 "LANE1_TX_PSC_A4,Transmitter A4 Power State Definition Register Lane 1" bitfld.word 0x08 14. " TX_PSC_A4_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x08 13. " TX_PSC_A4_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x08 12. " TX_PSC_A4_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x08 11. " TX_PSC_A4_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x08 10. " TX_PSC_A4_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x08 9. " TX_PSC_A4_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x08 8. " TX_PSC_A4_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x08 7. " TX_PSC_A4_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " TX_PSC_A4_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x08 5. " TX_PSC_A4_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x08 4. " TX_PSC_A4_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x08 3. " TX_PSC_A4_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x08 2. " TX_PSC_A4_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x08 1. " TX_PSC_A4_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " TX_PSC_A4_0 ,TX driver enable" "Disabled,Enabled" line.word 0x0A "LANE1_TX_PSC_A5,Transmitter A5 Power State Definition Register Lane 1" bitfld.word 0x0A 14. " TX_PSC_A5_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x0A 13. " TX_PSC_A5_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 12. " TX_PSC_A5_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x0A 11. " TX_PSC_A5_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 10. " TX_PSC_A5_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x0A 9. " TX_PSC_A5_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 8. " TX_PSC_A5_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x0A 7. " TX_PSC_A5_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x0A 6. " TX_PSC_A5_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x0A 5. " TX_PSC_A5_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x0A 4. " TX_PSC_A5_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x0A 3. " TX_PSC_A5_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 2. " TX_PSC_A5_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x0A 1. " TX_PSC_A5_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 0. " TX_PSC_A5_0 ,TX driver enable" "Disabled,Enabled" line.word 0x0C "LANE1_TX_PSC_CAL,Transmitter Calibration Power State Definition Register Lane 1" bitfld.word 0x0C 14. " TX_PSC_CAL_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x0C 13. " TX_PSC_CAL_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 12. " TX_PSC_CAL_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x0C 11. " TX_PSC_CAL_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 10. " TX_PSC_CAL_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x0C 9. " TX_PSC_CAL_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 8. " TX_PSC_CAL_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x0C 7. " TX_PSC_CAL_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " TX_PSC_CAL_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x0C 5. " TX_PSC_CAL_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x0C 4. " TX_PSC_CAL_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x0C 3. " TX_PSC_CAL_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 2. " TX_PSC_CAL_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x0C 1. " TX_PSC_CAL_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 0. " TX_PSC_CAL_0 ,TX driver enable" "Disabled,Enabled" line.word 0x0E "LANE1_TX_PSC_RDY,Transmitter Ready Power State Definition Register Lane 1" bitfld.word 0x0E 14. " TX_PSC_RDY_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x0E 13. " TX_PSC_RDY_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 12. " TX_PSC_RDY_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x0E 11. " TX_PSC_RDY_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 10. " TX_PSC_RDY_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x0E 9. " TX_PSC_RDY_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 8. " TX_PSC_RDY_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x0E 7. " TX_PSC_RDY_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x0E 6. " TX_PSC_RDY_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x0E 5. " TX_PSC_RDY_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x0E 4. " TX_PSC_RDY_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x0E 3. " TX_PSC_RDY_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 2. " TX_PSC_RDY_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x0E 1. " TX_PSC_RDY_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 0. " TX_PSC_RDY_0 ,TX driver enable" "Disabled,Enabled" group.word (0x4400+0x240)++0x07 line.word 0x00 "LANE1_TX_RCVDET_CTRL,Transmit Receiver Detect Control Register Lane 1" bitfld.word 0x00 15. " TX_RCVDET_CTRL_15 ,Start receiver detect" "Not started,Started" rbitfld.word 0x00 14. " TX_RCVDET_CTRL_14 ,Receiver detect process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " TX_RCVDET_CTRL_13 ,Receiver detected" "Not detected,Detected" line.word 0x02 "LANE1_TX_RCVDET_OVRD,Transmit Receiver Detect Override Register Lane 1" bitfld.word 0x02 15. " TX_RCVDET_OVRD_15 ,Receiver detect override enable" "Disabled,Enabled" bitfld.word 0x02 14. " TX_RCVDET_OVRD_14 ,Receiver detect override" "No override,Override" line.word 0x04 "LANE1_TX_RCVDET_EN_TMR,Transmit Receiver Detect Enable Timer Register Lane 1" hexmask.word 0x04 0.--11. 1. " TX_RCVDET_EN_TMR_11_0 ,Enable wait time value" line.word 0x06 "LANE1_TX_RCVDET_ST_TMR,Transmit Receiver Detect Start Timer Register Lane 1" hexmask.word 0x06 0.--11. 1. " TX_RCVDET_ST_TMR_11_0 ,Start wait time value" group.word (0x4400+0x280)++0x01 line.word 0x00 "LANE1_TX_BIST_CTRL,Transmit BIST Control Register Lane 1" bitfld.word 0x00 8.--11. " TX_BIST_CTRL_11_8 ,Transmitter BIST mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4. " TX_BIST_CTRL_4 ,Transmitter BIST force error" "Not forced,Forced" textline " " bitfld.word 0x00 1. " TX_BIST_CTRL_1 ,Transmitter BIST user defined data FIFO clear" "No clear,Clear" bitfld.word 0x00 0. " TX_BIST_CTRL_0 ,Transmitter BIST enable" "Disabled,Enabled" wgroup.word (0x4400+0x282)++0x01 line.word 0x00 "LANE1_TX_BIST_UDDWR,Transmit BIST User Defined Data Write Register Lane 1" hexmask.word 0x00 0.--9. 1. " TX_BIST_UDDWR_9_0 ,Transmitter BIST user defined data" group.word (0x4400+0x284)++0x03 line.word 0x00 "LANE1_TX_BIST_SEED0,Transmit BIST PRBS Seed 0 Register Lane 1" line.word 0x02 "LANE1_TX_BIST_SEED1,Transmit BIST PRBS Seed 1 Register Lane 1" hexmask.word 0x02 0.--14. 1. " TX_BIST_SEED1_14_0 ,Transmitter BIST PRBS seed (30:16)" group.word (0x4400+0x3C0)++0x0B line.word 0x00 "LANE1_TX_DIAG_TX_CTRL,TX Control Register Lane 1" bitfld.word 0x00 15. " TX_DIAG_TX_CTRL_15 ,TX serializer clock invert" "Not inverted,Inverted" bitfld.word 0x00 6.--7. " TX_DIAG_TX_CTRL_7_6 ,TX interface sub-rate standard mode 3" "0,1,2,3" textline " " bitfld.word 0x00 4.--5. " TX_DIAG_TX_CTRL_7_6 ,TX interface sub-rate standard mode 2" "0,1,2,3" bitfld.word 0x00 2.--3. " TX_DIAG_TX_CTRL_3_2 ,TX interface sub-rate standard mode 1" "0,1,2,3" textline " " bitfld.word 0x00 0.--1. " TX_DIAG_TX_CTRL_1_0 ,TX interface sub-rate standard mode 0" "0,1,2,3" line.word 0x02 "LANE1_TX_DIAG_TX_DRV,TX Driver Control Register Lane 1" bitfld.word 0x02 13. " TX_DIAG_TX_DRV_13 ,Transmitter reset pull down override enable" "Disabled,Enabled" bitfld.word 0x02 12. " TX_DIAG_TX_DRV_12 ,Transmitter reset pull down override" "Disabled,Enabled" textline " " bitfld.word 0x02 10. " TX_DIAG_TX_DRV_10 ,TX driver programmable boost enable" "Disabled,Enabled" bitfld.word 0x02 8.--9. " TX_DIAG_TX_DRV_9_8 ,TX driver programmable boost level" "0,1,2,3" textline " " bitfld.word 0x02 7. " TX_DIAG_TX_DRV_7 ,TX driver LDO bandgap dependent feedback reference enable" "Disabled,Enabled" bitfld.word 0x02 6. " TX_DIAG_TX_DRV_6 ,TX driver LDO bandgap dependent reference enable" "Disabled,Enabled" textline " " bitfld.word 0x02 5. " TX_DIAG_TX_DRV_5 ,TX driver LDO VDD dependent feedback reference enable" "Disabled,Enabled" bitfld.word 0x02 4. " TX_DIAG_TX_DRV_4 ,TX driver LDO VDD dependent reference enable" "Disabled,Enabled" textline " " bitfld.word 0x02 2. " TX_DIAG_TX_DRV_2 ,TD driver polarity control" "Low,High" bitfld.word 0x02 1. " TX_DIAG_TX_DRV_1 ,TX pre-driver pull up control" "0,1" textline " " bitfld.word 0x02 0. " TX_DIAG_TX_DRV_0 ,TX driver margin type" "0,1" line.word 0x04 "LANE1_TX_DIAG_ELEC_IDLE,TX Electrical Idle Diagnostic Register Lane 1" bitfld.word 0x04 4.--7. " TX_DIAG_ELEC_IDLE_7_4 ,TX electrical idle exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x04 0.--3. " TX_DIAG_ELEC_IDLE_3_0 ,TX electrical idle entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x06 "LANE1_TX_DIAG_SFIFO_CTRL,TX Sync FIFO Diagnostic Control Register Lane 1" bitfld.word 0x06 4. " TX_DIAG_SFIFO_CTRL_4 ,FIFO enqueue pointer bump" "Not decremented,Decremented" rbitfld.word 0x06 3. " TX_DIAG_SFIFO_CTRL_3 ,FIFO alignment error" "No error,Error" textline " " rbitfld.word 0x06 2. " TX_DIAG_SFIFO_CTRL_2 ,FIFO alignment acknowledge" "Not acknowledged,Acknowledged" bitfld.word 0x06 1. " TX_DIAG_SFIFO_CTRL_1 ,FIFO alignment enable override enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " TX_DIAG_SFIFO_CTRL_0 ,FIFO alignment enable override" "Disabled,Enabled" line.word 0x08 "LANE1_TX_DIAG_SFIFO_TMR,TX Sync FIFO Diagnostic Timer Register Lane 1" bitfld.word 0x08 8.--13. " TX_DIAG_SFIFO_TMR_13_8 ,FIFO alignment settle delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x08 0.--5. " TX_DIAG_SFIFO_TMR_5_0 ,FIFO alignment detect delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0A "LANE1_TX_DIAG_RDVDET_TUNE,TX Receiver Detect Tuning Register Lane 1" bitfld.word 0x0A 0.--1. " TX_DIAG_RDVDET_TUNE_1_0 ,Receiver detect reference DAC voltage" "0,1,2,3" rgroup.word (0x4400+0x3CC)++0x01 line.word 0x00 "LANE1_TX_DIAG_RST_DIAG,Transmitter Control Reset Diagnostic Register Lane 1" bitfld.word 0x00 8. " TX_DIAG_RST_DIAG_8 ,Current state of the dsync_power_reset_n reset" "No reset,Reset" bitfld.word 0x00 7. " TX_DIAG_RST_DIAG_7 ,Current state of the tfunc_power_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 6. " TX_DIAG_RST_DIAG_6 ,Current state of the xcal1_power_reset_n reset" "No reset,Reset" bitfld.word 0x00 5. " TX_DIAG_RST_DIAG_5 ,Current state of the xcaln_power_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 4. " TX_DIAG_RST_DIAG_4 ,Current state of the txda_tx_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 3. " TX_DIAG_RST_DIAG_3 ,Current state of the tx_dig_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 2. " TX_DIAG_RST_DIAG_2 ,Current state of the tx_sync_fifo_deq_rst_n reset" "No reset,Reset" bitfld.word 0x00 1. " TX_DIAG_RST_DIAG_1 ,Current state of the tx_sync_fifo_enq_rst_n reset" "No reset,Reset" textline " " bitfld.word 0x00 0. " TX_DIAG_RST_DIAG_0 ,Current state of the tx_lfps_reset_n reset" "No reset,Reset" group.word (0x4400+0x3CE)++0x05 line.word 0x00 "LANE1_TX_DIAG_BGREF_PREDRV_DELAY,TX Bandgap Reference And Pre-Drive Enable Delay Register Lane 1" hexmask.word.byte 0x00 0.--7. 1. " TX_DIAG_BGREF_PREDRV_DELAY_7_0 ,TX bandgap reference and pre-drive enable delay" line.word 0x02 "LANE1_TX_DIAG_MPHY_CTRL1,TX MPHY Control Register 1 Lane1" bitfld.word 0x02 8.--11. " TX_DIAG_MPHY_CTRL1_11_8 ,Register definition to be provided by the analog team" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x02 4. " TX_DIAG_MPHY_CTRL1_4 ,MPHY small amplitude mode" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " TX_DIAG_MPHY_CTRL1_3 ,AUX bias current enable" "Disabled,Enabled" bitfld.word 0x02 2. " TX_DIAG_MPHY_CTRL1_2 ,LDO no-load current reduce" "Not reduced,Reduced" textline " " bitfld.word 0x02 1. " TX_DIAG_MPHY_CTRL1_1 ,Register definition to be provided by the analog team" "0,1" bitfld.word 0x02 0. " TX_DIAG_MPHY_CTRL1_0 ,MPHY high load current mode enable" "Disabled,Enabled" line.word 0x04 "LANE1_TX_DIAG_MPHY_CTRL2,TX MPHY Control Register 2 Lane 1" bitfld.word 0x04 8.--11. " TX_DIAG_MPHY_CTRL2_11_8 ,Register definition to be provided by the analog team" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word.byte 0x04 0.--7. 1. " TX_DIAG_MPHY_CTRL2_7_0 ,MPHY slew rate control" group.word (0x4400+0x3E8)++0x03 line.word 0x00 "LANE1_TX_DIAG_DRV_LDO_PROG,TX Driver LDO Programming Register Lane 1" line.word 0x02 "LANE1_TX_DIAG_ECTRL_OVRD,TX Extra Enable Control Override Register Lane 1" bitfld.word 0x02 3. " TX_DIAG_ECTRL_OVRD_3 ,Driver pre-drive enable override enable" "Disabled,Enabled" bitfld.word 0x02 2. " TX_DIAG_ECTRL_OVRD_2 ,Driver pre-drive enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 1. " TX_DIAG_ECTRL_OVRD_1 ,Bandgap reference enable override enable" "Disabled,Enabled" bitfld.word 0x02 0. " TX_DIAG_ECTRL_OVRD_0 ,Bandgap reference enable override" "Disabled,Enabled" group.word 0x4800++0x21 line.word 0x00 "LANE2_XCVR_PSM_CTRL,Power State Machine Control Register Lane 2" bitfld.word 0x00 14. " XCVR_PSM_CTRL_14 ,Bypass A0 in delay from PSM ready" "Not bypassed,Bypassed" bitfld.word 0x00 13. " XCVR_PSM_CTRL_13 ,Bypass A0 in delay from A5" "Not bypassed,Bypassed" textline " " bitfld.word 0x00 12. " XCVR_PSM_CTRL_12 ,Bypass A0 in delay from A4" "Not bypassed,Bypassed" bitfld.word 0x00 11. " XCVR_PSM_CTRL_11 ,Bypass A0 in delay from A3" "Not bypassed,Bypassed" textline " " bitfld.word 0x00 10. " XCVR_PSM_CTRL_10 ,Bypass A0 in delay from A2" "Not bypassed,Bypassed" bitfld.word 0x00 9. " XCVR_PSM_CTRL_9 ,Bypass A0 in delay from A1" "Not bypassed,Bypassed" textline " " bitfld.word 0x00 0. " XCVR_PSM_CTRL_0 ,Skip lane re-calibration" "Not skipped,Skipped" line.word 0x02 "LANE2_XCVR_PSM_RCTRL,Power State Machine Reset Control Register Lane 2" bitfld.word 0x02 15. " XCVR_PSM_RCTRL_15 ,RX reset active ready" "No reset,Reset" bitfld.word 0x02 14. " XCVR_PSM_RCTRL_14 ,RX reset active calibration" "No reset,Reset" textline " " bitfld.word 0x02 13. " XCVR_PSM_RCTRL_13 ,RX reset active A5" "No reset,Reset" bitfld.word 0x02 12. " XCVR_PSM_RCTRL_12 ,RX reset active A4" "No reset,Reset" textline " " bitfld.word 0x02 11. " XCVR_PSM_RCTRL_11 ,RX reset active A3" "No reset,Reset" bitfld.word 0x02 10. " XCVR_PSM_RCTRL_10 ,RX reset active A2" "No reset,Reset" textline " " bitfld.word 0x02 9. " XCVR_PSM_RCTRL_9 ,RX reset active A1" "No reset,Reset" bitfld.word 0x02 8. " XCVR_PSM_RCTRL_8 ,RX reset active A0" "No reset,Reset" textline " " bitfld.word 0x02 7. " XCVR_PSM_RCTRL_7 ,TX reset active ready" "No reset,Reset" bitfld.word 0x02 6. " XCVR_PSM_RCTRL_6 ,TX reset active calibration" "No reset,Reset" textline " " bitfld.word 0x02 5. " XCVR_PSM_RCTRL_5 ,TX reset active A5" "No reset,Reset" bitfld.word 0x02 4. " XCVR_PSM_RCTRL_4 ,TX reset active A4" "No reset,Reset" textline " " bitfld.word 0x02 3. " XCVR_PSM_RCTRL_3 ,TX reset active A3" "No reset,Reset" bitfld.word 0x02 2. " XCVR_PSM_RCTRL_2 ,TX reset active A2" "No reset,Reset" textline " " bitfld.word 0x02 1. " XCVR_PSM_RCTRL_1 ,TX reset active A1" "No reset,Reset" bitfld.word 0x02 0. " XCVR_PSM_RCTRL_0 ,TX reset active A0" "No reset,Reset" line.word 0x04 "LANE2_XCVR_PSM_CAL_TMR,PSM Calibration Delay Timer Register Lane 2" hexmask.word 0x04 0.--9. 1. " XCVR_PSM_CAL_TMR_9_0 ,PSM calibration delay state timer value" line.word 0x06 "LANE2_XCVR_PSM_A0IN_TMR,A0 In Delay Timer Register Lane 2" hexmask.word 0x06 0.--9. 1. " XCVR_PSM_A0IN_TMR_9_0 ,A0 in delay state timer value" line.word 0x08 "LANE2_XCVR_PSM_A0BYP_TMR,A0 In Bypass Timer Register Lane 2" bitfld.word 0x08 0.--4. " XCVR_PSM_A0BYP_TMR_4_0 ,A0 in delay state bypass timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0A "LANE2_XCVR_PSM_A1IN_TMR,A1 In Delay Timer Register Lane 2" bitfld.word 0x0A 0.--4. " XCVR_PSM_A1IN_TMR_4_0 ,A1 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "LANE2_XCVR_PSM_A2IN_TMR,A2 In Delay Timer Register Lane 2" bitfld.word 0x0C 0.--4. " XCVR_PSM_A2IN_TMR_4_0 ,A2 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0E "LANE2_XCVR_PSM_A3IN_TMR,A3 In Delay Timer Register Lane 2" bitfld.word 0x0E 0.--4. " XCVR_PSM_A3IN_TMR_4_0 ,A3 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "LANE2_XCVR_PSM_A4IN_TMR,A4 In Delay Timer Register Lane 2" bitfld.word 0x10 0.--4. " XCVR_PSM_A4IN_TMR_4_0 ,A4 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x12 "LANE2_XCVR_PSM_A5IN_TMR,A5 In Delay Timer Register Lane 2" bitfld.word 0x12 0.--4. " XCVR_PSM_A5IN_TMR_4_0 ,A5 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "LANE2_XCVR_PSM_A0OUT_TMR,A0 Out Delay Timer Register Lane 2" bitfld.word 0x14 0.--4. " XCVR_PSM_A0OUT_TMR_4_0 ,A0 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x16 "LANE2_XCVR_PSM_A1OUT_TMR,A1 Out Delay Timer Register Lane 2" bitfld.word 0x16 0.--4. " XCVR_PSM_A1OUT_TMR_4_0 ,A1 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x18 "LANE2_XCVR_PSM_A2OUT_TMR,A2 Out Delay Timer Register Lane 2" bitfld.word 0x18 0.--4. " XCVR_PSM_A2OUT_TMR_4_0 ,A2 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x1A "LANE2_XCVR_PSM_A3OUT_TMR,A3 Out Delay Timer Register Lane 2" bitfld.word 0x1A 0.--4. " XCVR_PSM_A3OUT_TMR_4_0 ,A3 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x1C "LANE2_XCVR_PSM_A4OUT_TMR,A4 Out Delay Timer Register Lane 2" bitfld.word 0x1C 0.--4. " XCVR_PSM_A4OUT_TMR_4_0 ,A4 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x1E "LANE2_XCVR_PSM_A5OUT_TMR,A5 Out Delay Timer Register Lane 2" bitfld.word 0x1E 0.--4. " XCVR_PSM_A5OUT_TMR_4_0 ,A5 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x20 "LANE2_XCVR_PSM_DIAG,Power State Machine Diagnostic Register Lane 2" bitfld.word 0x20 13. " XCVR_PSM_DIAG_13 ,Force A5 exit acknowledge" "Not forced,Forced" bitfld.word 0x20 12. " XCVR_PSM_DIAG_12 ,Force A4 exit acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 11. " XCVR_PSM_DIAG_11 ,Force A3 exit acknowledge" "Not forced,Forced" bitfld.word 0x20 10. " XCVR_PSM_DIAG_10 ,Force A2 exit acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 9. " XCVR_PSM_DIAG_9 ,Force A1 exit acknowledge" "Not forced,Forced" bitfld.word 0x20 8. " XCVR_PSM_DIAG_8 ,Force A0 exit acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 5. " XCVR_PSM_DIAG_5 ,Force A5 entry acknowledge" "Not forced,Forced" bitfld.word 0x20 4. " XCVR_PSM_DIAG_4 ,Force A4 entry acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 3. " XCVR_PSM_DIAG_3 ,Force A3 entry acknowledge" "Not forced,Forced" bitfld.word 0x20 2. " XCVR_PSM_DIAG_2 ,Force A2 entry acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 1. " XCVR_PSM_DIAG_1 ,Force A1 entry acknowledge" "Not forced,Forced" bitfld.word 0x20 0. " XCVR_PSM_DIAG_0 ,Force A0 entry acknowledge" "Not forced,Forced" group.word (0x4800+0x3E)++0x01 line.word 0x00 "LANE2_XCVR_PSM_USER_DEF_CTRL,Power State Machine User Defined Control Register Lane 2" bitfld.word 0x00 1. " XCVR_PSM_USER_DEF_CTRL_1 ,Disable PSM clock gating" "No,Yes" bitfld.word 0x00 0. " XCVR_PSM_USER_DEF_CTRL_0 ,Disable early A0 acknowledge response" "No,Yes" group.word (0x4800+0x82)++0x05 line.word 0x00 "LANE2_TX_TXCC_PRE_OVRD,TX Pre-Cursor Override Register Lane 2" bitfld.word 0x00 8. " TX_TXCC_PRE_OVRD_8 ,Pre-cursor override enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " TX_TXCC_PRE_OVRD_5_0 ,Pre-cursor override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE2_TX_TXCC_MAIN_OVRD,TX Main-Cursor Override Register Lane 2" bitfld.word 0x02 8. " TX_TXCC_MAIN_OVRD_8 ,Main-cursor override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " TX_TXCC_MAIN_OVRD_5_0 ,Main-cursor override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE2_TX_TXCC_POST_OVRD,TX Post-Cursor Override Register Lane 2" bitfld.word 0x04 8. " TX_TXCC_POST_OVRD_8 ,Post-cursor override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " TX_TXCC_POST_OVRD_5_0 ,Post-cursor override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.word (0x4800+0x88)++0x05 line.word 0x00 "LANE2_TX_TXCC_PRE_CVAL,TX Pre-Cursor Current Value Register 2" bitfld.word 0x00 0.--5. " TX_TXCC_PRE_CVAL_5_0 ,Pre-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE2_TX_TXCC_MAIN_CVAL,TX Main-Cursor Current Value Register 2" bitfld.word 0x02 0.--5. " TX_TXCC_MAIN_CVAL_5_0 ,Main-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE2_TX_TXCC_POST_CVAL,TX Post-Cursor Current Value Register 2" bitfld.word 0x04 0.--5. " TX_TXCC_POST_CVAL_5_0 ,Post-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x4800+0x8E)++0x31 line.word 0x00 "LANE2_TX_TXCC_CAL_SCLR_MULT,Resistor Calibration Code Scaler Multiplier Value Register Lane 2" bitfld.word 0x00 8. " TX_TXCC_CAL_SCLR_MULT_8 ,Scaled resistor calibration code add" "0,1" hexmask.word.byte 0x00 0.--7. 1. " TX_TXCC_CAL_SCLR_MULT_7_0 ,Resistor calibration multiplier value" line.word 0x02 "LANE2_TX_TXCC_CPRE_MULT_00,Calculated Pre Emphasis Multiplier Value 00 Register Lane 2" hexmask.word.byte 0x02 0.--7. 1. " TX_TXCC_CPRE_MULT_00_7_0 ,Calculated pre emphasis multiplier value 00" line.word 0x04 "LANE2_TX_TXCC_CPRE_MULT_01,Calculated Pre Emphasis Multiplier Value 01 Register Lane 2" hexmask.word.byte 0x04 0.--7. 1. " TX_TXCC_CPRE_MULT_01_7_0 ,Calculated pre emphasis multiplier value 01" line.word 0x06 "LANE2_TX_TXCC_CPRE_MULT_10,Calculated Pre Emphasis Multiplier Value 10 Register Lane 2" hexmask.word.byte 0x06 0.--7. 1. " TX_TXCC_CPRE_MULT_10_7_0 ,Calculated pre emphasis multiplier value 10" line.word 0x08 "LANE2_TX_TXCC_CPRE_MULT_11,Calculated Pre Emphasis Multiplier Value 11 Register Lane 2" hexmask.word.byte 0x08 0.--7. 1. " TX_TXCC_CPRE_MULT_11_7_0 ,Calculated pre emphasis multiplier value 11" line.word 0x0A "LANE2_TX_TXCC_CPOST_MULT_00,Calculated Post Emphasis Multiplier Value 00 Register Lane 2" hexmask.word.byte 0x0A 0.--7. 1. " TX_TXCC_CPOST_MULT_00_7_0 ,Calculated post emphasis multiplier value 00" line.word 0x0C "LANE2_TX_TXCC_CPOST_MULT_01,Calculated Post Emphasis Multiplier Value 01 Register Lane 2" hexmask.word.byte 0x0C 0.--7. 1. " TX_TXCC_CPOST_MULT_01_7_0 ,Calculated post emphasis multiplier value 01" line.word 0x0E "LANE2_TX_TXCC_CPOST_MULT_10,Calculated Post Emphasis Multiplier Value 10 Register Lane 2" hexmask.word.byte 0x0E 0.--7. 1. " TX_TXCC_CPOST_MULT_10_7_0 ,Calculated post emphasis multiplier value 10" line.word 0x10 "LANE2_TX_TXCC_CPOST_MULT_11,Calculated Post Emphasis Multiplier Value 11 Register Lane 2" hexmask.word.byte 0x10 0.--7. 1. " TX_TXCC_CPOST_MULT_11_7_0 ,Calculated post emphasis multiplier value 11" line.word 0x12 "LANE2_TX_TXCC_MGNFS_MULT_000,Margin Full Swing Multiplier Value 000 Register Lane 2" hexmask.word.byte 0x12 0.--7. 1. " TX_TXCC_MGNFS_MULT_000_7_0 ,Margin full swing multiplier value 000" line.word 0x14 "LANE2_TX_TXCC_MGNFS_MULT_001,Margin Full Swing Multiplier Value 001 Register Lane 2" hexmask.word.byte 0x14 0.--7. 1. " TX_TXCC_MGNFS_MULT_001_7_0 ,Margin full swing multiplier value 001" line.word 0x16 "LANE2_TX_TXCC_MGNFS_MULT_010,Margin Full Swing Multiplier Value 010 Register Lane 2" hexmask.word.byte 0x16 0.--7. 1. " TX_TXCC_MGNFS_MULT_010_7_0 ,Margin full swing multiplier value 010" line.word 0x18 "LANE2_TX_TXCC_MGNFS_MULT_011,Margin Full Swing Multiplier Value 011 Register Lane 2" hexmask.word.byte 0x18 0.--7. 1. " TX_TXCC_MGNFS_MULT_011_7_0 ,Margin full swing multiplier value 011" line.word 0x1A "LANE2_TX_TXCC_MGNFS_MULT_100,Margin Full Swing Multiplier Value 100 Register Lane 2" hexmask.word.byte 0x1A 0.--7. 1. " TX_TXCC_MGNFS_MULT_100_7_0 ,Margin full swing multiplier value 100" line.word 0x1C "LANE2_TX_TXCC_MGNFS_MULT_101,Margin Full Swing Multiplier Value 101 Register Lane 2" hexmask.word.byte 0x1C 0.--7. 1. " TX_TXCC_MGNFS_MULT_101_7_0 ,Margin full swing multiplier value 101" line.word 0x1E "LANE2_TX_TXCC_MGNFS_MULT_110,Margin Full Swing Multiplier Value 110 Register Lane 2" hexmask.word.byte 0x1E 0.--7. 1. " TX_TXCC_MGNFS_MULT_110_7_0 ,Margin full swing multiplier value 110" line.word 0x20 "LANE2_TX_TXCC_MGNFS_MULT_111,Margin Full Swing Multiplier Value 111 Register Lane 2" hexmask.word.byte 0x20 0.--7. 1. " TX_TXCC_MGNFS_MULT_111_7_0 ,Margin full swing multiplier value 111" line.word 0x22 "LANE2_TX_TXCC_MGNLS_MULT_000,Margin Half Swing Multiplier Value 000 Register Lane 2" hexmask.word.byte 0x22 0.--7. 1. " TX_TXCC_MGNLS_MULT_000_7_0 ,Margin half swing multiplier value 000" line.word 0x24 "LANE2_TX_TXCC_MGNLS_MULT_001,Margin Half Swing Multiplier Value 001 Register Lane 2" hexmask.word.byte 0x24 0.--7. 1. " TX_TXCC_MGNLS_MULT_001_7_0 ,Margin half swing multiplier value 001" line.word 0x26 "LANE2_TX_TXCC_MGNLS_MULT_010,Margin Half Swing Multiplier Value 010 Register Lane 2" hexmask.word.byte 0x26 0.--7. 1. " TX_TXCC_MGNLS_MULT_010_7_0 ,Margin half swing multiplier value 010" line.word 0x28 "LANE2_TX_TXCC_MGNLS_MULT_011,Margin Half Swing Multiplier Value 011 Register Lane 2" hexmask.word.byte 0x28 0.--7. 1. " TX_TXCC_MGNLS_MULT_011_7_0 ,Margin half swing multiplier value 011" line.word 0x2A "LANE2_TX_TXCC_MGNLS_MULT_100,Margin Half Swing Multiplier Value 100 Register Lane 2" hexmask.word.byte 0x2A 0.--7. 1. " TX_TXCC_MGNLS_MULT_100_7_0 ,Margin half swing multiplier value 100" line.word 0x2C "LANE2_TX_TXCC_MGNLS_MULT_101,Margin Half Swing Multiplier Value 101 Register Lane 2" hexmask.word.byte 0x2C 0.--7. 1. " TX_TXCC_MGNLS_MULT_101_7_0 ,Margin half swing multiplier value 101" line.word 0x2E "LANE2_TX_TXCC_MGNLS_MULT_110,Margin Half Swing Multiplier Value 110 Register Lane 2" hexmask.word.byte 0x2E 0.--7. 1. " TX_TXCC_MGNLS_MULT_110_7_0 ,Margin half swing multiplier value 110" line.word 0x30 "LANE2_TX_TXCC_MGNLS_MULT_111,Margin Half Swing Multiplier Value 111 Register Lane 2" hexmask.word.byte 0x30 0.--7. 1. " TX_TXCC_MGNLS_MULT_111_7_0 ,Margin half swing multiplier value 111" group.word (0x4800+0x1C0)++0x07 line.word 0x00 "LANE2_XCVR_DIAG_PLLDRC_CTRL,Transceiver PLL Data Rate Clock Control Register Lane 2" bitfld.word 0x00 14. " XCVR_DIAG_PLLDRC_CTRL_14 ,Digital PLL clock select standard mode 3" "Not selected,Selected" bitfld.word 0x00 12.--13. " XCVR_DIAG_PLLDRC_CTRL_13_12 ,Digital PLL data rate divider standard mode 3 value" "0,1,2,3" textline " " bitfld.word 0x00 10. " XCVR_DIAG_PLLDRC_CTRL_10 ,Digital PLL clock select standard mode 2" "Not selected,Selected" bitfld.word 0x00 8.--9. " XCVR_DIAG_PLLDRC_CTRL_9_8 ,Digital PLL data rate divider standard mode 2 value" "0,1,2,3" textline " " bitfld.word 0x00 6. " XCVR_DIAG_PLLDRC_CTRL_6 ,Digital PLL clock select standard mode 1" "Not selected,Selected" bitfld.word 0x00 4.--5. " XCVR_DIAG_PLLDRC_CTRL_5_4 ,Digital PLL data rate divider standard mode 1 value" "0,1,2,3" textline " " bitfld.word 0x00 2. " XCVR_DIAG_PLLDRC_CTRL_2 ,Digital PLL clock select standard mode 0" "Not selected,Selected" bitfld.word 0x00 0.--1. " XCVR_DIAG_PLLDRC_CTRL_0_1 ,Digital PLL data rate divider standard mode 0 value" "0,1,2,3" line.word 0x02 "LANE2_XCVR_DIAG_HSCLK_SEL,Transceiver High Speed Clock Select Register Lane 2" bitfld.word 0x02 12.--13. " XCVR_DIAG_HSCLK_SEL_13_12 ,High speed clock select standard mode 3" "0,1,2,3" bitfld.word 0x02 8.--9. " XCVR_DIAG_HSCLK_SEL_9_8 ,High speed clock select standard mode 2" "0,1,2,3" textline " " bitfld.word 0x02 4.--5. " XCVR_DIAG_HSCLK_SEL_5_4 ,High speed clock select standard mode 1" "0,1,2,3" bitfld.word 0x02 0.--1. " XCVR_DIAG_HSCLK_SEL_5_4 ,High speed clock select standard mode 0" "0,1,2,3" line.word 0x04 "LANE2_XCVR_DIAG_HSCLKA_DCTRL,Transceiver High Speed Clock A Divider Control Register Lane 2" bitfld.word 0x04 12.--13. " XCVR_DIAG_HSCLKA_DCTRL_13_12 ,Transceiver clock A (transmitter) divider control standard mode 3" "0,1,2,3" bitfld.word 0x04 8.--9. " XCVR_DIAG_HSCLKA_DCTRL_9_8 ,Transceiver clock A (transmitter) divider control standard mode 2" "0,1,2,3" textline " " bitfld.word 0x04 4.--5. " XCVR_DIAG_HSCLKA_DCTRL_5_4 ,Transceiver clock A (transmitter) divider control standard mode 1" "0,1,2,3" bitfld.word 0x04 0.--1. " XCVR_DIAG_HSCLKA_DCTRL_1_0 ,Transceiver clock A (transmitter) divider control standard mode 0" "0,1,2,3" line.word 0x06 "LANE2_XCVR_DIAG_HSCLKB_DCTRL,Transceiver High Speed Clock B Divider Control Register Lane 2" bitfld.word 0x06 12.--13. " XCVR_DIAG_HSCLKB_DCTRL_13_12 ,Transceiver clock B (transmitter) divider control standard mode 3" "0,1,2,3" bitfld.word 0x06 8.--9. " XCVR_DIAG_HSCLKB_DCTRL_9_8 ,Transceiver clock B (transmitter) divider control standard mode 2" "0,1,2,3" textline " " bitfld.word 0x06 4.--5. " XCVR_DIAG_HSCLKB_DCTRL_5_4 ,Transceiver clock B (transmitter) divider control standard mode 1" "0,1,2,3" bitfld.word 0x06 0.--1. " XCVR_DIAG_HSCLKB_DCTRL_1_0 ,Transceiver clock B (transmitter) divider control standard mode 0" "0,1,2,3" rgroup.word (0x4800+0x1CE)++0x01 line.word 0x00 "LANE2_XCVR_DIAG_RST_DIAG,Transceiver Control Reset Diagnostic Register Lane 2" bitfld.word 0x00 1. " XCVR_DIAG_RST_DIAG_1 ,Current state of the xcvr_psm_reset_n reset" "No reset,Reset" bitfld.word 0x00 0. " XCVR_DIAG_RST_DIAG_0 ,Current state of the xcvr_ref_clk_reset_n reset" "No reset,Reset" group.word (0x4800+0x1D0)++0x05 line.word 0x00 "LANE2_XCVR_DIAG_BIDI_CTRL,Transceiver Bidirectional Control Register Lane 2" bitfld.word 0x00 7. " XCVR_DIAG_BIDI_CTRL_7 ,Receiver enable standard mode 3" "Disabled,Enabled" bitfld.word 0x00 6. " XCVR_DIAG_BIDI_CTRL_6 ,Receiver enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " XCVR_DIAG_BIDI_CTRL_5 ,Receiver enable standard mode 1" "Disabled,Enabled" bitfld.word 0x00 4. " XCVR_DIAG_BIDI_CTRL_4 ,Receiver enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " XCVR_DIAG_BIDI_CTRL_3 ,Transmitter enable standard mode 3" "Disabled,Enabled" bitfld.word 0x00 2. " XCVR_DIAG_BIDI_CTRL_2 ,Transmitter enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " XCVR_DIAG_BIDI_CTRL_1 ,Transmitter enable standard mode 1" "Disabled,Enabled" bitfld.word 0x00 0. " XCVR_DIAG_BIDI_CTRL_0 ,Transmitter enable standard mode 0" "Disabled,Enabled" line.word 0x02 "LANE2_XCVR_DIAG_PWR_CTRL,Transceiver Power Island Control Register Lane 2" bitfld.word 0x02 15. " XCVR_DIAG_PWR_CTRL_15 ,Transceiver dsync power down disable" "No,Yes" bitfld.word 0x02 14. " XCVR_DIAG_PWR_CTRL_14 ,Transceiver calibration one time power down disable" "No,Yes" textline " " bitfld.word 0x02 13. " XCVR_DIAG_PWR_CTRL_13 ,Transceiver calibration multiples time power down disable" "No,Yes" bitfld.word 0x02 11. " XCVR_DIAG_PWR_CTRL_11 ,Transceiver test functions power enable" "Disabled,Enabled" line.word 0x04 "LANE2_XCVR_DIAG_RX_LANE_CAL_RST_TMR,RX Lane Calibration Reset Timer Register Lane 2" hexmask.word 0x04 0.--9. 1. " XCVR_DIAG_RX_LANE_CAL_RST_TMR_9_0 ,Lane calibration receiver reset timer value" group.word (0x4800+0x1E0)++0x07 line.word 0x00 "LANE2_XCVR_DIAG_LANE_FCM_EN_TO,Lane Fast Common Mode Enable Timeout Register Lane 2" hexmask.word 0x00 0.--11. 1. " XCVR_DIAG_LANE_FCM_EN_TO_11_0 ,Lane fast common mode enable timeout value" line.word 0x02 "LANE2_XCVR_DIAG_LANE_FCM_EN_SWAIT_TMR,Lane Fast Common Mode Enable Sample Wait Timer Register Lane 2" bitfld.word 0x02 0.--3. " XCVR_DIAG_LANE_FCM_EN_SWAIT_TMR_3_0 ,Lane fast common mode enable sample wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "LANE2_XCVR_DIAG_LANE_FCM_EN_MGN_TMR,Lane Fast Common Mode Enable Margin Timer Register Lane 2" hexmask.word 0x04 0.--11. 1. " XCVR_DIAG_LANE_FCM_EN_MGN_TMR_11_0 ,Lane fast common mode enable margin timer value" line.word 0x06 "LANE2_XCVR_DIAG_LANE_FCM_EN_TUNE,Lane Fast Common Mode Enable Tuning Register Lane 2" bitfld.word 0x06 8.--9. " XCVR_DIAG_LANE_FCM_EN_TUNE_9_8 ,Common mode sense reference DAC voltage initial test" "0,1,2,3" bitfld.word 0x06 4.--5. " XCVR_DIAG_LANE_FCM_EN_TUNE_5_4 ,Common mode sense reference DAC voltage high test" "0,1,2,3" textline " " bitfld.word 0x06 0.--1. " XCVR_DIAG_LANE_FCM_EN_TUNE_1_0 ,Common mode sense reference DAC voltage low test" "0,1,2,3" group.word (0x4800+0x200)++0x0F line.word 0x00 "LANE2_TX_PSC_A0,Transmitter A0 Power State Definition Register Lane 2" bitfld.word 0x00 14. " TX_PSC_A0_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x00 13. " TX_PSC_A0_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TX_PSC_A0_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x00 11. " TX_PSC_A0_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " TX_PSC_A0_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x00 9. " TX_PSC_A0_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " TX_PSC_A0_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x00 7. " TX_PSC_A0_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TX_PSC_A0_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x00 5. " TX_PSC_A0_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TX_PSC_A0_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x00 3. " TX_PSC_A0_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TX_PSC_A0_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x00 1. " TX_PSC_A0_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TX_PSC_A0_0 ,TX driver enable" "Disabled,Enabled" line.word 0x02 "LANE2_TX_PSC_A1,Transmitter A1 Power State Definition Register Lane 2" bitfld.word 0x02 14. " TX_PSC_A1_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x02 13. " TX_PSC_A1_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " TX_PSC_A1_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x02 11. " TX_PSC_A1_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x02 10. " TX_PSC_A1_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x02 9. " TX_PSC_A1_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x02 8. " TX_PSC_A1_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x02 7. " TX_PSC_A1_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " TX_PSC_A1_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x02 5. " TX_PSC_A1_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x02 4. " TX_PSC_A1_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x02 3. " TX_PSC_A1_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x02 2. " TX_PSC_A1_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x02 1. " TX_PSC_A1_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " TX_PSC_A1_0 ,TX driver enable" "Disabled,Enabled" line.word 0x04 "LANE2_TX_PSC_A2,Transmitter A2 Power State Definition Register Lane 2" bitfld.word 0x04 14. " TX_PSC_A2_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x04 13. " TX_PSC_A2_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x04 12. " TX_PSC_A2_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x04 11. " TX_PSC_A2_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x04 10. " TX_PSC_A2_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x04 9. " TX_PSC_A2_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x04 8. " TX_PSC_A2_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x04 7. " TX_PSC_A2_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " TX_PSC_A2_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x04 5. " TX_PSC_A2_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x04 4. " TX_PSC_A2_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x04 3. " TX_PSC_A2_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x04 2. " TX_PSC_A2_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x04 1. " TX_PSC_A2_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x04 0. " TX_PSC_A2_0 ,TX driver enable" "Disabled,Enabled" line.word 0x06 "LANE2_TX_PSC_A3,Transmitter A3 Power State Definition Register Lane 2" bitfld.word 0x06 14. " TX_PSC_A3_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x06 13. " TX_PSC_A3_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x06 12. " TX_PSC_A3_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x06 11. " TX_PSC_A3_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x06 10. " TX_PSC_A3_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x06 9. " TX_PSC_A3_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x06 8. " TX_PSC_A3_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x06 7. " TX_PSC_A3_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " TX_PSC_A3_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x06 5. " TX_PSC_A3_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " TX_PSC_A3_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x06 3. " TX_PSC_A3_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x06 2. " TX_PSC_A3_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x06 1. " TX_PSC_A3_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " TX_PSC_A3_0 ,TX driver enable" "Disabled,Enabled" line.word 0x08 "LANE2_TX_PSC_A4,Transmitter A4 Power State Definition Register Lane 2" bitfld.word 0x08 14. " TX_PSC_A4_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x08 13. " TX_PSC_A4_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x08 12. " TX_PSC_A4_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x08 11. " TX_PSC_A4_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x08 10. " TX_PSC_A4_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x08 9. " TX_PSC_A4_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x08 8. " TX_PSC_A4_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x08 7. " TX_PSC_A4_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " TX_PSC_A4_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x08 5. " TX_PSC_A4_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x08 4. " TX_PSC_A4_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x08 3. " TX_PSC_A4_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x08 2. " TX_PSC_A4_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x08 1. " TX_PSC_A4_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " TX_PSC_A4_0 ,TX driver enable" "Disabled,Enabled" line.word 0x0A "LANE2_TX_PSC_A5,Transmitter A5 Power State Definition Register Lane 2" bitfld.word 0x0A 14. " TX_PSC_A5_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x0A 13. " TX_PSC_A5_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 12. " TX_PSC_A5_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x0A 11. " TX_PSC_A5_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 10. " TX_PSC_A5_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x0A 9. " TX_PSC_A5_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 8. " TX_PSC_A5_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x0A 7. " TX_PSC_A5_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x0A 6. " TX_PSC_A5_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x0A 5. " TX_PSC_A5_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x0A 4. " TX_PSC_A5_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x0A 3. " TX_PSC_A5_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 2. " TX_PSC_A5_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x0A 1. " TX_PSC_A5_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 0. " TX_PSC_A5_0 ,TX driver enable" "Disabled,Enabled" line.word 0x0C "LANE2_TX_PSC_CAL,Transmitter Calibration Power State Definition Register Lane 2" bitfld.word 0x0C 14. " TX_PSC_CAL_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x0C 13. " TX_PSC_CAL_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 12. " TX_PSC_CAL_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x0C 11. " TX_PSC_CAL_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 10. " TX_PSC_CAL_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x0C 9. " TX_PSC_CAL_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 8. " TX_PSC_CAL_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x0C 7. " TX_PSC_CAL_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " TX_PSC_CAL_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x0C 5. " TX_PSC_CAL_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x0C 4. " TX_PSC_CAL_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x0C 3. " TX_PSC_CAL_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 2. " TX_PSC_CAL_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x0C 1. " TX_PSC_CAL_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 0. " TX_PSC_CAL_0 ,TX driver enable" "Disabled,Enabled" line.word 0x0E "LANE2_TX_PSC_RDY,Transmitter Ready Power State Definition Register Lane 2" bitfld.word 0x0E 14. " TX_PSC_RDY_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x0E 13. " TX_PSC_RDY_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 12. " TX_PSC_RDY_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x0E 11. " TX_PSC_RDY_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 10. " TX_PSC_RDY_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x0E 9. " TX_PSC_RDY_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 8. " TX_PSC_RDY_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x0E 7. " TX_PSC_RDY_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x0E 6. " TX_PSC_RDY_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x0E 5. " TX_PSC_RDY_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x0E 4. " TX_PSC_RDY_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x0E 3. " TX_PSC_RDY_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 2. " TX_PSC_RDY_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x0E 1. " TX_PSC_RDY_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 0. " TX_PSC_RDY_0 ,TX driver enable" "Disabled,Enabled" group.word (0x4800+0x240)++0x07 line.word 0x00 "LANE2_TX_RCVDET_CTRL,Transmit Receiver Detect Control Register Lane 2" bitfld.word 0x00 15. " TX_RCVDET_CTRL_15 ,Start receiver detect" "Not started,Started" rbitfld.word 0x00 14. " TX_RCVDET_CTRL_14 ,Receiver detect process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " TX_RCVDET_CTRL_13 ,Receiver detected" "Not detected,Detected" line.word 0x02 "LANE2_TX_RCVDET_OVRD,Transmit Receiver Detect Override Register Lane 2" bitfld.word 0x02 15. " TX_RCVDET_OVRD_15 ,Receiver detect override enable" "Disabled,Enabled" bitfld.word 0x02 14. " TX_RCVDET_OVRD_14 ,Receiver detect override" "No override,Override" line.word 0x04 "LANE2_TX_RCVDET_EN_TMR,Transmit Receiver Detect Enable Timer Register Lane 2" hexmask.word 0x04 0.--11. 1. " TX_RCVDET_EN_TMR_11_0 ,Enable wait time value" line.word 0x06 "LANE2_TX_RCVDET_ST_TMR,Transmit Receiver Detect Start Timer Register Lane 2" hexmask.word 0x06 0.--11. 1. " TX_RCVDET_ST_TMR_11_0 ,Start wait time value" group.word (0x4800+0x280)++0x01 line.word 0x00 "LANE2_TX_BIST_CTRL,Transmit BIST Control Register Lane 2" bitfld.word 0x00 8.--11. " TX_BIST_CTRL_11_8 ,Transmitter BIST mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4. " TX_BIST_CTRL_4 ,Transmitter BIST force error" "Not forced,Forced" textline " " bitfld.word 0x00 1. " TX_BIST_CTRL_1 ,Transmitter BIST user defined data FIFO clear" "No clear,Clear" bitfld.word 0x00 0. " TX_BIST_CTRL_0 ,Transmitter BIST enable" "Disabled,Enabled" wgroup.word (0x4800+0x282)++0x01 line.word 0x00 "LANE2_TX_BIST_UDDWR,Transmit BIST User Defined Data Write Register Lane 2" hexmask.word 0x00 0.--9. 1. " TX_BIST_UDDWR_9_0 ,Transmitter BIST user defined data" group.word (0x4800+0x284)++0x03 line.word 0x00 "LANE2_TX_BIST_SEED0,Transmit BIST PRBS Seed 0 Register Lane 2" line.word 0x02 "LANE2_TX_BIST_SEED1,Transmit BIST PRBS Seed 1 Register Lane 2" hexmask.word 0x02 0.--14. 1. " TX_BIST_SEED1_14_0 ,Transmitter BIST PRBS seed (30:16)" group.word (0x4800+0x3C0)++0x0B line.word 0x00 "LANE2_TX_DIAG_TX_CTRL,TX Control Register Lane 2" bitfld.word 0x00 15. " TX_DIAG_TX_CTRL_15 ,TX serializer clock invert" "Not inverted,Inverted" bitfld.word 0x00 6.--7. " TX_DIAG_TX_CTRL_7_6 ,TX interface sub-rate standard mode 3" "0,1,2,3" textline " " bitfld.word 0x00 4.--5. " TX_DIAG_TX_CTRL_7_6 ,TX interface sub-rate standard mode 2" "0,1,2,3" bitfld.word 0x00 2.--3. " TX_DIAG_TX_CTRL_3_2 ,TX interface sub-rate standard mode 1" "0,1,2,3" textline " " bitfld.word 0x00 0.--1. " TX_DIAG_TX_CTRL_1_0 ,TX interface sub-rate standard mode 0" "0,1,2,3" line.word 0x02 "LANE2_TX_DIAG_TX_DRV,TX Driver Control Register Lane 2" bitfld.word 0x02 13. " TX_DIAG_TX_DRV_13 ,Transmitter reset pull down override enable" "Disabled,Enabled" bitfld.word 0x02 12. " TX_DIAG_TX_DRV_12 ,Transmitter reset pull down override" "Disabled,Enabled" textline " " bitfld.word 0x02 10. " TX_DIAG_TX_DRV_10 ,TX driver programmable boost enable" "Disabled,Enabled" bitfld.word 0x02 8.--9. " TX_DIAG_TX_DRV_9_8 ,TX driver programmable boost level" "0,1,2,3" textline " " bitfld.word 0x02 7. " TX_DIAG_TX_DRV_7 ,TX driver LDO bandgap dependent feedback reference enable" "Disabled,Enabled" bitfld.word 0x02 6. " TX_DIAG_TX_DRV_6 ,TX driver LDO bandgap dependent reference enable" "Disabled,Enabled" textline " " bitfld.word 0x02 5. " TX_DIAG_TX_DRV_5 ,TX driver LDO VDD dependent feedback reference enable" "Disabled,Enabled" bitfld.word 0x02 4. " TX_DIAG_TX_DRV_4 ,TX driver LDO VDD dependent reference enable" "Disabled,Enabled" textline " " bitfld.word 0x02 2. " TX_DIAG_TX_DRV_2 ,TD driver polarity control" "Low,High" bitfld.word 0x02 1. " TX_DIAG_TX_DRV_1 ,TX pre-driver pull up control" "0,1" textline " " bitfld.word 0x02 0. " TX_DIAG_TX_DRV_0 ,TX driver margin type" "0,1" line.word 0x04 "LANE2_TX_DIAG_ELEC_IDLE,TX Electrical Idle Diagnostic Register Lane 2" bitfld.word 0x04 4.--7. " TX_DIAG_ELEC_IDLE_7_4 ,TX electrical idle exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x04 0.--3. " TX_DIAG_ELEC_IDLE_3_0 ,TX electrical idle entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x06 "LANE2_TX_DIAG_SFIFO_CTRL,TX Sync FIFO Diagnostic Control Register Lane 2" bitfld.word 0x06 4. " TX_DIAG_SFIFO_CTRL_4 ,FIFO enqueue pointer bump" "Not decremented,Decremented" rbitfld.word 0x06 3. " TX_DIAG_SFIFO_CTRL_3 ,FIFO alignment error" "No error,Error" textline " " rbitfld.word 0x06 2. " TX_DIAG_SFIFO_CTRL_2 ,FIFO alignment acknowledge" "Not acknowledged,Acknowledged" bitfld.word 0x06 1. " TX_DIAG_SFIFO_CTRL_1 ,FIFO alignment enable override enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " TX_DIAG_SFIFO_CTRL_0 ,FIFO alignment enable override" "Disabled,Enabled" line.word 0x08 "LANE2_TX_DIAG_SFIFO_TMR,TX Sync FIFO Diagnostic Timer Register Lane 2" bitfld.word 0x08 8.--13. " TX_DIAG_SFIFO_TMR_13_8 ,FIFO alignment settle delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x08 0.--5. " TX_DIAG_SFIFO_TMR_5_0 ,FIFO alignment detect delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0A "LANE2_TX_DIAG_RDVDET_TUNE,TX Receiver Detect Tuning Register Lane 2" bitfld.word 0x0A 0.--1. " TX_DIAG_RDVDET_TUNE_1_0 ,Receiver detect reference DAC voltage" "0,1,2,3" rgroup.word (0x4800+0x3CC)++0x01 line.word 0x00 "LANE2_TX_DIAG_RST_DIAG,Transmitter Control Reset Diagnostic Register Lane 2" bitfld.word 0x00 8. " TX_DIAG_RST_DIAG_8 ,Current state of the dsync_power_reset_n reset" "No reset,Reset" bitfld.word 0x00 7. " TX_DIAG_RST_DIAG_7 ,Current state of the tfunc_power_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 6. " TX_DIAG_RST_DIAG_6 ,Current state of the xcal1_power_reset_n reset" "No reset,Reset" bitfld.word 0x00 5. " TX_DIAG_RST_DIAG_5 ,Current state of the xcaln_power_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 4. " TX_DIAG_RST_DIAG_4 ,Current state of the txda_tx_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 3. " TX_DIAG_RST_DIAG_3 ,Current state of the tx_dig_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 2. " TX_DIAG_RST_DIAG_2 ,Current state of the tx_sync_fifo_deq_rst_n reset" "No reset,Reset" bitfld.word 0x00 1. " TX_DIAG_RST_DIAG_1 ,Current state of the tx_sync_fifo_enq_rst_n reset" "No reset,Reset" textline " " bitfld.word 0x00 0. " TX_DIAG_RST_DIAG_0 ,Current state of the tx_lfps_reset_n reset" "No reset,Reset" group.word (0x4800+0x3CE)++0x05 line.word 0x00 "LANE2_TX_DIAG_BGREF_PREDRV_DELAY,TX Bandgap Reference And Pre-Drive Enable Delay Register Lane 2" hexmask.word.byte 0x00 0.--7. 1. " TX_DIAG_BGREF_PREDRV_DELAY_7_0 ,TX bandgap reference and pre-drive enable delay" line.word 0x02 "LANE2_TX_DIAG_MPHY_CTRL1,TX MPHY Control Register 1 Lane2" bitfld.word 0x02 8.--11. " TX_DIAG_MPHY_CTRL1_11_8 ,Register definition to be provided by the analog team" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x02 4. " TX_DIAG_MPHY_CTRL1_4 ,MPHY small amplitude mode" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " TX_DIAG_MPHY_CTRL1_3 ,AUX bias current enable" "Disabled,Enabled" bitfld.word 0x02 2. " TX_DIAG_MPHY_CTRL1_2 ,LDO no-load current reduce" "Not reduced,Reduced" textline " " bitfld.word 0x02 1. " TX_DIAG_MPHY_CTRL1_1 ,Register definition to be provided by the analog team" "0,1" bitfld.word 0x02 0. " TX_DIAG_MPHY_CTRL1_0 ,MPHY high load current mode enable" "Disabled,Enabled" line.word 0x04 "LANE2_TX_DIAG_MPHY_CTRL2,TX MPHY Control Register 2 Lane 2" bitfld.word 0x04 8.--11. " TX_DIAG_MPHY_CTRL2_11_8 ,Register definition to be provided by the analog team" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word.byte 0x04 0.--7. 1. " TX_DIAG_MPHY_CTRL2_7_0 ,MPHY slew rate control" group.word (0x4800+0x3E8)++0x03 line.word 0x00 "LANE2_TX_DIAG_DRV_LDO_PROG,TX Driver LDO Programming Register Lane 2" line.word 0x02 "LANE2_TX_DIAG_ECTRL_OVRD,TX Extra Enable Control Override Register Lane 2" bitfld.word 0x02 3. " TX_DIAG_ECTRL_OVRD_3 ,Driver pre-drive enable override enable" "Disabled,Enabled" bitfld.word 0x02 2. " TX_DIAG_ECTRL_OVRD_2 ,Driver pre-drive enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 1. " TX_DIAG_ECTRL_OVRD_1 ,Bandgap reference enable override enable" "Disabled,Enabled" bitfld.word 0x02 0. " TX_DIAG_ECTRL_OVRD_0 ,Bandgap reference enable override" "Disabled,Enabled" group.word 0x4C00++0x21 line.word 0x00 "LANE3_XCVR_PSM_CTRL,Power State Machine Control Register Lane 3" bitfld.word 0x00 14. " XCVR_PSM_CTRL_14 ,Bypass A0 in delay from PSM ready" "Not bypassed,Bypassed" bitfld.word 0x00 13. " XCVR_PSM_CTRL_13 ,Bypass A0 in delay from A5" "Not bypassed,Bypassed" textline " " bitfld.word 0x00 12. " XCVR_PSM_CTRL_12 ,Bypass A0 in delay from A4" "Not bypassed,Bypassed" bitfld.word 0x00 11. " XCVR_PSM_CTRL_11 ,Bypass A0 in delay from A3" "Not bypassed,Bypassed" textline " " bitfld.word 0x00 10. " XCVR_PSM_CTRL_10 ,Bypass A0 in delay from A2" "Not bypassed,Bypassed" bitfld.word 0x00 9. " XCVR_PSM_CTRL_9 ,Bypass A0 in delay from A1" "Not bypassed,Bypassed" textline " " bitfld.word 0x00 0. " XCVR_PSM_CTRL_0 ,Skip lane re-calibration" "Not skipped,Skipped" line.word 0x02 "LANE3_XCVR_PSM_RCTRL,Power State Machine Reset Control Register Lane 3" bitfld.word 0x02 15. " XCVR_PSM_RCTRL_15 ,RX reset active ready" "No reset,Reset" bitfld.word 0x02 14. " XCVR_PSM_RCTRL_14 ,RX reset active calibration" "No reset,Reset" textline " " bitfld.word 0x02 13. " XCVR_PSM_RCTRL_13 ,RX reset active A5" "No reset,Reset" bitfld.word 0x02 12. " XCVR_PSM_RCTRL_12 ,RX reset active A4" "No reset,Reset" textline " " bitfld.word 0x02 11. " XCVR_PSM_RCTRL_11 ,RX reset active A3" "No reset,Reset" bitfld.word 0x02 10. " XCVR_PSM_RCTRL_10 ,RX reset active A2" "No reset,Reset" textline " " bitfld.word 0x02 9. " XCVR_PSM_RCTRL_9 ,RX reset active A1" "No reset,Reset" bitfld.word 0x02 8. " XCVR_PSM_RCTRL_8 ,RX reset active A0" "No reset,Reset" textline " " bitfld.word 0x02 7. " XCVR_PSM_RCTRL_7 ,TX reset active ready" "No reset,Reset" bitfld.word 0x02 6. " XCVR_PSM_RCTRL_6 ,TX reset active calibration" "No reset,Reset" textline " " bitfld.word 0x02 5. " XCVR_PSM_RCTRL_5 ,TX reset active A5" "No reset,Reset" bitfld.word 0x02 4. " XCVR_PSM_RCTRL_4 ,TX reset active A4" "No reset,Reset" textline " " bitfld.word 0x02 3. " XCVR_PSM_RCTRL_3 ,TX reset active A3" "No reset,Reset" bitfld.word 0x02 2. " XCVR_PSM_RCTRL_2 ,TX reset active A2" "No reset,Reset" textline " " bitfld.word 0x02 1. " XCVR_PSM_RCTRL_1 ,TX reset active A1" "No reset,Reset" bitfld.word 0x02 0. " XCVR_PSM_RCTRL_0 ,TX reset active A0" "No reset,Reset" line.word 0x04 "LANE3_XCVR_PSM_CAL_TMR,PSM Calibration Delay Timer Register Lane 3" hexmask.word 0x04 0.--9. 1. " XCVR_PSM_CAL_TMR_9_0 ,PSM calibration delay state timer value" line.word 0x06 "LANE3_XCVR_PSM_A0IN_TMR,A0 In Delay Timer Register Lane 3" hexmask.word 0x06 0.--9. 1. " XCVR_PSM_A0IN_TMR_9_0 ,A0 in delay state timer value" line.word 0x08 "LANE3_XCVR_PSM_A0BYP_TMR,A0 In Bypass Timer Register Lane 3" bitfld.word 0x08 0.--4. " XCVR_PSM_A0BYP_TMR_4_0 ,A0 in delay state bypass timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0A "LANE3_XCVR_PSM_A1IN_TMR,A1 In Delay Timer Register Lane 3" bitfld.word 0x0A 0.--4. " XCVR_PSM_A1IN_TMR_4_0 ,A1 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "LANE3_XCVR_PSM_A2IN_TMR,A2 In Delay Timer Register Lane 3" bitfld.word 0x0C 0.--4. " XCVR_PSM_A2IN_TMR_4_0 ,A2 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0E "LANE3_XCVR_PSM_A3IN_TMR,A3 In Delay Timer Register Lane 3" bitfld.word 0x0E 0.--4. " XCVR_PSM_A3IN_TMR_4_0 ,A3 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "LANE3_XCVR_PSM_A4IN_TMR,A4 In Delay Timer Register Lane 3" bitfld.word 0x10 0.--4. " XCVR_PSM_A4IN_TMR_4_0 ,A4 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x12 "LANE3_XCVR_PSM_A5IN_TMR,A5 In Delay Timer Register Lane 3" bitfld.word 0x12 0.--4. " XCVR_PSM_A5IN_TMR_4_0 ,A5 in delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "LANE3_XCVR_PSM_A0OUT_TMR,A0 Out Delay Timer Register Lane 3" bitfld.word 0x14 0.--4. " XCVR_PSM_A0OUT_TMR_4_0 ,A0 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x16 "LANE3_XCVR_PSM_A1OUT_TMR,A1 Out Delay Timer Register Lane 3" bitfld.word 0x16 0.--4. " XCVR_PSM_A1OUT_TMR_4_0 ,A1 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x18 "LANE3_XCVR_PSM_A2OUT_TMR,A2 Out Delay Timer Register Lane 3" bitfld.word 0x18 0.--4. " XCVR_PSM_A2OUT_TMR_4_0 ,A2 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x1A "LANE3_XCVR_PSM_A3OUT_TMR,A3 Out Delay Timer Register Lane 3" bitfld.word 0x1A 0.--4. " XCVR_PSM_A3OUT_TMR_4_0 ,A3 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x1C "LANE3_XCVR_PSM_A4OUT_TMR,A4 Out Delay Timer Register Lane 3" bitfld.word 0x1C 0.--4. " XCVR_PSM_A4OUT_TMR_4_0 ,A4 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x1E "LANE3_XCVR_PSM_A5OUT_TMR,A5 Out Delay Timer Register Lane 3" bitfld.word 0x1E 0.--4. " XCVR_PSM_A5OUT_TMR_4_0 ,A5 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x20 "LANE3_XCVR_PSM_DIAG,Power State Machine Diagnostic Register Lane 3" bitfld.word 0x20 13. " XCVR_PSM_DIAG_13 ,Force A5 exit acknowledge" "Not forced,Forced" bitfld.word 0x20 12. " XCVR_PSM_DIAG_12 ,Force A4 exit acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 11. " XCVR_PSM_DIAG_11 ,Force A3 exit acknowledge" "Not forced,Forced" bitfld.word 0x20 10. " XCVR_PSM_DIAG_10 ,Force A2 exit acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 9. " XCVR_PSM_DIAG_9 ,Force A1 exit acknowledge" "Not forced,Forced" bitfld.word 0x20 8. " XCVR_PSM_DIAG_8 ,Force A0 exit acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 5. " XCVR_PSM_DIAG_5 ,Force A5 entry acknowledge" "Not forced,Forced" bitfld.word 0x20 4. " XCVR_PSM_DIAG_4 ,Force A4 entry acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 3. " XCVR_PSM_DIAG_3 ,Force A3 entry acknowledge" "Not forced,Forced" bitfld.word 0x20 2. " XCVR_PSM_DIAG_2 ,Force A2 entry acknowledge" "Not forced,Forced" textline " " bitfld.word 0x20 1. " XCVR_PSM_DIAG_1 ,Force A1 entry acknowledge" "Not forced,Forced" bitfld.word 0x20 0. " XCVR_PSM_DIAG_0 ,Force A0 entry acknowledge" "Not forced,Forced" group.word (0x4C00+0x3E)++0x01 line.word 0x00 "LANE3_XCVR_PSM_USER_DEF_CTRL,Power State Machine User Defined Control Register Lane 3" bitfld.word 0x00 1. " XCVR_PSM_USER_DEF_CTRL_1 ,Disable PSM clock gating" "No,Yes" bitfld.word 0x00 0. " XCVR_PSM_USER_DEF_CTRL_0 ,Disable early A0 acknowledge response" "No,Yes" group.word (0x4C00+0x82)++0x05 line.word 0x00 "LANE3_TX_TXCC_PRE_OVRD,TX Pre-Cursor Override Register Lane 3" bitfld.word 0x00 8. " TX_TXCC_PRE_OVRD_8 ,Pre-cursor override enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " TX_TXCC_PRE_OVRD_5_0 ,Pre-cursor override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE3_TX_TXCC_MAIN_OVRD,TX Main-Cursor Override Register Lane 3" bitfld.word 0x02 8. " TX_TXCC_MAIN_OVRD_8 ,Main-cursor override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " TX_TXCC_MAIN_OVRD_5_0 ,Main-cursor override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE3_TX_TXCC_POST_OVRD,TX Post-Cursor Override Register Lane 3" bitfld.word 0x04 8. " TX_TXCC_POST_OVRD_8 ,Post-cursor override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " TX_TXCC_POST_OVRD_5_0 ,Post-cursor override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.word (0x4C00+0x88)++0x05 line.word 0x00 "LANE3_TX_TXCC_PRE_CVAL,TX Pre-Cursor Current Value Register 3" bitfld.word 0x00 0.--5. " TX_TXCC_PRE_CVAL_5_0 ,Pre-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE3_TX_TXCC_MAIN_CVAL,TX Main-Cursor Current Value Register 3" bitfld.word 0x02 0.--5. " TX_TXCC_MAIN_CVAL_5_0 ,Main-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE3_TX_TXCC_POST_CVAL,TX Post-Cursor Current Value Register 3" bitfld.word 0x04 0.--5. " TX_TXCC_POST_CVAL_5_0 ,Post-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x4C00+0x8E)++0x31 line.word 0x00 "LANE3_TX_TXCC_CAL_SCLR_MULT,Resistor Calibration Code Scaler Multiplier Value Register Lane 3" bitfld.word 0x00 8. " TX_TXCC_CAL_SCLR_MULT_8 ,Scaled resistor calibration code add" "0,1" hexmask.word.byte 0x00 0.--7. 1. " TX_TXCC_CAL_SCLR_MULT_7_0 ,Resistor calibration multiplier value" line.word 0x02 "LANE3_TX_TXCC_CPRE_MULT_00,Calculated Pre Emphasis Multiplier Value 00 Register Lane 3" hexmask.word.byte 0x02 0.--7. 1. " TX_TXCC_CPRE_MULT_00_7_0 ,Calculated pre emphasis multiplier value 00" line.word 0x04 "LANE3_TX_TXCC_CPRE_MULT_01,Calculated Pre Emphasis Multiplier Value 01 Register Lane 3" hexmask.word.byte 0x04 0.--7. 1. " TX_TXCC_CPRE_MULT_01_7_0 ,Calculated pre emphasis multiplier value 01" line.word 0x06 "LANE3_TX_TXCC_CPRE_MULT_10,Calculated Pre Emphasis Multiplier Value 10 Register Lane 3" hexmask.word.byte 0x06 0.--7. 1. " TX_TXCC_CPRE_MULT_10_7_0 ,Calculated pre emphasis multiplier value 10" line.word 0x08 "LANE3_TX_TXCC_CPRE_MULT_11,Calculated Pre Emphasis Multiplier Value 11 Register Lane 3" hexmask.word.byte 0x08 0.--7. 1. " TX_TXCC_CPRE_MULT_11_7_0 ,Calculated pre emphasis multiplier value 11" line.word 0x0A "LANE3_TX_TXCC_CPOST_MULT_00,Calculated Post Emphasis Multiplier Value 00 Register Lane 3" hexmask.word.byte 0x0A 0.--7. 1. " TX_TXCC_CPOST_MULT_00_7_0 ,Calculated post emphasis multiplier value 00" line.word 0x0C "LANE3_TX_TXCC_CPOST_MULT_01,Calculated Post Emphasis Multiplier Value 01 Register Lane 3" hexmask.word.byte 0x0C 0.--7. 1. " TX_TXCC_CPOST_MULT_01_7_0 ,Calculated post emphasis multiplier value 01" line.word 0x0E "LANE3_TX_TXCC_CPOST_MULT_10,Calculated Post Emphasis Multiplier Value 10 Register Lane 3" hexmask.word.byte 0x0E 0.--7. 1. " TX_TXCC_CPOST_MULT_10_7_0 ,Calculated post emphasis multiplier value 10" line.word 0x10 "LANE3_TX_TXCC_CPOST_MULT_11,Calculated Post Emphasis Multiplier Value 11 Register Lane 3" hexmask.word.byte 0x10 0.--7. 1. " TX_TXCC_CPOST_MULT_11_7_0 ,Calculated post emphasis multiplier value 11" line.word 0x12 "LANE3_TX_TXCC_MGNFS_MULT_000,Margin Full Swing Multiplier Value 000 Register Lane 3" hexmask.word.byte 0x12 0.--7. 1. " TX_TXCC_MGNFS_MULT_000_7_0 ,Margin full swing multiplier value 000" line.word 0x14 "LANE3_TX_TXCC_MGNFS_MULT_001,Margin Full Swing Multiplier Value 001 Register Lane 3" hexmask.word.byte 0x14 0.--7. 1. " TX_TXCC_MGNFS_MULT_001_7_0 ,Margin full swing multiplier value 001" line.word 0x16 "LANE3_TX_TXCC_MGNFS_MULT_010,Margin Full Swing Multiplier Value 010 Register Lane 3" hexmask.word.byte 0x16 0.--7. 1. " TX_TXCC_MGNFS_MULT_010_7_0 ,Margin full swing multiplier value 010" line.word 0x18 "LANE3_TX_TXCC_MGNFS_MULT_011,Margin Full Swing Multiplier Value 011 Register Lane 3" hexmask.word.byte 0x18 0.--7. 1. " TX_TXCC_MGNFS_MULT_011_7_0 ,Margin full swing multiplier value 011" line.word 0x1A "LANE3_TX_TXCC_MGNFS_MULT_100,Margin Full Swing Multiplier Value 100 Register Lane 3" hexmask.word.byte 0x1A 0.--7. 1. " TX_TXCC_MGNFS_MULT_100_7_0 ,Margin full swing multiplier value 100" line.word 0x1C "LANE3_TX_TXCC_MGNFS_MULT_101,Margin Full Swing Multiplier Value 101 Register Lane 3" hexmask.word.byte 0x1C 0.--7. 1. " TX_TXCC_MGNFS_MULT_101_7_0 ,Margin full swing multiplier value 101" line.word 0x1E "LANE3_TX_TXCC_MGNFS_MULT_110,Margin Full Swing Multiplier Value 110 Register Lane 3" hexmask.word.byte 0x1E 0.--7. 1. " TX_TXCC_MGNFS_MULT_110_7_0 ,Margin full swing multiplier value 110" line.word 0x20 "LANE3_TX_TXCC_MGNFS_MULT_111,Margin Full Swing Multiplier Value 111 Register Lane 3" hexmask.word.byte 0x20 0.--7. 1. " TX_TXCC_MGNFS_MULT_111_7_0 ,Margin full swing multiplier value 111" line.word 0x22 "LANE3_TX_TXCC_MGNLS_MULT_000,Margin Half Swing Multiplier Value 000 Register Lane 3" hexmask.word.byte 0x22 0.--7. 1. " TX_TXCC_MGNLS_MULT_000_7_0 ,Margin half swing multiplier value 000" line.word 0x24 "LANE3_TX_TXCC_MGNLS_MULT_001,Margin Half Swing Multiplier Value 001 Register Lane 3" hexmask.word.byte 0x24 0.--7. 1. " TX_TXCC_MGNLS_MULT_001_7_0 ,Margin half swing multiplier value 001" line.word 0x26 "LANE3_TX_TXCC_MGNLS_MULT_010,Margin Half Swing Multiplier Value 010 Register Lane 3" hexmask.word.byte 0x26 0.--7. 1. " TX_TXCC_MGNLS_MULT_010_7_0 ,Margin half swing multiplier value 010" line.word 0x28 "LANE3_TX_TXCC_MGNLS_MULT_011,Margin Half Swing Multiplier Value 011 Register Lane 3" hexmask.word.byte 0x28 0.--7. 1. " TX_TXCC_MGNLS_MULT_011_7_0 ,Margin half swing multiplier value 011" line.word 0x2A "LANE3_TX_TXCC_MGNLS_MULT_100,Margin Half Swing Multiplier Value 100 Register Lane 3" hexmask.word.byte 0x2A 0.--7. 1. " TX_TXCC_MGNLS_MULT_100_7_0 ,Margin half swing multiplier value 100" line.word 0x2C "LANE3_TX_TXCC_MGNLS_MULT_101,Margin Half Swing Multiplier Value 101 Register Lane 3" hexmask.word.byte 0x2C 0.--7. 1. " TX_TXCC_MGNLS_MULT_101_7_0 ,Margin half swing multiplier value 101" line.word 0x2E "LANE3_TX_TXCC_MGNLS_MULT_110,Margin Half Swing Multiplier Value 110 Register Lane 3" hexmask.word.byte 0x2E 0.--7. 1. " TX_TXCC_MGNLS_MULT_110_7_0 ,Margin half swing multiplier value 110" line.word 0x30 "LANE3_TX_TXCC_MGNLS_MULT_111,Margin Half Swing Multiplier Value 111 Register Lane 3" hexmask.word.byte 0x30 0.--7. 1. " TX_TXCC_MGNLS_MULT_111_7_0 ,Margin half swing multiplier value 111" group.word (0x4C00+0x1C0)++0x07 line.word 0x00 "LANE3_XCVR_DIAG_PLLDRC_CTRL,Transceiver PLL Data Rate Clock Control Register Lane 3" bitfld.word 0x00 14. " XCVR_DIAG_PLLDRC_CTRL_14 ,Digital PLL clock select standard mode 3" "Not selected,Selected" bitfld.word 0x00 12.--13. " XCVR_DIAG_PLLDRC_CTRL_13_12 ,Digital PLL data rate divider standard mode 3 value" "0,1,2,3" textline " " bitfld.word 0x00 10. " XCVR_DIAG_PLLDRC_CTRL_10 ,Digital PLL clock select standard mode 2" "Not selected,Selected" bitfld.word 0x00 8.--9. " XCVR_DIAG_PLLDRC_CTRL_9_8 ,Digital PLL data rate divider standard mode 2 value" "0,1,2,3" textline " " bitfld.word 0x00 6. " XCVR_DIAG_PLLDRC_CTRL_6 ,Digital PLL clock select standard mode 1" "Not selected,Selected" bitfld.word 0x00 4.--5. " XCVR_DIAG_PLLDRC_CTRL_5_4 ,Digital PLL data rate divider standard mode 1 value" "0,1,2,3" textline " " bitfld.word 0x00 2. " XCVR_DIAG_PLLDRC_CTRL_2 ,Digital PLL clock select standard mode 0" "Not selected,Selected" bitfld.word 0x00 0.--1. " XCVR_DIAG_PLLDRC_CTRL_0_1 ,Digital PLL data rate divider standard mode 0 value" "0,1,2,3" line.word 0x02 "LANE3_XCVR_DIAG_HSCLK_SEL,Transceiver High Speed Clock Select Register Lane 3" bitfld.word 0x02 12.--13. " XCVR_DIAG_HSCLK_SEL_13_12 ,High speed clock select standard mode 3" "0,1,2,3" bitfld.word 0x02 8.--9. " XCVR_DIAG_HSCLK_SEL_9_8 ,High speed clock select standard mode 2" "0,1,2,3" textline " " bitfld.word 0x02 4.--5. " XCVR_DIAG_HSCLK_SEL_5_4 ,High speed clock select standard mode 1" "0,1,2,3" bitfld.word 0x02 0.--1. " XCVR_DIAG_HSCLK_SEL_5_4 ,High speed clock select standard mode 0" "0,1,2,3" line.word 0x04 "LANE3_XCVR_DIAG_HSCLKA_DCTRL,Transceiver High Speed Clock A Divider Control Register Lane 3" bitfld.word 0x04 12.--13. " XCVR_DIAG_HSCLKA_DCTRL_13_12 ,Transceiver clock A (transmitter) divider control standard mode 3" "0,1,2,3" bitfld.word 0x04 8.--9. " XCVR_DIAG_HSCLKA_DCTRL_9_8 ,Transceiver clock A (transmitter) divider control standard mode 2" "0,1,2,3" textline " " bitfld.word 0x04 4.--5. " XCVR_DIAG_HSCLKA_DCTRL_5_4 ,Transceiver clock A (transmitter) divider control standard mode 1" "0,1,2,3" bitfld.word 0x04 0.--1. " XCVR_DIAG_HSCLKA_DCTRL_1_0 ,Transceiver clock A (transmitter) divider control standard mode 0" "0,1,2,3" line.word 0x06 "LANE3_XCVR_DIAG_HSCLKB_DCTRL,Transceiver High Speed Clock B Divider Control Register Lane 3" bitfld.word 0x06 12.--13. " XCVR_DIAG_HSCLKB_DCTRL_13_12 ,Transceiver clock B (transmitter) divider control standard mode 3" "0,1,2,3" bitfld.word 0x06 8.--9. " XCVR_DIAG_HSCLKB_DCTRL_9_8 ,Transceiver clock B (transmitter) divider control standard mode 2" "0,1,2,3" textline " " bitfld.word 0x06 4.--5. " XCVR_DIAG_HSCLKB_DCTRL_5_4 ,Transceiver clock B (transmitter) divider control standard mode 1" "0,1,2,3" bitfld.word 0x06 0.--1. " XCVR_DIAG_HSCLKB_DCTRL_1_0 ,Transceiver clock B (transmitter) divider control standard mode 0" "0,1,2,3" rgroup.word (0x4C00+0x1CE)++0x01 line.word 0x00 "LANE3_XCVR_DIAG_RST_DIAG,Transceiver Control Reset Diagnostic Register Lane 3" bitfld.word 0x00 1. " XCVR_DIAG_RST_DIAG_1 ,Current state of the xcvr_psm_reset_n reset" "No reset,Reset" bitfld.word 0x00 0. " XCVR_DIAG_RST_DIAG_0 ,Current state of the xcvr_ref_clk_reset_n reset" "No reset,Reset" group.word (0x4C00+0x1D0)++0x05 line.word 0x00 "LANE3_XCVR_DIAG_BIDI_CTRL,Transceiver Bidirectional Control Register Lane 3" bitfld.word 0x00 7. " XCVR_DIAG_BIDI_CTRL_7 ,Receiver enable standard mode 3" "Disabled,Enabled" bitfld.word 0x00 6. " XCVR_DIAG_BIDI_CTRL_6 ,Receiver enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " XCVR_DIAG_BIDI_CTRL_5 ,Receiver enable standard mode 1" "Disabled,Enabled" bitfld.word 0x00 4. " XCVR_DIAG_BIDI_CTRL_4 ,Receiver enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " XCVR_DIAG_BIDI_CTRL_3 ,Transmitter enable standard mode 3" "Disabled,Enabled" bitfld.word 0x00 2. " XCVR_DIAG_BIDI_CTRL_2 ,Transmitter enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " XCVR_DIAG_BIDI_CTRL_1 ,Transmitter enable standard mode 1" "Disabled,Enabled" bitfld.word 0x00 0. " XCVR_DIAG_BIDI_CTRL_0 ,Transmitter enable standard mode 0" "Disabled,Enabled" line.word 0x02 "LANE3_XCVR_DIAG_PWR_CTRL,Transceiver Power Island Control Register Lane 3" bitfld.word 0x02 15. " XCVR_DIAG_PWR_CTRL_15 ,Transceiver dsync power down disable" "No,Yes" bitfld.word 0x02 14. " XCVR_DIAG_PWR_CTRL_14 ,Transceiver calibration one time power down disable" "No,Yes" textline " " bitfld.word 0x02 13. " XCVR_DIAG_PWR_CTRL_13 ,Transceiver calibration multiples time power down disable" "No,Yes" bitfld.word 0x02 11. " XCVR_DIAG_PWR_CTRL_11 ,Transceiver test functions power enable" "Disabled,Enabled" line.word 0x04 "LANE3_XCVR_DIAG_RX_LANE_CAL_RST_TMR,RX Lane Calibration Reset Timer Register Lane 3" hexmask.word 0x04 0.--9. 1. " XCVR_DIAG_RX_LANE_CAL_RST_TMR_9_0 ,Lane calibration receiver reset timer value" group.word (0x4C00+0x1E0)++0x07 line.word 0x00 "LANE3_XCVR_DIAG_LANE_FCM_EN_TO,Lane Fast Common Mode Enable Timeout Register Lane 3" hexmask.word 0x00 0.--11. 1. " XCVR_DIAG_LANE_FCM_EN_TO_11_0 ,Lane fast common mode enable timeout value" line.word 0x02 "LANE3_XCVR_DIAG_LANE_FCM_EN_SWAIT_TMR,Lane Fast Common Mode Enable Sample Wait Timer Register Lane 3" bitfld.word 0x02 0.--3. " XCVR_DIAG_LANE_FCM_EN_SWAIT_TMR_3_0 ,Lane fast common mode enable sample wait timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "LANE3_XCVR_DIAG_LANE_FCM_EN_MGN_TMR,Lane Fast Common Mode Enable Margin Timer Register Lane 3" hexmask.word 0x04 0.--11. 1. " XCVR_DIAG_LANE_FCM_EN_MGN_TMR_11_0 ,Lane fast common mode enable margin timer value" line.word 0x06 "LANE3_XCVR_DIAG_LANE_FCM_EN_TUNE,Lane Fast Common Mode Enable Tuning Register Lane 3" bitfld.word 0x06 8.--9. " XCVR_DIAG_LANE_FCM_EN_TUNE_9_8 ,Common mode sense reference DAC voltage initial test" "0,1,2,3" bitfld.word 0x06 4.--5. " XCVR_DIAG_LANE_FCM_EN_TUNE_5_4 ,Common mode sense reference DAC voltage high test" "0,1,2,3" textline " " bitfld.word 0x06 0.--1. " XCVR_DIAG_LANE_FCM_EN_TUNE_1_0 ,Common mode sense reference DAC voltage low test" "0,1,2,3" group.word (0x4C00+0x200)++0x0F line.word 0x00 "LANE3_TX_PSC_A0,Transmitter A0 Power State Definition Register Lane 3" bitfld.word 0x00 14. " TX_PSC_A0_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x00 13. " TX_PSC_A0_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TX_PSC_A0_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x00 11. " TX_PSC_A0_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " TX_PSC_A0_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x00 9. " TX_PSC_A0_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " TX_PSC_A0_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x00 7. " TX_PSC_A0_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TX_PSC_A0_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x00 5. " TX_PSC_A0_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TX_PSC_A0_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x00 3. " TX_PSC_A0_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TX_PSC_A0_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x00 1. " TX_PSC_A0_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TX_PSC_A0_0 ,TX driver enable" "Disabled,Enabled" line.word 0x02 "LANE3_TX_PSC_A1,Transmitter A1 Power State Definition Register Lane 3" bitfld.word 0x02 14. " TX_PSC_A1_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x02 13. " TX_PSC_A1_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " TX_PSC_A1_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x02 11. " TX_PSC_A1_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x02 10. " TX_PSC_A1_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x02 9. " TX_PSC_A1_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x02 8. " TX_PSC_A1_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x02 7. " TX_PSC_A1_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " TX_PSC_A1_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x02 5. " TX_PSC_A1_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x02 4. " TX_PSC_A1_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x02 3. " TX_PSC_A1_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x02 2. " TX_PSC_A1_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x02 1. " TX_PSC_A1_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " TX_PSC_A1_0 ,TX driver enable" "Disabled,Enabled" line.word 0x04 "LANE3_TX_PSC_A2,Transmitter A2 Power State Definition Register Lane 3" bitfld.word 0x04 14. " TX_PSC_A2_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x04 13. " TX_PSC_A2_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x04 12. " TX_PSC_A2_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x04 11. " TX_PSC_A2_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x04 10. " TX_PSC_A2_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x04 9. " TX_PSC_A2_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x04 8. " TX_PSC_A2_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x04 7. " TX_PSC_A2_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " TX_PSC_A2_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x04 5. " TX_PSC_A2_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x04 4. " TX_PSC_A2_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x04 3. " TX_PSC_A2_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x04 2. " TX_PSC_A2_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x04 1. " TX_PSC_A2_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x04 0. " TX_PSC_A2_0 ,TX driver enable" "Disabled,Enabled" line.word 0x06 "LANE3_TX_PSC_A3,Transmitter A3 Power State Definition Register Lane 3" bitfld.word 0x06 14. " TX_PSC_A3_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x06 13. " TX_PSC_A3_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x06 12. " TX_PSC_A3_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x06 11. " TX_PSC_A3_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x06 10. " TX_PSC_A3_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x06 9. " TX_PSC_A3_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x06 8. " TX_PSC_A3_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x06 7. " TX_PSC_A3_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " TX_PSC_A3_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x06 5. " TX_PSC_A3_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " TX_PSC_A3_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x06 3. " TX_PSC_A3_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x06 2. " TX_PSC_A3_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x06 1. " TX_PSC_A3_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " TX_PSC_A3_0 ,TX driver enable" "Disabled,Enabled" line.word 0x08 "LANE3_TX_PSC_A4,Transmitter A4 Power State Definition Register Lane 3" bitfld.word 0x08 14. " TX_PSC_A4_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x08 13. " TX_PSC_A4_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x08 12. " TX_PSC_A4_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x08 11. " TX_PSC_A4_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x08 10. " TX_PSC_A4_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x08 9. " TX_PSC_A4_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x08 8. " TX_PSC_A4_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x08 7. " TX_PSC_A4_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " TX_PSC_A4_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x08 5. " TX_PSC_A4_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x08 4. " TX_PSC_A4_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x08 3. " TX_PSC_A4_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x08 2. " TX_PSC_A4_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x08 1. " TX_PSC_A4_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " TX_PSC_A4_0 ,TX driver enable" "Disabled,Enabled" line.word 0x0A "LANE3_TX_PSC_A5,Transmitter A5 Power State Definition Register Lane 3" bitfld.word 0x0A 14. " TX_PSC_A5_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x0A 13. " TX_PSC_A5_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 12. " TX_PSC_A5_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x0A 11. " TX_PSC_A5_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 10. " TX_PSC_A5_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x0A 9. " TX_PSC_A5_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 8. " TX_PSC_A5_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x0A 7. " TX_PSC_A5_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x0A 6. " TX_PSC_A5_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x0A 5. " TX_PSC_A5_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x0A 4. " TX_PSC_A5_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x0A 3. " TX_PSC_A5_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 2. " TX_PSC_A5_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x0A 1. " TX_PSC_A5_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 0. " TX_PSC_A5_0 ,TX driver enable" "Disabled,Enabled" line.word 0x0C "LANE3_TX_PSC_CAL,Transmitter Calibration Power State Definition Register Lane 3" bitfld.word 0x0C 14. " TX_PSC_CAL_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x0C 13. " TX_PSC_CAL_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 12. " TX_PSC_CAL_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x0C 11. " TX_PSC_CAL_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 10. " TX_PSC_CAL_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x0C 9. " TX_PSC_CAL_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 8. " TX_PSC_CAL_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x0C 7. " TX_PSC_CAL_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " TX_PSC_CAL_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x0C 5. " TX_PSC_CAL_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x0C 4. " TX_PSC_CAL_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x0C 3. " TX_PSC_CAL_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 2. " TX_PSC_CAL_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x0C 1. " TX_PSC_CAL_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 0. " TX_PSC_CAL_0 ,TX driver enable" "Disabled,Enabled" line.word 0x0E "LANE3_TX_PSC_RDY,Transmitter Ready Power State Definition Register Lane 3" bitfld.word 0x0E 14. " TX_PSC_RDY_14 ,TX DCAP enable" "Disabled,Enabled" bitfld.word 0x0E 13. " TX_PSC_RDY_13 ,TX UPHY supply enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 12. " TX_PSC_RDY_12 ,LFPS controller enable" "Disabled,Enabled" bitfld.word 0x0E 11. " TX_PSC_RDY_11 ,MPHY pre-driver enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 10. " TX_PSC_RDY_10 ,TX serializer clock enable" "Disabled,Enabled" bitfld.word 0x0E 9. " TX_PSC_RDY_9 ,TX serializer enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 8. " TX_PSC_RDY_8 ,TX clock enable" "Disabled,Enabled" bitfld.word 0x0E 7. " TX_PSC_RDY_7 ,Transmitter low current mode" "Disabled,Enabled" textline " " bitfld.word 0x0E 6. " TX_PSC_RDY_6 ,Transmitter mission mode enable" "Disabled,Enabled" bitfld.word 0x0E 5. " TX_PSC_RDY_5 ,TX driver common mode enable extend control" "Disabled,Enabled" textline " " bitfld.word 0x0E 4. " TX_PSC_RDY_4 ,TX driver common mode enable" "Disabled,Enabled" bitfld.word 0x0E 3. " TX_PSC_RDY_3 ,TX post-emphasis enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 2. " TX_PSC_RDY_2 ,TX pre-emphasis enable" "Disabled,Enabled" bitfld.word 0x0E 1. " TX_PSC_RDY_1 ,TX driver LDO enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 0. " TX_PSC_RDY_0 ,TX driver enable" "Disabled,Enabled" group.word (0x4C00+0x240)++0x07 line.word 0x00 "LANE3_TX_RCVDET_CTRL,Transmit Receiver Detect Control Register Lane 3" bitfld.word 0x00 15. " TX_RCVDET_CTRL_15 ,Start receiver detect" "Not started,Started" rbitfld.word 0x00 14. " TX_RCVDET_CTRL_14 ,Receiver detect process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " TX_RCVDET_CTRL_13 ,Receiver detected" "Not detected,Detected" line.word 0x02 "LANE3_TX_RCVDET_OVRD,Transmit Receiver Detect Override Register Lane 3" bitfld.word 0x02 15. " TX_RCVDET_OVRD_15 ,Receiver detect override enable" "Disabled,Enabled" bitfld.word 0x02 14. " TX_RCVDET_OVRD_14 ,Receiver detect override" "No override,Override" line.word 0x04 "LANE3_TX_RCVDET_EN_TMR,Transmit Receiver Detect Enable Timer Register Lane 3" hexmask.word 0x04 0.--11. 1. " TX_RCVDET_EN_TMR_11_0 ,Enable wait time value" line.word 0x06 "LANE3_TX_RCVDET_ST_TMR,Transmit Receiver Detect Start Timer Register Lane 3" hexmask.word 0x06 0.--11. 1. " TX_RCVDET_ST_TMR_11_0 ,Start wait time value" group.word (0x4C00+0x280)++0x01 line.word 0x00 "LANE3_TX_BIST_CTRL,Transmit BIST Control Register Lane 3" bitfld.word 0x00 8.--11. " TX_BIST_CTRL_11_8 ,Transmitter BIST mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4. " TX_BIST_CTRL_4 ,Transmitter BIST force error" "Not forced,Forced" textline " " bitfld.word 0x00 1. " TX_BIST_CTRL_1 ,Transmitter BIST user defined data FIFO clear" "No clear,Clear" bitfld.word 0x00 0. " TX_BIST_CTRL_0 ,Transmitter BIST enable" "Disabled,Enabled" wgroup.word (0x4C00+0x282)++0x01 line.word 0x00 "LANE3_TX_BIST_UDDWR,Transmit BIST User Defined Data Write Register Lane 3" hexmask.word 0x00 0.--9. 1. " TX_BIST_UDDWR_9_0 ,Transmitter BIST user defined data" group.word (0x4C00+0x284)++0x03 line.word 0x00 "LANE3_TX_BIST_SEED0,Transmit BIST PRBS Seed 0 Register Lane 3" line.word 0x02 "LANE3_TX_BIST_SEED1,Transmit BIST PRBS Seed 1 Register Lane 3" hexmask.word 0x02 0.--14. 1. " TX_BIST_SEED1_14_0 ,Transmitter BIST PRBS seed (30:16)" group.word (0x4C00+0x3C0)++0x0B line.word 0x00 "LANE3_TX_DIAG_TX_CTRL,TX Control Register Lane 3" bitfld.word 0x00 15. " TX_DIAG_TX_CTRL_15 ,TX serializer clock invert" "Not inverted,Inverted" bitfld.word 0x00 6.--7. " TX_DIAG_TX_CTRL_7_6 ,TX interface sub-rate standard mode 3" "0,1,2,3" textline " " bitfld.word 0x00 4.--5. " TX_DIAG_TX_CTRL_7_6 ,TX interface sub-rate standard mode 2" "0,1,2,3" bitfld.word 0x00 2.--3. " TX_DIAG_TX_CTRL_3_2 ,TX interface sub-rate standard mode 1" "0,1,2,3" textline " " bitfld.word 0x00 0.--1. " TX_DIAG_TX_CTRL_1_0 ,TX interface sub-rate standard mode 0" "0,1,2,3" line.word 0x02 "LANE3_TX_DIAG_TX_DRV,TX Driver Control Register Lane 3" bitfld.word 0x02 13. " TX_DIAG_TX_DRV_13 ,Transmitter reset pull down override enable" "Disabled,Enabled" bitfld.word 0x02 12. " TX_DIAG_TX_DRV_12 ,Transmitter reset pull down override" "Disabled,Enabled" textline " " bitfld.word 0x02 10. " TX_DIAG_TX_DRV_10 ,TX driver programmable boost enable" "Disabled,Enabled" bitfld.word 0x02 8.--9. " TX_DIAG_TX_DRV_9_8 ,TX driver programmable boost level" "0,1,2,3" textline " " bitfld.word 0x02 7. " TX_DIAG_TX_DRV_7 ,TX driver LDO bandgap dependent feedback reference enable" "Disabled,Enabled" bitfld.word 0x02 6. " TX_DIAG_TX_DRV_6 ,TX driver LDO bandgap dependent reference enable" "Disabled,Enabled" textline " " bitfld.word 0x02 5. " TX_DIAG_TX_DRV_5 ,TX driver LDO VDD dependent feedback reference enable" "Disabled,Enabled" bitfld.word 0x02 4. " TX_DIAG_TX_DRV_4 ,TX driver LDO VDD dependent reference enable" "Disabled,Enabled" textline " " bitfld.word 0x02 2. " TX_DIAG_TX_DRV_2 ,TD driver polarity control" "Low,High" bitfld.word 0x02 1. " TX_DIAG_TX_DRV_1 ,TX pre-driver pull up control" "0,1" textline " " bitfld.word 0x02 0. " TX_DIAG_TX_DRV_0 ,TX driver margin type" "0,1" line.word 0x04 "LANE3_TX_DIAG_ELEC_IDLE,TX Electrical Idle Diagnostic Register Lane 3" bitfld.word 0x04 4.--7. " TX_DIAG_ELEC_IDLE_7_4 ,TX electrical idle exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x04 0.--3. " TX_DIAG_ELEC_IDLE_3_0 ,TX electrical idle entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x06 "LANE3_TX_DIAG_SFIFO_CTRL,TX Sync FIFO Diagnostic Control Register Lane 3" bitfld.word 0x06 4. " TX_DIAG_SFIFO_CTRL_4 ,FIFO enqueue pointer bump" "Not decremented,Decremented" rbitfld.word 0x06 3. " TX_DIAG_SFIFO_CTRL_3 ,FIFO alignment error" "No error,Error" textline " " rbitfld.word 0x06 2. " TX_DIAG_SFIFO_CTRL_2 ,FIFO alignment acknowledge" "Not acknowledged,Acknowledged" bitfld.word 0x06 1. " TX_DIAG_SFIFO_CTRL_1 ,FIFO alignment enable override enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " TX_DIAG_SFIFO_CTRL_0 ,FIFO alignment enable override" "Disabled,Enabled" line.word 0x08 "LANE3_TX_DIAG_SFIFO_TMR,TX Sync FIFO Diagnostic Timer Register Lane 3" bitfld.word 0x08 8.--13. " TX_DIAG_SFIFO_TMR_13_8 ,FIFO alignment settle delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x08 0.--5. " TX_DIAG_SFIFO_TMR_5_0 ,FIFO alignment detect delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0A "LANE3_TX_DIAG_RDVDET_TUNE,TX Receiver Detect Tuning Register Lane 3" bitfld.word 0x0A 0.--1. " TX_DIAG_RDVDET_TUNE_1_0 ,Receiver detect reference DAC voltage" "0,1,2,3" rgroup.word (0x4C00+0x3CC)++0x01 line.word 0x00 "LANE3_TX_DIAG_RST_DIAG,Transmitter Control Reset Diagnostic Register Lane 3" bitfld.word 0x00 8. " TX_DIAG_RST_DIAG_8 ,Current state of the dsync_power_reset_n reset" "No reset,Reset" bitfld.word 0x00 7. " TX_DIAG_RST_DIAG_7 ,Current state of the tfunc_power_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 6. " TX_DIAG_RST_DIAG_6 ,Current state of the xcal1_power_reset_n reset" "No reset,Reset" bitfld.word 0x00 5. " TX_DIAG_RST_DIAG_5 ,Current state of the xcaln_power_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 4. " TX_DIAG_RST_DIAG_4 ,Current state of the txda_tx_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 3. " TX_DIAG_RST_DIAG_3 ,Current state of the tx_dig_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 2. " TX_DIAG_RST_DIAG_2 ,Current state of the tx_sync_fifo_deq_rst_n reset" "No reset,Reset" bitfld.word 0x00 1. " TX_DIAG_RST_DIAG_1 ,Current state of the tx_sync_fifo_enq_rst_n reset" "No reset,Reset" textline " " bitfld.word 0x00 0. " TX_DIAG_RST_DIAG_0 ,Current state of the tx_lfps_reset_n reset" "No reset,Reset" group.word (0x4C00+0x3CE)++0x05 line.word 0x00 "LANE3_TX_DIAG_BGREF_PREDRV_DELAY,TX Bandgap Reference And Pre-Drive Enable Delay Register Lane 3" hexmask.word.byte 0x00 0.--7. 1. " TX_DIAG_BGREF_PREDRV_DELAY_7_0 ,TX bandgap reference and pre-drive enable delay" line.word 0x02 "LANE3_TX_DIAG_MPHY_CTRL1,TX MPHY Control Register 1 Lane3" bitfld.word 0x02 8.--11. " TX_DIAG_MPHY_CTRL1_11_8 ,Register definition to be provided by the analog team" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x02 4. " TX_DIAG_MPHY_CTRL1_4 ,MPHY small amplitude mode" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " TX_DIAG_MPHY_CTRL1_3 ,AUX bias current enable" "Disabled,Enabled" bitfld.word 0x02 2. " TX_DIAG_MPHY_CTRL1_2 ,LDO no-load current reduce" "Not reduced,Reduced" textline " " bitfld.word 0x02 1. " TX_DIAG_MPHY_CTRL1_1 ,Register definition to be provided by the analog team" "0,1" bitfld.word 0x02 0. " TX_DIAG_MPHY_CTRL1_0 ,MPHY high load current mode enable" "Disabled,Enabled" line.word 0x04 "LANE3_TX_DIAG_MPHY_CTRL2,TX MPHY Control Register 2 Lane 3" bitfld.word 0x04 8.--11. " TX_DIAG_MPHY_CTRL2_11_8 ,Register definition to be provided by the analog team" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word.byte 0x04 0.--7. 1. " TX_DIAG_MPHY_CTRL2_7_0 ,MPHY slew rate control" group.word (0x4C00+0x3E8)++0x03 line.word 0x00 "LANE3_TX_DIAG_DRV_LDO_PROG,TX Driver LDO Programming Register Lane 3" line.word 0x02 "LANE3_TX_DIAG_ECTRL_OVRD,TX Extra Enable Control Override Register Lane 3" bitfld.word 0x02 3. " TX_DIAG_ECTRL_OVRD_3 ,Driver pre-drive enable override enable" "Disabled,Enabled" bitfld.word 0x02 2. " TX_DIAG_ECTRL_OVRD_2 ,Driver pre-drive enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 1. " TX_DIAG_ECTRL_OVRD_1 ,Bandgap reference enable override enable" "Disabled,Enabled" bitfld.word 0x02 0. " TX_DIAG_ECTRL_OVRD_0 ,Bandgap reference enable override" "Disabled,Enabled" textline " " group.word 0x5040++0x0F line.word 0x00 "TX_ANA_CTRL_REG_1,DP Aux Analog Control 1" bitfld.word 0x00 15. " TX_ANA_CTRL_REG_1_15 ,Controls txda_dp_aux_en" "Disabled,Enabled" bitfld.word 0x00 14. " TX_ANA_CTRL_REG_1_14 ,Controls auxda_se_en" "Disabled,Enabled" bitfld.word 0x00 13. " TX_ANA_CTRL_REG_1_13 ,Controls txda_cal_latch_en" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TX_ANA_CTRL_REG_1_12 ,Controls auxda_polarity" "Low,High" bitfld.word 0x00 11. " TX_ANA_CTRL_REG_1_11 ,Controls txda_drv_power_isolation_en" "Disabled,Enabled" bitfld.word 0x00 10. " TX_ANA_CTRL_REG_1_10 ,Controls txda_drv_power_en_ph_2_n" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TX_ANA_CTRL_REG_1_9 ,Controls txda_drv_power_en_ph_1_n" "Disabled,Enabled" bitfld.word 0x00 8. " TX_ANA_CTRL_REG_1_8 ,Controls txda_bgref_en" "Disabled,Enabled" bitfld.word 0x00 7. " TX_ANA_CTRL_REG_1_7 ,Controls txda_drv_ldo_en" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TX_ANA_CTRL_REG_1_6 ,Controls txda_decap_en_del" "Disabled,Enabled" bitfld.word 0x00 5. " TX_ANA_CTRL_REG_1_5 ,Controls txda_decap_en" "Disabled,Enabled" bitfld.word 0x00 4. " TX_ANA_CTRL_REG_1_4 ,Controls txda_uphy_supply_en_del" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TX_ANA_CTRL_REG_1_3 ,Controls txda_uphy_supply_en" "Disabled,Enabled" bitfld.word 0x00 2. " TX_ANA_CTRL_REG_1_2 ,Controls txda_low_leakage_en" "Disabled,Enabled" bitfld.word 0x00 1. " TX_ANA_CTRL_REG_1_1 ,Controls txda_drv_idle_lowi_en" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TX_ANA_CTRL_REG_1_0 ,Controls txda_drv_cmn_mode_en" "Disabled,Enabled" line.word 0x02 "TX_ANA_CTRL_REG_2,DP Aux Analog Control 2" bitfld.word 0x02 15. " TX_ANA_CTRL_REG_2_15 ,Controls auxda_debouncing_clk" "Disabled,Enabled" bitfld.word 0x02 14. " TX_ANA_CTRL_REG_2_14 ,Controls txda_lpbk_recovered_clk_en" "Disabled,Enabled" bitfld.word 0x02 13. " TX_ANA_CTRL_REG_2_13 ,Controls txda_lpbk_isi_gen_en" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " TX_ANA_CTRL_REG_2_12 ,Controls txda_lpbk_serial_en" "Disabled,Enabled" bitfld.word 0x02 11. " TX_ANA_CTRL_REG_2_11 ,Controls txda_lpbk_line_en" "Disabled,Enabled" bitfld.word 0x02 10. " TX_ANA_CTRL_REG_2_10 ,Controls txda_drv_ldo_redc_sinkiq" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " TX_ANA_CTRL_REG_2_9 ,Controls xcvr_decap_en_del" "Disabled,Enabled" bitfld.word 0x02 8. " TX_ANA_CTRL_REG_2_8 ,Controls xcvr_decap_en" "Disabled,Enabled" bitfld.word 0x02 7. " TX_ANA_CTRL_REG_2_7 ,Controls txda_mphy_enable_hs_nt" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " TX_ANA_CTRL_REG_2_6 ,Controls txda_mphy_sa_mode" "Disabled,Enabled" bitfld.word 0x02 5. " TX_ANA_CTRL_REG_2_5 ,Controls txda_drv_ldo_rbyr_fb_en" "Disabled,Enabled" bitfld.word 0x02 4. " TX_ANA_CTRL_REG_2_4 ,Controls txda_drv_rst_pull_down" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " TX_ANA_CTRL_REG_2_3 ,Controls txda_drv_ldo_bg_fb_en" "Disabled,Enabled" bitfld.word 0x02 2. " TX_ANA_CTRL_REG_2_2 ,Controls txda_drv_ldo_bg_ref_en" "Disabled,Enabled" bitfld.word 0x02 1. " TX_ANA_CTRL_REG_2_1 ,Controls txda_drv_predrv_en_del" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " TX_ANA_CTRL_REG_2_0 ,Controls txda_drv_predrv_en" "Disabled,Enabled" line.word 0x04 "TXDA_COEFF_CALC_CTRL,Tx_Coef_Calc Module Inputs" bitfld.word 0x04 6. " TXDA_COEFF_CALC_CTRL_6 ,Controls tx_high_z" "Low impedance,High impedance" bitfld.word 0x04 3.--5. " TXDA_COEFF_CALC_CTRL_5_3 ,Controls tx_vmargin" "0,1,2,3,4,5,6,7" bitfld.word 0x04 2. " TXDA_COEFF_CALC_CTRL_2 ,Controls low_power_swing_en" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " TXDA_COEFF_CALC_CTRL_1 ,Controls tx_fcm_drv_main_en" "Disabled,Enabled" bitfld.word 0x04 0. " TXDA_COEFF_CALC_CTRL_0 ,Controls tx_fcm_full_margin" "Disabled,Enabled" line.word 0x06 "TX_DIG_CTRL_REG_1,Tx Dig Control Reg 1" bitfld.word 0x06 0.--1. " TX_DIG_CTRL_REG_1_1_0 ,De-emphasis level of the transmitter as specified below" "0,1,2,3" line.word 0x08 "TX_DIG_CTRL_REG_2,Tx Dig Control Reg 2" bitfld.word 0x08 15. " TX_DIG_CTRL_REG_2_15 ,Controls tx_high_z_tm_en" "Disabled,Enabled" bitfld.word 0x08 0.--5. " TX_DIG_CTRL_REG_2_5_0 ,Average of the pull up and pull down resistor calibration values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0A "TXDA_CYA_AUXDA_CYA,DP Aux Analog Control 3" bitfld.word 0x0A 12.--15. " TXDA_CYA_AUXDA_CYA_15_12 ,Txda_cya_auxda_cya_15_12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0A 10.--11. " TXDA_CYA_AUXDA_CYA_11_10 ,Txda_cya_auxda_cya_11_10" "0,1,2,3" bitfld.word 0x0A 8.--9. " TXDA_CYA_AUXDA_CYA_8_9 ,Txda_cya_auxda_cya_8_9" "0,1,2,3" textline " " hexmask.word.byte 0x0A 0.--7. 1. " TXDA_CYA_AUXDA_CYA_7_0 ,Controls txda_cya the TX testmode signal" line.word 0x0C "TX_ANA_CTRL_REG_3,DP Aux Analog Control 4" bitfld.word 0x0C 12.--15. " TX_ANA_CTRL_REG_3_15_12 ,Programs txda_vcmhold_prog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0C 6.--8. " TX_ANA_CTRL_REG_3_8_6 ,Level of the boost" "0,1,2,3,4,5,6,7" bitfld.word 0x0C 4.--5. " TX_ANA_CTRL_REG_3_5_4 ,Programs txda_cm_sense_vref_dac" "0,1,2,3" textline " " bitfld.word 0x0C 3. " TX_ANA_CTRL_REG_3_3 ,Controls txda_drv_mission_en" "Disabled,Enabled" line.word 0x0E "TX_ANA_CTRL_REG_4,DP Aux Analog Control 5" rgroup.word 0x5050++0x01 line.word 0x00 "TX_ANA_STATUS_REG_1,DP Aux Analog Status 1" bitfld.word 0x00 0. " TX_ANA_STATUS_REG_1_0 ,Common mode sense comparator output" "0,1" group.word 0x5052++0x01 line.word 0x00 "TX_ANA_CTRL_REG_5,DP Aux Analog Status 6" bitfld.word 0x00 4. " TX_ANA_CTRL_REG_5_4 ,HDMI_ARC mode transmission/reception" "Transmission,Reception" bitfld.word 0x00 3. " TX_ANA_CTRL_REG_5_3 ,MHL/eCBUS mode transmission/reception" "Transmission,Reception" bitfld.word 0x00 2. " TX_ANA_CTRL_REG_5_2 ,Programs txda_bidi_term_en" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TX_ANA_CTRL_REG_5_1 ,Programmable boost function enable" "Disabled,Enabled" bitfld.word 0x00 0. " TX_ANA_CTRL_REG_5_0 ,Controls txda_drv_ldo_vdd_ref_en" "Disabled,Enabled" textline " " group.word 0x8000++0x0F line.word 0x00 "LANE0_RX_PSC_A0,Receiver A0 Power State Definition Register Lane 0" bitfld.word 0x00 15. " RX_PSC_A0_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x00 14. " RX_PSC_A0_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x00 13. " RX_PSC_A0_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RX_PSC_A0_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x00 11. " RX_PSC_A0_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_PSC_A0_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_PSC_A0_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_PSC_A0_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x00 7. " RX_PSC_A0_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " RX_PSC_A0_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x00 5. " RX_PSC_A0_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x00 4. " RX_PSC_A0_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RX_PSC_A0_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x00 2. " RX_PSC_A0_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x00 1. " RX_PSC_A0_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RX_PSC_A0_0 ,RX enable" "Disabled,Enabled" line.word 0x02 "LANE0_RX_PSC_A1,Receiver A1 Power State Definition Register Lane 0" bitfld.word 0x02 15. " RX_PSC_A1_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x02 14. " RX_PSC_A1_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x02 13. " RX_PSC_A1_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RX_PSC_A1_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x02 11. " RX_PSC_A1_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x02 10. " RX_PSC_A1_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RX_PSC_A1_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x02 8. " RX_PSC_A1_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x02 7. " RX_PSC_A1_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " RX_PSC_A1_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x02 5. " RX_PSC_A1_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x02 4. " RX_PSC_A1_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RX_PSC_A1_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x02 2. " RX_PSC_A1_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x02 1. " RX_PSC_A1_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RX_PSC_A1_0 ,RX enable" "Disabled,Enabled" line.word 0x04 "LANE0_RX_PSC_A2,Receiver A2 Power State Definition Register Lane 0" bitfld.word 0x04 15. " RX_PSC_A2_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x04 14. " RX_PSC_A2_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x04 13. " RX_PSC_A2_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x04 12. " RX_PSC_A2_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x04 11. " RX_PSC_A2_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x04 10. " RX_PSC_A2_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x04 9. " RX_PSC_A2_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x04 8. " RX_PSC_A2_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x04 7. " RX_PSC_A2_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " RX_PSC_A2_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x04 5. " RX_PSC_A2_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x04 4. " RX_PSC_A2_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x04 3. " RX_PSC_A2_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x04 2. " RX_PSC_A2_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x04 1. " RX_PSC_A2_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x04 0. " RX_PSC_A2_0 ,RX enable" "Disabled,Enabled" line.word 0x06 "LANE0_RX_PSC_A3,Receiver A3 Power State Definition Register Lane 0" bitfld.word 0x06 15. " RX_PSC_A3_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x06 14. " RX_PSC_A3_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x06 13. " RX_PSC_A3_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x06 12. " RX_PSC_A3_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x06 11. " RX_PSC_A3_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x06 10. " RX_PSC_A3_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x06 9. " RX_PSC_A3_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x06 8. " RX_PSC_A3_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x06 7. " RX_PSC_A3_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " RX_PSC_A3_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x06 5. " RX_PSC_A3_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x06 4. " RX_PSC_A3_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x06 3. " RX_PSC_A3_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x06 2. " RX_PSC_A3_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x06 1. " RX_PSC_A3_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " RX_PSC_A3_0 ,RX enable" "Disabled,Enabled" line.word 0x08 "LANE0_RX_PSC_A4,Receiver A4 Power State Definition Register Lane 0" bitfld.word 0x08 15. " RX_PSC_A4_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x08 14. " RX_PSC_A4_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x08 13. " RX_PSC_A4_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x08 12. " RX_PSC_A4_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x08 11. " RX_PSC_A4_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x08 10. " RX_PSC_A4_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x08 9. " RX_PSC_A4_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x08 8. " RX_PSC_A4_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x08 7. " RX_PSC_A4_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " RX_PSC_A4_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x08 5. " RX_PSC_A4_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x08 4. " RX_PSC_A4_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x08 3. " RX_PSC_A4_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x08 2. " RX_PSC_A4_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x08 1. " RX_PSC_A4_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " RX_PSC_A4_0 ,RX enable" "Disabled,Enabled" line.word 0x0A "LANE0_RX_PSC_A5,Receiver A5 Power State Definition Register Lane 0" bitfld.word 0x0A 15. " RX_PSC_A5_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x0A 14. " RX_PSC_A5_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x0A 13. " RX_PSC_A5_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 12. " RX_PSC_A5_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x0A 11. " RX_PSC_A5_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x0A 10. " RX_PSC_A5_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 9. " RX_PSC_A5_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x0A 8. " RX_PSC_A5_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x0A 7. " RX_PSC_A5_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 6. " RX_PSC_A5_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x0A 5. " RX_PSC_A5_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x0A 4. " RX_PSC_A5_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 3. " RX_PSC_A5_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x0A 2. " RX_PSC_A5_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x0A 1. " RX_PSC_A5_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 0. " RX_PSC_A5_0 ,RX enable" "Disabled,Enabled" line.word 0x0C "LANE0_RX_PSC_CAL,Receiver Calibration Power State Definition Register Lane 0" bitfld.word 0x0C 15. " RX_PSC_CAL_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x0C 14. " RX_PSC_CAL_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x0C 13. " RX_PSC_CAL_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 12. " RX_PSC_CAL_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x0C 11. " RX_PSC_CAL_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x0C 10. " RX_PSC_CAL_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 9. " RX_PSC_CAL_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x0C 8. " RX_PSC_CAL_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x0C 7. " RX_PSC_CAL_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " RX_PSC_CAL_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x0C 5. " RX_PSC_CAL_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x0C 4. " RX_PSC_CAL_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 3. " RX_PSC_CAL_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x0C 2. " RX_PSC_CAL_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x0C 1. " RX_PSC_CAL_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 0. " RX_PSC_CAL_0 ,RX enable" "Disabled,Enabled" line.word 0x0E "LANE0_RX_PSC_RDY,Receiver Ready Power State Definition Register Lane 0" bitfld.word 0x0E 15. " RX_PSC_RDY_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x0E 14. " RX_PSC_RDY_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x0E 13. " RX_PSC_RDY_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 12. " RX_PSC_RDY_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x0E 11. " RX_PSC_RDY_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x0E 10. " RX_PSC_RDY_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 9. " RX_PSC_RDY_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x0E 8. " RX_PSC_RDY_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x0E 7. " RX_PSC_RDY_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 6. " RX_PSC_RDY_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x0E 5. " RX_PSC_RDY_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x0E 4. " RX_PSC_RDY_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 3. " RX_PSC_RDY_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x0E 2. " RX_PSC_RDY_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x0E 1. " RX_PSC_RDY_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 0. " RX_PSC_RDY_0 ,RX enable" "Disabled,Enabled" textline " " group.word (0x8000+0x40)++0x0D line.word 0x00 "LANE0_RX_IQPI_ILL_CAL_CTRL,RX IQ PI ILL Calibration Control Register Lane 0" bitfld.word 0x00 15. " RX_IQPI_ILL_CAL_CTRL_15 ,Start ILL calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_IQPI_ILL_CAL_CTRL_15 ,ILL calibration process done" "Not done,Done" textline " " hexmask.word.byte 0x00 0.--7. 1. " RX_IQPI_ILL_CAL_CTRL_7_0 ,ILL calibration code" line.word 0x02 "LANE0_RX_IQPI_ILL_CAL_START,RX IQ PI ILL Calibration Start Point Register Lane 0" bitfld.word 0x02 12.--14. " RX_IQPI_ILL_CAL_START_14_12 ,ILL calibration initial step size control" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x02 0.--7. 1. " RX_IQPI_ILL_CAL_START_7_0 ,ILL calibration code starting point value" line.word 0x04 "LANE0_RX_IQPI_ILL_CAL_TCTRL,RX IQ PI ILL Calibration Timer Control Register Lane 0" bitfld.word 0x04 0.--2. " RX_IQPI_ILL_CAL_TCTRL_2_0 ,ILL calibration initial time scale control" "0,1,2,3,4,5,6,7" line.word 0x06 "LANE0_RX_IQPI_ILL_CAL_OVRD,RX IQ PI ILL Calibration Override Register Lane 0" bitfld.word 0x06 15. " RX_IQPI_ILL_CAL_OVRD_15 ,ILL calibration code override enable" "Disabled,Enabled" hexmask.word.byte 0x06 0.--7. 1. " RX_IQPI_ILL_CAL_OVRD_7_0 ,ILL calibration code override value" line.word 0x08 "LANE0_RX_IQPI_ILL_CAL_INIT_TMR,RX IQ PI ILL Calibration Initialization Timer Register Lane 0" hexmask.word 0x08 0.--11. 1. " RX_IQPI_ILL_CAL_INIT_TMR_11_0 ,Initialization wait timer value" line.word 0x0A "LANE0_RX_IQPI_ILL_CAL_ITER_TMR,RX IQ PI ILL Calibration Iteration Timer Register Lane 0" hexmask.word 0x0A 0.--11. 1. " RX_IQPI_ILL_CAL_ITER_TMR_11_0 ,Iteration wait timer value" line.word 0x0C "LANE0_RX_IQPI_ILL_LOCK_REFTMR_START,RX IQ PI ILL Lock Reference Timer Start Value Register Lane 0" hexmask.word 0x0C 0.--11. 1. " RX_IQPI_ILL_LOCK_REFTMR_START_11_0 ,ILL lock reference timer start value" group.word (0x8000+0x50)++0x07 line.word 0x00 "LANE0_RX_IQPI_ILL_LOCK_CALCNT_START_0,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 0 Register Lane 0" hexmask.word 0x00 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_0_11_0 ,ILL lock calibration counter start value" line.word 0x02 "LANE0_RX_IQPI_ILL_LOCK_CALCNT_START_1,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 1 Register Lane 0" hexmask.word 0x02 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_1_11_0 ,ILL lock calibration counter start value" line.word 0x04 "LANE0_RX_IQPI_ILL_LOCK_CALCNT_START_2,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 2 Register Lane 0" hexmask.word 0x04 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_2_11_0 ,ILL lock calibration counter start value" line.word 0x06 "LANE0_RX_IQPI_ILL_LOCK_CALCNT_START_3,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 3 Register Lane 0" hexmask.word 0x06 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_3_11_0 ,ILL lock calibration counter start value" group.word (0x8000+0x60)++0x0D line.word 0x00 "LANE0_RX_EPI_ILL_CAL_CTRL,RX E PI ILL Calibration Control Register Lane 0" bitfld.word 0x00 15. " RX_EPI_ILL_CAL_CTRL_15 ,Start ILL calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_EPI_ILL_CAL_CTRL_14 ,ILL calibration process done" "Not done,Done" textline " " hexmask.word.byte 0x00 0.--7. 1. " RX_EPI_ILL_CAL_CTRL_7_0 ,ILL calibration code" line.word 0x02 "LANE0_RX_EPI_ILL_CAL_START,RX E PI ILL Calibration Start Point Register Lane 0" bitfld.word 0x02 12.--14. " RX_EPI_ILL_CAL_START_14_12 ,ILL calibration initial step size control" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x02 0.--7. 1. " RX_EPI_ILL_CAL_START_7_0 ,ILL calibration code starting point value" line.word 0x04 "LANE0_RX_EPI_ILL_CAL_TCTRL,RX E PI ILL Calibration Timer Control Register Lane 0" bitfld.word 0x04 0.--2. " RX_EPI_ILL_CAL_TCTRL_2_0 ,ILL calibration initial time scale control" "0,1,2,3,4,5,6,7" line.word 0x06 "LANE0_RX_EPI_ILL_CAL_OVRD,RX E PI ILL Calibration Override Register Lane 0" bitfld.word 0x06 15. " RX_EPI_ILL_CAL_OVRD_15 ,ILL calibration code override enable" "Disabled,Enabled" hexmask.word.byte 0x06 0.--7. 1. " RX_EPI_ILL_CAL_OVRD_7_0 ,ILL calibration code override value" line.word 0x08 "LANE0_RX_EPI_ILL_CAL_INIT_TMR,RX E PI ILL Calibration Initialization Timer Register 0" hexmask.word 0x08 0.--11. 1. " RX_EPI_ILL_CAL_INIT_TMR_11_0 ,Initialization wait timer value" line.word 0x0A "LANE0_RX_EPI_ILL_CAL_ITER_TMR,RX E PI ILL Calibration Iteration Timer Register Lane 0" hexmask.word 0x0A 0.--11. 1. " RX_EPI_ILL_CAL_ITER_TMR_11_0 ,Iteration wait timer value" line.word 0x0C "LANE0_RX_EPI_ILL_LOCK_REFTMR_START,RX E PI ILL Lock Reference Timer Start Value Register Lane 0" hexmask.word 0x0C 0.--11. 1. " RX_EPI_ILL_LOCK_REFTMR_START_11_0 ,ILL lock reference timer start value" group.word (0x8000+0x70)++0x07 line.word 0x00 "LANE0_RX_EPI_ILL_LOCK_CALCNT_START_0,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 0 Register Lane 0" hexmask.word 0x00 0.--11. 1. " RX_EPI_ILL_LOCK_CALCNT_START_0_11_0 ,ILL lock calibration counter start value" line.word 0x02 "LANE0_RX_EPI_ILL_LOCK_CALCNT_START_1,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 1 Register Lane 0" hexmask.word 0x02 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_1_11_0 ,ILL lock calibration counter start value" line.word 0x04 "LANE0_RX_IQPI_ILL_LOCK_CALCNT_START_2,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 2 Register Lane 0" hexmask.word 0x04 0.--11. 1. " RX_EPI_ILL_LOCK_CALCNT_START_2_11_0 ,ILL lock calibration counter start value" line.word 0x06 "LANE0_RX_IQPI_ILL_LOCK_CALCNT_START_3,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 3 Register Lane 0" hexmask.word 0x06 0.--11. 1. " RX_EPI_ILL_LOCK_CALCNT_START_3_11_0 ,ILL lock calibration counter start value" group.word (0x8000+0x80)++0x0B line.word 0x00 "LANE0_RX_SDCAL0_CTRL,Signal Detect Calibration 0 Control Register Lane 0" bitfld.word 0x00 15. " RX_SDCAL0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SDCAL0_CTRL_14 ,Calibration process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " RX_EPI_ILL_CAL_CTRL_14 ,No analog calibration response" "Not responded,Responded" rbitfld.word 0x00 12. " RX_SDCAL0_CTRL_14 ,Current analog comparator response" "Not responded,Responded" textline " " bitfld.word 0x00 0.--3. " RX_SDCAL0_CTRL_3_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE0_RX_SDCAL0_OVRD,Signal Detect Calibration 0 Override Register Lane 0" bitfld.word 0x02 15. " RX_SDCAL0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " RX_SDCAL0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 0.--3. " RX_SDCAL0_OVRD_3_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "LANE0_RX_SDCAL0_START,Signal Detect Calibration 0 Start Register Lane 0" bitfld.word 0x04 15. " RX_SDCAL0_START_15 ,Calibration direction" "0,1" bitfld.word 0x04 0.--3. " RX_SDCAL0_START_3_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x06 "LANE0_RX_SDCAL0_TUNE,Signal Detect Calibration 0 Tune Register Lane 0" bitfld.word 0x06 0.--3. " RX_SDCAL0_TUNE_3_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "LANE0_RX_SDCAL0_INIT_TMR,Signal Detect Calibration 0 Initialization Timer Register Lane0" hexmask.word 0x08 0.--8. 1. " RX_SDCAL0_INIT_TMR_8_0 ,Initialization wait timer value" line.word 0x0A "LANE0_RX_SDCAL0_ITER_TMR,Signal Detect Calibration 0 Iteration Timer Register Lane 0" hexmask.word 0x0A 0.--8. 1. " RX_SDCAL0_ITER_TMR_8_0 ,Iteration wait timer value" group.word (0x8000+0x90)++0x0B line.word 0x00 "LANE0_RX_SDCAL1_CTRL,Signal Detect Calibration 1 Control Register Lane 0" bitfld.word 0x00 15. " RX_SDCAL1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SDCAL1_CTRL_14 ,Calibration process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " RX_SDCAL1_CTRL_13 ,No analog calibration response" "Not responded,Responded" rbitfld.word 0x00 12. " RX_SDCAL1_CTRL_12 ,Current analog comparator response" "Not responded,Responded" textline " " bitfld.word 0x00 0.--3. " RX_SDCAL1_CTRL_3_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE0_RX_SDCAL1_OVRD,Signal Detect Calibration 1 Override Register Lane 0" bitfld.word 0x02 15. " RX_SDCAL1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " RX_SDCAL1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 0.--3. " RX_SDCAL1_OVRD_3_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "LANE0_RX_SDCAL1_START,Signal Detect Calibration 1 Start Register Lane 0" bitfld.word 0x04 15. " RX_SDCAL1_START_15 ,Calibration direction" "0,1" bitfld.word 0x04 0.--3. " RX_SDCAL1_START_3_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x06 "LANE0_RX_SDCAL1_TUNE,Signal Detect Calibration 1 Tune Register Lane 0" bitfld.word 0x06 0.--3. " RX_SDCAL1_TUNE_3_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "LANE0_RX_SDCAL1_INIT_TMR,Signal Detect Calibration 1 Initialization Timer Register Lane 0" hexmask.word 0x08 0.--8. 1. " RX_SDCAL1_INIT_TMR_8_0 ,Initialization wait timer value" line.word 0x0A "LANE0_RX_SDCAL1_ITER_TMR,Signal Detect Calibration 1 Iteration Timer Register Lane 0" hexmask.word 0x0A 0.--8. 1. " RX_SDCAL1_ITER_TMR_8_0 ,Iteration wait timer value" group.word (0x8000+0xB0)++0x01 line.word 0x00 "LANE0_RX_SAMP_DAC_CTRL,Sampler Error DAC Control Register Lane 0" bitfld.word 0x00 0.--5. " RX_SAMP_DAC_CTRL_5_0 ,Sampler error DAC value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8000+0x100)++0x0B line.word 0x00 "LANE0_RX_CDRLF_CNFG,CDRLF Configuration Register Lane 0" rbitfld.word 0x00 15. " RX_CDRLF_CNFG_15 ,CDRLF fast phase lock locked detected" "Not detected,Detected" bitfld.word 0x00 14. " RX_CDRLF_CNFG_14 ,CDRLF fast phase lock diagnostic enable" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " RX_CDRLF_CNFG_13 ,CDRLF fast phase lock enable" "Disabled,Enabled" bitfld.word 0x00 12. " RX_CDRLF_CNFG_12 ,CDRLF fast frequency lock enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " RX_CDRLF_CNFG_11 ,CDRLF second order loop integrator max clear enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_CDRLF_CNFG_10 ,CDRLF reset on CDRLF PM accumulator max" "No reset,Reset" textline " " bitfld.word 0x00 9. " RX_CDRLF_CNFG_9 ,CDRLF freeze on electrical idle detect" "Not detected,Detected" bitfld.word 0x00 8. " RX_CDRLF_CNFG_8 ,CDRLF reset on electrical idle detect" "Not detected,Detected" textline " " bitfld.word 0x00 7. " RX_CDRLF_CNFG_7 ,CDRLF data filter enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " RX_CDRLF_CNFG_5_0 ,CDRLF second order loop integrator threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE0_RX_CDRLF_CNFG2,CDRLF Configuration Register 2 Lane 0" bitfld.word 0x02 4.--6. " RX_CDRLF_CNFG2_6 ,CDRLF diagnostic mode control" "0,1,2,3,4,5,6,7" bitfld.word 0x02 2. " RX_CDRLF_CNFG2_2 ,CDLRF reset hold" "Not held,Held" textline " " bitfld.word 0x02 1. " RX_CDRLF_CNFG2_1 ,CDRLF second order loop disable" "No,Yes" bitfld.word 0x02 0. " RX_CDRLF_CNFG2_0 ,CDRLF first order loop disable" "No,Yes" line.word 0x04 "LANE0_RX_CDRLF_MGN_DIAG,CDRLF Margin Diagnostic Register 2 Lane 0" bitfld.word 0x04 2. " RX_CDRLF_MGN_DIAG_2 ,CDRLF PI override down" "No override,Override" bitfld.word 0x04 1. " RX_CDRLF_MGN_DIAG_1 ,CDRLF PI override up" "No override,Override" textline " " bitfld.word 0x04 0. " RX_CDRLF_MGN_DIAG_0 ,CDRLF PI override enable" "Disabled,Enabled" line.word 0x06 "LANE0_RX_CDRLF_FPL_TMR0,CDRLF Fast Phase Lock Timer Value Register 0 Lane 0" bitfld.word 0x06 4.--7. " RX_CDRLF_FPL_TMR0_7_4 ,Fast phase lock timer accumulate state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x06 0.--3. " RX_CDRLF_FPL_TMR0_3_0 ,Fast phase lock timer delay state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "LANE0_RX_CDRLF_FPL_TMR1,CDRLF Fast Phase Lock Timer Value Register 1 Lane 0" bitfld.word 0x08 8.--11. " RX_CDRLF_FPL_TMR1_11_8 ,Fast phase lock timer trigger 1 state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x08 4.--7. " RX_CDRLF_FPL_TMR1_7_4 ,Fast phase lock timer trigger 2 state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x08 0.--3. " RX_CDRLF_FPL_TMR1_3_0 ,Fast phase lock timer trigger 3 state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0A "LANE0_RX_CDRLF_FFL_TMR,CDRLF Fast Frequency Lock Timer Value Register Lane 0" bitfld.word 0x0A 0.--5. " RX_CDRLF_FFL_TMR_5_0 ,Fast frequency lock step timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8000+0x110)++0x09 line.word 0x00 "LANE0_RX_CDRLF_FFL0_CTRL,CDRLF Fast Frequency Lock Step 0 Control Register Lane 0" bitfld.word 0x00 14.--15. " RX_CDRLF_FFL0_CTRL_15_14 ,FFL step 0 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x00 8.--12. " RX_CDRLF_FFL0_CTRL_12_8 ,FFL step 0 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x00 0.--4. " RX_CDRLF_FFL0_CTRL_4_0 ,FFL step 0 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x02 "LANE0_RX_CDRLF_FFL1_CTRL,CDRLF Fast Frequency Lock Step 1 Control Register Lane 0" bitfld.word 0x02 14.--15. " RX_CDRLF_FFL1_CTRL_15_14 ,FFL step 1 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x02 8.--12. " RX_CDRLF_FFL1_CTRL_12_8 ,FFL step 1 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x02 0.--4. " RX_CDRLF_FFL1_CTRL_4_0 ,FFL step 1 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE0_RX_CDRLF_FFL2_CTRL,CDRLF Fast Frequency Lock Step 2 Control Register Lane 0" bitfld.word 0x04 14.--15. " RX_CDRLF_FFL2_CTRL_15_14 ,FFL step 2 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x04 8.--12. " RX_CDRLF_FFL2_CTRL_12_8 ,FFL step 2 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x04 0.--4. " RX_CDRLF_FFL2_CTRL_4_0 ,FFL step 2 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "LANE0_RX_CDRLF_FFL3_CTRL,CDRLF Fast Frequency Lock Step 3 Control Register Lane 0" bitfld.word 0x06 14.--15. " RX_CDRLF_FFL3_CTRL_15_14 ,FFL step 3 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x06 8.--12. " RX_CDRLF_FFL3_CTRL_12_8 ,FFL step 3 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x06 0.--4. " RX_CDRLF_FFL3_CTRL_4_0 ,FFL step 3 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "LANE0_RX_CDRLF_FFL4_CTRL,CDRLF Fast Frequency Lock Step 4 Control Register Lane 0" bitfld.word 0x08 14.--15. " RX_CDRLF_FFL4_CTRL_15_14 ,FFL step 4 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x08 8.--12. " RX_CDRLF_FFL4_CTRL_12_8 ,FFL step 4 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x08 0.--4. " RX_CDRLF_FFL4_CTRL_4_0 ,FFL step 4 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (0x8000+0x120)++0x17 line.word 0x00 "LANE0_RX_SIGDET_HL_FILT_TMR,Receiver Signal Detect Filter High To Low Filter Timer Register Lane 0" hexmask.word 0x00 0.--9. 1. " RX_SIGDET_HL_FILT_TMR_9_0 ,Signal detect filter high to low filter timer value" line.word 0x02 "LANE0_RX_SIGDET_HL_DLY_TMR,Receiver Signal Detect Filter High To Low Delay Timer Register Lane 0" hexmask.word 0x02 0.--9. 1. " RX_SIGDET_HL_DLY_TMR_9_0 ,Signal detect filter high to low delay timer value" line.word 0x04 "LANE0_RX_SIGDET_HL_MIN_TMR,Receiver Signal Detect Filter High To Low Min Timer Register Lane 0" hexmask.word 0x04 0.--9. 1. " RX_SIGDET_HL_MIN_TMR_9_0 ,Signal detect filter high to low min timer value" line.word 0x06 "LANE0_RX_SIGDET_HL_MIN_TMR,Receiver Signal Detect Filter High To Low Init Timer Register Lane 0" hexmask.word 0x06 0.--9. 1. " RX_SIGDET_HL_INIT_TMR_9_0 ,Signal detect init timer value" line.word 0x08 "LANE0_RX_SIGDET_LH_FILT_TMR,Receiver Signal Detect Filter Low To High Filter Timer Register Lane 0" hexmask.word 0x08 0.--9. 1. " RX_SIGDET_LH_FILT_TMR_9_0 ,Signal detect filter low to high filter timer value" line.word 0x0A "LANE0_RX_SIGDET_LH_DLY_TMR,Receiver Signal Detect Filter Low To High Delay Timer Register Lane 0" hexmask.word 0x0A 0.--9. 1. " RX_SIGDET_LH_DLY_TMR_9_0 ,Signal detect filter low to high delay timer value" line.word 0x0C "LANE0_RX_SIGDET_LH_MIN_TMR,Receiver Signal Detect Filter Low To High Min Timer Register Lane 0" hexmask.word 0x0C 0.--9. 1. " RX_SIGDET_LH_MIN_TMR_9_0 ,Signal detect filter low to high min timer value" line.word 0x0E "LANE0_RX_SIGDET_LH_INIT_TMR,Receiver Signal Detect Filter Low To High Init Timer Register Lane 0" hexmask.word 0x0E 0.--9. 1. " RX_SIGDET_LH_INIT_TMR_9_0 ,Signal detect init timer value" line.word 0x10 "LANE0_RX_LFPSDET_FILT_TMR,Receiver LFPS Detect Filter Filter Timer Register Lane 0" hexmask.word 0x10 0.--9. 1. " RX_LFPSDET_FILT_TMR_9_0 ,LFPS detect filter timer value" line.word 0x12 "LANE0_RX_LFPSDET_DLY_TMR,Receiver LFPS Detect Filter Delay Timer Register Lane 0" hexmask.word 0x12 0.--9. 1. " RX_LFPSDET_DLY_TMR_9_0 ,LFPS detect filter delay timer value" line.word 0x14 "LANE0_RX_LFPSDET_MIN_TMR,Receiver LFPS Detect Min Timer Register Lane 0" hexmask.word 0x14 0.--9. 1. " RX_LFPSDET_MIN_TMR_9_0 ,LFPS detect min timer value" line.word 0x16 "LANE0_RX_LFPSDET_INIT_TMR,Receiver LFPS Detect Init Timer Register Lane 0" hexmask.word 0x16 0.--9. 1. " RX_LFPSDET_INIT_TMR_9_0 ,LFPS detect init timer value" group.word (0x8000+0x140)++0x01 line.word 0x00 "LANE0_RX_EYESURF_CTRL,Eye Surf Control Register Lane 0" bitfld.word 0x00 15. " RX_EYESURF_CTRL_15 ,Eye surf process enable" "Disabled,Enabled" rbitfld.word 0x00 14. " RX_EYESURF_CTRL_14 ,Eye surf process has completed" "Not completed,Completed" group.word (0x8000+0x148)++0x0B line.word 0x00 "LANE0_RX_EYESURF_TMR_DELLOW,Eye Surf Timer Delay Low Register Lane 0" line.word 0x02 "LANE0_RX_EYESURF_TMR_DELHIGH,Eye Surf Timer Delay High Register Lane 0" line.word 0x04 "LANE0_RX_EYESURF_TMR_TESTLOW,Eye Surf Timer Test Low Register Lane 0" line.word 0x06 "LANE0_RX_EYESURF_TMR_TESTHIGH,Eye Surf Timer Test High Register Lane 0" line.word 0x08 "LANE0_RX_EYESURF_NS_COORD,Eye Surf North South Test Point Coordinate Register Lane 0" bitfld.word 0x08 8. " RX_EYESURF_NS_COORD_8 ,Test point coordinate north south direction" "0,1" hexmask.word.byte 0x08 0.--6. 0x01 " RX_EYESURF_NS_COORD_6_0 ,Test point coordinate north south offset" line.word 0x0A "LANE0_RX_EYESURF_EW_COORD,Eye Surf East West Test Point Coordinate Register Lane 0" bitfld.word 0x0A 8. " RX_EYESURF_EW_COORD_8 ,Test point coordinate east west direction" "0,1" hexmask.word.byte 0x0A 0.--4. 0x01 " RX_EYESURF_EW_COORD_4_0 ,Test point coordinate east west offset" rgroup.word (0x8000+0x154)++0x01 line.word 0x00 "LANE0_RX_EYESURF_ERRCNT,Eye Surf Bit Error Count Register Lane 0" group.word (0x8000+0x160)++0x03 line.word 0x00 "LANE0_RX_BIST_CTRL,Receiver BIST Control Register Lane 0" bitfld.word 0x00 8.--11. " RX_BIST_CTRL_11_8 ,Receiver BIST mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4. " RX_BIST_CTRL_4 ,Receiver BIST error reset" "No reset,Reset" textline " " bitfld.word 0x00 1. " RX_BIST_CTRL_1 ,Receiver BIST user defined data FIFO clear" "No clear,Clear" bitfld.word 0x00 0. " RX_BIST_CTRL_0 ,Receiver BIST enable" "Disabled,Enabled" line.word 0x02 "LANE0_RX_BIST_SYNCCNT,Receiver BIST Sync Count Register Lane 0" wgroup.word (0x8000+0x164)++0x01 line.word 0x00 "LANE0_RX_BIST_UDDWR,Receiver BIST User Defined Data Write Register Lane 0" hexmask.word 0x00 0.--9. 1. " RX_BIST_UDDWR_9_0 ,Receiver BIST user defined data" rgroup.word (0x8000+0x166)++0x01 line.word 0x00 "LANE0_RX_BIST_ERRCNT,Receiver BIST Error Count Register Lane 0" group.word (0x8000+0x168)++0x05 line.word 0x00 "LANE0_XCVR_CMSMT_CLK_FREQ_MSMT_CTRL,Clock Frequency Measurement Control Register Lane 0" bitfld.word 0x00 15. " XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_15 ,Start test clock measurement" "Not started,Started" rbitfld.word 0x00 14. " XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_14 ,Test clock measurement done" "Not done,Done" line.word 0x02 "LANE0_XCVR_CMSMT_TEST_CLK_SEL,Test Clock Selection Register Lane 0" bitfld.word 0x02 0.--2. " XCVR_CMSMT_TEST_CLK_SEL_2_0 ,Test clock select" "0,1,2,3,4,5,6,7" line.word 0x04 "LANE0_XCVR_CMSMT_REF_CLK_TMR_VALUE,Reference Clock Timer Value Register Lane 0" hexmask.word 0x04 0.--11. 1. " XCVR_CMSMT_REF_CLK_TMR_VALUE_11_0 ,Reference clock timer value" rgroup.word (0x8000+0x16E)++0x01 line.word 0x00 "LANE0_XCVR_CMSMT_TEST_CLK_CNT_VALUE,Test Clock Counter Value Register Lane 0" hexmask.word 0x00 0.--11. 1. " XCVR_CMSMT_TEST_CLK_CNT_VALUE_11_0 ,Test clock counter value" group.word (0x8000+0x1C0)++0x15 line.word 0x00 "LANE0_RX_SLC_CTRL,RX Sampler Latch Calibration Control Register Lane 0" bitfld.word 0x00 15. " RX_SLC_CTRL_15 ,Start RX sampler latch calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SLC_CTRL_14 ,RX sampler latch calibration done" "Not done,Done" textline " " bitfld.word 0x00 13. " RX_SLC_CTRL_13 ,Analog calibration enable override" "Disabled,Enabled" bitfld.word 0x00 11. " RX_SLC_CTRL_11 ,I odd positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " RX_SLC_CTRL_10 ,Q odd positive calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 9. " RX_SLC_CTRL_9 ,E odd positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " RX_SLC_CTRL_8 ,I odd negative calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 7. " RX_SLC_CTRL_7 ,Q odd negative calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " RX_SLC_CTRL_6 ,E odd negative calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 5. " RX_SLC_CTRL_5 ,I even positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_SLC_CTRL_4 ,Q even positive calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 3. " RX_SLC_CTRL_3 ,E even positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " RX_SLC_CTRL_2 ,I even negative calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 1. " RX_SLC_CTRL_1 ,Q even negative calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RX_SLC_CTRL_0 ,E even negative calibration unit enable" "Disabled,Enabled" line.word 0x02 "LANE0_RX_SLC_EN_INIT_TMR,RX Sampler Latch Calibration Enable Initialization Timer Value Register Lane 0" bitfld.word 0x02 0.--5. " RX_SLC_EN_INIT_TMR_5_0 ,RX sampler latch calibration enable initialization timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE0_RX_SLC_CU_INIT_TMR,RX Sampler Latch Calibration Unit Initialization Timer Value Register Lane 0" bitfld.word 0x04 0.--5. " RX_SLC_CU_INIT_TMR_5_0 ,RX sampler latch calibration unit initialization timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x06 "LANE0_RX_SLC_CU_ITER_TMR,RX Sampler Latch Calibration Unit Iteration Timer Value Register Lane 0" bitfld.word 0x06 0.--5. " RX_SLC_CU_ITER_TMR_5_0 ,RX sampler latch calibration unit iteration timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "LANE0_RX_SLC_IE_MASK,RX Sampler Latch Calibration I Even Data Mask Register Lane 0" bitfld.word 0x08 9. " RX_SLC_IE_MASK_9 ,I even data mask 9" "Not masked,Masked" bitfld.word 0x08 8. " RX_SLC_IE_MASK_8 ,I even data mask 8" "Not masked,Masked" textline " " bitfld.word 0x08 7. " RX_SLC_IE_MASK_7 ,I even data mask 7" "Not masked,Masked" bitfld.word 0x08 6. " RX_SLC_IE_MASK_6 ,I even data mask 6" "Not masked,Masked" textline " " bitfld.word 0x08 5. " RX_SLC_IE_MASK_5 ,I even data mask 5" "Not masked,Masked" bitfld.word 0x08 4. " RX_SLC_IE_MASK_4 ,I even data mask 4" "Not masked,Masked" textline " " bitfld.word 0x08 3. " RX_SLC_IE_MASK_3 ,I even data mask 3" "Not masked,Masked" bitfld.word 0x08 2. " RX_SLC_IE_MASK_2 ,I even data mask 2" "Not masked,Masked" textline " " bitfld.word 0x08 1. " RX_SLC_IE_MASK_1 ,I even data mask 1" "Not masked,Masked" bitfld.word 0x08 0. " RX_SLC_IE_MASK_0 ,I even data mask 0" "Not masked,Masked" line.word 0x0A "LANE0_RX_SLC_IO_MASK,RX Sampler Latch Calibration I Odd Data Mask Register Lane 0" bitfld.word 0x0A 9. " RX_SLC_IO_MASK_9 ,I odd data mask 9" "Not masked,Masked" bitfld.word 0x0A 8. " RX_SLC_IO_MASK_8 ,I odd data mask 8" "Not masked,Masked" textline " " bitfld.word 0x0A 7. " RX_SLC_IO_MASK_7 ,I odd data mask 7" "Not masked,Masked" bitfld.word 0x0A 6. " RX_SLC_IO_MASK_6 ,I odd data mask 6" "Not masked,Masked" textline " " bitfld.word 0x0A 5. " RX_SLC_IO_MASK_5 ,I odd data mask 5" "Not masked,Masked" bitfld.word 0x0A 4. " RX_SLC_IO_MASK_4 ,I odd data mask 4" "Not masked,Masked" textline " " bitfld.word 0x0A 3. " RX_SLC_IO_MASK_3 ,I odd data mask 3" "Not masked,Masked" bitfld.word 0x0A 2. " RX_SLC_IO_MASK_2 ,I odd data mask 2" "Not masked,Masked" textline " " bitfld.word 0x0A 1. " RX_SLC_IO_MASK_1 ,I odd data mask 1" "Not masked,Masked" bitfld.word 0x0A 0. " RX_SLC_IO_MASK_0 ,I odd data mask 0" "Not masked,Masked" line.word 0x0C "LANE0_RX_SLC_QE_MASK,RX Sampler Latch Calibration Q Even Data Mask Register Lane 0" bitfld.word 0x0C 9. " RX_SLC_QE_MASK_9 ,Q even data mask 9" "Not masked,Masked" bitfld.word 0x0C 8. " RX_SLC_QE_MASK_8 ,Q even data mask 8" "Not masked,Masked" textline " " bitfld.word 0x0C 7. " RX_SLC_QE_MASK_7 ,Q even data mask 7" "Not masked,Masked" bitfld.word 0x0C 6. " RX_SLC_QE_MASK_6 ,Q even data mask 6" "Not masked,Masked" textline " " bitfld.word 0x0C 5. " RX_SLC_QE_MASK_5 ,Q even data mask 5" "Not masked,Masked" bitfld.word 0x0C 4. " RX_SLC_QE_MASK_4 ,Q even data mask 4" "Not masked,Masked" textline " " bitfld.word 0x0C 3. " RX_SLC_QE_MASK_3 ,Q even data mask 3" "Not masked,Masked" bitfld.word 0x0C 2. " RX_SLC_QE_MASK_2 ,Q even data mask 2" "Not masked,Masked" textline " " bitfld.word 0x0C 1. " RX_SLC_QE_MASK_1 ,Q even data mask 1" "Not masked,Masked" bitfld.word 0x0C 0. " RX_SLC_QE_MASK_0 ,Q even data mask 0" "Not masked,Masked" line.word 0x0E "LANE0_RX_SLC_QO_MASK,RX Sampler Latch Calibration Q Odd Data Mask Register Lane 0" bitfld.word 0x0E 9. " RX_SLC_QO_MASK_9 ,Q odd data mask 9" "Not masked,Masked" bitfld.word 0x0E 8. " RX_SLC_QO_MASK_8 ,Q odd data mask 8" "Not masked,Masked" textline " " bitfld.word 0x0E 7. " RX_SLC_QO_MASK_7 ,Q odd data mask 7" "Not masked,Masked" bitfld.word 0x0E 6. " RX_SLC_QO_MASK_6 ,Q odd data mask 6" "Not masked,Masked" textline " " bitfld.word 0x0E 5. " RX_SLC_QO_MASK_5 ,Q odd data mask 5" "Not masked,Masked" bitfld.word 0x0E 4. " RX_SLC_QO_MASK_4 ,Q odd data mask 4" "Not masked,Masked" textline " " bitfld.word 0x0E 3. " RX_SLC_QO_MASK_3 ,Q odd data mask 3" "Not masked,Masked" bitfld.word 0x0E 2. " RX_SLC_QO_MASK_2 ,Q odd data mask 2" "Not masked,Masked" textline " " bitfld.word 0x0E 1. " RX_SLC_QO_MASK_1 ,Q odd data mask 1" "Not masked,Masked" bitfld.word 0x0E 0. " RX_SLC_QO_MASK_0 ,Q odd data mask 0" "Not masked,Masked" line.word 0x10 "LANE0_RX_SLC_EE_MASK,RX Sampler Latch Calibration E Even Data Mask Register Lane 0" bitfld.word 0x10 9. " RX_SLC_EE_MASK_9 ,E even data mask 9" "Not masked,Masked" bitfld.word 0x10 8. " RX_SLC_EE_MASK_8 ,E even data mask 8" "Not masked,Masked" textline " " bitfld.word 0x10 7. " RX_SLC_EE_MASK_7 ,E even data mask 7" "Not masked,Masked" bitfld.word 0x10 6. " RX_SLC_EE_MASK_6 ,E even data mask 6" "Not masked,Masked" textline " " bitfld.word 0x10 5. " RX_SLC_EE_MASK_5 ,E even data mask 5" "Not masked,Masked" bitfld.word 0x10 4. " RX_SLC_EE_MASK_4 ,E even data mask 4" "Not masked,Masked" textline " " bitfld.word 0x10 3. " RX_SLC_EE_MASK_3 ,E even data mask 3" "Not masked,Masked" bitfld.word 0x10 2. " RX_SLC_EE_MASK_2 ,E even data mask 2" "Not masked,Masked" textline " " bitfld.word 0x10 1. " RX_SLC_EE_MASK_1 ,E even data mask 1" "Not masked,Masked" bitfld.word 0x10 0. " RX_SLC_EE_MASK_0 ,E even data mask 0" "Not masked,Masked" line.word 0x12 "LANE0_RX_SLC_EO_MASK,RX Sampler Latch Calibration E Odd Data Mask Register Lane 0" bitfld.word 0x12 9. " RX_SLC_EO_MASK_9 ,E odd data mask 9" "Not masked,Masked" bitfld.word 0x12 8. " RX_SLC_EO_MASK_8 ,E odd data mask 8" "Not masked,Masked" textline " " bitfld.word 0x12 7. " RX_SLC_EO_MASK_7 ,E odd data mask 7" "Not masked,Masked" bitfld.word 0x12 6. " RX_SLC_EO_MASK_6 ,E odd data mask 6" "Not masked,Masked" textline " " bitfld.word 0x12 5. " RX_SLC_EO_MASK_5 ,E odd data mask 5" "Not masked,Masked" bitfld.word 0x12 4. " RX_SLC_EO_MASK_4 ,E odd data mask 4" "Not masked,Masked" textline " " bitfld.word 0x12 3. " RX_SLC_EO_MASK_3 ,E odd data mask 3" "Not masked,Masked" bitfld.word 0x12 2. " RX_SLC_EO_MASK_2 ,E odd data mask 2" "Not masked,Masked" textline " " bitfld.word 0x12 1. " RX_SLC_EO_MASK_1 ,E odd data mask 1" "Not masked,Masked" bitfld.word 0x12 0. " RX_SLC_EO_MASK_0 ,E odd data mask 0" "Not masked,Masked" line.word 0x14 "LANE0_RX_SLC_DATA_THR,RX Sampler Latch Calibration Data Threshold Register Lane 0" bitfld.word 0x14 0.--3. " RX_SLC_DATA_THR_3_0 ,Data threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word (0x8000+0x200)++0xCB line.word 0x00 "LANE0_RX_SLC_IOP0_CTRL,RX Sampler Latch I Odd Positive 0 Calibration Unit Control Register Lane 0" bitfld.word 0x00 15. " RX_SLC_IOP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SLC_IOP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x00 13. " RX_SLC_IOP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x00 12. " RX_SLC_IOP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x00 0.--5. " RX_SLC_IOP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE0_RX_SLC_IOP0_OVRD,RX Sampler Latch I Odd Positive 0 Calibration Unit Override Register Lane 0" bitfld.word 0x02 15. " RX_SLC_IOP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " RX_SLC_IOP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 0.--5. " RX_SLC_IOP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE0_RX_SLC_IOP0_START,RX Sampler Latch I Odd Positive 0 Calibration Unit Start Register Lane 0" bitfld.word 0x04 15. " RX_SLC_IOP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x04 0.--5. " RX_SLC_IOP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x06 "LANE0_RX_SLC_IOP0_TUNE,RX Sampler Latch I Odd Positive 0 Calibration Unit Tune Register Lane 0" bitfld.word 0x06 0.--5. " RX_SLC_IOP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "LANE0_RX_SLC_IOP1_CTRL,RX Sampler Latch I Odd Positive 1 Calibration Unit Control Register Lane 0" bitfld.word 0x08 15. " RX_SLC_IOP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x08 14. " RX_SLC_IOP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x08 13. " RX_SLC_IOP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x08 12. " RX_SLC_IOP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x08 0.--5. " RX_SLC_IOP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0A "LANE0_RX_SLC_IOP1_OVRD,RX Sampler Latch I Odd Positive 1 Calibration Unit Override Register Lane 0" bitfld.word 0x0A 15. " RX_SLC_IOP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x0A 14. " RX_SLC_IOP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x0A 0.--5. " RX_SLC_IOP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0C "LANE0_RX_SLC_IOP1_START,RX Sampler Latch I Odd Positive 1 Calibration Unit Start Register Lane 0" bitfld.word 0x0C 15. " RX_SLC_IOP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x0C 0.--5. " RX_SLC_IOP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0E "LANE0_RX_SLC_IOP1_TUNE,RX Sampler Latch I Odd Positive 1 Calibration Unit Tune Register Lane 0" bitfld.word 0x0E 0.--5. " RX_SLC_IOP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x10 "LANE0_RX_SLC_QOP0_CTRL,RX Sampler Latch Q Odd Positive 0 Calibration Unit Control Register Lane 0" bitfld.word 0x10 15. " RX_SLC_QOP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x10 14. " RX_SLC_QOP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x10 13. " RX_SLC_QOP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x10 12. " RX_SLC_QOP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x10 0.--5. " RX_SLC_QOP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x12 "LANE0_RX_SLC_QOP0_OVRD,RX Sampler Latch Q Odd Positive 0 Calibration Unit Override Register Lane 0" bitfld.word 0x12 15. " RX_SLC_QOP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x12 14. " RX_SLC_QOP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x12 0.--5. " RX_SLC_QOP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x14 "LANE0_RX_SLC_QOP0_START,RX Sampler Latch Q Odd Positive 0 Calibration Unit Start Register Lane 0" bitfld.word 0x14 15. " RX_SLC_QOP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x14 0.--5. " RX_SLC_QOP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x16 "LANE0_RX_SLC_QOP0_TUNE,RX Sampler Latch Q Odd Positive 0 Calibration Unit Tune Register Lane 0" bitfld.word 0x16 0.--5. " RX_SLC_QOP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x18 "LANE0_RX_SLC_QOP1_CTRL,RX Sampler Latch Q Odd Positive 1 Calibration Unit Control Register Lane 0" bitfld.word 0x18 15. " RX_SLC_QOP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x18 14. " RX_SLC_QOP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x18 13. " RX_SLC_QOP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x18 12. " RX_SLC_QOP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x18 0.--5. " RX_SLC_QOP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x1A "LANE0_RX_SLC_QOP1_OVRD,RX Sampler Latch Q Odd Positive 1 Calibration Unit Override Register Lane 0" bitfld.word 0x1A 15. " RX_SLC_QOP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x1A 14. " RX_SLC_QOP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x1A 0.--5. " RX_SLC_QOP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x1C "LANE0_RX_SLC_QOP1_START,RX Sampler Latch Q Odd Positive 1 Calibration Unit Start Register Lane 0" bitfld.word 0x1C 15. " RX_SLC_QOP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x1C 0.--5. " RX_SLC_QOP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x1E "LANE0_RX_SLC_QOP1_TUNE,RX Sampler Latch Q Odd Positive 1 Calibration Unit Tune Register Lane 0" bitfld.word 0x1E 0.--5. " RX_SLC_QOP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x20 "LANE0_RX_SLC_EOP0_CTRL,RX Sampler Latch E Odd Positive 0 Calibration Unit Control Register Lane 0" bitfld.word 0x20 15. " RX_SLC_EOP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x20 14. " RX_SLC_EOP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x20 13. " RX_SLC_EOP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x20 12. " RX_SLC_EOP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x20 0.--5. " RX_SLC_EOP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x22 "LANE0_RX_SLC_EOP0_OVRD,RX Sampler Latch E Odd Positive 0 Calibration Unit Override Register Lane 0" bitfld.word 0x22 15. " RX_SLC_EOP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x22 14. " RX_SLC_EOP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x22 0.--5. " RX_SLC_EOP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x24 "LANE0_RX_SLC_EOP0_START,RX Sampler Latch E Odd Positive 0 Calibration Unit Start Register Lane 0" bitfld.word 0x24 15. " RX_SLC_EOP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x24 0.--5. " RX_SLC_EOP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x26 "LANE0_RX_SLC_EOP0_TUNE,RX Sampler Latch E Odd Positive 0 Calibration Unit Tune Register Lane 0" bitfld.word 0x26 0.--5. " RX_SLC_EOP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x28 "LANE0_RX_SLC_EOP1_CTRL,RX Sampler Latch E Odd Positive 1 Calibration Unit Control Register Lane 0" bitfld.word 0x28 15. " RX_SLC_EOP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x28 14. " RX_SLC_EOP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x28 13. " RX_SLC_EOP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x28 12. " RX_SLC_EOP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x28 0.--5. " RX_SLC_EOP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x2A "LANE0_RX_SLC_EOP1_OVRD,RX Sampler Latch E Odd Positive 1 Calibration Unit Override Register Lane 0" bitfld.word 0x2A 15. " RX_SLC_EOP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x2A 14. " RX_SLC_EOP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x2A 0.--5. " RX_SLC_EOP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x2C "LANE0_RX_SLC_EOP1_START,RX Sampler Latch E Odd Positive 1 Calibration Unit Start Register Lane 0" bitfld.word 0x2C 15. " RX_SLC_EOP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x2C 0.--5. " RX_SLC_EOP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x2E "LANE0_RX_SLC_EOP1_TUNE,RX Sampler Latch E Odd Positive 1 Calibration Unit Tune Register Lane 0" bitfld.word 0x2E 0.--5. " RX_SLC_EOP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x30 "LANE0_RX_SLC_ION0_CTRL,RX Sampler Latch I Odd Negative 0 Calibration Unit Control Register Lane 0" bitfld.word 0x30 15. " RX_SLC_ION0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x30 14. " RX_SLC_ION0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x30 13. " RX_SLC_ION0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x30 12. " RX_SLC_ION0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x30 0.--5. " RX_SLC_ION0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x32 "LANE0_RX_SLC_ION0_OVRD,RX Sampler Latch I Odd Negative 0 Calibration Unit Override Register Lane 0" bitfld.word 0x32 15. " RX_SLC_ION0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x32 14. " RX_SLC_ION0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x32 0.--5. " RX_SLC_ION0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x34 "LANE0_RX_SLC_ION0_START,RX Sampler Latch I Odd Negative 0 Calibration Unit Start Register Lane 0" bitfld.word 0x34 15. " RX_SLC_ION0_START_15 ,Calibration direction" "0,1" bitfld.word 0x34 0.--5. " RX_SLC_ION0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x36 "LANE0_RX_SLC_ION0_TUNE,RX Sampler Latch I Odd Negative 0 Calibration Unit Tune Register Lane 0" bitfld.word 0x36 0.--5. " RX_SLC_ION0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x38 "LANE0_RX_SLC_ION1_CTRL,RX Sampler Latch I Odd Negative 1 Calibration Unit Control Register Lane 0" bitfld.word 0x38 15. " RX_SLC_ION1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x38 14. " RX_SLC_ION1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x38 13. " RX_SLC_ION1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x38 12. " RX_SLC_ION1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x38 0.--5. " RX_SLC_ION1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x3A "LANE0_RX_SLC_ION1_OVRD,RX Sampler Latch I Odd Negative 1 Calibration Unit Override Register Lane 0" bitfld.word 0x3A 15. " RX_SLC_ION1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x3A 14. " RX_SLC_ION1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x3A 0.--5. " RX_SLC_ION1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x3C "LANE0_RX_SLC_ION1_START,RX Sampler Latch I Odd Negative 1 Calibration Unit Start Register Lane 0" bitfld.word 0x3C 15. " RX_SLC_ION1_START_15 ,Calibration direction" "0,1" bitfld.word 0x3C 0.--5. " RX_SLC_ION1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x3E "LANE0_RX_SLC_ION1_TUNE,RX Sampler Latch I Odd Negative 1 Calibration Unit Tune Register Lane 0" bitfld.word 0x3E 0.--5. " RX_SLC_ION1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x40 "LANE0_RX_SLC_QON0_CTRL,RX Sampler Latch Q Odd Negative 0 Calibration Unit Control Register Lane 0" bitfld.word 0x40 15. " RX_SLC_QON0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x40 14. " RX_SLC_QON0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x40 13. " RX_SLC_QON0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x40 12. " RX_SLC_QON0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x40 0.--5. " RX_SLC_QON0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x42 "LANE0_RX_SLC_QON0_OVRD,RX Sampler Latch Q Odd Negative 0 Calibration Unit Override Register Lane 0" bitfld.word 0x42 15. " RX_SLC_QON0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x42 14. " RX_SLC_QON0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x42 0.--5. " RX_SLC_QON0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x44 "LANE0_RX_SLC_QON0_START,RX Sampler Latch Q Odd Negative 0 Calibration Unit Start Register Lane 0" bitfld.word 0x44 15. " RX_SLC_QON0_START_15 ,Calibration direction" "0,1" bitfld.word 0x44 0.--5. " RX_SLC_QON0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x46 "LANE0_RX_SLC_QON0_TUNE,RX Sampler Latch Q Odd Negative 0 Calibration Unit Tune Register Lane 0" bitfld.word 0x46 0.--5. " RX_SLC_QON0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x48 "LANE0_RX_SLC_QON1_CTRL,RX Sampler Latch Q Odd Negative 1 Calibration Unit Control Register Lane 0" bitfld.word 0x48 15. " RX_SLC_QON1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x48 14. " RX_SLC_QON1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x48 13. " RX_SLC_QON1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x48 12. " RX_SLC_QON1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x48 0.--5. " RX_SLC_QON1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x4A "LANE0_RX_SLC_QON1_OVRD,RX Sampler Latch Q Odd Negative 1 Calibration Unit Override Register Lane 0" bitfld.word 0x4A 15. " RX_SLC_QON1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x4A 14. " RX_SLC_QON1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x4A 0.--5. " RX_SLC_QON1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x4C "LANE0_RX_SLC_QON1_START,RX Sampler Latch Q Odd Negative 1 Calibration Unit Start Register Lane 0" bitfld.word 0x4C 15. " RX_SLC_QON1_START_15 ,Calibration direction" "0,1" bitfld.word 0x4C 0.--5. " RX_SLC_QON1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x4E "LANE0_RX_SLC_QON1_TUNE,RX Sampler Latch Q Odd Negative 1 Calibration Unit Tune Register Lane 0" bitfld.word 0x4E 0.--5. " RX_SLC_QON1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x50 "LANE0_RX_SLC_EON0_CTRL,RX Sampler Latch E Odd Negative 0 Calibration Unit Control Register Lane 0" bitfld.word 0x50 15. " RX_SLC_EON0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x50 14. " RX_SLC_EON0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x50 13. " RX_SLC_EON0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x50 12. " RX_SLC_EON0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x50 0.--5. " RX_SLC_EON0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x52 "LANE0_RX_SLC_EON0_OVRD,RX Sampler Latch E Odd Negative 0 Calibration Unit Override Register Lane 0" bitfld.word 0x52 15. " RX_SLC_EON0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x52 14. " RX_SLC_EON0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x52 0.--5. " RX_SLC_EON0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x54 "LANE0_RX_SLC_EON0_START,RX Sampler Latch E Odd Negative 0 Calibration Unit Start Register Lane 0" bitfld.word 0x54 15. " RX_SLC_EON0_START_15 ,Calibration direction" "0,1" bitfld.word 0x54 0.--5. " RX_SLC_EON0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x56 "LANE0_RX_SLC_EON0_TUNE,RX Sampler Latch E Odd Negative 0 Calibration Unit Tune Register Lane 0" bitfld.word 0x56 0.--5. " RX_SLC_EON0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x58 "LANE0_RX_SLC_EON1_CTRL,RX Sampler Latch E Odd Negative 1 Calibration Unit Control Register Lane 0" bitfld.word 0x58 15. " RX_SLC_EON1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x58 14. " RX_SLC_EON1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x58 13. " RX_SLC_EON1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x58 12. " RX_SLC_EON1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x58 0.--5. " RX_SLC_EON1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x5A "LANE0_RX_SLC_EON1_OVRD,RX Sampler Latch E Odd Negative 1 Calibration Unit Override Register Lane 0" bitfld.word 0x5A 15. " RX_SLC_EON1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x5A 14. " RX_SLC_EON1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x5A 0.--5. " RX_SLC_EON1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x5C "LANE0_RX_SLC_EON1_START,RX Sampler Latch E Odd Negative 1 Calibration Unit Start Register Lane 0" bitfld.word 0x5C 15. " RX_SLC_EON1_START_15 ,Calibration direction" "0,1" bitfld.word 0x5C 0.--5. " RX_SLC_EON1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x5E "LANE0_RX_SLC_EON1_TUNE,RX Sampler Latch E Odd Negative 1 Calibration Unit Tune Register Lane 0" bitfld.word 0x5E 0.--5. " RX_SLC_EON1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x60 "LANE0_RX_SLC_IEP0_CTRL,RX Sampler Latch I Even Positive 0 Calibration Unit Control Register Lane 0" bitfld.word 0x60 15. " RX_SLC_IEP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x60 14. " RX_SLC_IEP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x60 13. " RX_SLC_IEP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x60 12. " RX_SLC_IEP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x60 0.--5. " RX_SLC_IEP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x62 "LANE0_RX_SLC_IEP0_OVRD,RX Sampler Latch I Even Positive 0 Calibration Unit Override Register Lane 0" bitfld.word 0x62 15. " RX_SLC_IEP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x62 14. " RX_SLC_IEP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x62 0.--5. " RX_SLC_IEP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x64 "LANE0_RX_SLC_IEP0_START,RX Sampler Latch I Even Positive 0 Calibration Unit Start Register Lane 0" bitfld.word 0x64 15. " RX_SLC_IEP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x64 0.--5. " RX_SLC_IEP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x66 "LANE0_RX_SLC_IEP0_TUNE,RX Sampler Latch I Even Positive 0 Calibration Unit Tune Register Lane 0" bitfld.word 0x66 0.--5. " RX_SLC_IEP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x68 "LANE0_RX_SLC_IEP1_CTRL,RX Sampler Latch I Even Positive 1 Calibration Unit Control Register Lane 0" bitfld.word 0x68 15. " RX_SLC_IEP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x68 14. " RX_SLC_IEP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x68 13. " RX_SLC_IEP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x68 12. " RX_SLC_IEP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x68 0.--5. " RX_SLC_IEP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x6A "LANE0_RX_SLC_IEP1_OVRD,RX Sampler Latch I Even Positive 1 Calibration Unit Override Register Lane 0" bitfld.word 0x6A 15. " RX_SLC_IEP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x6A 14. " RX_SLC_IEP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x6A 0.--5. " RX_SLC_IEP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x6C "LANE0_RX_SLC_IEP1_START,RX Sampler Latch I Even Positive 1 Calibration Unit Start Register Lane 0" bitfld.word 0x6C 15. " RX_SLC_IEP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x6C 0.--5. " RX_SLC_IEP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x6E "LANE0_RX_SLC_IEP1_TUNE,RX Sampler Latch I Even Positive 1 Calibration Unit Tune Register Lane 0" bitfld.word 0x6E 0.--5. " RX_SLC_IEP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x70 "LANE0_RX_SLC_QEP0_CTRL,RX Sampler Latch Q Even Positive 0 Calibration Unit Control Register Lane 0" bitfld.word 0x70 15. " RX_SLC_QEP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x70 14. " RX_SLC_QEP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x70 13. " RX_SLC_QEP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x70 12. " RX_SLC_QEP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x70 0.--5. " RX_SLC_QEP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x72 "LANE0_RX_SLC_QEP0_OVRD,RX Sampler Latch Q Even Positive 0 Calibration Unit Override Register Lane 0" bitfld.word 0x72 15. " RX_SLC_QEP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x72 14. " RX_SLC_QEP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x72 0.--5. " RX_SLC_QEP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x74 "LANE0_RX_SLC_QEP0_START,RX Sampler Latch Q Even Positive 0 Calibration Unit Start Register Lane 0" bitfld.word 0x74 15. " RX_SLC_QEP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x74 0.--5. " RX_SLC_QEP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x76 "LANE0_RX_SLC_QEP0_TUNE,RX Sampler Latch Q Even Positive 0 Calibration Unit Tune Register Lane 0" bitfld.word 0x76 0.--5. " RX_SLC_QEP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x78 "LANE0_RX_SLC_QEP1_CTRL,RX Sampler Latch Q Even Positive 1 Calibration Unit Control Register Lane 0" bitfld.word 0x78 15. " RX_SLC_QEP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x78 14. " RX_SLC_QEP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x78 13. " RX_SLC_QEP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x78 12. " RX_SLC_QEP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x78 0.--5. " RX_SLC_QEP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x7A "LANE0_RX_SLC_QEP1_OVRD,RX Sampler Latch Q Even Positive 1 Calibration Unit Override Register Lane 0" bitfld.word 0x7A 15. " RX_SLC_QEP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x7A 14. " RX_SLC_QEP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x7A 0.--5. " RX_SLC_QEP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x7C "LANE0_RX_SLC_QEP1_START,RX Sampler Latch Q Even Positive 1 Calibration Unit Start Register Lane 0" bitfld.word 0x7C 15. " RX_SLC_QEP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x7C 0.--5. " RX_SLC_QEP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x7E "LANE0_RX_SLC_QEP1_TUNE,RX Sampler Latch Q Even Positive 1 Calibration Unit Tune Register Lane0" bitfld.word 0x7E 0.--5. " RX_SLC_QEP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x80 "LANE0_RX_SLC_EEP0_CTRL,RX Sampler Latch E Even Positive 0 Calibration Unit Control Register Lane 0" bitfld.word 0x80 15. " RX_SLC_EEP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x80 14. " RX_SLC_EEP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x80 13. " RX_SLC_EEP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x80 12. " RX_SLC_EEP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x80 0.--5. " RX_SLC_EEP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x82 "LANE0_RX_SLC_EEP0_OVRD,RX Sampler Latch E Even Positive 0 Calibration Unit Override Register Lane 0" bitfld.word 0x82 15. " RX_SLC_EEP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x82 14. " RX_SLC_EEP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x82 0.--5. " RX_SLC_EEP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x84 "LANE0_RX_SLC_EEP0_START,RX Sampler Latch E Even Positive 0 Calibration Unit Start Register Lane 0" bitfld.word 0x84 15. " RX_SLC_EEP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x84 0.--5. " RX_SLC_EEP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x86 "LANE0_RX_SLC_EEP0_TUNE,RX Sampler Latch E Even Positive 0 Calibration Unit Tune Register Lane0" bitfld.word 0x86 0.--5. " RX_SLC_EEP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x88 "LANE0_RX_SLC_EEP1_CTRL,RX Sampler Latch E Even Positive 1 Calibration Unit Control Register Lane 0" bitfld.word 0x88 15. " RX_SLC_EEP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x88 14. " RX_SLC_EEP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x88 13. " RX_SLC_EEP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x88 12. " RX_SLC_EEP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x88 0.--5. " RX_SLC_EEP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x8A "LANE0_RX_SLC_EEP1_OVRD,RX Sampler Latch E Even Positive 1 Calibration Unit Override Register Lane 0" bitfld.word 0x8A 15. " RX_SLC_EEP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x8A 14. " RX_SLC_EEP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x8A 0.--5. " RX_SLC_EEP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x8C "LANE0_RX_SLC_EEP1_START,RX Sampler Latch E Even Positive 1 Calibration Unit Start Register Lane 0" bitfld.word 0x8C 15. " RX_SLC_EEP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x8C 0.--5. " RX_SLC_EEP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x8E "LANE0_RX_SLC_EEP1_TUNE,RX Sampler Latch E Even Positive 1 Calibration Unit Tune Register Lane 0" bitfld.word 0x8E 0.--5. " RX_SLC_EEP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x90 "LANE0_RX_SLC_IEN0_CTRL,RX Sampler Latch I Even Negative 0 Calibration Unit Control Register Lane 0" bitfld.word 0x90 15. " RX_SLC_IEN0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x90 14. " RX_SLC_IEN0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x90 13. " RX_SLC_IEN0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x90 12. " RX_SLC_IEN0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x90 0.--5. " RX_SLC_IEN0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x92 "LANE0_RX_SLC_IEN0_OVRD,RX Sampler Latch I Even Negative 0 Calibration Unit Override Register Lane 0" bitfld.word 0x92 15. " RX_SLC_IEN0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x92 14. " RX_SLC_IEN0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x92 0.--5. " RX_SLC_IEN0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x94 "LANE0_RX_SLC_IEN0_START,RX Sampler Latch I Even Negative 0 Calibration Unit Start Register Lane 0" bitfld.word 0x94 15. " RX_SLC_IEN0_START_15 ,Calibration direction" "0,1" bitfld.word 0x94 0.--5. " RX_SLC_IEN0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x96 "LANE0_RX_SLC_IEN0_TUNE,RX Sampler Latch I Even Negative 0 Calibration Unit Tune Register Lane 0" bitfld.word 0x96 0.--5. " RX_SLC_IEN0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x98 "LANE0_RX_SLC_IEN1_CTRL,RX Sampler Latch I Even Negative 1 Calibration Unit Control Register Lane 0" bitfld.word 0x98 15. " RX_SLC_IEN1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x98 14. " RX_SLC_IEN1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x98 13. " RX_SLC_IEN1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x98 12. " RX_SLC_IEN1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x98 0.--5. " RX_SLC_IEN1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x9A "LANE0_RX_SLC_IEN1_OVRD,RX Sampler Latch I Even Negative 1 Calibration Unit Override Register Lane 0" bitfld.word 0x9A 15. " RX_SLC_IEN1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x9A 14. " RX_SLC_IEN1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x9A 0.--5. " RX_SLC_IEN1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x9C "LANE0_RX_SLC_IEN1_START,RX Sampler Latch I Even Negative 1 Calibration Unit Start Register Lane 0" bitfld.word 0x9C 15. " RX_SLC_IEN1_START_15 ,Calibration direction" "0,1" bitfld.word 0x9C 0.--5. " RX_SLC_IEN1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x9E "LANE0_RX_SLC_IEN1_TUNE,RX Sampler Latch I Even Negative 1 Calibration Unit Tune Register Lane 0" bitfld.word 0x9E 0.--5. " RX_SLC_IEN1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA0 "LANE0_RX_SLC_QEN0_CTRL,RX Sampler Latch Q Even Negative 0 Calibration Unit Control Register Lane 0" bitfld.word 0xA0 15. " RX_SLC_QEN0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xA0 14. " RX_SLC_QEN0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xA0 13. " RX_SLC_QEN0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xA0 12. " RX_SLC_QEN0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xA0 0.--5. " RX_SLC_QEN0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA2 "LANE0_RX_SLC_QEN0_OVRD,RX Sampler Latch Q Even Negative 0 Calibration Unit Override Register Lane 0" bitfld.word 0xA2 15. " RX_SLC_QEN0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xA2 14. " RX_SLC_QEN0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xA2 0.--5. " RX_SLC_QEN0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA4 "LANE0_RX_SLC_QEN0_START,RX Sampler Latch Q Even Negative 0 Calibration Unit Start Register Lane 0" bitfld.word 0xA4 15. " RX_SLC_QEN0_START_15 ,Calibration direction" "0,1" bitfld.word 0xA4 0.--5. " RX_SLC_QEN0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA6 "LANE0_RX_SLC_QEN0_TUNE,RX Sampler Latch Q Even Negative 0 Calibration Unit Tune Register Lane 0" bitfld.word 0xA6 0.--5. " RX_SLC_QEN0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA8 "LANE0_RX_SLC_QEN1_CTRL,RX Sampler Latch Q Even Negative 1 Calibration Unit Control Register Lane 0" bitfld.word 0xA8 15. " RX_SLC_QEN1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xA8 14. " RX_SLC_QEN1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xA8 13. " RX_SLC_QEN1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xA8 12. " RX_SLC_QEN1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xA8 0.--5. " RX_SLC_QEN1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xAA "LANE0_RX_SLC_QEN1_OVRD,RX Sampler Latch Q Even Negative 1 Calibration Unit Override Register Lane 0" bitfld.word 0xAA 15. " RX_SLC_QEN1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xAA 14. " RX_SLC_QEN1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xAA 0.--5. " RX_SLC_QEN1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xAC "LANE0_RX_SLC_QEN1_START,RX Sampler Latch Q Even Negative 1 Calibration Unit Start Register Lane 0" bitfld.word 0xAC 15. " RX_SLC_QEN1_START_15 ,Calibration direction" "0,1" bitfld.word 0xAC 0.--5. " RX_SLC_QEN1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xAE "LANE0_RX_SLC_QEN1_TUNE,RX Sampler Latch Q Even Negative 1 Calibration Unit Tune Register Lane 0" bitfld.word 0xAE 0.--5. " RX_SLC_QEN1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB0 "LANE0_RX_SLC_EEN0_CTRL,RX Sampler Latch E Even Negative 0 Calibration Unit Control Register Lane 0" bitfld.word 0xB0 15. " RX_SLC_EEN0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xB0 14. " RX_SLC_EEN0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xB0 13. " RX_SLC_EEN0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xB0 12. " RX_SLC_EEN0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xB0 0.--5. " RX_SLC_EEN0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB2 "LANE0_RX_SLC_EEN0_OVRD,RX Sampler Latch E Even Negative 0 Calibration Unit Override Register Lane 0" bitfld.word 0xB2 15. " RX_SLC_EEN0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xB2 14. " RX_SLC_EEN0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xB2 0.--5. " RX_SLC_EEN0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB4 "LANE0_RX_SLC_EEN0_START,RX Sampler Latch E Even Negative 0 Calibration Unit Start Register Lane 0" bitfld.word 0xB4 15. " RX_SLC_EEN0_START_15 ,Calibration direction" "0,1" bitfld.word 0xB4 0.--5. " RX_SLC_EEN0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB6 "LANE0_RX_SLC_EEN0_TUNE,RX Sampler Latch E Even Negative 0 Calibration Unit Tune Register 0" bitfld.word 0xB6 0.--5. " RX_SLC_EEN0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB8 "LANE0_RX_SLC_EEN1_CTRL,RX Sampler Latch E Even Negative 1 Calibration Unit Control Register Lane 0" bitfld.word 0xB8 15. " RX_SLC_EEN1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xB8 14. " RX_SLC_EEN1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xB8 13. " RX_SLC_EEN1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xB8 12. " RX_SLC_EEN1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xB8 0.--5. " RX_SLC_EEN1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xBA "LANE0_RX_SLC_EEN1_OVRD,RX Sampler Latch E Even Negative 1 Calibration Unit Override Register Lane 0" bitfld.word 0xBA 15. " RX_SLC_EEN1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xBA 14. " RX_SLC_EEN1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xBA 0.--5. " RX_SLC_EEN1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xBC "LANE0_RX_SLC_EEN1_START,RX Sampler Latch E Even Negative 1 Calibration Unit Start Register Lane 0" bitfld.word 0xBC 15. " RX_SLC_EEN1_START_15 ,Calibration direction" "0,1" bitfld.word 0xBC 0.--5. " RX_SLC_EEN1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xBE "LANE0_RX_SLC_EEN1_TUNE,RX Sampler Latch E Even Negative 1 Calibration Unit Tune Register Lane 0" bitfld.word 0xBE 0.--5. " RX_SLC_EEN1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xC0 "LANE0_RX_REE_U3GCSM_CTRL,REE USB 3 General Control State Machine Control Register Lane 0" bitfld.word 0xC0 1. " RX_REE_U3GCSM_CTRL_1 ,Force run equalization" "Not forced,Forced" bitfld.word 0xC0 0. " RX_REE_U3GCSM_CTRL_0 ,General control state machine function enable" "Disabled,Enabled" line.word 0xC2 "LANE0_RX_REE_U3GCSM_EQENM_PH1,REE USB 3 General Control State Machine Phase 1 Equalization Enable Mask Register Lane 0" bitfld.word 0xC2 14. " RX_REE_U3GCSM_EQENM_PH1_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0xC2 9. " RX_REE_U3GCSM_EQENM_PH1_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0xC2 8. " RX_REE_U3GCSM_EQENM_PH1_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0xC2 7. " RX_REE_U3GCSM_EQENM_PH1_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0xC2 6. " RX_REE_U3GCSM_EQENM_PH1_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0xC2 5. " RX_REE_U3GCSM_EQENM_PH1_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0xC2 2. " RX_REE_U3GCSM_EQENM_PH1_2 ,RX tap 3" "0,1" bitfld.word 0xC2 1. " RX_REE_U3GCSM_EQENM_PH1_1 ,RX tap 2" "0,1" textline " " bitfld.word 0xC2 0. " RX_REE_U3GCSM_EQENM_PH1_0 ,RX tap 1" "0,1" line.word 0xC4 "LANE0_RX_REE_U3GCSM_EQENM_PH2,REE USB 3 General Control State Machine Phase 2 Equalization Enable Mask Register Lane 0" bitfld.word 0xC4 14. " RX_REE_U3GCSM_EQENM_PH2_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0xC4 9. " RX_REE_U3GCSM_EQENM_PH2_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0xC4 8. " RX_REE_U3GCSM_EQENM_PH2_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0xC4 7. " RX_REE_U3GCSM_EQENM_PH2_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0xC4 6. " RX_REE_U3GCSM_EQENM_PH2_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0xC4 5. " RX_REE_U3GCSM_EQENM_PH2_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0xC4 2. " RX_REE_U3GCSM_EQENM_PH2_2 ,RX tap 3" "0,1" bitfld.word 0xC4 1. " RX_REE_U3GCSM_EQENM_PH2_1 ,RX tap 2" "0,1" textline " " bitfld.word 0xC4 0. " RX_REE_U3GCSM_EQENM_PH2_0 ,RX tap 1" "0,1" line.word 0xC6 "LANE0_RX_REE_U3GCSM_START_TMR,REE USB 3 General Control State Machine Start Timer Value Register Lane 0" line.word 0xC8 "LANE0_RX_REE_U3GCSM_RUN_PH1_TMR,REE USB 3 General Control State Machine Run Phase 1 Timer Value Register Lane 0" line.word 0xCA "LANE0_RX_REE_U3GCSM_RUN_PH2_TMR,REE USB 3 General Control State Machine Run Phase 2 Timer Value Register Lane 0" group.word (0x8000+0xD0)++0x0B line.word 0x00 "LANE0_RX_REE_G2GCSM_CTRL,REE PCIe Gen 2 General Control State Machine Control Register Lane 0" bitfld.word 0x00 1. " RX_REE_G2GCSM_CTRL_1 ,Force run equalization" "Not forced,Forced" bitfld.word 0x00 0. " RX_REE_G2GCSM_CTRL_0 ,General control state machine function enable" "Disabled,Enabled" line.word 0x02 "LANE0_RX_REE_G2GCSM_EQENM_PH1,REE PCIe Gen 2 General Control State Machine Phase 1 Equalization Enable Mask Register Lane 0" bitfld.word 0x02 14. " RX_REE_G2GCSM_EQENM_PH1_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x02 9. " RX_REE_G2GCSM_EQENM_PH1_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x02 8. " RX_REE_G2GCSM_EQENM_PH1_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x02 7. " RX_REE_G2GCSM_EQENM_PH1_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x02 6. " RX_REE_G2GCSM_EQENM_PH1_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x02 5. " RX_REE_G2GCSM_EQENM_PH1_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x02 2. " RX_REE_G2GCSM_EQENM_PH1_2 ,RX tap 3" "0,1" bitfld.word 0x02 1. " RX_REE_G2GCSM_EQENM_PH1_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x02 0. " RX_REE_G2GCSM_EQENM_PH1_0 ,RX tap 1" "0,1" line.word 0x04 "LANE0_RX_REE_G2GCSM_EQENM_PH2,REE USB 2 General Control State Machine Phase 2 Equalization Enable Mask Register Lane 0" bitfld.word 0x04 14. " RX_REE_G2GCSM_EQENM_PH2_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x04 9. " RX_REE_G2GCSM_EQENM_PH2_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x04 8. " RX_REE_G2GCSM_EQENM_PH2_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x04 7. " RX_REE_G2GCSM_EQENM_PH2_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x04 6. " RX_REE_G2GCSM_EQENM_PH2_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x04 5. " RX_REE_G2GCSM_EQENM_PH2_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x04 2. " RX_REE_G2GCSM_EQENM_PH2_2 ,RX tap 3" "0,1" bitfld.word 0x04 1. " RX_REE_G2GCSM_EQENM_PH2_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x04 0. " RX_REE_G2GCSM_EQENM_PH2_0 ,RX tap 1" "0,1" line.word 0x06 "LANE0_RX_REE_G2GCSM_START_TMR,REE PCIe Gen 2 General Control State Machine Start Timer Value Register Lane 0" line.word 0x08 "LANE0_RX_REE_G2GCSM_RUN_PH1_TMR,REE PCIe Gen 2 General Control State Machine Run Phase 1 Timer Value Register Lane 0" line.word 0x0A "LANE0_RX_REE_G2GCSM_RUN_PH2_TMR,REE PCIe Gen 2 General Control State Machine Run Phase 2 Timer Value Register Lane 0" group.word (0x8000+0xF0)++0x0B line.word 0x00 "LANE0_RX_REE_PERGCSM_CTRL,REE Periodic General Control State Machine Control Register Lane 0" bitfld.word 0x00 1. " RX_REE_PERGCSM_CTRL_1 ,Force run equalization" "Not forced,Forced" bitfld.word 0x00 0. " RX_REE_PERGCSM_CTRL_0 ,General control state machine function enable" "Disabled,Enabled" line.word 0x02 "LANE0_RX_REE_PERGCSM_EQENM_PH1,REE Periodic General Control State Machine Phase 1 Equalization Enable Mask Register Lane 0" bitfld.word 0x02 14. " RX_REE_PERGCSM_EQENM_PH1_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x02 9. " RX_REE_PERGCSM_EQENM_PH1_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x02 8. " RX_REE_PERGCSM_EQENM_PH1_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x02 7. " RX_REE_PERGCSM_EQENM_PH1_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x02 6. " RX_REE_PERGCSM_EQENM_PH1_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x02 5. " RX_REE_PERGCSM_EQENM_PH1_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x02 2. " RX_REE_PERGCSM_EQENM_PH1_2 ,RX tap 3" "0,1" bitfld.word 0x02 1. " RX_REE_PERGCSM_EQENM_PH1_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x02 0. " RX_REE_PERGCSM_EQENM_PH1_0 ,RX tap 1" "0,1" line.word 0x04 "LANE0_RX_REE_PERGCSM_EQENM_PH2,REE Periodic General Control State Machine Phase 2 Equalization Enable Mask Register Lane 0" bitfld.word 0x04 14. " RX_REE_PERGCSM_EQENM_PH2_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x04 9. " RX_REE_PERGCSM_EQENM_PH2_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x04 8. " RX_REE_PERGCSM_EQENM_PH2_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x04 7. " RX_REE_PERGCSM_EQENM_PH2_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x04 6. " RX_REE_PERGCSM_EQENM_PH2_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x04 5. " RX_REE_PERGCSM_EQENM_PH2_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x04 2. " RX_REE_PERGCSM_EQENM_PH2_2 ,RX tap 3" "0,1" bitfld.word 0x04 1. " RX_REE_PERGCSM_EQENM_PH2_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x04 0. " RX_REE_PERGCSM_EQENM_PH2_0 ,RX tap 1" "0,1" line.word 0x06 "LANE0_RX_REE_PERGCSM_START_TMR,REE Periodic General Control State Machine Start Timer Value Register Lane 0" line.word 0x08 "LANE0_RX_REE_PERGCSM_RUN_PH1_TMR,REE Periodic General Control State Machine Run Phase 1 Timer Value Register Lane 0" line.word 0x0A "LANE0_RX_REE_PERGCSM_RUN_PH2_TMR,REE Periodic General Control State Machine Run Phase 2 Timer Value Register Lane 0" group.word (0x8000+0x100)++0x05 line.word 0x00 "LANE0_RX_REE_TAP1_CTRL,REE Tap 1 Control Register Lane 0" bitfld.word 0x00 11. " RX_REE_TAP1_CTRL_11 ,Tap coefficient combinational logic zero crossing enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_REE_TAP1_CTRL_10 ,Tap coefficient combinational logic non zero crossing enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_REE_TAP1_CTRL_9 ,Tap coefficient combinational logic bit 0 only enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_REE_TAP1_CTRL_8 ,Receiver DFE tap coefficient disable" "No,Yes" textline " " bitfld.word 0x00 4.--6. " RX_REE_TAP1_CTRL_6_4 ,Tap integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_TAP1_CTRL_3_0 ,Tap sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE0_RX_REE_TAP1_OVRD,REE Tap 1 Override Register Lane 0" bitfld.word 0x02 7. " RX_REE_TAP1_OVRD_7 ,Tap override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_TAP1_OVRD_5_0 ,Tap override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE0_RX_REE_TAP1_DIAG,REE Tap 1 Diagnostics Register Lane 0" bitfld.word 0x04 14. " RX_REE_TAP1_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_TAP1_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_TAP1_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_TAP1_DIAG_5_0 ,Current tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8000+0x108)++0x05 line.word 0x00 "LANE0_RX_REE_TAP2_CTRL,REE Tap 2 Control Register Lane 0" bitfld.word 0x00 11. " RX_REE_TAP2_CTRL_11 ,Tap coefficient combinational logic zero crossing enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_REE_TAP2_CTRL_10 ,Tap coefficient combinational logic non zero crossing enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_REE_TAP2_CTRL_9 ,Tap coefficient combinational logic bit 0 only enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_REE_TAP2_CTRL_8 ,Receiver DFE tap coefficient disable" "No,Yes" textline " " bitfld.word 0x00 4.--6. " RX_REE_TAP2_CTRL_6_4 ,Tap integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_TAP2_CTRL_3_0 ,Tap sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE0_RX_REE_TAP2_OVRD,REE Tap 2 Override Register Lane 0" bitfld.word 0x02 7. " RX_REE_TAP2_OVRD_7 ,Tap override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_TAP2_OVRD_5_0 ,Tap override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE0_RX_REE_TAP2_DIAG,REE Tap 2 Diagnostics Register Lane 0" bitfld.word 0x04 14. " RX_REE_TAP2_DIAG_14 ,Voter override neg" "No override,Override" bitfld.word 0x04 13. " RX_REE_TAP2_DIAG_13 ,Voter override pos" "0,1" textline " " bitfld.word 0x04 12. " RX_REE_TAP2_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_TAP2_DIAG_5_0 ,Current tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8000+0x110)++0x05 line.word 0x00 "LANE0_RX_REE_TAP3_CTRL,REE Tap 3 Control Register Lane 0" bitfld.word 0x00 11. " RX_REE_TAP3_CTRL_11 ,Tap coefficient combinational logic zero crossing enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_REE_TAP3_CTRL_10 ,Tap coefficient combinational logic non zero crossing enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_REE_TAP3_CTRL_9 ,Tap coefficient combinational logic bit 0 only enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_REE_TAP3_CTRL_8 ,Receiver DFE tap coefficient disable" "No,Yes" textline " " bitfld.word 0x00 4.--6. " RX_REE_TAP3_CTRL_6_4 ,Tap integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_TAP3_CTRL_3_0 ,Tap sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE0_RX_REE_TAP3_OVRD,REE Tap 3 Override Register Lane 0" bitfld.word 0x02 7. " RX_REE_TAP3_OVRD_7 ,Tap override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_TAP3_OVRD_5_0 ,Tap override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE0_RX_REE_TAP3_DIAG,REE Tap 3 Diagnostics Register Lane 0" bitfld.word 0x04 14. " RX_REE_TAP3_DIAG_14 ,Voter override neg" "No override,Override" bitfld.word 0x04 13. " RX_REE_TAP3_DIAG_13 ,Voter override pos" "0,1" textline " " bitfld.word 0x04 12. " RX_REE_TAP3_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_TAP3_DIAG_5_0 ,Current tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8000+0x128)++0x01 line.word 0x00 "LANE0_RX_REE_ANAENSM_DEL_TMR,REE Analog Enable Control State Machine Delay Timer Value Register Lane 0" group.word (0x8000+0x130)++0x0D line.word 0x00 "LANE0_RX_REE_PEAK_CTRL,REE Peaking Amp Control Register Lane 0" bitfld.word 0x00 11. " RX_REE_PEAK_CTRL_11 ,Peaking amp feedback path enable" "Disabled,Enabled" bitfld.word 0x00 8.--10. " RX_REE_PEAK_CTRL_10_8 ,Peaking amp feedback scaler value" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 4.--6. " RX_REE_PEAK_CTRL_6_4 ,Peaking amp integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_PEAK_CTRL_3_0 ,Peaking amp sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE0_RX_REE_PEAK_CODE_CTRL,REE Peaking Amp Code Control Register Lane 0" bitfld.word 0x02 8.--13. " RX_REE_PEAK_CODE_CTRL_13_8 ,Peaking amp code maximum value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x02 0.--5. " RX_REE_PEAK_CODE_CTRL_5_0 ,Peaking amp initial code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE0_RX_REE_PEAK_UTHR,REE Peaking Amp Upper Threshold Register Lane 0" hexmask.word 0x04 0.--8. 1. " RX_REE_PEAK_UTHR_8_0 ,Peaking amp algorithm upper threshold" line.word 0x06 "LANE0_RX_REE_PEAK_LTHR,REE Peaking Amp Lower Threshold Register Lane 0" hexmask.word 0x06 0.--8. 1. " RX_REE_PEAK_LTHR_8_0 ,Peaking amp algorithm lower threshold" line.word 0x08 "LANE0_RX_REE_PEAK_IOVRD,REE Peaking Amp Input Override Register Lane 0" bitfld.word 0x08 15. " RX_REE_PEAK_IOVRD_15 ,Peaking amp tap accumulator input override enable" "Disabled,Enabled" hexmask.word.byte 0x08 0.--7. 1. " RX_REE_PEAK_IOVRD_7_0 ,Peaking amp tap accumulator input override" line.word 0x0A "LANE0_RX_REE_PEAK_COVRD,REE Peaking Amp Code Override Register Lane 0" bitfld.word 0x0A 15. " RX_REE_PEAK_COVRD_15 ,Peaking amp code override enable" "Disabled,Enabled" bitfld.word 0x0A 0.--5. " RX_REE_PEAK_COVRD_5_0 ,Peaking amp code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0C "LANE0_RX_REE_PEAK_DIAG,REE Peaking Amp Diagnostics Register Lane 0" bitfld.word 0x0C 14. " RX_REE_PEAK_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x0C 13. " RX_REE_PEAK_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x0C 12. " RX_REE_PEAK_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x0C 0.--5. " RX_REE_TAP3_DIAG_5_0 ,Current peaking amp integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8000+0x140)++0x07 line.word 0x00 "LANE0_RX_REE_ATTEN_CTRL,REE Attenuation Control Register Lane 0" bitfld.word 0x00 0.--4. " RX_REE_ATTEN_CTRL_4_0 ,Receiver DFE attenuation maximum value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x02 "LANE0_RX_REE_ATTEN_THR,REE Attenuation Threshold Register Lane 0" bitfld.word 0x02 8.--12. " RX_REE_ATTEN_THR_12_8 ,Attenuation high threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--4. " RX_REE_ATTEN_THR_4_0 ,Attenuation low threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE0_RX_REE_ATTEN_CNT,REE Attenuation Counter Register Lane 0" line.word 0x06 "LANE0_RX_REE_ATTEN_OVRD,REE Attenuation Override Register Lane 0" bitfld.word 0x06 8. " RX_REE_ATTEN_OVRD_8 ,Attenuation override enable" "Disabled,Enabled" bitfld.word 0x06 0.--4. " RX_REE_ATTEN_OVRD_4_0 ,Attenuation override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word (0x8000+0x148)++0x01 line.word 0x00 "LANE0_RX_REE_ATTEN_DIAG,REE Attenuation Diagnostics Register Lane 0" bitfld.word 0x00 0.--4. " RX_REE_ATTEN_DIAG_4_0 ,Current attenuation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (0x8000+0x150)++0x05 line.word 0x00 "LANE0_RX_REE_LFEQ_CTRL,REE Low Frequency Equalizer Control Register Lane 0" bitfld.word 0x00 8. " RX_REE_LFEQ_CTRL_8 ,Receiver DFE coefficient disable" "No,Yes" bitfld.word 0x00 4.--6. " RX_REE_LFEQ_CTRL_6_4 ,Integrator accumulator scaler value" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 0.--3. " RX_REE_LFEQ_CTRL_3_0 ,Sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE0_RX_REE_LFEQ_OVRD,REE Low Frequency Equalizer Override Register Lane 0" bitfld.word 0x02 7. " RX_REE_LFEQ_OVRD_7 ,Override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_LFEQ_OVRD_5_0 ,Override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE0_RX_REE_LFEQ_DIAG,REE Low Frequency Equalizer Diagnostics Register Lane 0" bitfld.word 0x04 14. " RX_REE_LFEQ_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_LFEQ_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_LFEQ_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_LFEQ_DIAG_5_0 ,Current integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8000+0x158)++0x05 line.word 0x00 "LANE0_RX_REE_VGA_GAIN_CTRL,REE VGA Gain Control Register Lane 0" bitfld.word 0x00 8.--12. " RX_REE_VGA_GAIN_CTRL_12_8 ,VGA gain max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 4.--6. " RX_REE_VGA_GAIN_CTRL_6_4 ,VGA gain integrator accumulator scaler value" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 0.--3. " RX_REE_VGA_GAIN_CTRL_3_0 ,VGA gain sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE0_RX_REE_VGA_GAIN_OVRD,REE VGA Gain Override Register Lane 0" bitfld.word 0x02 15. " RX_REE_VGA_GAIN_OVRD_15 ,VGA gain target adjust override enable" "Disabled,Enabled" bitfld.word 0x02 8.--12. " RX_REE_VGA_GAIN_OVRD_12_8 ,VGA gain target adjust override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x02 7. " RX_REE_VGA_GAIN_OVRD_7 ,VGA gain override enable" "Disabled,Enabled" bitfld.word 0x02 0.--4. " RX_REE_VGA_GAIN_OVRD_4_0 ,VGA gain override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE0_RX_REE_VGA_GAIN_DIAG,REE VGA Gain Diagnostics Register Lane 0" bitfld.word 0x04 14. " RX_REE_VGA_GAIN_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_VGA_GAIN_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_VGA_GAIN_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_VGA_GAIN_DIAG_5_0 ,Current VGA gain integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.word (0x8000+0x15E)++0x01 line.word 0x00 "LANE0_RX_REE_VGA_GAIN_TGT_DIAG,REE VGA Gain Target Adjust Diagnostics Register Lane 0" bitfld.word 0x00 0.--4. " RX_REE_VGA_GAIN_TGT_DIAG_4_0 ,Current VGA gain integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (0x8000+0x160)++0x05 line.word 0x00 "LANE0_RX_REE_OFF_COR_CTRL,REE Offset Correction Control Register Lane 0" bitfld.word 0x00 4.--6. " RX_REE_OFF_COR_CTRL_6_4 ,Offset correction integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_OFF_COR_CTRL_3_0 ,Offset correction sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE0_RX_REE_OFF_COR_OVRD,REE Offset Correction Override Register Lane 0" bitfld.word 0x02 7. " RX_REE_OFF_COR_OVRD_7 ,Offset correction override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_OFF_COR_OVRD_5_0 ,Offset correction override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE0_RX_REE_OFF_COR_DIAG,REE Offset Correction Diagnostics Register Lane 0" bitfld.word 0x04 14. " RX_REE_OFF_COR_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_OFF_COR_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_OFF_COR_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_OFF_COR_DIAG_5_0 ,Current offset correction integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8000+0x170)++0x0D line.word 0x00 "LANE0_RX_REE_ADDR_CFG,REE Adder Configuration Register Lane 0" bitfld.word 0x00 2. " RX_REE_ADDR_CFG_2 ,RX peaking tap 3 adder enable" "Disabled,Enabled" bitfld.word 0x00 1. " RX_REE_ADDR_CFG_1 ,RX peaking tap 2 adder enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RX_REE_ADDR_CFG_0 ,RX peaking tap 1 adder enable" "Disabled,Enabled" line.word 0x02 "LANE0_RX_REE_ADDR_CFG,REE Tap 1 Clip Control Register Lane 0" bitfld.word 0x02 8.--10. " RX_REE_TAP1_CLIP_10_8 ,VGA target gain adjust multiplier" "0,1,2,3,4,5,6,7" bitfld.word 0x02 0.--4. " RX_REE_TAP1_CLIP_4_0 ,Threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE0_RX_REE_TAP2TON_CLIP,REE Taps 2 And 3 Clip Control Register Lane 0" bitfld.word 0x04 8.--10. " RX_REE_TAP2TON_CLIP_10_8 ,VGA target gain adjust multiplier" "0,1,2,3,4,5,6,7" bitfld.word 0x04 0.--4. " RX_REE_TAP2TON_CLIP_4_0 ,Threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "LANE0_RX_REE_CTRL_DATA_MASK,REE Control Data Mask Register Lane 0" rbitfld.word 0x06 14. " RX_REE_CTRL_DATA_MASK_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x06 9. " RX_REE_CTRL_DATA_MASK_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x06 8. " RX_REE_CTRL_DATA_MASK_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x06 7. " RX_REE_CTRL_DATA_MASK_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x06 6. " RX_REE_CTRL_DATA_MASK_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x06 5. " RX_REE_CTRL_DATA_MASK_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x06 2. " RX_REE_CTRL_DATA_MASK_2 ,RX tap 3" "0,1" bitfld.word 0x06 1. " RX_REE_CTRL_DATA_MASK_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x06 0. " RX_REE_CTRL_DATA_MASK_0 ,RX tap 1" "0,1" line.word 0x08 "LANE0_RX_REE_DIAG_CTRL,REE Diagnostic Control Register Lane 0" bitfld.word 0x08 6. " RX_REE_DIAG_CTRL_6 ,Hold periodic equalization while RX idle" "Not held,Held" bitfld.word 0x08 4. " RX_REE_DIAG_CTRL_4 ,Hold gen 2 equalization while RX idle" "Not held,Held" textline " " bitfld.word 0x08 1. " RX_REE_DIAG_CTRL_1 ,Force REE controller clock on" "Not forced,Forced" bitfld.word 0x08 0. " RX_REE_DIAG_CTRL_0 ,Force REE function clock on" "Not forced,Forced" line.word 0x0A "LANE0_RX_REE_SMGM_CTRL1,REE Control State Machine Gen Mode Control Register 1 Lane 0" bitfld.word 0x0A 15. " RX_REE_SMGM_CTRL1_15 ,REE periodic general control state machine E path enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 14. " RX_REE_SMGM_CTRL1_14 ,REE periodic general control state machine E path enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 13. " RX_REE_SMGM_CTRL1_13 ,REE periodic general control state machine E path enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 12. " RX_REE_SMGM_CTRL1_12 ,REE periodic general control state machine E path enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x0A 11. " RX_REE_SMGM_CTRL1_11 ,REE periodic general control state machine enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 10. " RX_REE_SMGM_CTRL1_10 ,REE periodic general control state machine enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 9. " RX_REE_SMGM_CTRL1_9 ,REE periodic general control state machine enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 8. " RX_REE_SMGM_CTRL1_8 ,REE periodic general control state machine enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x0A 7. " RX_REE_SMGM_CTRL1_7 ,REE Gen 2 general control state machine E path enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 6. " RX_REE_SMGM_CTRL1_6 ,REE Gen 2 general control state machine E path enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 5. " RX_REE_SMGM_CTRL1_5 ,REE Gen 2 general control state machine E path enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 4. " RX_REE_SMGM_CTRL1_4 ,REE Gen 2 general control state machine E path enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x0A 3. " RX_REE_SMGM_CTRL1_3 ,REE Gen 2 general control state machine enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 2. " RX_REE_SMGM_CTRL1_2 ,REE Gen 2 general control state machine enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 1. " RX_REE_SMGM_CTRL1_1 ,REE Gen 2 general control state machine enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 0. " RX_REE_SMGM_CTRL1_0 ,REE Gen 2 general control state machine enable standard mode 0" "Disabled,Enabled" line.word 0x0C "LANE0_RX_REE_SMGM_CTRL2,REE Control State Machine Gen Mode Control Register 2 Lane 0" bitfld.word 0x0C 0. " RX_REE_SMGM_CTRL2_0 ,REE USB 3 general control state machine E path enable" "Disabled,Enabled" group.word (0x8000+0x180)++0x13 line.word 0x00 "LANE0_RX_DIAG_ILL_CTRL,RX ILL Diagnostic Control Register Lane 0" bitfld.word 0x00 3. " RX_DIAG_ILL_CTRL_3 ,IQ PI ILL calibration enable override enable" "Disabled,Enabled" bitfld.word 0x00 2. " RX_DIAG_ILL_CTRL_2 ,IQ PI ILL calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " RX_DIAG_ILL_CTRL_1 ,E PI ILL calibration enable override enable" "Disabled,Enabled" bitfld.word 0x00 0. " RX_DIAG_ILL_CTRL_0 ,E PI ILL calibration enable override" "Disabled,Enabled" line.word 0x02 "LANE0_RX_DIAG_ILL_IQ_TRIM0,RX ILL IQ Trim 0 Register Lane 0" bitfld.word 0x02 12.--14. " RX_DIAG_ILL_IQ_TRIM0_14_12 ,Rx_diag_ill_iq_trim0_14_12" "0,1,2,3,4,5,6,7" bitfld.word 0x02 8.--10. " RX_DIAG_ILL_IQ_TRIM0_10_8 ,Rx_diag_ill_iq_trim0_10_8" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x02 6.--7. " RX_DIAG_ILL_IQ_TRIM0_7_6 ,Rx_diag_ill_iq_trim0_7_6" "0,1,2,3" bitfld.word 0x02 4.--5. " RX_DIAG_ILL_IQ_TRIM0_5_4 ,Rx_diag_ill_iq_trim0_5_4" "0,1,2,3" textline " " bitfld.word 0x02 2.--3. " RX_DIAG_ILL_IQ_TRIM0_3_2 ,Rx_diag_ill_iq_trim0_3_2" "0,1,2,3" bitfld.word 0x02 0.--1. " RX_DIAG_ILL_IQ_TRIM0_1_0 ,Rx_diag_ill_iq_trim0_1_0" "0,1,2,3" line.word 0x04 "LANE0_RX_DIAG_ILL_E_TRIM0,RX ILL E Trim 0 Register Lane 0" bitfld.word 0x04 12.--14. " RX_DIAG_ILL_E_TRIM0_14_12 ,Rx_diag_ill_e_trim0_14_12" "0,1,2,3,4,5,6,7" bitfld.word 0x04 8.--10. " RX_DIAG_ILL_E_TRIM0_10_8 ,Rx_diag_ill_e_trim0_10_8" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x04 6.--7. " RX_DIAG_ILL_E_TRIM0_7_6 ,Rx_diag_ill_e_trim0_7_6" "0,1,2,3" bitfld.word 0x04 4.--5. " RX_DIAG_ILL_E_TRIM0_5_4 ,Rx_diag_ill_e_trim0_5_4" "0,1,2,3" textline " " bitfld.word 0x04 2.--3. " RX_DIAG_ILL_E_TRIM0_3_2 ,Rx_diag_ill_e_trim0_3_2" "0,1,2,3" bitfld.word 0x04 0.--1. " RX_DIAG_ILL_E_TRIM0_1_0 ,Rx_diag_ill_e_trim0_1_0" "0,1,2,3" line.word 0x06 "LANE0_RX_DIAG_ILL_IQ_TRIM1,RX ILL IQ Trim 1 Register Lane 0" bitfld.word 0x06 4.--5. " RX_DIAG_ILL_IQ_TRIM1_5_4 ,Rx_diag_ill_iq_trim1_5_4" "0,1,2,3" bitfld.word 0x06 0.--2. " RX_DIAG_ILL_IQ_TRIM1_2_0 ,Rx_diag_ill_iq_trim1_2_0" "0,1,2,3,4,5,6,7" line.word 0x08 "LANE0_RX_DIAG_ILL_E_TRIM1,RX ILL E Trim 1 Register Lane 0" bitfld.word 0x08 4.--5. " RX_DIAG_ILL_E_TRIM1_5_4 ,Rx_diag_ill_e_trim1_5_4" "0,1,2,3" bitfld.word 0x08 0.--2. " RX_DIAG_ILL_E_TRIM1_2_0 ,Rx_diag_ill_e_trim1_2_0" "0,1,2,3,4,5,6,7" line.word 0x0A "LANE0_RX_DIAG_ILL_IQE_TRIM2,RX ILL IQ E Trim 2 Register Lane 0" bitfld.word 0x0A 14.--15. " RX_DIAG_ILL_IQE_TRIM2_15_14 ,Rx_diag_ill_iqe_trim2_15_14" "0,1,2,3" bitfld.word 0x0A 12.--13. " RX_DIAG_ILL_IQE_TRIM2_13_12 ,Rx_diag_ill_iqe_trim2_13_12" "0,1,2,3" textline " " bitfld.word 0x0A 10.--11. " RX_DIAG_ILL_IQE_TRIM2_11_10 ,Rx_diag_ill_iqe_trim2_11_10" "0,1,2,3" bitfld.word 0x0A 8.--9. " RX_DIAG_ILL_IQE_TRIM2_9_8 ,Rx_diag_ill_iqe_trim2_9_8" "0,1,2,3" textline " " bitfld.word 0x0A 6.--7. " RX_DIAG_ILL_IQE_TRIM2_7_6 ,Rx_diag_ill_iqe_trim2_7_6" "0,1,2,3" bitfld.word 0x0A 4.--5. " RX_DIAG_ILL_IQE_TRIM2_5_4 ,Rx_diag_ill_iqe_trim2_5_4" "0,1,2,3" textline " " bitfld.word 0x0A 2.--3. " RX_DIAG_ILL_IQE_TRIM2_3_2 ,Rx_diag_ill_iqe_trim2_3_2" "0,1,2,3" bitfld.word 0x0A 0.--1. " RX_DIAG_ILL_IQE_TRIM2_1_0 ,Rx_diag_ill_iqe_trim2_1_0" "0,1,2,3" line.word 0x0C "LANE0_RX_DIAG_ILL_IQE_TRIM3,RX ILL IQ E Trim 3 Register Lane 0" hexmask.word.byte 0x0C 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM3_15_8 ,Rx_diag_ill_iqe_trim3_15_8" hexmask.word.byte 0x0C 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM3_7_0 ,Rx_diag_ill_iqe_trim3_7_0" line.word 0x0E "LANE0_RX_DIAG_ILL_IQE_TRIM4,RX ILL IQ E Trim 4 Register Lane 0" hexmask.word.byte 0x0E 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM4_15_8 ,Rx_diag_ill_iqe_trim4_15_8" hexmask.word.byte 0x0E 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM4_7_0 ,Rx_diag_ill_iqe_trim4_7_0" line.word 0x10 "LANE0_RX_DIAG_ILL_IQE_TRIM5,RX ILL IQ E Trim 5 Register Lane 0" hexmask.word.byte 0x10 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM5_15_8 ,Rx_diag_ill_iqe_trim5_15_8" hexmask.word.byte 0x10 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM5_7_0 ,Rx_diag_ill_iqe_trim5_7_0" line.word 0x12 "LANE0_RX_DIAG_ILL_IQE_TRIM6,RX ILL IQ E Trim 6 Register Lane 0" hexmask.word.byte 0x12 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM6_15_8 ,Rx_diag_ill_iqe_trim6_15_8" hexmask.word.byte 0x12 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM6_7_0 ,Rx_diag_ill_iqe_trim6_7_0" group.word (0x8000+0x1A0)++0x11 line.word 0x00 "LANE0_RX_DIAG_DFE_AMP_TUNE,DFE Amp Fine Tuning Register Lane 0" bitfld.word 0x00 12.--14. " RX_DIAG_DFE_AMP_TUNE_14_12 ,DFE constant gm bias tune" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " RX_DIAG_DFE_AMP_TUNE_11 ,DFE VGA constant gm bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--10. " RX_DIAG_DFE_AMP_TUNE_10_8 ,DFE VGA amp current adjust" "0,1,2,3,4,5,6,7" bitfld.word 0x00 7. " RX_DIAG_DFE_AMP_TUNE_7 ,DFE peaking constant gm bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4.--6. " RX_DIAG_DFE_AMP_TUNE_6_4 ,DFE peaking amp current adjust" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " RX_DIAG_DFE_AMP_TUNE_3 ,DFE summing constant gm bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--2. " RX_DIAG_DFE_AMP_TUNE_2_0 ,DFE summing amp current adjust" "0,1,2,3,4,5,6,7" line.word 0x02 "LANE0_RX_DIAG_DFE_AMP_TUNE_2,DFE Amp Fine Tuning 2 Register Lane 0" bitfld.word 0x02 11. " RX_DIAG_DFE_AMP_TUNE_2_11 ,DFE low frequency equalizer constant gm bias enable" "Disabled,Enabled" bitfld.word 0x02 8.--10. " RX_DIAG_DFE_AMP_TUNE_2_10_8 ,DFE low frequency equalizer current adjust" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x02 7. " RX_DIAG_DFE_AMP_TUNE_2_7 ,Enable active inductors boost function in the peaking amp for high data rates" "Disabled,Enabled" bitfld.word 0x02 6. " RX_DIAG_DFE_AMP_TUNE_2_6 ,Enable active inductors boost function in stage 1 of the VGA for high data rates" "Disabled,Enabled" textline " " bitfld.word 0x02 5. " RX_DIAG_DFE_AMP_TUNE_2_5 ,Enable active inductors boost function in stage 2 of the VGA for high data rates" "Disabled,Enabled" bitfld.word 0x02 4. " RX_DIAG_DFE_AMP_TUNE_2_4 ,DFE RX tap 1 DAC range select" "0,1" textline " " bitfld.word 0x02 0.--1. " RX_DIAG_DFE_AMP_TUNE_2_1_0 ,DFE RX amp current adjust" "0,1,2,3" line.word 0x04 "LANE0_RX_DIAG_REE_DAC_CTRL,REE DAC Control Register Lane 0" bitfld.word 0x04 2. " RX_DIAG_REE_DAC_CTRL_2 ,DFE offset DAC enable" "Disabled,Enabled" bitfld.word 0x04 1. " RX_DIAG_REE_DAC_CTRL_1 ,DFE Offset DAC attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x04 0. " RX_DIAG_REE_DAC_CTRL_0 ,DFE DAC attenuation" "No attenuation,Attenuation" line.word 0x06 "LANE0_RX_DIAG_DFE_CTRL1,Receiver DFE Control Register 1 Lane 0" bitfld.word 0x06 15. " RX_DIAG_DFE_CTRL1_15 ,DFE tap 1 deserializer MUX select" "0,1" bitfld.word 0x06 7. " RX_DIAG_DFE_CTRL1_7 ,Receiver DFE low frequency equalization enable value standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " RX_DIAG_DFE_CTRL1_6 ,Receiver DFE low frequency equalization enable value standard mode 2" "Disabled,Enabled" bitfld.word 0x06 5. " RX_DIAG_DFE_CTRL1_5 ,Receiver DFE low frequency equalization enable value standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " RX_DIAG_DFE_CTRL1_4 ,Receiver DFE low frequency equalization enable value standard mode 0" "Disabled,Enabled" bitfld.word 0x06 3. " RX_DIAG_DFE_CTRL1_3 ,Receiver DFE equalization enable mask value standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x06 2. " RX_DIAG_DFE_CTRL1_2 ,Receiver DFE equalization enable mask value standard mode 2" "Disabled,Enabled" bitfld.word 0x06 1. " RX_DIAG_DFE_CTRL1_1 ,Receiver DFE equalization enable mask value standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " RX_DIAG_DFE_CTRL1_0 ,Receiver DFE equalization enable mask value standard mode 0" "Disabled,Enabled" line.word 0x08 "LANE0_RX_DIAG_DFE_CTRL2,Receiver DFE Control Register 2 Lane 0" bitfld.word 0x08 6.--7. " RX_DIAG_DFE_CTRL2_7_6 ,RX equalizer range select standard mode 3" "0,1,2,3" bitfld.word 0x08 4.--5. " RX_DIAG_DFE_CTRL2_5_4 ,RX equalizer range select standard mode 2" "0,1,2,3" textline " " bitfld.word 0x08 2.--3. " RX_DIAG_DFE_CTRL2_3_2 ,RX equalizer range select standard mode 1" "0,1,2,3" bitfld.word 0x08 0.--1. " RX_DIAG_DFE_CTRL2_1_0 ,RX equalizer range select standard mode 0" "0,1,2,3" line.word 0x0A "LANE0_RX_DIAG_DFE_CTRL3,Receiver DFE Control Register 3 Lane 0" bitfld.word 0x0A 12.--15. " RX_DIAG_DFE_CTRL3_15_12 ,RX DFE peaking resistor code select standard mode 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0A 8.--11. " RX_DIAG_DFE_CTRL3_11_8 ,RX DFE peaking resistor code select standard mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x0A 4.--7. " RX_DIAG_DFE_CTRL3_7_4 ,RX DFE peaking resistor code select standard mode 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0A 0.--3. " RX_DIAG_DFE_CTRL3_3_0 ,RX DFE peaking resistor code select standard mode 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0C "LANE0_RX_DIAG_NQST_CTRL,Nyquist Control Register Lane 0" bitfld.word 0x0C 12.--15. " RX_DIAG_NQST_CTRL_15_12 ,RX nyquist select value standard mode 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0C 8.--11. " RX_DIAG_NQST_CTRL_11_8 ,RX nyquist select value standard mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x0C 4.--7. " RX_DIAG_NQST_CTRL_7_4 ,RX nyquist select value standard mode 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0C 0.--3. " RX_DIAG_NQST_CTRL_3_0 ,RX nyquist select value standard mode 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0E "LANE0_RX_DIAG_LFEQ_TUNE,Low Frequency Equalizer Tuning Register Lane 0" bitfld.word 0x0E 6.--7. " RX_DIAG_LFEQ_TUNE_7_6 ,RX low frequency equalization zero frequency value standard mode 3" "0,1,2,3" bitfld.word 0x0E 4.--5. " RX_DIAG_LFEQ_TUNE_5_4 ,RX low frequency equalization zero frequency value standard mode 2" "0,1,2,3" textline " " bitfld.word 0x0E 2.--3. " RX_DIAG_LFEQ_TUNE_3_2 ,RX low frequency equalization zero frequency value standard mode 1" "0,1,2,3" bitfld.word 0x0E 0.--1. " RX_DIAG_LFEQ_TUNE_1_0 ,RX low frequency equalization zero frequency value standard mode 0" "0,1,2,3" line.word 0x10 "LANE0_RX_DIAG_RXCTRL,RX Control Register Lane 0" bitfld.word 0x10 15. " RX_DIAG_RXCTRL_15 ,RX deserializer clock invert" "Not inverted,Inverted" bitfld.word 0x10 11. " RX_DIAG_RXCTRL_11 ,PI output clock divider enable standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x10 10. " RX_DIAG_RXCTRL_10 ,PI output clock divider enable standard mode 2" "Disabled,Enabled" bitfld.word 0x10 9. " RX_DIAG_RXCTRL_9 ,PI output clock divider enable standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x10 8. " RX_DIAG_RXCTRL_8 ,PI output clock divider enable standard mode 0" "Disabled,Enabled" bitfld.word 0x10 7. " RX_DIAG_RXCTRL_7 ,Receiver CML to CMOS rate select value standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x10 6. " RX_DIAG_RXCTRL_6 ,Receiver CML to CMOS rate select value standard mode 2" "Disabled,Enabled" bitfld.word 0x10 5. " RX_DIAG_RXCTRL_5 ,Receiver CML to CMOS rate select value standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x10 4. " RX_DIAG_RXCTRL_4 ,Receiver CML to CMOS rate select value standard mode 0" "Disabled,Enabled" bitfld.word 0x10 3. " RX_DIAG_RXCTRL_3 ,RX interface sub-rate standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x10 2. " RX_DIAG_RXCTRL_2 ,RX interface sub-rate standard mode 2" "Disabled,Enabled" bitfld.word 0x10 1. " RX_DIAG_RXCTRL_1 ,RX interface sub-rate standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x10 0. " RX_DIAG_RXCTRL_0 ,RX interface sub-rate standard mode 0" "Disabled,Enabled" rgroup.word (0x8000+0x1B2)++0x01 line.word 0x00 "LANE0_RX_DIAG_RST_DIAG,Receiver Control Reset Diagnostic Register Lane 0" bitfld.word 0x00 8. " RX_DIAG_RST_DIAG_8 ,Current state of the rxda_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 7. " RX_DIAG_RST_DIAG_7 ,Current state of the rx_dig_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 6. " RX_DIAG_RST_DIAG_6 ,Current state of the rxda_cdrlf_reset_n reset" "No reset,Reset" bitfld.word 0x00 5. " RX_DIAG_RST_DIAG_5 ,Current state of the rx_ree_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 4. " RX_DIAG_RST_DIAG_4 ,Current state of the rx_lfps_det_filter_reset_n reset" "No reset,Reset" bitfld.word 0x00 3. " RX_DIAG_RST_DIAG_3 ,Current state of the rx_epi_ill_cal_lock_det_clk_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 2. " RX_DIAG_RST_DIAG_2 ,Current state of the rx_epi_ill_cal_ref_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 1. " RX_DIAG_RST_DIAG_1 ,Current state of the rx_iqpi_ill_cal_lock_det_clk_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 0. " RX_DIAG_RST_DIAG_0 ,Current state of the rx_iqpi_ill_cal_ref_clk_reset_n reset" "No reset,Reset" group.word (0x8000+0x1B8)++0x05 line.word 0x00 "LANE0_RX_DIAG_SIGDET_TUNE,RX Signal Detect Tuning And Control Register Lane 0" bitfld.word 0x00 12.--13. " RX_DIAG_SIGDET_TUNE_13_12 ,Signal detect filter function select" "0,1,2,3" bitfld.word 0x00 4.--5. " RX_DIAG_SIGDET_TUNE_5_4 ,Signal definition to be provided by the analog team" "0,1,2,3" textline " " bitfld.word 0x00 0.--3. " RX_DIAG_SIGDET_TUNE_3_0 ,Signal detect level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE0_RX_DIAG_LFPSDET_TUNE,RX LFPS Detect Tuning And Control Register Lane 0" hexmask.word.byte 0x02 8.--15. 1. " RX_DIAG_LFPSDET_TUNE_15_8 ,Signal definition to be provided by the analog team" hexmask.word.byte 0x02 0.--7. 1. " RX_DIAG_LFPSDET_TUNE_7_0 ,LFPS detect level" line.word 0x04 "LANE0_RX_DIAG_SD_TEST,Signal Detect Test Register Lane 0" bitfld.word 0x04 3. " RX_DIAG_SD_TEST_3 ,LFPS detected low test bit" "Not detected,Detected" bitfld.word 0x04 2. " RX_DIAG_SD_TEST_2 ,LFPS detected high test bit" "Not detected,Detected" textline " " bitfld.word 0x04 1. " RX_DIAG_SD_TEST_1 ,Signal detected low test bit" "Not detected,Detected" bitfld.word 0x04 0. " RX_DIAG_SD_TEST_0 ,Signal detected high test bit" "Not detected,Detected" group.word (0x8000+0x1C0)++0x03 line.word 0x00 "LANE0_RX_DIAG_SAMP_CTRL,RX Sampler Diagnostic Control Register Lane 0" bitfld.word 0x00 0. " RX_DIAG_SAMP_CTRL_0 ,Analog sampler" "0,1" line.word 0x02 "LANE0_RX_DIAG_SC2C_DELAY,RX Sampler CML TO CMOS Enable Delay Register Lane 0" hexmask.word 0x02 0.--9. 1. " RX_DIAG_SC2C_DELAY_9_0 ,Sampler CML to CMOS enable delay" group.word (0x8000+0x1C8)++0x03 line.word 0x00 "LANE0_RX_DIAG_MPHY_CTRL_1,MPHY Control Register 1 Lane 0" bitfld.word 0x00 14. " RX_DIAG_MPHY_CTRL_1_14 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x00 13. " RX_DIAG_MPHY_CTRL_1_13 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x00 12. " RX_DIAG_MPHY_CTRL_1_12 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x00 8.--9. " RX_DIAG_MPHY_CTRL_1_9_8 ,Signal definition to be provided by the analog team" "0,1,2,3" textline " " bitfld.word 0x00 0.--5. " RX_DIAG_MPHY_CTRL_1_5_0 ,Signal definition to be provided by the analog team" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE0_RX_DIAG_MPHY_CTRL_2,MPHY Control Register 2 Lane 0" rbitfld.word 0x02 10. " RX_DIAG_MPHY_CTRL_2_10 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 9. " RX_DIAG_MPHY_CTRL_2_9 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x02 8. " RX_DIAG_MPHY_CTRL_2_8 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 7. " RX_DIAG_MPHY_CTRL_2_7 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x02 6. " RX_DIAG_MPHY_CTRL_2_6 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 5. " RX_DIAG_MPHY_CTRL_2_5 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x02 4. " RX_DIAG_MPHY_CTRL_2_4 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 0.--1. " RX_DIAG_MPHY_CTRL_2_1_0 ,Signal definition to be provided by the analog team" "0,1,2,3" group.word (0x8000+0x1D0)++0x03 line.word 0x00 "LANE0_RX_DIAG_LPBK_CTRL,RX Loopback Controller Register Lane 0" bitfld.word 0x00 4. " RX_DIAG_LPBK_CTRL_4 ,Recovered clock loopback select" "0,1" bitfld.word 0x00 0.--3. " RX_DIAG_LPBK_CTRL_3_0 ,Attenuation settings" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE0_RX_DIAG_ECTRL_OVRD,RX Extra Enable Control Override Register Lane0" bitfld.word 0x02 1. " RX_DIAG_ECTRL_OVRD_1 ,Sampler CML to CMOS enable override enable" "Disabled,Enabled" bitfld.word 0x02 0. " RX_DIAG_ECTRL_OVRD_0 ,Sampler CML to CMOS enable override" "Disabled,Enabled" group.word (0x8000+0x1E0)++0x0F line.word 0x00 "LANE0_RX_DIAG_CML2CMOS_BTRIM,CML To CMOS Bias Trim Register Lane 0" bitfld.word 0x00 12.--14. " RX_DIAG_CML2CMOS_BTRIM_14_12 ,CML to CMOS IQ bias sink current trim" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--10. " RX_DIAG_CML2CMOS_BTRIM_10_8 ,CML to CMOS IQ bias source current trim" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 4.--6. " RX_DIAG_CML2CMOS_BTRIM_6_4 ,CML to CMOS E bias sink current trim" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--2. " RX_DIAG_CML2CMOS_BTRIM_2_0 ,CML to CMOS E bias source current trim" "0,1,2,3,4,5,6,7" line.word 0x02 "LANE0_RX_DIAG_BIAS_GEN_CTRL1,RX Bias Gen Control Register 1 Lane 0" bitfld.word 0x02 14.--15. " RX_DIAG_BIAS_GEN_CTRL1_15_14 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 12.--13. " RX_DIAG_BIAS_GEN_CTRL1_13_12 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 10.--11. " RX_DIAG_BIAS_GEN_CTRL1_11_10 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 8.--9. " RX_DIAG_BIAS_GEN_CTRL1_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 6.--7. " RX_DIAG_BIAS_GEN_CTRL1_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 4.--5. " RX_DIAG_BIAS_GEN_CTRL1_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 2.--3. " RX_DIAG_BIAS_GEN_CTRL1_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 0.--1. " RX_DIAG_BIAS_GEN_CTRL1_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x04 "LANE0_RX_DIAG_BIAS_GEN_CTRL2,RX Bias Gen Control Register 2 Lane 0" bitfld.word 0x04 14.--15. " RX_DIAG_BIAS_GEN_CTRL2_15_14 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 12.--13. " RX_DIAG_BIAS_GEN_CTRL2_13_12 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 10.--11. " RX_DIAG_BIAS_GEN_CTRL2_11_10 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 8.--9. " RX_DIAG_BIAS_GEN_CTRL2_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 6.--7. " RX_DIAG_BIAS_GEN_CTRL2_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 4.--5. " RX_DIAG_BIAS_GEN_CTRL2_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 2.--3. " RX_DIAG_BIAS_GEN_CTRL2_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 0.--1. " RX_DIAG_BIAS_GEN_CTRL2_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x06 "LANE0_RX_DIAG_BIAS_GEN_CTRL3,RX Bias Gen Control Register 3 Lane 0" bitfld.word 0x06 14.--15. " RX_DIAG_BIAS_GEN_CTRL3_15_14 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 12.--13. " RX_DIAG_BIAS_GEN_CTRL3_13_12 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 10.--11. " RX_DIAG_BIAS_GEN_CTRL3_11_10 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 8.--9. " RX_DIAG_BIAS_GEN_CTRL3_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 6.--7. " RX_DIAG_BIAS_GEN_CTRL3_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 4.--5. " RX_DIAG_BIAS_GEN_CTRL3_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 2.--3. " RX_DIAG_BIAS_GEN_CTRL3_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 0.--1. " RX_DIAG_BIAS_GEN_CTRL3_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x08 "LANE0_RX_DIAG_BIAS_GEN_CTRL4,RX Bias Gen Control Register 4 Lane 0" bitfld.word 0x08 15. " RX_DIAG_BIAS_GEN_CTRL4_15 ,Enable base unit on all the current outputs from the RX bias generation block" "Disabled,Enabled" bitfld.word 0x08 8.--9. " RX_DIAG_BIAS_GEN_CTRL4_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x08 6.--7. " RX_DIAG_BIAS_GEN_CTRL4_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x08 4.--5. " RX_DIAG_BIAS_GEN_CTRL4_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x08 2.--3. " RX_DIAG_BIAS_GEN_CTRL4_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x08 0.--1. " RX_DIAG_BIAS_GEN_CTRL4_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x0A "LANE0_RX_DIAG_BS_TM,RX Boundary Scan Test Mode Register" line.word 0x0C "LANE0_RX_DIAG_RXFE_TM1,RX Receiver Front End Test Mode Register 1 Lane 0" line.word 0x0E "LANE0_RX_DIAG_RXFE_TM2,RX Receiver Front End Test Mode Register 2 Lane 0" group.word 0x8400++0x0F line.word 0x00 "LANE1_RX_PSC_A0,Receiver A0 Power State Definition Register Lane 1" bitfld.word 0x00 15. " RX_PSC_A0_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x00 14. " RX_PSC_A0_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x00 13. " RX_PSC_A0_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RX_PSC_A0_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x00 11. " RX_PSC_A0_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_PSC_A0_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_PSC_A0_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_PSC_A0_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x00 7. " RX_PSC_A0_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " RX_PSC_A0_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x00 5. " RX_PSC_A0_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x00 4. " RX_PSC_A0_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RX_PSC_A0_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x00 2. " RX_PSC_A0_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x00 1. " RX_PSC_A0_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RX_PSC_A0_0 ,RX enable" "Disabled,Enabled" line.word 0x02 "LANE1_RX_PSC_A1,Receiver A1 Power State Definition Register Lane 1" bitfld.word 0x02 15. " RX_PSC_A1_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x02 14. " RX_PSC_A1_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x02 13. " RX_PSC_A1_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RX_PSC_A1_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x02 11. " RX_PSC_A1_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x02 10. " RX_PSC_A1_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RX_PSC_A1_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x02 8. " RX_PSC_A1_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x02 7. " RX_PSC_A1_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " RX_PSC_A1_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x02 5. " RX_PSC_A1_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x02 4. " RX_PSC_A1_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RX_PSC_A1_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x02 2. " RX_PSC_A1_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x02 1. " RX_PSC_A1_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RX_PSC_A1_0 ,RX enable" "Disabled,Enabled" line.word 0x04 "LANE1_RX_PSC_A2,Receiver A2 Power State Definition Register Lane 1" bitfld.word 0x04 15. " RX_PSC_A2_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x04 14. " RX_PSC_A2_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x04 13. " RX_PSC_A2_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x04 12. " RX_PSC_A2_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x04 11. " RX_PSC_A2_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x04 10. " RX_PSC_A2_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x04 9. " RX_PSC_A2_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x04 8. " RX_PSC_A2_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x04 7. " RX_PSC_A2_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " RX_PSC_A2_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x04 5. " RX_PSC_A2_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x04 4. " RX_PSC_A2_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x04 3. " RX_PSC_A2_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x04 2. " RX_PSC_A2_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x04 1. " RX_PSC_A2_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x04 0. " RX_PSC_A2_0 ,RX enable" "Disabled,Enabled" line.word 0x06 "LANE1_RX_PSC_A3,Receiver A3 Power State Definition Register Lane 1" bitfld.word 0x06 15. " RX_PSC_A3_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x06 14. " RX_PSC_A3_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x06 13. " RX_PSC_A3_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x06 12. " RX_PSC_A3_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x06 11. " RX_PSC_A3_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x06 10. " RX_PSC_A3_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x06 9. " RX_PSC_A3_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x06 8. " RX_PSC_A3_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x06 7. " RX_PSC_A3_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " RX_PSC_A3_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x06 5. " RX_PSC_A3_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x06 4. " RX_PSC_A3_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x06 3. " RX_PSC_A3_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x06 2. " RX_PSC_A3_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x06 1. " RX_PSC_A3_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " RX_PSC_A3_0 ,RX enable" "Disabled,Enabled" line.word 0x08 "LANE1_RX_PSC_A4,Receiver A4 Power State Definition Register Lane 1" bitfld.word 0x08 15. " RX_PSC_A4_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x08 14. " RX_PSC_A4_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x08 13. " RX_PSC_A4_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x08 12. " RX_PSC_A4_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x08 11. " RX_PSC_A4_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x08 10. " RX_PSC_A4_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x08 9. " RX_PSC_A4_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x08 8. " RX_PSC_A4_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x08 7. " RX_PSC_A4_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " RX_PSC_A4_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x08 5. " RX_PSC_A4_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x08 4. " RX_PSC_A4_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x08 3. " RX_PSC_A4_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x08 2. " RX_PSC_A4_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x08 1. " RX_PSC_A4_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " RX_PSC_A4_0 ,RX enable" "Disabled,Enabled" line.word 0x0A "LANE1_RX_PSC_A5,Receiver A5 Power State Definition Register Lane 1" bitfld.word 0x0A 15. " RX_PSC_A5_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x0A 14. " RX_PSC_A5_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x0A 13. " RX_PSC_A5_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 12. " RX_PSC_A5_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x0A 11. " RX_PSC_A5_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x0A 10. " RX_PSC_A5_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 9. " RX_PSC_A5_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x0A 8. " RX_PSC_A5_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x0A 7. " RX_PSC_A5_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 6. " RX_PSC_A5_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x0A 5. " RX_PSC_A5_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x0A 4. " RX_PSC_A5_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 3. " RX_PSC_A5_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x0A 2. " RX_PSC_A5_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x0A 1. " RX_PSC_A5_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 0. " RX_PSC_A5_0 ,RX enable" "Disabled,Enabled" line.word 0x0C "LANE1_RX_PSC_CAL,Receiver Calibration Power State Definition Register Lane 1" bitfld.word 0x0C 15. " RX_PSC_CAL_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x0C 14. " RX_PSC_CAL_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x0C 13. " RX_PSC_CAL_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 12. " RX_PSC_CAL_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x0C 11. " RX_PSC_CAL_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x0C 10. " RX_PSC_CAL_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 9. " RX_PSC_CAL_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x0C 8. " RX_PSC_CAL_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x0C 7. " RX_PSC_CAL_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " RX_PSC_CAL_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x0C 5. " RX_PSC_CAL_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x0C 4. " RX_PSC_CAL_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 3. " RX_PSC_CAL_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x0C 2. " RX_PSC_CAL_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x0C 1. " RX_PSC_CAL_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 0. " RX_PSC_CAL_0 ,RX enable" "Disabled,Enabled" line.word 0x0E "LANE1_RX_PSC_RDY,Receiver Ready Power State Definition Register Lane 1" bitfld.word 0x0E 15. " RX_PSC_RDY_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x0E 14. " RX_PSC_RDY_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x0E 13. " RX_PSC_RDY_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 12. " RX_PSC_RDY_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x0E 11. " RX_PSC_RDY_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x0E 10. " RX_PSC_RDY_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 9. " RX_PSC_RDY_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x0E 8. " RX_PSC_RDY_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x0E 7. " RX_PSC_RDY_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 6. " RX_PSC_RDY_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x0E 5. " RX_PSC_RDY_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x0E 4. " RX_PSC_RDY_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 3. " RX_PSC_RDY_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x0E 2. " RX_PSC_RDY_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x0E 1. " RX_PSC_RDY_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 0. " RX_PSC_RDY_0 ,RX enable" "Disabled,Enabled" textline " " group.word (0x8400+0x40)++0x0D line.word 0x00 "LANE1_RX_IQPI_ILL_CAL_CTRL,RX IQ PI ILL Calibration Control Register Lane 1" bitfld.word 0x00 15. " RX_IQPI_ILL_CAL_CTRL_15 ,Start ILL calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_IQPI_ILL_CAL_CTRL_15 ,ILL calibration process done" "Not done,Done" textline " " hexmask.word.byte 0x00 0.--7. 1. " RX_IQPI_ILL_CAL_CTRL_7_0 ,ILL calibration code" line.word 0x02 "LANE1_RX_IQPI_ILL_CAL_START,RX IQ PI ILL Calibration Start Point Register Lane 1" bitfld.word 0x02 12.--14. " RX_IQPI_ILL_CAL_START_14_12 ,ILL calibration initial step size control" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x02 0.--7. 1. " RX_IQPI_ILL_CAL_START_7_0 ,ILL calibration code starting point value" line.word 0x04 "LANE1_RX_IQPI_ILL_CAL_TCTRL,RX IQ PI ILL Calibration Timer Control Register Lane 1" bitfld.word 0x04 0.--2. " RX_IQPI_ILL_CAL_TCTRL_2_0 ,ILL calibration initial time scale control" "0,1,2,3,4,5,6,7" line.word 0x06 "LANE1_RX_IQPI_ILL_CAL_OVRD,RX IQ PI ILL Calibration Override Register Lane 1" bitfld.word 0x06 15. " RX_IQPI_ILL_CAL_OVRD_15 ,ILL calibration code override enable" "Disabled,Enabled" hexmask.word.byte 0x06 0.--7. 1. " RX_IQPI_ILL_CAL_OVRD_7_0 ,ILL calibration code override value" line.word 0x08 "LANE1_RX_IQPI_ILL_CAL_INIT_TMR,RX IQ PI ILL Calibration Initialization Timer Register Lane 1" hexmask.word 0x08 0.--11. 1. " RX_IQPI_ILL_CAL_INIT_TMR_11_0 ,Initialization wait timer value" line.word 0x0A "LANE1_RX_IQPI_ILL_CAL_ITER_TMR,RX IQ PI ILL Calibration Iteration Timer Register Lane 1" hexmask.word 0x0A 0.--11. 1. " RX_IQPI_ILL_CAL_ITER_TMR_11_0 ,Iteration wait timer value" line.word 0x0C "LANE1_RX_IQPI_ILL_LOCK_REFTMR_START,RX IQ PI ILL Lock Reference Timer Start Value Register Lane 1" hexmask.word 0x0C 0.--11. 1. " RX_IQPI_ILL_LOCK_REFTMR_START_11_0 ,ILL lock reference timer start value" group.word (0x8400+0x50)++0x07 line.word 0x00 "LANE1_RX_IQPI_ILL_LOCK_CALCNT_START_0,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 0 Register Lane 1" hexmask.word 0x00 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_0_11_0 ,ILL lock calibration counter start value" line.word 0x02 "LANE1_RX_IQPI_ILL_LOCK_CALCNT_START_1,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 1 Register Lane 1" hexmask.word 0x02 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_1_11_0 ,ILL lock calibration counter start value" line.word 0x04 "LANE1_RX_IQPI_ILL_LOCK_CALCNT_START_2,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 2 Register Lane 1" hexmask.word 0x04 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_2_11_0 ,ILL lock calibration counter start value" line.word 0x06 "LANE1_RX_IQPI_ILL_LOCK_CALCNT_START_3,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 3 Register Lane 1" hexmask.word 0x06 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_3_11_0 ,ILL lock calibration counter start value" group.word (0x8400+0x60)++0x0D line.word 0x00 "LANE1_RX_EPI_ILL_CAL_CTRL,RX E PI ILL Calibration Control Register Lane 1" bitfld.word 0x00 15. " RX_EPI_ILL_CAL_CTRL_15 ,Start ILL calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_EPI_ILL_CAL_CTRL_14 ,ILL calibration process done" "Not done,Done" textline " " hexmask.word.byte 0x00 0.--7. 1. " RX_EPI_ILL_CAL_CTRL_7_0 ,ILL calibration code" line.word 0x02 "LANE1_RX_EPI_ILL_CAL_START,RX E PI ILL Calibration Start Point Register Lane 1" bitfld.word 0x02 12.--14. " RX_EPI_ILL_CAL_START_14_12 ,ILL calibration initial step size control" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x02 0.--7. 1. " RX_EPI_ILL_CAL_START_7_0 ,ILL calibration code starting point value" line.word 0x04 "LANE1_RX_EPI_ILL_CAL_TCTRL,RX E PI ILL Calibration Timer Control Register Lane 1" bitfld.word 0x04 0.--2. " RX_EPI_ILL_CAL_TCTRL_2_0 ,ILL calibration initial time scale control" "0,1,2,3,4,5,6,7" line.word 0x06 "LANE1_RX_EPI_ILL_CAL_OVRD,RX E PI ILL Calibration Override Register Lane 1" bitfld.word 0x06 15. " RX_EPI_ILL_CAL_OVRD_15 ,ILL calibration code override enable" "Disabled,Enabled" hexmask.word.byte 0x06 0.--7. 1. " RX_EPI_ILL_CAL_OVRD_7_0 ,ILL calibration code override value" line.word 0x08 "LANE1_RX_EPI_ILL_CAL_INIT_TMR,RX E PI ILL Calibration Initialization Timer Register 1" hexmask.word 0x08 0.--11. 1. " RX_EPI_ILL_CAL_INIT_TMR_11_0 ,Initialization wait timer value" line.word 0x0A "LANE1_RX_EPI_ILL_CAL_ITER_TMR,RX E PI ILL Calibration Iteration Timer Register Lane 1" hexmask.word 0x0A 0.--11. 1. " RX_EPI_ILL_CAL_ITER_TMR_11_0 ,Iteration wait timer value" line.word 0x0C "LANE1_RX_EPI_ILL_LOCK_REFTMR_START,RX E PI ILL Lock Reference Timer Start Value Register Lane 1" hexmask.word 0x0C 0.--11. 1. " RX_EPI_ILL_LOCK_REFTMR_START_11_0 ,ILL lock reference timer start value" group.word (0x8400+0x70)++0x07 line.word 0x00 "LANE1_RX_EPI_ILL_LOCK_CALCNT_START_0,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 0 Register Lane 1" hexmask.word 0x00 0.--11. 1. " RX_EPI_ILL_LOCK_CALCNT_START_0_11_0 ,ILL lock calibration counter start value" line.word 0x02 "LANE1_RX_EPI_ILL_LOCK_CALCNT_START_1,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 1 Register Lane 1" hexmask.word 0x02 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_1_11_0 ,ILL lock calibration counter start value" line.word 0x04 "LANE1_RX_IQPI_ILL_LOCK_CALCNT_START_2,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 2 Register Lane 1" hexmask.word 0x04 0.--11. 1. " RX_EPI_ILL_LOCK_CALCNT_START_2_11_0 ,ILL lock calibration counter start value" line.word 0x06 "LANE1_RX_IQPI_ILL_LOCK_CALCNT_START_3,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 3 Register Lane 1" hexmask.word 0x06 0.--11. 1. " RX_EPI_ILL_LOCK_CALCNT_START_3_11_0 ,ILL lock calibration counter start value" group.word (0x8400+0x80)++0x0B line.word 0x00 "LANE1_RX_SDCAL0_CTRL,Signal Detect Calibration 0 Control Register Lane 1" bitfld.word 0x00 15. " RX_SDCAL0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SDCAL0_CTRL_14 ,Calibration process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " RX_EPI_ILL_CAL_CTRL_14 ,No analog calibration response" "Not responded,Responded" rbitfld.word 0x00 12. " RX_SDCAL0_CTRL_14 ,Current analog comparator response" "Not responded,Responded" textline " " bitfld.word 0x00 0.--3. " RX_SDCAL0_CTRL_3_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE1_RX_SDCAL0_OVRD,Signal Detect Calibration 0 Override Register Lane 1" bitfld.word 0x02 15. " RX_SDCAL0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " RX_SDCAL0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 0.--3. " RX_SDCAL0_OVRD_3_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "LANE1_RX_SDCAL0_START,Signal Detect Calibration 0 Start Register Lane 1" bitfld.word 0x04 15. " RX_SDCAL0_START_15 ,Calibration direction" "0,1" bitfld.word 0x04 0.--3. " RX_SDCAL0_START_3_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x06 "LANE1_RX_SDCAL0_TUNE,Signal Detect Calibration 0 Tune Register Lane 1" bitfld.word 0x06 0.--3. " RX_SDCAL0_TUNE_3_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "LANE1_RX_SDCAL0_INIT_TMR,Signal Detect Calibration 0 Initialization Timer Register Lane1" hexmask.word 0x08 0.--8. 1. " RX_SDCAL0_INIT_TMR_8_0 ,Initialization wait timer value" line.word 0x0A "LANE1_RX_SDCAL0_ITER_TMR,Signal Detect Calibration 0 Iteration Timer Register Lane 1" hexmask.word 0x0A 0.--8. 1. " RX_SDCAL0_ITER_TMR_8_0 ,Iteration wait timer value" group.word (0x8400+0x90)++0x0B line.word 0x00 "LANE1_RX_SDCAL1_CTRL,Signal Detect Calibration 1 Control Register Lane 1" bitfld.word 0x00 15. " RX_SDCAL1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SDCAL1_CTRL_14 ,Calibration process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " RX_SDCAL1_CTRL_13 ,No analog calibration response" "Not responded,Responded" rbitfld.word 0x00 12. " RX_SDCAL1_CTRL_12 ,Current analog comparator response" "Not responded,Responded" textline " " bitfld.word 0x00 0.--3. " RX_SDCAL1_CTRL_3_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE1_RX_SDCAL1_OVRD,Signal Detect Calibration 1 Override Register Lane 1" bitfld.word 0x02 15. " RX_SDCAL1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " RX_SDCAL1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 0.--3. " RX_SDCAL1_OVRD_3_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "LANE1_RX_SDCAL1_START,Signal Detect Calibration 1 Start Register Lane 1" bitfld.word 0x04 15. " RX_SDCAL1_START_15 ,Calibration direction" "0,1" bitfld.word 0x04 0.--3. " RX_SDCAL1_START_3_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x06 "LANE1_RX_SDCAL1_TUNE,Signal Detect Calibration 1 Tune Register Lane 1" bitfld.word 0x06 0.--3. " RX_SDCAL1_TUNE_3_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "LANE1_RX_SDCAL1_INIT_TMR,Signal Detect Calibration 1 Initialization Timer Register Lane 1" hexmask.word 0x08 0.--8. 1. " RX_SDCAL1_INIT_TMR_8_0 ,Initialization wait timer value" line.word 0x0A "LANE1_RX_SDCAL1_ITER_TMR,Signal Detect Calibration 1 Iteration Timer Register Lane 1" hexmask.word 0x0A 0.--8. 1. " RX_SDCAL1_ITER_TMR_8_0 ,Iteration wait timer value" group.word (0x8400+0xB0)++0x01 line.word 0x00 "LANE1_RX_SAMP_DAC_CTRL,Sampler Error DAC Control Register Lane 1" bitfld.word 0x00 0.--5. " RX_SAMP_DAC_CTRL_5_0 ,Sampler error DAC value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8400+0x100)++0x0B line.word 0x00 "LANE1_RX_CDRLF_CNFG,CDRLF Configuration Register Lane 1" rbitfld.word 0x00 15. " RX_CDRLF_CNFG_15 ,CDRLF fast phase lock locked detected" "Not detected,Detected" bitfld.word 0x00 14. " RX_CDRLF_CNFG_14 ,CDRLF fast phase lock diagnostic enable" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " RX_CDRLF_CNFG_13 ,CDRLF fast phase lock enable" "Disabled,Enabled" bitfld.word 0x00 12. " RX_CDRLF_CNFG_12 ,CDRLF fast frequency lock enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " RX_CDRLF_CNFG_11 ,CDRLF second order loop integrator max clear enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_CDRLF_CNFG_10 ,CDRLF reset on CDRLF PM accumulator max" "No reset,Reset" textline " " bitfld.word 0x00 9. " RX_CDRLF_CNFG_9 ,CDRLF freeze on electrical idle detect" "Not detected,Detected" bitfld.word 0x00 8. " RX_CDRLF_CNFG_8 ,CDRLF reset on electrical idle detect" "Not detected,Detected" textline " " bitfld.word 0x00 7. " RX_CDRLF_CNFG_7 ,CDRLF data filter enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " RX_CDRLF_CNFG_5_0 ,CDRLF second order loop integrator threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE1_RX_CDRLF_CNFG2,CDRLF Configuration Register 2 Lane 1" bitfld.word 0x02 4.--6. " RX_CDRLF_CNFG2_6 ,CDRLF diagnostic mode control" "0,1,2,3,4,5,6,7" bitfld.word 0x02 2. " RX_CDRLF_CNFG2_2 ,CDLRF reset hold" "Not held,Held" textline " " bitfld.word 0x02 1. " RX_CDRLF_CNFG2_1 ,CDRLF second order loop disable" "No,Yes" bitfld.word 0x02 0. " RX_CDRLF_CNFG2_0 ,CDRLF first order loop disable" "No,Yes" line.word 0x04 "LANE1_RX_CDRLF_MGN_DIAG,CDRLF Margin Diagnostic Register 2 Lane 1" bitfld.word 0x04 2. " RX_CDRLF_MGN_DIAG_2 ,CDRLF PI override down" "No override,Override" bitfld.word 0x04 1. " RX_CDRLF_MGN_DIAG_1 ,CDRLF PI override up" "No override,Override" textline " " bitfld.word 0x04 0. " RX_CDRLF_MGN_DIAG_0 ,CDRLF PI override enable" "Disabled,Enabled" line.word 0x06 "LANE1_RX_CDRLF_FPL_TMR0,CDRLF Fast Phase Lock Timer Value Register 0 Lane 1" bitfld.word 0x06 4.--7. " RX_CDRLF_FPL_TMR0_7_4 ,Fast phase lock timer accumulate state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x06 0.--3. " RX_CDRLF_FPL_TMR0_3_0 ,Fast phase lock timer delay state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "LANE1_RX_CDRLF_FPL_TMR1,CDRLF Fast Phase Lock Timer Value Register 1 Lane 1" bitfld.word 0x08 8.--11. " RX_CDRLF_FPL_TMR1_11_8 ,Fast phase lock timer trigger 1 state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x08 4.--7. " RX_CDRLF_FPL_TMR1_7_4 ,Fast phase lock timer trigger 2 state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x08 0.--3. " RX_CDRLF_FPL_TMR1_3_0 ,Fast phase lock timer trigger 3 state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0A "LANE1_RX_CDRLF_FFL_TMR,CDRLF Fast Frequency Lock Timer Value Register Lane 1" bitfld.word 0x0A 0.--5. " RX_CDRLF_FFL_TMR_5_0 ,Fast frequency lock step timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8400+0x110)++0x09 line.word 0x00 "LANE1_RX_CDRLF_FFL0_CTRL,CDRLF Fast Frequency Lock Step 0 Control Register Lane 1" bitfld.word 0x00 14.--15. " RX_CDRLF_FFL0_CTRL_15_14 ,FFL step 0 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x00 8.--12. " RX_CDRLF_FFL0_CTRL_12_8 ,FFL step 0 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x00 0.--4. " RX_CDRLF_FFL0_CTRL_4_0 ,FFL step 0 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x02 "LANE1_RX_CDRLF_FFL1_CTRL,CDRLF Fast Frequency Lock Step 1 Control Register Lane 1" bitfld.word 0x02 14.--15. " RX_CDRLF_FFL1_CTRL_15_14 ,FFL step 1 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x02 8.--12. " RX_CDRLF_FFL1_CTRL_12_8 ,FFL step 1 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x02 0.--4. " RX_CDRLF_FFL1_CTRL_4_0 ,FFL step 1 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE1_RX_CDRLF_FFL2_CTRL,CDRLF Fast Frequency Lock Step 2 Control Register Lane 1" bitfld.word 0x04 14.--15. " RX_CDRLF_FFL2_CTRL_15_14 ,FFL step 2 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x04 8.--12. " RX_CDRLF_FFL2_CTRL_12_8 ,FFL step 2 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x04 0.--4. " RX_CDRLF_FFL2_CTRL_4_0 ,FFL step 2 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "LANE1_RX_CDRLF_FFL3_CTRL,CDRLF Fast Frequency Lock Step 3 Control Register Lane 1" bitfld.word 0x06 14.--15. " RX_CDRLF_FFL3_CTRL_15_14 ,FFL step 3 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x06 8.--12. " RX_CDRLF_FFL3_CTRL_12_8 ,FFL step 3 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x06 0.--4. " RX_CDRLF_FFL3_CTRL_4_0 ,FFL step 3 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "LANE1_RX_CDRLF_FFL4_CTRL,CDRLF Fast Frequency Lock Step 4 Control Register Lane 1" bitfld.word 0x08 14.--15. " RX_CDRLF_FFL4_CTRL_15_14 ,FFL step 4 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x08 8.--12. " RX_CDRLF_FFL4_CTRL_12_8 ,FFL step 4 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x08 0.--4. " RX_CDRLF_FFL4_CTRL_4_0 ,FFL step 4 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (0x8400+0x120)++0x17 line.word 0x00 "LANE1_RX_SIGDET_HL_FILT_TMR,Receiver Signal Detect Filter High To Low Filter Timer Register Lane 1" hexmask.word 0x00 0.--9. 1. " RX_SIGDET_HL_FILT_TMR_9_0 ,Signal detect filter high to low filter timer value" line.word 0x02 "LANE1_RX_SIGDET_HL_DLY_TMR,Receiver Signal Detect Filter High To Low Delay Timer Register Lane 1" hexmask.word 0x02 0.--9. 1. " RX_SIGDET_HL_DLY_TMR_9_0 ,Signal detect filter high to low delay timer value" line.word 0x04 "LANE1_RX_SIGDET_HL_MIN_TMR,Receiver Signal Detect Filter High To Low Min Timer Register Lane 1" hexmask.word 0x04 0.--9. 1. " RX_SIGDET_HL_MIN_TMR_9_0 ,Signal detect filter high to low min timer value" line.word 0x06 "LANE1_RX_SIGDET_HL_MIN_TMR,Receiver Signal Detect Filter High To Low Init Timer Register Lane 1" hexmask.word 0x06 0.--9. 1. " RX_SIGDET_HL_INIT_TMR_9_0 ,Signal detect init timer value" line.word 0x08 "LANE1_RX_SIGDET_LH_FILT_TMR,Receiver Signal Detect Filter Low To High Filter Timer Register Lane 1" hexmask.word 0x08 0.--9. 1. " RX_SIGDET_LH_FILT_TMR_9_0 ,Signal detect filter low to high filter timer value" line.word 0x0A "LANE1_RX_SIGDET_LH_DLY_TMR,Receiver Signal Detect Filter Low To High Delay Timer Register Lane 1" hexmask.word 0x0A 0.--9. 1. " RX_SIGDET_LH_DLY_TMR_9_0 ,Signal detect filter low to high delay timer value" line.word 0x0C "LANE1_RX_SIGDET_LH_MIN_TMR,Receiver Signal Detect Filter Low To High Min Timer Register Lane 1" hexmask.word 0x0C 0.--9. 1. " RX_SIGDET_LH_MIN_TMR_9_0 ,Signal detect filter low to high min timer value" line.word 0x0E "LANE1_RX_SIGDET_LH_INIT_TMR,Receiver Signal Detect Filter Low To High Init Timer Register Lane 1" hexmask.word 0x0E 0.--9. 1. " RX_SIGDET_LH_INIT_TMR_9_0 ,Signal detect init timer value" line.word 0x10 "LANE1_RX_LFPSDET_FILT_TMR,Receiver LFPS Detect Filter Filter Timer Register Lane 1" hexmask.word 0x10 0.--9. 1. " RX_LFPSDET_FILT_TMR_9_0 ,LFPS detect filter timer value" line.word 0x12 "LANE1_RX_LFPSDET_DLY_TMR,Receiver LFPS Detect Filter Delay Timer Register Lane 1" hexmask.word 0x12 0.--9. 1. " RX_LFPSDET_DLY_TMR_9_0 ,LFPS detect filter delay timer value" line.word 0x14 "LANE1_RX_LFPSDET_MIN_TMR,Receiver LFPS Detect Min Timer Register Lane 1" hexmask.word 0x14 0.--9. 1. " RX_LFPSDET_MIN_TMR_9_0 ,LFPS detect min timer value" line.word 0x16 "LANE1_RX_LFPSDET_INIT_TMR,Receiver LFPS Detect Init Timer Register Lane 1" hexmask.word 0x16 0.--9. 1. " RX_LFPSDET_INIT_TMR_9_0 ,LFPS detect init timer value" group.word (0x8400+0x140)++0x01 line.word 0x00 "LANE1_RX_EYESURF_CTRL,Eye Surf Control Register Lane 1" bitfld.word 0x00 15. " RX_EYESURF_CTRL_15 ,Eye surf process enable" "Disabled,Enabled" rbitfld.word 0x00 14. " RX_EYESURF_CTRL_14 ,Eye surf process has completed" "Not completed,Completed" group.word (0x8400+0x148)++0x0B line.word 0x00 "LANE1_RX_EYESURF_TMR_DELLOW,Eye Surf Timer Delay Low Register Lane 1" line.word 0x02 "LANE1_RX_EYESURF_TMR_DELHIGH,Eye Surf Timer Delay High Register Lane 1" line.word 0x04 "LANE1_RX_EYESURF_TMR_TESTLOW,Eye Surf Timer Test Low Register Lane 1" line.word 0x06 "LANE1_RX_EYESURF_TMR_TESTHIGH,Eye Surf Timer Test High Register Lane 1" line.word 0x08 "LANE1_RX_EYESURF_NS_COORD,Eye Surf North South Test Point Coordinate Register Lane 1" bitfld.word 0x08 8. " RX_EYESURF_NS_COORD_8 ,Test point coordinate north south direction" "0,1" hexmask.word.byte 0x08 0.--6. 0x01 " RX_EYESURF_NS_COORD_6_0 ,Test point coordinate north south offset" line.word 0x0A "LANE1_RX_EYESURF_EW_COORD,Eye Surf East West Test Point Coordinate Register Lane 1" bitfld.word 0x0A 8. " RX_EYESURF_EW_COORD_8 ,Test point coordinate east west direction" "0,1" hexmask.word.byte 0x0A 0.--4. 0x01 " RX_EYESURF_EW_COORD_4_0 ,Test point coordinate east west offset" rgroup.word (0x8400+0x154)++0x01 line.word 0x00 "LANE1_RX_EYESURF_ERRCNT,Eye Surf Bit Error Count Register Lane 1" group.word (0x8400+0x160)++0x03 line.word 0x00 "LANE1_RX_BIST_CTRL,Receiver BIST Control Register Lane 1" bitfld.word 0x00 8.--11. " RX_BIST_CTRL_11_8 ,Receiver BIST mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4. " RX_BIST_CTRL_4 ,Receiver BIST error reset" "No reset,Reset" textline " " bitfld.word 0x00 1. " RX_BIST_CTRL_1 ,Receiver BIST user defined data FIFO clear" "No clear,Clear" bitfld.word 0x00 0. " RX_BIST_CTRL_0 ,Receiver BIST enable" "Disabled,Enabled" line.word 0x02 "LANE1_RX_BIST_SYNCCNT,Receiver BIST Sync Count Register Lane 1" wgroup.word (0x8400+0x164)++0x01 line.word 0x00 "LANE1_RX_BIST_UDDWR,Receiver BIST User Defined Data Write Register Lane 1" hexmask.word 0x00 0.--9. 1. " RX_BIST_UDDWR_9_0 ,Receiver BIST user defined data" rgroup.word (0x8400+0x166)++0x01 line.word 0x00 "LANE1_RX_BIST_ERRCNT,Receiver BIST Error Count Register Lane 1" group.word (0x8400+0x168)++0x05 line.word 0x00 "LANE1_XCVR_CMSMT_CLK_FREQ_MSMT_CTRL,Clock Frequency Measurement Control Register Lane 1" bitfld.word 0x00 15. " XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_15 ,Start test clock measurement" "Not started,Started" rbitfld.word 0x00 14. " XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_14 ,Test clock measurement done" "Not done,Done" line.word 0x02 "LANE1_XCVR_CMSMT_TEST_CLK_SEL,Test Clock Selection Register Lane 1" bitfld.word 0x02 0.--2. " XCVR_CMSMT_TEST_CLK_SEL_2_0 ,Test clock select" "0,1,2,3,4,5,6,7" line.word 0x04 "LANE1_XCVR_CMSMT_REF_CLK_TMR_VALUE,Reference Clock Timer Value Register Lane 1" hexmask.word 0x04 0.--11. 1. " XCVR_CMSMT_REF_CLK_TMR_VALUE_11_0 ,Reference clock timer value" rgroup.word (0x8400+0x16E)++0x01 line.word 0x00 "LANE1_XCVR_CMSMT_TEST_CLK_CNT_VALUE,Test Clock Counter Value Register Lane 1" hexmask.word 0x00 0.--11. 1. " XCVR_CMSMT_TEST_CLK_CNT_VALUE_11_0 ,Test clock counter value" group.word (0x8400+0x1C0)++0x15 line.word 0x00 "LANE1_RX_SLC_CTRL,RX Sampler Latch Calibration Control Register Lane 1" bitfld.word 0x00 15. " RX_SLC_CTRL_15 ,Start RX sampler latch calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SLC_CTRL_14 ,RX sampler latch calibration done" "Not done,Done" textline " " bitfld.word 0x00 13. " RX_SLC_CTRL_13 ,Analog calibration enable override" "Disabled,Enabled" bitfld.word 0x00 11. " RX_SLC_CTRL_11 ,I odd positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " RX_SLC_CTRL_10 ,Q odd positive calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 9. " RX_SLC_CTRL_9 ,E odd positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " RX_SLC_CTRL_8 ,I odd negative calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 7. " RX_SLC_CTRL_7 ,Q odd negative calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " RX_SLC_CTRL_6 ,E odd negative calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 5. " RX_SLC_CTRL_5 ,I even positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_SLC_CTRL_4 ,Q even positive calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 3. " RX_SLC_CTRL_3 ,E even positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " RX_SLC_CTRL_2 ,I even negative calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 1. " RX_SLC_CTRL_1 ,Q even negative calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RX_SLC_CTRL_0 ,E even negative calibration unit enable" "Disabled,Enabled" line.word 0x02 "LANE1_RX_SLC_EN_INIT_TMR,RX Sampler Latch Calibration Enable Initialization Timer Value Register Lane 1" bitfld.word 0x02 0.--5. " RX_SLC_EN_INIT_TMR_5_0 ,RX sampler latch calibration enable initialization timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE1_RX_SLC_CU_INIT_TMR,RX Sampler Latch Calibration Unit Initialization Timer Value Register Lane 1" bitfld.word 0x04 0.--5. " RX_SLC_CU_INIT_TMR_5_0 ,RX sampler latch calibration unit initialization timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x06 "LANE1_RX_SLC_CU_ITER_TMR,RX Sampler Latch Calibration Unit Iteration Timer Value Register Lane 1" bitfld.word 0x06 0.--5. " RX_SLC_CU_ITER_TMR_5_0 ,RX sampler latch calibration unit iteration timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "LANE1_RX_SLC_IE_MASK,RX Sampler Latch Calibration I Even Data Mask Register Lane 1" bitfld.word 0x08 9. " RX_SLC_IE_MASK_9 ,I even data mask 9" "Not masked,Masked" bitfld.word 0x08 8. " RX_SLC_IE_MASK_8 ,I even data mask 8" "Not masked,Masked" textline " " bitfld.word 0x08 7. " RX_SLC_IE_MASK_7 ,I even data mask 7" "Not masked,Masked" bitfld.word 0x08 6. " RX_SLC_IE_MASK_6 ,I even data mask 6" "Not masked,Masked" textline " " bitfld.word 0x08 5. " RX_SLC_IE_MASK_5 ,I even data mask 5" "Not masked,Masked" bitfld.word 0x08 4. " RX_SLC_IE_MASK_4 ,I even data mask 4" "Not masked,Masked" textline " " bitfld.word 0x08 3. " RX_SLC_IE_MASK_3 ,I even data mask 3" "Not masked,Masked" bitfld.word 0x08 2. " RX_SLC_IE_MASK_2 ,I even data mask 2" "Not masked,Masked" textline " " bitfld.word 0x08 1. " RX_SLC_IE_MASK_1 ,I even data mask 1" "Not masked,Masked" bitfld.word 0x08 0. " RX_SLC_IE_MASK_0 ,I even data mask 0" "Not masked,Masked" line.word 0x0A "LANE1_RX_SLC_IO_MASK,RX Sampler Latch Calibration I Odd Data Mask Register Lane 1" bitfld.word 0x0A 9. " RX_SLC_IO_MASK_9 ,I odd data mask 9" "Not masked,Masked" bitfld.word 0x0A 8. " RX_SLC_IO_MASK_8 ,I odd data mask 8" "Not masked,Masked" textline " " bitfld.word 0x0A 7. " RX_SLC_IO_MASK_7 ,I odd data mask 7" "Not masked,Masked" bitfld.word 0x0A 6. " RX_SLC_IO_MASK_6 ,I odd data mask 6" "Not masked,Masked" textline " " bitfld.word 0x0A 5. " RX_SLC_IO_MASK_5 ,I odd data mask 5" "Not masked,Masked" bitfld.word 0x0A 4. " RX_SLC_IO_MASK_4 ,I odd data mask 4" "Not masked,Masked" textline " " bitfld.word 0x0A 3. " RX_SLC_IO_MASK_3 ,I odd data mask 3" "Not masked,Masked" bitfld.word 0x0A 2. " RX_SLC_IO_MASK_2 ,I odd data mask 2" "Not masked,Masked" textline " " bitfld.word 0x0A 1. " RX_SLC_IO_MASK_1 ,I odd data mask 1" "Not masked,Masked" bitfld.word 0x0A 0. " RX_SLC_IO_MASK_0 ,I odd data mask 0" "Not masked,Masked" line.word 0x0C "LANE1_RX_SLC_QE_MASK,RX Sampler Latch Calibration Q Even Data Mask Register Lane 1" bitfld.word 0x0C 9. " RX_SLC_QE_MASK_9 ,Q even data mask 9" "Not masked,Masked" bitfld.word 0x0C 8. " RX_SLC_QE_MASK_8 ,Q even data mask 8" "Not masked,Masked" textline " " bitfld.word 0x0C 7. " RX_SLC_QE_MASK_7 ,Q even data mask 7" "Not masked,Masked" bitfld.word 0x0C 6. " RX_SLC_QE_MASK_6 ,Q even data mask 6" "Not masked,Masked" textline " " bitfld.word 0x0C 5. " RX_SLC_QE_MASK_5 ,Q even data mask 5" "Not masked,Masked" bitfld.word 0x0C 4. " RX_SLC_QE_MASK_4 ,Q even data mask 4" "Not masked,Masked" textline " " bitfld.word 0x0C 3. " RX_SLC_QE_MASK_3 ,Q even data mask 3" "Not masked,Masked" bitfld.word 0x0C 2. " RX_SLC_QE_MASK_2 ,Q even data mask 2" "Not masked,Masked" textline " " bitfld.word 0x0C 1. " RX_SLC_QE_MASK_1 ,Q even data mask 1" "Not masked,Masked" bitfld.word 0x0C 0. " RX_SLC_QE_MASK_0 ,Q even data mask 0" "Not masked,Masked" line.word 0x0E "LANE1_RX_SLC_QO_MASK,RX Sampler Latch Calibration Q Odd Data Mask Register Lane 1" bitfld.word 0x0E 9. " RX_SLC_QO_MASK_9 ,Q odd data mask 9" "Not masked,Masked" bitfld.word 0x0E 8. " RX_SLC_QO_MASK_8 ,Q odd data mask 8" "Not masked,Masked" textline " " bitfld.word 0x0E 7. " RX_SLC_QO_MASK_7 ,Q odd data mask 7" "Not masked,Masked" bitfld.word 0x0E 6. " RX_SLC_QO_MASK_6 ,Q odd data mask 6" "Not masked,Masked" textline " " bitfld.word 0x0E 5. " RX_SLC_QO_MASK_5 ,Q odd data mask 5" "Not masked,Masked" bitfld.word 0x0E 4. " RX_SLC_QO_MASK_4 ,Q odd data mask 4" "Not masked,Masked" textline " " bitfld.word 0x0E 3. " RX_SLC_QO_MASK_3 ,Q odd data mask 3" "Not masked,Masked" bitfld.word 0x0E 2. " RX_SLC_QO_MASK_2 ,Q odd data mask 2" "Not masked,Masked" textline " " bitfld.word 0x0E 1. " RX_SLC_QO_MASK_1 ,Q odd data mask 1" "Not masked,Masked" bitfld.word 0x0E 0. " RX_SLC_QO_MASK_0 ,Q odd data mask 0" "Not masked,Masked" line.word 0x10 "LANE1_RX_SLC_EE_MASK,RX Sampler Latch Calibration E Even Data Mask Register Lane 1" bitfld.word 0x10 9. " RX_SLC_EE_MASK_9 ,E even data mask 9" "Not masked,Masked" bitfld.word 0x10 8. " RX_SLC_EE_MASK_8 ,E even data mask 8" "Not masked,Masked" textline " " bitfld.word 0x10 7. " RX_SLC_EE_MASK_7 ,E even data mask 7" "Not masked,Masked" bitfld.word 0x10 6. " RX_SLC_EE_MASK_6 ,E even data mask 6" "Not masked,Masked" textline " " bitfld.word 0x10 5. " RX_SLC_EE_MASK_5 ,E even data mask 5" "Not masked,Masked" bitfld.word 0x10 4. " RX_SLC_EE_MASK_4 ,E even data mask 4" "Not masked,Masked" textline " " bitfld.word 0x10 3. " RX_SLC_EE_MASK_3 ,E even data mask 3" "Not masked,Masked" bitfld.word 0x10 2. " RX_SLC_EE_MASK_2 ,E even data mask 2" "Not masked,Masked" textline " " bitfld.word 0x10 1. " RX_SLC_EE_MASK_1 ,E even data mask 1" "Not masked,Masked" bitfld.word 0x10 0. " RX_SLC_EE_MASK_0 ,E even data mask 0" "Not masked,Masked" line.word 0x12 "LANE1_RX_SLC_EO_MASK,RX Sampler Latch Calibration E Odd Data Mask Register Lane 1" bitfld.word 0x12 9. " RX_SLC_EO_MASK_9 ,E odd data mask 9" "Not masked,Masked" bitfld.word 0x12 8. " RX_SLC_EO_MASK_8 ,E odd data mask 8" "Not masked,Masked" textline " " bitfld.word 0x12 7. " RX_SLC_EO_MASK_7 ,E odd data mask 7" "Not masked,Masked" bitfld.word 0x12 6. " RX_SLC_EO_MASK_6 ,E odd data mask 6" "Not masked,Masked" textline " " bitfld.word 0x12 5. " RX_SLC_EO_MASK_5 ,E odd data mask 5" "Not masked,Masked" bitfld.word 0x12 4. " RX_SLC_EO_MASK_4 ,E odd data mask 4" "Not masked,Masked" textline " " bitfld.word 0x12 3. " RX_SLC_EO_MASK_3 ,E odd data mask 3" "Not masked,Masked" bitfld.word 0x12 2. " RX_SLC_EO_MASK_2 ,E odd data mask 2" "Not masked,Masked" textline " " bitfld.word 0x12 1. " RX_SLC_EO_MASK_1 ,E odd data mask 1" "Not masked,Masked" bitfld.word 0x12 0. " RX_SLC_EO_MASK_0 ,E odd data mask 0" "Not masked,Masked" line.word 0x14 "LANE1_RX_SLC_DATA_THR,RX Sampler Latch Calibration Data Threshold Register Lane 1" bitfld.word 0x14 0.--3. " RX_SLC_DATA_THR_3_0 ,Data threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word (0x8400+0x200)++0xCB line.word 0x00 "LANE1_RX_SLC_IOP0_CTRL,RX Sampler Latch I Odd Positive 0 Calibration Unit Control Register Lane 1" bitfld.word 0x00 15. " RX_SLC_IOP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SLC_IOP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x00 13. " RX_SLC_IOP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x00 12. " RX_SLC_IOP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x00 0.--5. " RX_SLC_IOP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE1_RX_SLC_IOP0_OVRD,RX Sampler Latch I Odd Positive 0 Calibration Unit Override Register Lane 1" bitfld.word 0x02 15. " RX_SLC_IOP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " RX_SLC_IOP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 0.--5. " RX_SLC_IOP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE1_RX_SLC_IOP0_START,RX Sampler Latch I Odd Positive 0 Calibration Unit Start Register Lane 1" bitfld.word 0x04 15. " RX_SLC_IOP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x04 0.--5. " RX_SLC_IOP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x06 "LANE1_RX_SLC_IOP0_TUNE,RX Sampler Latch I Odd Positive 0 Calibration Unit Tune Register Lane 1" bitfld.word 0x06 0.--5. " RX_SLC_IOP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "LANE1_RX_SLC_IOP1_CTRL,RX Sampler Latch I Odd Positive 1 Calibration Unit Control Register Lane 1" bitfld.word 0x08 15. " RX_SLC_IOP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x08 14. " RX_SLC_IOP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x08 13. " RX_SLC_IOP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x08 12. " RX_SLC_IOP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x08 0.--5. " RX_SLC_IOP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0A "LANE1_RX_SLC_IOP1_OVRD,RX Sampler Latch I Odd Positive 1 Calibration Unit Override Register Lane 1" bitfld.word 0x0A 15. " RX_SLC_IOP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x0A 14. " RX_SLC_IOP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x0A 0.--5. " RX_SLC_IOP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0C "LANE1_RX_SLC_IOP1_START,RX Sampler Latch I Odd Positive 1 Calibration Unit Start Register Lane 1" bitfld.word 0x0C 15. " RX_SLC_IOP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x0C 0.--5. " RX_SLC_IOP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0E "LANE1_RX_SLC_IOP1_TUNE,RX Sampler Latch I Odd Positive 1 Calibration Unit Tune Register Lane 1" bitfld.word 0x0E 0.--5. " RX_SLC_IOP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x10 "LANE1_RX_SLC_QOP0_CTRL,RX Sampler Latch Q Odd Positive 0 Calibration Unit Control Register Lane 1" bitfld.word 0x10 15. " RX_SLC_QOP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x10 14. " RX_SLC_QOP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x10 13. " RX_SLC_QOP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x10 12. " RX_SLC_QOP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x10 0.--5. " RX_SLC_QOP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x12 "LANE1_RX_SLC_QOP0_OVRD,RX Sampler Latch Q Odd Positive 0 Calibration Unit Override Register Lane 1" bitfld.word 0x12 15. " RX_SLC_QOP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x12 14. " RX_SLC_QOP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x12 0.--5. " RX_SLC_QOP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x14 "LANE1_RX_SLC_QOP0_START,RX Sampler Latch Q Odd Positive 0 Calibration Unit Start Register Lane 1" bitfld.word 0x14 15. " RX_SLC_QOP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x14 0.--5. " RX_SLC_QOP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x16 "LANE1_RX_SLC_QOP0_TUNE,RX Sampler Latch Q Odd Positive 0 Calibration Unit Tune Register Lane 1" bitfld.word 0x16 0.--5. " RX_SLC_QOP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x18 "LANE1_RX_SLC_QOP1_CTRL,RX Sampler Latch Q Odd Positive 1 Calibration Unit Control Register Lane 1" bitfld.word 0x18 15. " RX_SLC_QOP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x18 14. " RX_SLC_QOP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x18 13. " RX_SLC_QOP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x18 12. " RX_SLC_QOP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x18 0.--5. " RX_SLC_QOP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x1A "LANE1_RX_SLC_QOP1_OVRD,RX Sampler Latch Q Odd Positive 1 Calibration Unit Override Register Lane 1" bitfld.word 0x1A 15. " RX_SLC_QOP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x1A 14. " RX_SLC_QOP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x1A 0.--5. " RX_SLC_QOP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x1C "LANE1_RX_SLC_QOP1_START,RX Sampler Latch Q Odd Positive 1 Calibration Unit Start Register Lane 1" bitfld.word 0x1C 15. " RX_SLC_QOP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x1C 0.--5. " RX_SLC_QOP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x1E "LANE1_RX_SLC_QOP1_TUNE,RX Sampler Latch Q Odd Positive 1 Calibration Unit Tune Register Lane 1" bitfld.word 0x1E 0.--5. " RX_SLC_QOP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x20 "LANE1_RX_SLC_EOP0_CTRL,RX Sampler Latch E Odd Positive 0 Calibration Unit Control Register Lane 1" bitfld.word 0x20 15. " RX_SLC_EOP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x20 14. " RX_SLC_EOP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x20 13. " RX_SLC_EOP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x20 12. " RX_SLC_EOP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x20 0.--5. " RX_SLC_EOP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x22 "LANE1_RX_SLC_EOP0_OVRD,RX Sampler Latch E Odd Positive 0 Calibration Unit Override Register Lane 1" bitfld.word 0x22 15. " RX_SLC_EOP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x22 14. " RX_SLC_EOP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x22 0.--5. " RX_SLC_EOP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x24 "LANE1_RX_SLC_EOP0_START,RX Sampler Latch E Odd Positive 0 Calibration Unit Start Register Lane 1" bitfld.word 0x24 15. " RX_SLC_EOP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x24 0.--5. " RX_SLC_EOP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x26 "LANE1_RX_SLC_EOP0_TUNE,RX Sampler Latch E Odd Positive 0 Calibration Unit Tune Register Lane 1" bitfld.word 0x26 0.--5. " RX_SLC_EOP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x28 "LANE1_RX_SLC_EOP1_CTRL,RX Sampler Latch E Odd Positive 1 Calibration Unit Control Register Lane 1" bitfld.word 0x28 15. " RX_SLC_EOP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x28 14. " RX_SLC_EOP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x28 13. " RX_SLC_EOP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x28 12. " RX_SLC_EOP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x28 0.--5. " RX_SLC_EOP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x2A "LANE1_RX_SLC_EOP1_OVRD,RX Sampler Latch E Odd Positive 1 Calibration Unit Override Register Lane 1" bitfld.word 0x2A 15. " RX_SLC_EOP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x2A 14. " RX_SLC_EOP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x2A 0.--5. " RX_SLC_EOP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x2C "LANE1_RX_SLC_EOP1_START,RX Sampler Latch E Odd Positive 1 Calibration Unit Start Register Lane 1" bitfld.word 0x2C 15. " RX_SLC_EOP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x2C 0.--5. " RX_SLC_EOP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x2E "LANE1_RX_SLC_EOP1_TUNE,RX Sampler Latch E Odd Positive 1 Calibration Unit Tune Register Lane 1" bitfld.word 0x2E 0.--5. " RX_SLC_EOP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x30 "LANE1_RX_SLC_ION0_CTRL,RX Sampler Latch I Odd Negative 0 Calibration Unit Control Register Lane 1" bitfld.word 0x30 15. " RX_SLC_ION0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x30 14. " RX_SLC_ION0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x30 13. " RX_SLC_ION0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x30 12. " RX_SLC_ION0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x30 0.--5. " RX_SLC_ION0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x32 "LANE1_RX_SLC_ION0_OVRD,RX Sampler Latch I Odd Negative 0 Calibration Unit Override Register Lane 1" bitfld.word 0x32 15. " RX_SLC_ION0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x32 14. " RX_SLC_ION0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x32 0.--5. " RX_SLC_ION0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x34 "LANE1_RX_SLC_ION0_START,RX Sampler Latch I Odd Negative 0 Calibration Unit Start Register Lane 1" bitfld.word 0x34 15. " RX_SLC_ION0_START_15 ,Calibration direction" "0,1" bitfld.word 0x34 0.--5. " RX_SLC_ION0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x36 "LANE1_RX_SLC_ION0_TUNE,RX Sampler Latch I Odd Negative 0 Calibration Unit Tune Register Lane 1" bitfld.word 0x36 0.--5. " RX_SLC_ION0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x38 "LANE1_RX_SLC_ION1_CTRL,RX Sampler Latch I Odd Negative 1 Calibration Unit Control Register Lane 1" bitfld.word 0x38 15. " RX_SLC_ION1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x38 14. " RX_SLC_ION1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x38 13. " RX_SLC_ION1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x38 12. " RX_SLC_ION1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x38 0.--5. " RX_SLC_ION1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x3A "LANE1_RX_SLC_ION1_OVRD,RX Sampler Latch I Odd Negative 1 Calibration Unit Override Register Lane 1" bitfld.word 0x3A 15. " RX_SLC_ION1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x3A 14. " RX_SLC_ION1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x3A 0.--5. " RX_SLC_ION1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x3C "LANE1_RX_SLC_ION1_START,RX Sampler Latch I Odd Negative 1 Calibration Unit Start Register Lane 1" bitfld.word 0x3C 15. " RX_SLC_ION1_START_15 ,Calibration direction" "0,1" bitfld.word 0x3C 0.--5. " RX_SLC_ION1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x3E "LANE1_RX_SLC_ION1_TUNE,RX Sampler Latch I Odd Negative 1 Calibration Unit Tune Register Lane 1" bitfld.word 0x3E 0.--5. " RX_SLC_ION1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x40 "LANE1_RX_SLC_QON0_CTRL,RX Sampler Latch Q Odd Negative 0 Calibration Unit Control Register Lane 1" bitfld.word 0x40 15. " RX_SLC_QON0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x40 14. " RX_SLC_QON0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x40 13. " RX_SLC_QON0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x40 12. " RX_SLC_QON0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x40 0.--5. " RX_SLC_QON0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x42 "LANE1_RX_SLC_QON0_OVRD,RX Sampler Latch Q Odd Negative 0 Calibration Unit Override Register Lane 1" bitfld.word 0x42 15. " RX_SLC_QON0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x42 14. " RX_SLC_QON0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x42 0.--5. " RX_SLC_QON0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x44 "LANE1_RX_SLC_QON0_START,RX Sampler Latch Q Odd Negative 0 Calibration Unit Start Register Lane 1" bitfld.word 0x44 15. " RX_SLC_QON0_START_15 ,Calibration direction" "0,1" bitfld.word 0x44 0.--5. " RX_SLC_QON0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x46 "LANE1_RX_SLC_QON0_TUNE,RX Sampler Latch Q Odd Negative 0 Calibration Unit Tune Register Lane 1" bitfld.word 0x46 0.--5. " RX_SLC_QON0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x48 "LANE1_RX_SLC_QON1_CTRL,RX Sampler Latch Q Odd Negative 1 Calibration Unit Control Register Lane 1" bitfld.word 0x48 15. " RX_SLC_QON1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x48 14. " RX_SLC_QON1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x48 13. " RX_SLC_QON1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x48 12. " RX_SLC_QON1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x48 0.--5. " RX_SLC_QON1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x4A "LANE1_RX_SLC_QON1_OVRD,RX Sampler Latch Q Odd Negative 1 Calibration Unit Override Register Lane 1" bitfld.word 0x4A 15. " RX_SLC_QON1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x4A 14. " RX_SLC_QON1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x4A 0.--5. " RX_SLC_QON1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x4C "LANE1_RX_SLC_QON1_START,RX Sampler Latch Q Odd Negative 1 Calibration Unit Start Register Lane 1" bitfld.word 0x4C 15. " RX_SLC_QON1_START_15 ,Calibration direction" "0,1" bitfld.word 0x4C 0.--5. " RX_SLC_QON1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x4E "LANE1_RX_SLC_QON1_TUNE,RX Sampler Latch Q Odd Negative 1 Calibration Unit Tune Register Lane 1" bitfld.word 0x4E 0.--5. " RX_SLC_QON1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x50 "LANE1_RX_SLC_EON0_CTRL,RX Sampler Latch E Odd Negative 0 Calibration Unit Control Register Lane 1" bitfld.word 0x50 15. " RX_SLC_EON0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x50 14. " RX_SLC_EON0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x50 13. " RX_SLC_EON0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x50 12. " RX_SLC_EON0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x50 0.--5. " RX_SLC_EON0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x52 "LANE1_RX_SLC_EON0_OVRD,RX Sampler Latch E Odd Negative 0 Calibration Unit Override Register Lane 1" bitfld.word 0x52 15. " RX_SLC_EON0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x52 14. " RX_SLC_EON0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x52 0.--5. " RX_SLC_EON0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x54 "LANE1_RX_SLC_EON0_START,RX Sampler Latch E Odd Negative 0 Calibration Unit Start Register Lane 1" bitfld.word 0x54 15. " RX_SLC_EON0_START_15 ,Calibration direction" "0,1" bitfld.word 0x54 0.--5. " RX_SLC_EON0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x56 "LANE1_RX_SLC_EON0_TUNE,RX Sampler Latch E Odd Negative 0 Calibration Unit Tune Register Lane 1" bitfld.word 0x56 0.--5. " RX_SLC_EON0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x58 "LANE1_RX_SLC_EON1_CTRL,RX Sampler Latch E Odd Negative 1 Calibration Unit Control Register Lane 1" bitfld.word 0x58 15. " RX_SLC_EON1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x58 14. " RX_SLC_EON1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x58 13. " RX_SLC_EON1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x58 12. " RX_SLC_EON1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x58 0.--5. " RX_SLC_EON1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x5A "LANE1_RX_SLC_EON1_OVRD,RX Sampler Latch E Odd Negative 1 Calibration Unit Override Register Lane 1" bitfld.word 0x5A 15. " RX_SLC_EON1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x5A 14. " RX_SLC_EON1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x5A 0.--5. " RX_SLC_EON1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x5C "LANE1_RX_SLC_EON1_START,RX Sampler Latch E Odd Negative 1 Calibration Unit Start Register Lane 1" bitfld.word 0x5C 15. " RX_SLC_EON1_START_15 ,Calibration direction" "0,1" bitfld.word 0x5C 0.--5. " RX_SLC_EON1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x5E "LANE1_RX_SLC_EON1_TUNE,RX Sampler Latch E Odd Negative 1 Calibration Unit Tune Register Lane 1" bitfld.word 0x5E 0.--5. " RX_SLC_EON1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x60 "LANE1_RX_SLC_IEP0_CTRL,RX Sampler Latch I Even Positive 0 Calibration Unit Control Register Lane 1" bitfld.word 0x60 15. " RX_SLC_IEP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x60 14. " RX_SLC_IEP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x60 13. " RX_SLC_IEP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x60 12. " RX_SLC_IEP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x60 0.--5. " RX_SLC_IEP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x62 "LANE1_RX_SLC_IEP0_OVRD,RX Sampler Latch I Even Positive 0 Calibration Unit Override Register Lane 1" bitfld.word 0x62 15. " RX_SLC_IEP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x62 14. " RX_SLC_IEP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x62 0.--5. " RX_SLC_IEP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x64 "LANE1_RX_SLC_IEP0_START,RX Sampler Latch I Even Positive 0 Calibration Unit Start Register Lane 1" bitfld.word 0x64 15. " RX_SLC_IEP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x64 0.--5. " RX_SLC_IEP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x66 "LANE1_RX_SLC_IEP0_TUNE,RX Sampler Latch I Even Positive 0 Calibration Unit Tune Register Lane 1" bitfld.word 0x66 0.--5. " RX_SLC_IEP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x68 "LANE1_RX_SLC_IEP1_CTRL,RX Sampler Latch I Even Positive 1 Calibration Unit Control Register Lane 1" bitfld.word 0x68 15. " RX_SLC_IEP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x68 14. " RX_SLC_IEP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x68 13. " RX_SLC_IEP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x68 12. " RX_SLC_IEP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x68 0.--5. " RX_SLC_IEP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x6A "LANE1_RX_SLC_IEP1_OVRD,RX Sampler Latch I Even Positive 1 Calibration Unit Override Register Lane 1" bitfld.word 0x6A 15. " RX_SLC_IEP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x6A 14. " RX_SLC_IEP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x6A 0.--5. " RX_SLC_IEP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x6C "LANE1_RX_SLC_IEP1_START,RX Sampler Latch I Even Positive 1 Calibration Unit Start Register Lane 1" bitfld.word 0x6C 15. " RX_SLC_IEP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x6C 0.--5. " RX_SLC_IEP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x6E "LANE1_RX_SLC_IEP1_TUNE,RX Sampler Latch I Even Positive 1 Calibration Unit Tune Register Lane 1" bitfld.word 0x6E 0.--5. " RX_SLC_IEP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x70 "LANE1_RX_SLC_QEP0_CTRL,RX Sampler Latch Q Even Positive 0 Calibration Unit Control Register Lane 1" bitfld.word 0x70 15. " RX_SLC_QEP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x70 14. " RX_SLC_QEP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x70 13. " RX_SLC_QEP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x70 12. " RX_SLC_QEP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x70 0.--5. " RX_SLC_QEP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x72 "LANE1_RX_SLC_QEP0_OVRD,RX Sampler Latch Q Even Positive 0 Calibration Unit Override Register Lane 1" bitfld.word 0x72 15. " RX_SLC_QEP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x72 14. " RX_SLC_QEP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x72 0.--5. " RX_SLC_QEP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x74 "LANE1_RX_SLC_QEP0_START,RX Sampler Latch Q Even Positive 0 Calibration Unit Start Register Lane 1" bitfld.word 0x74 15. " RX_SLC_QEP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x74 0.--5. " RX_SLC_QEP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x76 "LANE1_RX_SLC_QEP0_TUNE,RX Sampler Latch Q Even Positive 0 Calibration Unit Tune Register Lane 1" bitfld.word 0x76 0.--5. " RX_SLC_QEP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x78 "LANE1_RX_SLC_QEP1_CTRL,RX Sampler Latch Q Even Positive 1 Calibration Unit Control Register Lane 1" bitfld.word 0x78 15. " RX_SLC_QEP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x78 14. " RX_SLC_QEP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x78 13. " RX_SLC_QEP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x78 12. " RX_SLC_QEP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x78 0.--5. " RX_SLC_QEP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x7A "LANE1_RX_SLC_QEP1_OVRD,RX Sampler Latch Q Even Positive 1 Calibration Unit Override Register Lane 1" bitfld.word 0x7A 15. " RX_SLC_QEP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x7A 14. " RX_SLC_QEP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x7A 0.--5. " RX_SLC_QEP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x7C "LANE1_RX_SLC_QEP1_START,RX Sampler Latch Q Even Positive 1 Calibration Unit Start Register Lane 1" bitfld.word 0x7C 15. " RX_SLC_QEP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x7C 0.--5. " RX_SLC_QEP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x7E "LANE1_RX_SLC_QEP1_TUNE,RX Sampler Latch Q Even Positive 1 Calibration Unit Tune Register Lane1" bitfld.word 0x7E 0.--5. " RX_SLC_QEP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x80 "LANE1_RX_SLC_EEP0_CTRL,RX Sampler Latch E Even Positive 0 Calibration Unit Control Register Lane 1" bitfld.word 0x80 15. " RX_SLC_EEP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x80 14. " RX_SLC_EEP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x80 13. " RX_SLC_EEP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x80 12. " RX_SLC_EEP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x80 0.--5. " RX_SLC_EEP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x82 "LANE1_RX_SLC_EEP0_OVRD,RX Sampler Latch E Even Positive 0 Calibration Unit Override Register Lane 1" bitfld.word 0x82 15. " RX_SLC_EEP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x82 14. " RX_SLC_EEP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x82 0.--5. " RX_SLC_EEP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x84 "LANE1_RX_SLC_EEP0_START,RX Sampler Latch E Even Positive 0 Calibration Unit Start Register Lane 1" bitfld.word 0x84 15. " RX_SLC_EEP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x84 0.--5. " RX_SLC_EEP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x86 "LANE1_RX_SLC_EEP0_TUNE,RX Sampler Latch E Even Positive 0 Calibration Unit Tune Register Lane1" bitfld.word 0x86 0.--5. " RX_SLC_EEP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x88 "LANE1_RX_SLC_EEP1_CTRL,RX Sampler Latch E Even Positive 1 Calibration Unit Control Register Lane 1" bitfld.word 0x88 15. " RX_SLC_EEP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x88 14. " RX_SLC_EEP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x88 13. " RX_SLC_EEP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x88 12. " RX_SLC_EEP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x88 0.--5. " RX_SLC_EEP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x8A "LANE1_RX_SLC_EEP1_OVRD,RX Sampler Latch E Even Positive 1 Calibration Unit Override Register Lane 1" bitfld.word 0x8A 15. " RX_SLC_EEP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x8A 14. " RX_SLC_EEP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x8A 0.--5. " RX_SLC_EEP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x8C "LANE1_RX_SLC_EEP1_START,RX Sampler Latch E Even Positive 1 Calibration Unit Start Register Lane 1" bitfld.word 0x8C 15. " RX_SLC_EEP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x8C 0.--5. " RX_SLC_EEP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x8E "LANE1_RX_SLC_EEP1_TUNE,RX Sampler Latch E Even Positive 1 Calibration Unit Tune Register Lane 1" bitfld.word 0x8E 0.--5. " RX_SLC_EEP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x90 "LANE1_RX_SLC_IEN0_CTRL,RX Sampler Latch I Even Negative 0 Calibration Unit Control Register Lane 1" bitfld.word 0x90 15. " RX_SLC_IEN0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x90 14. " RX_SLC_IEN0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x90 13. " RX_SLC_IEN0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x90 12. " RX_SLC_IEN0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x90 0.--5. " RX_SLC_IEN0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x92 "LANE1_RX_SLC_IEN0_OVRD,RX Sampler Latch I Even Negative 0 Calibration Unit Override Register Lane 1" bitfld.word 0x92 15. " RX_SLC_IEN0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x92 14. " RX_SLC_IEN0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x92 0.--5. " RX_SLC_IEN0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x94 "LANE1_RX_SLC_IEN0_START,RX Sampler Latch I Even Negative 0 Calibration Unit Start Register Lane 1" bitfld.word 0x94 15. " RX_SLC_IEN0_START_15 ,Calibration direction" "0,1" bitfld.word 0x94 0.--5. " RX_SLC_IEN0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x96 "LANE1_RX_SLC_IEN0_TUNE,RX Sampler Latch I Even Negative 0 Calibration Unit Tune Register Lane 1" bitfld.word 0x96 0.--5. " RX_SLC_IEN0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x98 "LANE1_RX_SLC_IEN1_CTRL,RX Sampler Latch I Even Negative 1 Calibration Unit Control Register Lane 1" bitfld.word 0x98 15. " RX_SLC_IEN1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x98 14. " RX_SLC_IEN1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x98 13. " RX_SLC_IEN1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x98 12. " RX_SLC_IEN1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x98 0.--5. " RX_SLC_IEN1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x9A "LANE1_RX_SLC_IEN1_OVRD,RX Sampler Latch I Even Negative 1 Calibration Unit Override Register Lane 1" bitfld.word 0x9A 15. " RX_SLC_IEN1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x9A 14. " RX_SLC_IEN1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x9A 0.--5. " RX_SLC_IEN1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x9C "LANE1_RX_SLC_IEN1_START,RX Sampler Latch I Even Negative 1 Calibration Unit Start Register Lane 1" bitfld.word 0x9C 15. " RX_SLC_IEN1_START_15 ,Calibration direction" "0,1" bitfld.word 0x9C 0.--5. " RX_SLC_IEN1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x9E "LANE1_RX_SLC_IEN1_TUNE,RX Sampler Latch I Even Negative 1 Calibration Unit Tune Register Lane 1" bitfld.word 0x9E 0.--5. " RX_SLC_IEN1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA0 "LANE1_RX_SLC_QEN0_CTRL,RX Sampler Latch Q Even Negative 0 Calibration Unit Control Register Lane 1" bitfld.word 0xA0 15. " RX_SLC_QEN0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xA0 14. " RX_SLC_QEN0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xA0 13. " RX_SLC_QEN0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xA0 12. " RX_SLC_QEN0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xA0 0.--5. " RX_SLC_QEN0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA2 "LANE1_RX_SLC_QEN0_OVRD,RX Sampler Latch Q Even Negative 0 Calibration Unit Override Register Lane 1" bitfld.word 0xA2 15. " RX_SLC_QEN0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xA2 14. " RX_SLC_QEN0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xA2 0.--5. " RX_SLC_QEN0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA4 "LANE1_RX_SLC_QEN0_START,RX Sampler Latch Q Even Negative 0 Calibration Unit Start Register Lane 1" bitfld.word 0xA4 15. " RX_SLC_QEN0_START_15 ,Calibration direction" "0,1" bitfld.word 0xA4 0.--5. " RX_SLC_QEN0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA6 "LANE1_RX_SLC_QEN0_TUNE,RX Sampler Latch Q Even Negative 0 Calibration Unit Tune Register Lane 1" bitfld.word 0xA6 0.--5. " RX_SLC_QEN0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA8 "LANE1_RX_SLC_QEN1_CTRL,RX Sampler Latch Q Even Negative 1 Calibration Unit Control Register Lane 1" bitfld.word 0xA8 15. " RX_SLC_QEN1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xA8 14. " RX_SLC_QEN1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xA8 13. " RX_SLC_QEN1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xA8 12. " RX_SLC_QEN1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xA8 0.--5. " RX_SLC_QEN1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xAA "LANE1_RX_SLC_QEN1_OVRD,RX Sampler Latch Q Even Negative 1 Calibration Unit Override Register Lane 1" bitfld.word 0xAA 15. " RX_SLC_QEN1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xAA 14. " RX_SLC_QEN1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xAA 0.--5. " RX_SLC_QEN1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xAC "LANE1_RX_SLC_QEN1_START,RX Sampler Latch Q Even Negative 1 Calibration Unit Start Register Lane 1" bitfld.word 0xAC 15. " RX_SLC_QEN1_START_15 ,Calibration direction" "0,1" bitfld.word 0xAC 0.--5. " RX_SLC_QEN1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xAE "LANE1_RX_SLC_QEN1_TUNE,RX Sampler Latch Q Even Negative 1 Calibration Unit Tune Register Lane 1" bitfld.word 0xAE 0.--5. " RX_SLC_QEN1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB0 "LANE1_RX_SLC_EEN0_CTRL,RX Sampler Latch E Even Negative 0 Calibration Unit Control Register Lane 1" bitfld.word 0xB0 15. " RX_SLC_EEN0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xB0 14. " RX_SLC_EEN0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xB0 13. " RX_SLC_EEN0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xB0 12. " RX_SLC_EEN0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xB0 0.--5. " RX_SLC_EEN0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB2 "LANE1_RX_SLC_EEN0_OVRD,RX Sampler Latch E Even Negative 0 Calibration Unit Override Register Lane 1" bitfld.word 0xB2 15. " RX_SLC_EEN0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xB2 14. " RX_SLC_EEN0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xB2 0.--5. " RX_SLC_EEN0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB4 "LANE1_RX_SLC_EEN0_START,RX Sampler Latch E Even Negative 0 Calibration Unit Start Register Lane 1" bitfld.word 0xB4 15. " RX_SLC_EEN0_START_15 ,Calibration direction" "0,1" bitfld.word 0xB4 0.--5. " RX_SLC_EEN0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB6 "LANE1_RX_SLC_EEN0_TUNE,RX Sampler Latch E Even Negative 0 Calibration Unit Tune Register 1" bitfld.word 0xB6 0.--5. " RX_SLC_EEN0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB8 "LANE1_RX_SLC_EEN1_CTRL,RX Sampler Latch E Even Negative 1 Calibration Unit Control Register Lane 1" bitfld.word 0xB8 15. " RX_SLC_EEN1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xB8 14. " RX_SLC_EEN1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xB8 13. " RX_SLC_EEN1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xB8 12. " RX_SLC_EEN1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xB8 0.--5. " RX_SLC_EEN1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xBA "LANE1_RX_SLC_EEN1_OVRD,RX Sampler Latch E Even Negative 1 Calibration Unit Override Register Lane 1" bitfld.word 0xBA 15. " RX_SLC_EEN1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xBA 14. " RX_SLC_EEN1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xBA 0.--5. " RX_SLC_EEN1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xBC "LANE1_RX_SLC_EEN1_START,RX Sampler Latch E Even Negative 1 Calibration Unit Start Register Lane 1" bitfld.word 0xBC 15. " RX_SLC_EEN1_START_15 ,Calibration direction" "0,1" bitfld.word 0xBC 0.--5. " RX_SLC_EEN1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xBE "LANE1_RX_SLC_EEN1_TUNE,RX Sampler Latch E Even Negative 1 Calibration Unit Tune Register Lane 1" bitfld.word 0xBE 0.--5. " RX_SLC_EEN1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xC0 "LANE1_RX_REE_U3GCSM_CTRL,REE USB 3 General Control State Machine Control Register Lane 1" bitfld.word 0xC0 1. " RX_REE_U3GCSM_CTRL_1 ,Force run equalization" "Not forced,Forced" bitfld.word 0xC0 0. " RX_REE_U3GCSM_CTRL_0 ,General control state machine function enable" "Disabled,Enabled" line.word 0xC2 "LANE1_RX_REE_U3GCSM_EQENM_PH1,REE USB 3 General Control State Machine Phase 1 Equalization Enable Mask Register Lane 1" bitfld.word 0xC2 14. " RX_REE_U3GCSM_EQENM_PH1_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0xC2 9. " RX_REE_U3GCSM_EQENM_PH1_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0xC2 8. " RX_REE_U3GCSM_EQENM_PH1_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0xC2 7. " RX_REE_U3GCSM_EQENM_PH1_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0xC2 6. " RX_REE_U3GCSM_EQENM_PH1_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0xC2 5. " RX_REE_U3GCSM_EQENM_PH1_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0xC2 2. " RX_REE_U3GCSM_EQENM_PH1_2 ,RX tap 3" "0,1" bitfld.word 0xC2 1. " RX_REE_U3GCSM_EQENM_PH1_1 ,RX tap 2" "0,1" textline " " bitfld.word 0xC2 0. " RX_REE_U3GCSM_EQENM_PH1_0 ,RX tap 1" "0,1" line.word 0xC4 "LANE1_RX_REE_U3GCSM_EQENM_PH2,REE USB 3 General Control State Machine Phase 2 Equalization Enable Mask Register Lane 1" bitfld.word 0xC4 14. " RX_REE_U3GCSM_EQENM_PH2_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0xC4 9. " RX_REE_U3GCSM_EQENM_PH2_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0xC4 8. " RX_REE_U3GCSM_EQENM_PH2_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0xC4 7. " RX_REE_U3GCSM_EQENM_PH2_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0xC4 6. " RX_REE_U3GCSM_EQENM_PH2_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0xC4 5. " RX_REE_U3GCSM_EQENM_PH2_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0xC4 2. " RX_REE_U3GCSM_EQENM_PH2_2 ,RX tap 3" "0,1" bitfld.word 0xC4 1. " RX_REE_U3GCSM_EQENM_PH2_1 ,RX tap 2" "0,1" textline " " bitfld.word 0xC4 0. " RX_REE_U3GCSM_EQENM_PH2_0 ,RX tap 1" "0,1" line.word 0xC6 "LANE1_RX_REE_U3GCSM_START_TMR,REE USB 3 General Control State Machine Start Timer Value Register Lane 1" line.word 0xC8 "LANE1_RX_REE_U3GCSM_RUN_PH1_TMR,REE USB 3 General Control State Machine Run Phase 1 Timer Value Register Lane 1" line.word 0xCA "LANE1_RX_REE_U3GCSM_RUN_PH2_TMR,REE USB 3 General Control State Machine Run Phase 2 Timer Value Register Lane 1" group.word (0x8400+0xD0)++0x0B line.word 0x00 "LANE1_RX_REE_G2GCSM_CTRL,REE PCIe Gen 2 General Control State Machine Control Register Lane 1" bitfld.word 0x00 1. " RX_REE_G2GCSM_CTRL_1 ,Force run equalization" "Not forced,Forced" bitfld.word 0x00 0. " RX_REE_G2GCSM_CTRL_0 ,General control state machine function enable" "Disabled,Enabled" line.word 0x02 "LANE1_RX_REE_G2GCSM_EQENM_PH1,REE PCIe Gen 2 General Control State Machine Phase 1 Equalization Enable Mask Register Lane 1" bitfld.word 0x02 14. " RX_REE_G2GCSM_EQENM_PH1_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x02 9. " RX_REE_G2GCSM_EQENM_PH1_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x02 8. " RX_REE_G2GCSM_EQENM_PH1_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x02 7. " RX_REE_G2GCSM_EQENM_PH1_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x02 6. " RX_REE_G2GCSM_EQENM_PH1_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x02 5. " RX_REE_G2GCSM_EQENM_PH1_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x02 2. " RX_REE_G2GCSM_EQENM_PH1_2 ,RX tap 3" "0,1" bitfld.word 0x02 1. " RX_REE_G2GCSM_EQENM_PH1_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x02 0. " RX_REE_G2GCSM_EQENM_PH1_0 ,RX tap 1" "0,1" line.word 0x04 "LANE1_RX_REE_G2GCSM_EQENM_PH2,REE USB 2 General Control State Machine Phase 2 Equalization Enable Mask Register Lane 1" bitfld.word 0x04 14. " RX_REE_G2GCSM_EQENM_PH2_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x04 9. " RX_REE_G2GCSM_EQENM_PH2_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x04 8. " RX_REE_G2GCSM_EQENM_PH2_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x04 7. " RX_REE_G2GCSM_EQENM_PH2_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x04 6. " RX_REE_G2GCSM_EQENM_PH2_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x04 5. " RX_REE_G2GCSM_EQENM_PH2_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x04 2. " RX_REE_G2GCSM_EQENM_PH2_2 ,RX tap 3" "0,1" bitfld.word 0x04 1. " RX_REE_G2GCSM_EQENM_PH2_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x04 0. " RX_REE_G2GCSM_EQENM_PH2_0 ,RX tap 1" "0,1" line.word 0x06 "LANE1_RX_REE_G2GCSM_START_TMR,REE PCIe Gen 2 General Control State Machine Start Timer Value Register Lane 1" line.word 0x08 "LANE1_RX_REE_G2GCSM_RUN_PH1_TMR,REE PCIe Gen 2 General Control State Machine Run Phase 1 Timer Value Register Lane 1" line.word 0x0A "LANE1_RX_REE_G2GCSM_RUN_PH2_TMR,REE PCIe Gen 2 General Control State Machine Run Phase 2 Timer Value Register Lane 1" group.word (0x8400+0xF0)++0x0B line.word 0x00 "LANE1_RX_REE_PERGCSM_CTRL,REE Periodic General Control State Machine Control Register Lane 1" bitfld.word 0x00 1. " RX_REE_PERGCSM_CTRL_1 ,Force run equalization" "Not forced,Forced" bitfld.word 0x00 0. " RX_REE_PERGCSM_CTRL_0 ,General control state machine function enable" "Disabled,Enabled" line.word 0x02 "LANE1_RX_REE_PERGCSM_EQENM_PH1,REE Periodic General Control State Machine Phase 1 Equalization Enable Mask Register Lane 1" bitfld.word 0x02 14. " RX_REE_PERGCSM_EQENM_PH1_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x02 9. " RX_REE_PERGCSM_EQENM_PH1_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x02 8. " RX_REE_PERGCSM_EQENM_PH1_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x02 7. " RX_REE_PERGCSM_EQENM_PH1_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x02 6. " RX_REE_PERGCSM_EQENM_PH1_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x02 5. " RX_REE_PERGCSM_EQENM_PH1_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x02 2. " RX_REE_PERGCSM_EQENM_PH1_2 ,RX tap 3" "0,1" bitfld.word 0x02 1. " RX_REE_PERGCSM_EQENM_PH1_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x02 0. " RX_REE_PERGCSM_EQENM_PH1_0 ,RX tap 1" "0,1" line.word 0x04 "LANE1_RX_REE_PERGCSM_EQENM_PH2,REE Periodic General Control State Machine Phase 2 Equalization Enable Mask Register Lane 1" bitfld.word 0x04 14. " RX_REE_PERGCSM_EQENM_PH2_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x04 9. " RX_REE_PERGCSM_EQENM_PH2_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x04 8. " RX_REE_PERGCSM_EQENM_PH2_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x04 7. " RX_REE_PERGCSM_EQENM_PH2_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x04 6. " RX_REE_PERGCSM_EQENM_PH2_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x04 5. " RX_REE_PERGCSM_EQENM_PH2_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x04 2. " RX_REE_PERGCSM_EQENM_PH2_2 ,RX tap 3" "0,1" bitfld.word 0x04 1. " RX_REE_PERGCSM_EQENM_PH2_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x04 0. " RX_REE_PERGCSM_EQENM_PH2_0 ,RX tap 1" "0,1" line.word 0x06 "LANE1_RX_REE_PERGCSM_START_TMR,REE Periodic General Control State Machine Start Timer Value Register Lane 1" line.word 0x08 "LANE1_RX_REE_PERGCSM_RUN_PH1_TMR,REE Periodic General Control State Machine Run Phase 1 Timer Value Register Lane 1" line.word 0x0A "LANE1_RX_REE_PERGCSM_RUN_PH2_TMR,REE Periodic General Control State Machine Run Phase 2 Timer Value Register Lane 1" group.word (0x8400+0x100)++0x05 line.word 0x00 "LANE1_RX_REE_TAP1_CTRL,REE Tap 1 Control Register Lane 1" bitfld.word 0x00 11. " RX_REE_TAP1_CTRL_11 ,Tap coefficient combinational logic zero crossing enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_REE_TAP1_CTRL_10 ,Tap coefficient combinational logic non zero crossing enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_REE_TAP1_CTRL_9 ,Tap coefficient combinational logic bit 0 only enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_REE_TAP1_CTRL_8 ,Receiver DFE tap coefficient disable" "No,Yes" textline " " bitfld.word 0x00 4.--6. " RX_REE_TAP1_CTRL_6_4 ,Tap integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_TAP1_CTRL_3_0 ,Tap sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE1_RX_REE_TAP1_OVRD,REE Tap 1 Override Register Lane 1" bitfld.word 0x02 7. " RX_REE_TAP1_OVRD_7 ,Tap override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_TAP1_OVRD_5_0 ,Tap override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE1_RX_REE_TAP1_DIAG,REE Tap 1 Diagnostics Register Lane 1" bitfld.word 0x04 14. " RX_REE_TAP1_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_TAP1_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_TAP1_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_TAP1_DIAG_5_0 ,Current tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8400+0x108)++0x05 line.word 0x00 "LANE1_RX_REE_TAP2_CTRL,REE Tap 2 Control Register Lane 1" bitfld.word 0x00 11. " RX_REE_TAP2_CTRL_11 ,Tap coefficient combinational logic zero crossing enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_REE_TAP2_CTRL_10 ,Tap coefficient combinational logic non zero crossing enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_REE_TAP2_CTRL_9 ,Tap coefficient combinational logic bit 0 only enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_REE_TAP2_CTRL_8 ,Receiver DFE tap coefficient disable" "No,Yes" textline " " bitfld.word 0x00 4.--6. " RX_REE_TAP2_CTRL_6_4 ,Tap integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_TAP2_CTRL_3_0 ,Tap sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE1_RX_REE_TAP2_OVRD,REE Tap 2 Override Register Lane 1" bitfld.word 0x02 7. " RX_REE_TAP2_OVRD_7 ,Tap override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_TAP2_OVRD_5_0 ,Tap override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE1_RX_REE_TAP2_DIAG,REE Tap 2 Diagnostics Register Lane 1" bitfld.word 0x04 14. " RX_REE_TAP2_DIAG_14 ,Voter override neg" "No override,Override" bitfld.word 0x04 13. " RX_REE_TAP2_DIAG_13 ,Voter override pos" "0,1" textline " " bitfld.word 0x04 12. " RX_REE_TAP2_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_TAP2_DIAG_5_0 ,Current tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8400+0x110)++0x05 line.word 0x00 "LANE1_RX_REE_TAP3_CTRL,REE Tap 3 Control Register Lane 1" bitfld.word 0x00 11. " RX_REE_TAP3_CTRL_11 ,Tap coefficient combinational logic zero crossing enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_REE_TAP3_CTRL_10 ,Tap coefficient combinational logic non zero crossing enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_REE_TAP3_CTRL_9 ,Tap coefficient combinational logic bit 0 only enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_REE_TAP3_CTRL_8 ,Receiver DFE tap coefficient disable" "No,Yes" textline " " bitfld.word 0x00 4.--6. " RX_REE_TAP3_CTRL_6_4 ,Tap integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_TAP3_CTRL_3_0 ,Tap sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE1_RX_REE_TAP3_OVRD,REE Tap 3 Override Register Lane 1" bitfld.word 0x02 7. " RX_REE_TAP3_OVRD_7 ,Tap override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_TAP3_OVRD_5_0 ,Tap override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE1_RX_REE_TAP3_DIAG,REE Tap 3 Diagnostics Register Lane 1" bitfld.word 0x04 14. " RX_REE_TAP3_DIAG_14 ,Voter override neg" "No override,Override" bitfld.word 0x04 13. " RX_REE_TAP3_DIAG_13 ,Voter override pos" "0,1" textline " " bitfld.word 0x04 12. " RX_REE_TAP3_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_TAP3_DIAG_5_0 ,Current tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8400+0x128)++0x01 line.word 0x00 "LANE1_RX_REE_ANAENSM_DEL_TMR,REE Analog Enable Control State Machine Delay Timer Value Register Lane 1" group.word (0x8400+0x130)++0x0D line.word 0x00 "LANE1_RX_REE_PEAK_CTRL,REE Peaking Amp Control Register Lane 1" bitfld.word 0x00 11. " RX_REE_PEAK_CTRL_11 ,Peaking amp feedback path enable" "Disabled,Enabled" bitfld.word 0x00 8.--10. " RX_REE_PEAK_CTRL_10_8 ,Peaking amp feedback scaler value" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 4.--6. " RX_REE_PEAK_CTRL_6_4 ,Peaking amp integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_PEAK_CTRL_3_0 ,Peaking amp sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE1_RX_REE_PEAK_CODE_CTRL,REE Peaking Amp Code Control Register Lane 1" bitfld.word 0x02 8.--13. " RX_REE_PEAK_CODE_CTRL_13_8 ,Peaking amp code maximum value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x02 0.--5. " RX_REE_PEAK_CODE_CTRL_5_0 ,Peaking amp initial code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE1_RX_REE_PEAK_UTHR,REE Peaking Amp Upper Threshold Register Lane 1" hexmask.word 0x04 0.--8. 1. " RX_REE_PEAK_UTHR_8_0 ,Peaking amp algorithm upper threshold" line.word 0x06 "LANE1_RX_REE_PEAK_LTHR,REE Peaking Amp Lower Threshold Register Lane 1" hexmask.word 0x06 0.--8. 1. " RX_REE_PEAK_LTHR_8_0 ,Peaking amp algorithm lower threshold" line.word 0x08 "LANE1_RX_REE_PEAK_IOVRD,REE Peaking Amp Input Override Register Lane 1" bitfld.word 0x08 15. " RX_REE_PEAK_IOVRD_15 ,Peaking amp tap accumulator input override enable" "Disabled,Enabled" hexmask.word.byte 0x08 0.--7. 1. " RX_REE_PEAK_IOVRD_7_0 ,Peaking amp tap accumulator input override" line.word 0x0A "LANE1_RX_REE_PEAK_COVRD,REE Peaking Amp Code Override Register Lane 1" bitfld.word 0x0A 15. " RX_REE_PEAK_COVRD_15 ,Peaking amp code override enable" "Disabled,Enabled" bitfld.word 0x0A 0.--5. " RX_REE_PEAK_COVRD_5_0 ,Peaking amp code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0C "LANE1_RX_REE_PEAK_DIAG,REE Peaking Amp Diagnostics Register Lane 1" bitfld.word 0x0C 14. " RX_REE_PEAK_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x0C 13. " RX_REE_PEAK_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x0C 12. " RX_REE_PEAK_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x0C 0.--5. " RX_REE_TAP3_DIAG_5_0 ,Current peaking amp integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8400+0x140)++0x07 line.word 0x00 "LANE1_RX_REE_ATTEN_CTRL,REE Attenuation Control Register Lane 1" bitfld.word 0x00 0.--4. " RX_REE_ATTEN_CTRL_4_0 ,Receiver DFE attenuation maximum value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x02 "LANE1_RX_REE_ATTEN_THR,REE Attenuation Threshold Register Lane 1" bitfld.word 0x02 8.--12. " RX_REE_ATTEN_THR_12_8 ,Attenuation high threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--4. " RX_REE_ATTEN_THR_4_0 ,Attenuation low threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE1_RX_REE_ATTEN_CNT,REE Attenuation Counter Register Lane 1" line.word 0x06 "LANE1_RX_REE_ATTEN_OVRD,REE Attenuation Override Register Lane 1" bitfld.word 0x06 8. " RX_REE_ATTEN_OVRD_8 ,Attenuation override enable" "Disabled,Enabled" bitfld.word 0x06 0.--4. " RX_REE_ATTEN_OVRD_4_0 ,Attenuation override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word (0x8400+0x148)++0x01 line.word 0x00 "LANE1_RX_REE_ATTEN_DIAG,REE Attenuation Diagnostics Register Lane 1" bitfld.word 0x00 0.--4. " RX_REE_ATTEN_DIAG_4_0 ,Current attenuation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (0x8400+0x150)++0x05 line.word 0x00 "LANE1_RX_REE_LFEQ_CTRL,REE Low Frequency Equalizer Control Register Lane 1" bitfld.word 0x00 8. " RX_REE_LFEQ_CTRL_8 ,Receiver DFE coefficient disable" "No,Yes" bitfld.word 0x00 4.--6. " RX_REE_LFEQ_CTRL_6_4 ,Integrator accumulator scaler value" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 0.--3. " RX_REE_LFEQ_CTRL_3_0 ,Sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE1_RX_REE_LFEQ_OVRD,REE Low Frequency Equalizer Override Register Lane 1" bitfld.word 0x02 7. " RX_REE_LFEQ_OVRD_7 ,Override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_LFEQ_OVRD_5_0 ,Override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE1_RX_REE_LFEQ_DIAG,REE Low Frequency Equalizer Diagnostics Register Lane 1" bitfld.word 0x04 14. " RX_REE_LFEQ_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_LFEQ_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_LFEQ_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_LFEQ_DIAG_5_0 ,Current integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8400+0x158)++0x05 line.word 0x00 "LANE1_RX_REE_VGA_GAIN_CTRL,REE VGA Gain Control Register Lane 1" bitfld.word 0x00 8.--12. " RX_REE_VGA_GAIN_CTRL_12_8 ,VGA gain max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 4.--6. " RX_REE_VGA_GAIN_CTRL_6_4 ,VGA gain integrator accumulator scaler value" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 0.--3. " RX_REE_VGA_GAIN_CTRL_3_0 ,VGA gain sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE1_RX_REE_VGA_GAIN_OVRD,REE VGA Gain Override Register Lane 1" bitfld.word 0x02 15. " RX_REE_VGA_GAIN_OVRD_15 ,VGA gain target adjust override enable" "Disabled,Enabled" bitfld.word 0x02 8.--12. " RX_REE_VGA_GAIN_OVRD_12_8 ,VGA gain target adjust override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x02 7. " RX_REE_VGA_GAIN_OVRD_7 ,VGA gain override enable" "Disabled,Enabled" bitfld.word 0x02 0.--4. " RX_REE_VGA_GAIN_OVRD_4_0 ,VGA gain override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE1_RX_REE_VGA_GAIN_DIAG,REE VGA Gain Diagnostics Register Lane 1" bitfld.word 0x04 14. " RX_REE_VGA_GAIN_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_VGA_GAIN_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_VGA_GAIN_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_VGA_GAIN_DIAG_5_0 ,Current VGA gain integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.word (0x8400+0x15E)++0x01 line.word 0x00 "LANE1_RX_REE_VGA_GAIN_TGT_DIAG,REE VGA Gain Target Adjust Diagnostics Register Lane 1" bitfld.word 0x00 0.--4. " RX_REE_VGA_GAIN_TGT_DIAG_4_0 ,Current VGA gain integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (0x8400+0x160)++0x05 line.word 0x00 "LANE1_RX_REE_OFF_COR_CTRL,REE Offset Correction Control Register Lane 1" bitfld.word 0x00 4.--6. " RX_REE_OFF_COR_CTRL_6_4 ,Offset correction integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_OFF_COR_CTRL_3_0 ,Offset correction sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE1_RX_REE_OFF_COR_OVRD,REE Offset Correction Override Register Lane 1" bitfld.word 0x02 7. " RX_REE_OFF_COR_OVRD_7 ,Offset correction override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_OFF_COR_OVRD_5_0 ,Offset correction override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE1_RX_REE_OFF_COR_DIAG,REE Offset Correction Diagnostics Register Lane 1" bitfld.word 0x04 14. " RX_REE_OFF_COR_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_OFF_COR_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_OFF_COR_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_OFF_COR_DIAG_5_0 ,Current offset correction integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8400+0x170)++0x0D line.word 0x00 "LANE1_RX_REE_ADDR_CFG,REE Adder Configuration Register Lane 1" bitfld.word 0x00 2. " RX_REE_ADDR_CFG_2 ,RX peaking tap 3 adder enable" "Disabled,Enabled" bitfld.word 0x00 1. " RX_REE_ADDR_CFG_1 ,RX peaking tap 2 adder enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RX_REE_ADDR_CFG_0 ,RX peaking tap 1 adder enable" "Disabled,Enabled" line.word 0x02 "LANE1_RX_REE_ADDR_CFG,REE Tap 1 Clip Control Register Lane 1" bitfld.word 0x02 8.--10. " RX_REE_TAP1_CLIP_10_8 ,VGA target gain adjust multiplier" "0,1,2,3,4,5,6,7" bitfld.word 0x02 0.--4. " RX_REE_TAP1_CLIP_4_0 ,Threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE1_RX_REE_TAP2TON_CLIP,REE Taps 2 And 3 Clip Control Register Lane 1" bitfld.word 0x04 8.--10. " RX_REE_TAP2TON_CLIP_10_8 ,VGA target gain adjust multiplier" "0,1,2,3,4,5,6,7" bitfld.word 0x04 0.--4. " RX_REE_TAP2TON_CLIP_4_0 ,Threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "LANE1_RX_REE_CTRL_DATA_MASK,REE Control Data Mask Register Lane 1" rbitfld.word 0x06 14. " RX_REE_CTRL_DATA_MASK_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x06 9. " RX_REE_CTRL_DATA_MASK_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x06 8. " RX_REE_CTRL_DATA_MASK_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x06 7. " RX_REE_CTRL_DATA_MASK_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x06 6. " RX_REE_CTRL_DATA_MASK_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x06 5. " RX_REE_CTRL_DATA_MASK_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x06 2. " RX_REE_CTRL_DATA_MASK_2 ,RX tap 3" "0,1" bitfld.word 0x06 1. " RX_REE_CTRL_DATA_MASK_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x06 0. " RX_REE_CTRL_DATA_MASK_0 ,RX tap 1" "0,1" line.word 0x08 "LANE1_RX_REE_DIAG_CTRL,REE Diagnostic Control Register Lane 1" bitfld.word 0x08 6. " RX_REE_DIAG_CTRL_6 ,Hold periodic equalization while RX idle" "Not held,Held" bitfld.word 0x08 4. " RX_REE_DIAG_CTRL_4 ,Hold gen 2 equalization while RX idle" "Not held,Held" textline " " bitfld.word 0x08 1. " RX_REE_DIAG_CTRL_1 ,Force REE controller clock on" "Not forced,Forced" bitfld.word 0x08 0. " RX_REE_DIAG_CTRL_0 ,Force REE function clock on" "Not forced,Forced" line.word 0x0A "LANE1_RX_REE_SMGM_CTRL1,REE Control State Machine Gen Mode Control Register 1 Lane 1" bitfld.word 0x0A 15. " RX_REE_SMGM_CTRL1_15 ,REE periodic general control state machine E path enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 14. " RX_REE_SMGM_CTRL1_14 ,REE periodic general control state machine E path enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 13. " RX_REE_SMGM_CTRL1_13 ,REE periodic general control state machine E path enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 12. " RX_REE_SMGM_CTRL1_12 ,REE periodic general control state machine E path enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x0A 11. " RX_REE_SMGM_CTRL1_11 ,REE periodic general control state machine enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 10. " RX_REE_SMGM_CTRL1_10 ,REE periodic general control state machine enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 9. " RX_REE_SMGM_CTRL1_9 ,REE periodic general control state machine enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 8. " RX_REE_SMGM_CTRL1_8 ,REE periodic general control state machine enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x0A 7. " RX_REE_SMGM_CTRL1_7 ,REE Gen 2 general control state machine E path enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 6. " RX_REE_SMGM_CTRL1_6 ,REE Gen 2 general control state machine E path enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 5. " RX_REE_SMGM_CTRL1_5 ,REE Gen 2 general control state machine E path enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 4. " RX_REE_SMGM_CTRL1_4 ,REE Gen 2 general control state machine E path enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x0A 3. " RX_REE_SMGM_CTRL1_3 ,REE Gen 2 general control state machine enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 2. " RX_REE_SMGM_CTRL1_2 ,REE Gen 2 general control state machine enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 1. " RX_REE_SMGM_CTRL1_1 ,REE Gen 2 general control state machine enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 0. " RX_REE_SMGM_CTRL1_0 ,REE Gen 2 general control state machine enable standard mode 0" "Disabled,Enabled" line.word 0x0C "LANE1_RX_REE_SMGM_CTRL2,REE Control State Machine Gen Mode Control Register 2 Lane 1" bitfld.word 0x0C 0. " RX_REE_SMGM_CTRL2_0 ,REE USB 3 general control state machine E path enable" "Disabled,Enabled" group.word (0x8400+0x180)++0x13 line.word 0x00 "LANE1_RX_DIAG_ILL_CTRL,RX ILL Diagnostic Control Register Lane 1" bitfld.word 0x00 3. " RX_DIAG_ILL_CTRL_3 ,IQ PI ILL calibration enable override enable" "Disabled,Enabled" bitfld.word 0x00 2. " RX_DIAG_ILL_CTRL_2 ,IQ PI ILL calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " RX_DIAG_ILL_CTRL_1 ,E PI ILL calibration enable override enable" "Disabled,Enabled" bitfld.word 0x00 0. " RX_DIAG_ILL_CTRL_0 ,E PI ILL calibration enable override" "Disabled,Enabled" line.word 0x02 "LANE1_RX_DIAG_ILL_IQ_TRIM0,RX ILL IQ Trim 0 Register Lane 1" bitfld.word 0x02 12.--14. " RX_DIAG_ILL_IQ_TRIM0_14_12 ,Rx_diag_ill_iq_trim0_14_12" "0,1,2,3,4,5,6,7" bitfld.word 0x02 8.--10. " RX_DIAG_ILL_IQ_TRIM0_10_8 ,Rx_diag_ill_iq_trim0_10_8" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x02 6.--7. " RX_DIAG_ILL_IQ_TRIM0_7_6 ,Rx_diag_ill_iq_trim0_7_6" "0,1,2,3" bitfld.word 0x02 4.--5. " RX_DIAG_ILL_IQ_TRIM0_5_4 ,Rx_diag_ill_iq_trim0_5_4" "0,1,2,3" textline " " bitfld.word 0x02 2.--3. " RX_DIAG_ILL_IQ_TRIM0_3_2 ,Rx_diag_ill_iq_trim0_3_2" "0,1,2,3" bitfld.word 0x02 0.--1. " RX_DIAG_ILL_IQ_TRIM0_1_0 ,Rx_diag_ill_iq_trim0_1_0" "0,1,2,3" line.word 0x04 "LANE1_RX_DIAG_ILL_E_TRIM0,RX ILL E Trim 0 Register Lane 1" bitfld.word 0x04 12.--14. " RX_DIAG_ILL_E_TRIM0_14_12 ,Rx_diag_ill_e_trim0_14_12" "0,1,2,3,4,5,6,7" bitfld.word 0x04 8.--10. " RX_DIAG_ILL_E_TRIM0_10_8 ,Rx_diag_ill_e_trim0_10_8" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x04 6.--7. " RX_DIAG_ILL_E_TRIM0_7_6 ,Rx_diag_ill_e_trim0_7_6" "0,1,2,3" bitfld.word 0x04 4.--5. " RX_DIAG_ILL_E_TRIM0_5_4 ,Rx_diag_ill_e_trim0_5_4" "0,1,2,3" textline " " bitfld.word 0x04 2.--3. " RX_DIAG_ILL_E_TRIM0_3_2 ,Rx_diag_ill_e_trim0_3_2" "0,1,2,3" bitfld.word 0x04 0.--1. " RX_DIAG_ILL_E_TRIM0_1_0 ,Rx_diag_ill_e_trim0_1_0" "0,1,2,3" line.word 0x06 "LANE1_RX_DIAG_ILL_IQ_TRIM1,RX ILL IQ Trim 1 Register Lane 1" bitfld.word 0x06 4.--5. " RX_DIAG_ILL_IQ_TRIM1_5_4 ,Rx_diag_ill_iq_trim1_5_4" "0,1,2,3" bitfld.word 0x06 0.--2. " RX_DIAG_ILL_IQ_TRIM1_2_0 ,Rx_diag_ill_iq_trim1_2_0" "0,1,2,3,4,5,6,7" line.word 0x08 "LANE1_RX_DIAG_ILL_E_TRIM1,RX ILL E Trim 1 Register Lane 1" bitfld.word 0x08 4.--5. " RX_DIAG_ILL_E_TRIM1_5_4 ,Rx_diag_ill_e_trim1_5_4" "0,1,2,3" bitfld.word 0x08 0.--2. " RX_DIAG_ILL_E_TRIM1_2_0 ,Rx_diag_ill_e_trim1_2_0" "0,1,2,3,4,5,6,7" line.word 0x0A "LANE1_RX_DIAG_ILL_IQE_TRIM2,RX ILL IQ E Trim 2 Register Lane 1" bitfld.word 0x0A 14.--15. " RX_DIAG_ILL_IQE_TRIM2_15_14 ,Rx_diag_ill_iqe_trim2_15_14" "0,1,2,3" bitfld.word 0x0A 12.--13. " RX_DIAG_ILL_IQE_TRIM2_13_12 ,Rx_diag_ill_iqe_trim2_13_12" "0,1,2,3" textline " " bitfld.word 0x0A 10.--11. " RX_DIAG_ILL_IQE_TRIM2_11_10 ,Rx_diag_ill_iqe_trim2_11_10" "0,1,2,3" bitfld.word 0x0A 8.--9. " RX_DIAG_ILL_IQE_TRIM2_9_8 ,Rx_diag_ill_iqe_trim2_9_8" "0,1,2,3" textline " " bitfld.word 0x0A 6.--7. " RX_DIAG_ILL_IQE_TRIM2_7_6 ,Rx_diag_ill_iqe_trim2_7_6" "0,1,2,3" bitfld.word 0x0A 4.--5. " RX_DIAG_ILL_IQE_TRIM2_5_4 ,Rx_diag_ill_iqe_trim2_5_4" "0,1,2,3" textline " " bitfld.word 0x0A 2.--3. " RX_DIAG_ILL_IQE_TRIM2_3_2 ,Rx_diag_ill_iqe_trim2_3_2" "0,1,2,3" bitfld.word 0x0A 0.--1. " RX_DIAG_ILL_IQE_TRIM2_1_0 ,Rx_diag_ill_iqe_trim2_1_0" "0,1,2,3" line.word 0x0C "LANE1_RX_DIAG_ILL_IQE_TRIM3,RX ILL IQ E Trim 3 Register Lane 1" hexmask.word.byte 0x0C 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM3_15_8 ,Rx_diag_ill_iqe_trim3_15_8" hexmask.word.byte 0x0C 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM3_7_0 ,Rx_diag_ill_iqe_trim3_7_0" line.word 0x0E "LANE1_RX_DIAG_ILL_IQE_TRIM4,RX ILL IQ E Trim 4 Register Lane 1" hexmask.word.byte 0x0E 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM4_15_8 ,Rx_diag_ill_iqe_trim4_15_8" hexmask.word.byte 0x0E 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM4_7_0 ,Rx_diag_ill_iqe_trim4_7_0" line.word 0x10 "LANE1_RX_DIAG_ILL_IQE_TRIM5,RX ILL IQ E Trim 5 Register Lane 1" hexmask.word.byte 0x10 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM5_15_8 ,Rx_diag_ill_iqe_trim5_15_8" hexmask.word.byte 0x10 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM5_7_0 ,Rx_diag_ill_iqe_trim5_7_0" line.word 0x12 "LANE1_RX_DIAG_ILL_IQE_TRIM6,RX ILL IQ E Trim 6 Register Lane 1" hexmask.word.byte 0x12 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM6_15_8 ,Rx_diag_ill_iqe_trim6_15_8" hexmask.word.byte 0x12 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM6_7_0 ,Rx_diag_ill_iqe_trim6_7_0" group.word (0x8400+0x1A0)++0x11 line.word 0x00 "LANE1_RX_DIAG_DFE_AMP_TUNE,DFE Amp Fine Tuning Register Lane 1" bitfld.word 0x00 12.--14. " RX_DIAG_DFE_AMP_TUNE_14_12 ,DFE constant gm bias tune" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " RX_DIAG_DFE_AMP_TUNE_11 ,DFE VGA constant gm bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--10. " RX_DIAG_DFE_AMP_TUNE_10_8 ,DFE VGA amp current adjust" "0,1,2,3,4,5,6,7" bitfld.word 0x00 7. " RX_DIAG_DFE_AMP_TUNE_7 ,DFE peaking constant gm bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4.--6. " RX_DIAG_DFE_AMP_TUNE_6_4 ,DFE peaking amp current adjust" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " RX_DIAG_DFE_AMP_TUNE_3 ,DFE summing constant gm bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--2. " RX_DIAG_DFE_AMP_TUNE_2_0 ,DFE summing amp current adjust" "0,1,2,3,4,5,6,7" line.word 0x02 "LANE1_RX_DIAG_DFE_AMP_TUNE_2,DFE Amp Fine Tuning 2 Register Lane 1" bitfld.word 0x02 11. " RX_DIAG_DFE_AMP_TUNE_2_11 ,DFE low frequency equalizer constant gm bias enable" "Disabled,Enabled" bitfld.word 0x02 8.--10. " RX_DIAG_DFE_AMP_TUNE_2_10_8 ,DFE low frequency equalizer current adjust" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x02 7. " RX_DIAG_DFE_AMP_TUNE_2_7 ,Enable active inductors boost function in the peaking amp for high data rates" "Disabled,Enabled" bitfld.word 0x02 6. " RX_DIAG_DFE_AMP_TUNE_2_6 ,Enable active inductors boost function in stage 1 of the VGA for high data rates" "Disabled,Enabled" textline " " bitfld.word 0x02 5. " RX_DIAG_DFE_AMP_TUNE_2_5 ,Enable active inductors boost function in stage 2 of the VGA for high data rates" "Disabled,Enabled" bitfld.word 0x02 4. " RX_DIAG_DFE_AMP_TUNE_2_4 ,DFE RX tap 1 DAC range select" "0,1" textline " " bitfld.word 0x02 0.--1. " RX_DIAG_DFE_AMP_TUNE_2_1_0 ,DFE RX amp current adjust" "0,1,2,3" line.word 0x04 "LANE1_RX_DIAG_REE_DAC_CTRL,REE DAC Control Register Lane 1" bitfld.word 0x04 2. " RX_DIAG_REE_DAC_CTRL_2 ,DFE offset DAC enable" "Disabled,Enabled" bitfld.word 0x04 1. " RX_DIAG_REE_DAC_CTRL_1 ,DFE Offset DAC attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x04 0. " RX_DIAG_REE_DAC_CTRL_0 ,DFE DAC attenuation" "No attenuation,Attenuation" line.word 0x06 "LANE1_RX_DIAG_DFE_CTRL1,Receiver DFE Control Register 1 Lane 1" bitfld.word 0x06 15. " RX_DIAG_DFE_CTRL1_15 ,DFE tap 1 deserializer MUX select" "0,1" bitfld.word 0x06 7. " RX_DIAG_DFE_CTRL1_7 ,Receiver DFE low frequency equalization enable value standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " RX_DIAG_DFE_CTRL1_6 ,Receiver DFE low frequency equalization enable value standard mode 2" "Disabled,Enabled" bitfld.word 0x06 5. " RX_DIAG_DFE_CTRL1_5 ,Receiver DFE low frequency equalization enable value standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " RX_DIAG_DFE_CTRL1_4 ,Receiver DFE low frequency equalization enable value standard mode 0" "Disabled,Enabled" bitfld.word 0x06 3. " RX_DIAG_DFE_CTRL1_3 ,Receiver DFE equalization enable mask value standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x06 2. " RX_DIAG_DFE_CTRL1_2 ,Receiver DFE equalization enable mask value standard mode 2" "Disabled,Enabled" bitfld.word 0x06 1. " RX_DIAG_DFE_CTRL1_1 ,Receiver DFE equalization enable mask value standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " RX_DIAG_DFE_CTRL1_0 ,Receiver DFE equalization enable mask value standard mode 0" "Disabled,Enabled" line.word 0x08 "LANE1_RX_DIAG_DFE_CTRL2,Receiver DFE Control Register 2 Lane 1" bitfld.word 0x08 6.--7. " RX_DIAG_DFE_CTRL2_7_6 ,RX equalizer range select standard mode 3" "0,1,2,3" bitfld.word 0x08 4.--5. " RX_DIAG_DFE_CTRL2_5_4 ,RX equalizer range select standard mode 2" "0,1,2,3" textline " " bitfld.word 0x08 2.--3. " RX_DIAG_DFE_CTRL2_3_2 ,RX equalizer range select standard mode 1" "0,1,2,3" bitfld.word 0x08 0.--1. " RX_DIAG_DFE_CTRL2_1_0 ,RX equalizer range select standard mode 0" "0,1,2,3" line.word 0x0A "LANE1_RX_DIAG_DFE_CTRL3,Receiver DFE Control Register 3 Lane 1" bitfld.word 0x0A 12.--15. " RX_DIAG_DFE_CTRL3_15_12 ,RX DFE peaking resistor code select standard mode 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0A 8.--11. " RX_DIAG_DFE_CTRL3_11_8 ,RX DFE peaking resistor code select standard mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x0A 4.--7. " RX_DIAG_DFE_CTRL3_7_4 ,RX DFE peaking resistor code select standard mode 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0A 0.--3. " RX_DIAG_DFE_CTRL3_3_0 ,RX DFE peaking resistor code select standard mode 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0C "LANE1_RX_DIAG_NQST_CTRL,Nyquist Control Register Lane 1" bitfld.word 0x0C 12.--15. " RX_DIAG_NQST_CTRL_15_12 ,RX nyquist select value standard mode 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0C 8.--11. " RX_DIAG_NQST_CTRL_11_8 ,RX nyquist select value standard mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x0C 4.--7. " RX_DIAG_NQST_CTRL_7_4 ,RX nyquist select value standard mode 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0C 0.--3. " RX_DIAG_NQST_CTRL_3_0 ,RX nyquist select value standard mode 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0E "LANE1_RX_DIAG_LFEQ_TUNE,Low Frequency Equalizer Tuning Register Lane 1" bitfld.word 0x0E 6.--7. " RX_DIAG_LFEQ_TUNE_7_6 ,RX low frequency equalization zero frequency value standard mode 3" "0,1,2,3" bitfld.word 0x0E 4.--5. " RX_DIAG_LFEQ_TUNE_5_4 ,RX low frequency equalization zero frequency value standard mode 2" "0,1,2,3" textline " " bitfld.word 0x0E 2.--3. " RX_DIAG_LFEQ_TUNE_3_2 ,RX low frequency equalization zero frequency value standard mode 1" "0,1,2,3" bitfld.word 0x0E 0.--1. " RX_DIAG_LFEQ_TUNE_1_0 ,RX low frequency equalization zero frequency value standard mode 0" "0,1,2,3" line.word 0x10 "LANE1_RX_DIAG_RXCTRL,RX Control Register Lane 1" bitfld.word 0x10 15. " RX_DIAG_RXCTRL_15 ,RX deserializer clock invert" "Not inverted,Inverted" bitfld.word 0x10 11. " RX_DIAG_RXCTRL_11 ,PI output clock divider enable standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x10 10. " RX_DIAG_RXCTRL_10 ,PI output clock divider enable standard mode 2" "Disabled,Enabled" bitfld.word 0x10 9. " RX_DIAG_RXCTRL_9 ,PI output clock divider enable standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x10 8. " RX_DIAG_RXCTRL_8 ,PI output clock divider enable standard mode 0" "Disabled,Enabled" bitfld.word 0x10 7. " RX_DIAG_RXCTRL_7 ,Receiver CML to CMOS rate select value standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x10 6. " RX_DIAG_RXCTRL_6 ,Receiver CML to CMOS rate select value standard mode 2" "Disabled,Enabled" bitfld.word 0x10 5. " RX_DIAG_RXCTRL_5 ,Receiver CML to CMOS rate select value standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x10 4. " RX_DIAG_RXCTRL_4 ,Receiver CML to CMOS rate select value standard mode 0" "Disabled,Enabled" bitfld.word 0x10 3. " RX_DIAG_RXCTRL_3 ,RX interface sub-rate standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x10 2. " RX_DIAG_RXCTRL_2 ,RX interface sub-rate standard mode 2" "Disabled,Enabled" bitfld.word 0x10 1. " RX_DIAG_RXCTRL_1 ,RX interface sub-rate standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x10 0. " RX_DIAG_RXCTRL_0 ,RX interface sub-rate standard mode 0" "Disabled,Enabled" rgroup.word (0x8400+0x1B2)++0x01 line.word 0x00 "LANE1_RX_DIAG_RST_DIAG,Receiver Control Reset Diagnostic Register Lane 1" bitfld.word 0x00 8. " RX_DIAG_RST_DIAG_8 ,Current state of the rxda_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 7. " RX_DIAG_RST_DIAG_7 ,Current state of the rx_dig_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 6. " RX_DIAG_RST_DIAG_6 ,Current state of the rxda_cdrlf_reset_n reset" "No reset,Reset" bitfld.word 0x00 5. " RX_DIAG_RST_DIAG_5 ,Current state of the rx_ree_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 4. " RX_DIAG_RST_DIAG_4 ,Current state of the rx_lfps_det_filter_reset_n reset" "No reset,Reset" bitfld.word 0x00 3. " RX_DIAG_RST_DIAG_3 ,Current state of the rx_epi_ill_cal_lock_det_clk_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 2. " RX_DIAG_RST_DIAG_2 ,Current state of the rx_epi_ill_cal_ref_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 1. " RX_DIAG_RST_DIAG_1 ,Current state of the rx_iqpi_ill_cal_lock_det_clk_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 0. " RX_DIAG_RST_DIAG_0 ,Current state of the rx_iqpi_ill_cal_ref_clk_reset_n reset" "No reset,Reset" group.word (0x8400+0x1B8)++0x05 line.word 0x00 "LANE1_RX_DIAG_SIGDET_TUNE,RX Signal Detect Tuning And Control Register Lane 1" bitfld.word 0x00 12.--13. " RX_DIAG_SIGDET_TUNE_13_12 ,Signal detect filter function select" "0,1,2,3" bitfld.word 0x00 4.--5. " RX_DIAG_SIGDET_TUNE_5_4 ,Signal definition to be provided by the analog team" "0,1,2,3" textline " " bitfld.word 0x00 0.--3. " RX_DIAG_SIGDET_TUNE_3_0 ,Signal detect level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE1_RX_DIAG_LFPSDET_TUNE,RX LFPS Detect Tuning And Control Register Lane 1" hexmask.word.byte 0x02 8.--15. 1. " RX_DIAG_LFPSDET_TUNE_15_8 ,Signal definition to be provided by the analog team" hexmask.word.byte 0x02 0.--7. 1. " RX_DIAG_LFPSDET_TUNE_7_0 ,LFPS detect level" line.word 0x04 "LANE1_RX_DIAG_SD_TEST,Signal Detect Test Register Lane 1" bitfld.word 0x04 3. " RX_DIAG_SD_TEST_3 ,LFPS detected low test bit" "Not detected,Detected" bitfld.word 0x04 2. " RX_DIAG_SD_TEST_2 ,LFPS detected high test bit" "Not detected,Detected" textline " " bitfld.word 0x04 1. " RX_DIAG_SD_TEST_1 ,Signal detected low test bit" "Not detected,Detected" bitfld.word 0x04 0. " RX_DIAG_SD_TEST_0 ,Signal detected high test bit" "Not detected,Detected" group.word (0x8400+0x1C0)++0x03 line.word 0x00 "LANE1_RX_DIAG_SAMP_CTRL,RX Sampler Diagnostic Control Register Lane 1" bitfld.word 0x00 0. " RX_DIAG_SAMP_CTRL_0 ,Analog sampler" "0,1" line.word 0x02 "LANE1_RX_DIAG_SC2C_DELAY,RX Sampler CML TO CMOS Enable Delay Register Lane 1" hexmask.word 0x02 0.--9. 1. " RX_DIAG_SC2C_DELAY_9_0 ,Sampler CML to CMOS enable delay" group.word (0x8400+0x1C8)++0x03 line.word 0x00 "LANE1_RX_DIAG_MPHY_CTRL_1,MPHY Control Register 1 Lane 1" bitfld.word 0x00 14. " RX_DIAG_MPHY_CTRL_1_14 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x00 13. " RX_DIAG_MPHY_CTRL_1_13 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x00 12. " RX_DIAG_MPHY_CTRL_1_12 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x00 8.--9. " RX_DIAG_MPHY_CTRL_1_9_8 ,Signal definition to be provided by the analog team" "0,1,2,3" textline " " bitfld.word 0x00 0.--5. " RX_DIAG_MPHY_CTRL_1_5_0 ,Signal definition to be provided by the analog team" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE1_RX_DIAG_MPHY_CTRL_2,MPHY Control Register 2 Lane 1" rbitfld.word 0x02 10. " RX_DIAG_MPHY_CTRL_2_10 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 9. " RX_DIAG_MPHY_CTRL_2_9 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x02 8. " RX_DIAG_MPHY_CTRL_2_8 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 7. " RX_DIAG_MPHY_CTRL_2_7 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x02 6. " RX_DIAG_MPHY_CTRL_2_6 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 5. " RX_DIAG_MPHY_CTRL_2_5 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x02 4. " RX_DIAG_MPHY_CTRL_2_4 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 0.--1. " RX_DIAG_MPHY_CTRL_2_1_0 ,Signal definition to be provided by the analog team" "0,1,2,3" group.word (0x8400+0x1D0)++0x03 line.word 0x00 "LANE1_RX_DIAG_LPBK_CTRL,RX Loopback Controller Register Lane 1" bitfld.word 0x00 4. " RX_DIAG_LPBK_CTRL_4 ,Recovered clock loopback select" "0,1" bitfld.word 0x00 0.--3. " RX_DIAG_LPBK_CTRL_3_0 ,Attenuation settings" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE1_RX_DIAG_ECTRL_OVRD,RX Extra Enable Control Override Register Lane1" bitfld.word 0x02 1. " RX_DIAG_ECTRL_OVRD_1 ,Sampler CML to CMOS enable override enable" "Disabled,Enabled" bitfld.word 0x02 0. " RX_DIAG_ECTRL_OVRD_0 ,Sampler CML to CMOS enable override" "Disabled,Enabled" group.word (0x8400+0x1E0)++0x0F line.word 0x00 "LANE1_RX_DIAG_CML2CMOS_BTRIM,CML To CMOS Bias Trim Register Lane 1" bitfld.word 0x00 12.--14. " RX_DIAG_CML2CMOS_BTRIM_14_12 ,CML to CMOS IQ bias sink current trim" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--10. " RX_DIAG_CML2CMOS_BTRIM_10_8 ,CML to CMOS IQ bias source current trim" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 4.--6. " RX_DIAG_CML2CMOS_BTRIM_6_4 ,CML to CMOS E bias sink current trim" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--2. " RX_DIAG_CML2CMOS_BTRIM_2_0 ,CML to CMOS E bias source current trim" "0,1,2,3,4,5,6,7" line.word 0x02 "LANE1_RX_DIAG_BIAS_GEN_CTRL1,RX Bias Gen Control Register 1 Lane 1" bitfld.word 0x02 14.--15. " RX_DIAG_BIAS_GEN_CTRL1_15_14 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 12.--13. " RX_DIAG_BIAS_GEN_CTRL1_13_12 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 10.--11. " RX_DIAG_BIAS_GEN_CTRL1_11_10 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 8.--9. " RX_DIAG_BIAS_GEN_CTRL1_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 6.--7. " RX_DIAG_BIAS_GEN_CTRL1_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 4.--5. " RX_DIAG_BIAS_GEN_CTRL1_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 2.--3. " RX_DIAG_BIAS_GEN_CTRL1_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 0.--1. " RX_DIAG_BIAS_GEN_CTRL1_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x04 "LANE1_RX_DIAG_BIAS_GEN_CTRL2,RX Bias Gen Control Register 2 Lane 1" bitfld.word 0x04 14.--15. " RX_DIAG_BIAS_GEN_CTRL2_15_14 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 12.--13. " RX_DIAG_BIAS_GEN_CTRL2_13_12 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 10.--11. " RX_DIAG_BIAS_GEN_CTRL2_11_10 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 8.--9. " RX_DIAG_BIAS_GEN_CTRL2_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 6.--7. " RX_DIAG_BIAS_GEN_CTRL2_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 4.--5. " RX_DIAG_BIAS_GEN_CTRL2_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 2.--3. " RX_DIAG_BIAS_GEN_CTRL2_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 0.--1. " RX_DIAG_BIAS_GEN_CTRL2_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x06 "LANE1_RX_DIAG_BIAS_GEN_CTRL3,RX Bias Gen Control Register 3 Lane 1" bitfld.word 0x06 14.--15. " RX_DIAG_BIAS_GEN_CTRL3_15_14 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 12.--13. " RX_DIAG_BIAS_GEN_CTRL3_13_12 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 10.--11. " RX_DIAG_BIAS_GEN_CTRL3_11_10 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 8.--9. " RX_DIAG_BIAS_GEN_CTRL3_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 6.--7. " RX_DIAG_BIAS_GEN_CTRL3_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 4.--5. " RX_DIAG_BIAS_GEN_CTRL3_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 2.--3. " RX_DIAG_BIAS_GEN_CTRL3_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 0.--1. " RX_DIAG_BIAS_GEN_CTRL3_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x08 "LANE1_RX_DIAG_BIAS_GEN_CTRL4,RX Bias Gen Control Register 4 Lane 1" bitfld.word 0x08 15. " RX_DIAG_BIAS_GEN_CTRL4_15 ,Enable base unit on all the current outputs from the RX bias generation block" "Disabled,Enabled" bitfld.word 0x08 8.--9. " RX_DIAG_BIAS_GEN_CTRL4_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x08 6.--7. " RX_DIAG_BIAS_GEN_CTRL4_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x08 4.--5. " RX_DIAG_BIAS_GEN_CTRL4_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x08 2.--3. " RX_DIAG_BIAS_GEN_CTRL4_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x08 0.--1. " RX_DIAG_BIAS_GEN_CTRL4_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x0A "LANE1_RX_DIAG_BS_TM,RX Boundary Scan Test Mode Register" line.word 0x0C "LANE1_RX_DIAG_RXFE_TM1,RX Receiver Front End Test Mode Register 1 Lane 1" line.word 0x0E "LANE1_RX_DIAG_RXFE_TM2,RX Receiver Front End Test Mode Register 2 Lane 1" group.word 0x8800++0x0F line.word 0x00 "LANE2_RX_PSC_A0,Receiver A0 Power State Definition Register Lane 2" bitfld.word 0x00 15. " RX_PSC_A0_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x00 14. " RX_PSC_A0_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x00 13. " RX_PSC_A0_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RX_PSC_A0_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x00 11. " RX_PSC_A0_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_PSC_A0_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_PSC_A0_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_PSC_A0_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x00 7. " RX_PSC_A0_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " RX_PSC_A0_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x00 5. " RX_PSC_A0_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x00 4. " RX_PSC_A0_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RX_PSC_A0_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x00 2. " RX_PSC_A0_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x00 1. " RX_PSC_A0_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RX_PSC_A0_0 ,RX enable" "Disabled,Enabled" line.word 0x02 "LANE2_RX_PSC_A1,Receiver A1 Power State Definition Register Lane 2" bitfld.word 0x02 15. " RX_PSC_A1_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x02 14. " RX_PSC_A1_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x02 13. " RX_PSC_A1_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RX_PSC_A1_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x02 11. " RX_PSC_A1_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x02 10. " RX_PSC_A1_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RX_PSC_A1_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x02 8. " RX_PSC_A1_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x02 7. " RX_PSC_A1_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " RX_PSC_A1_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x02 5. " RX_PSC_A1_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x02 4. " RX_PSC_A1_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RX_PSC_A1_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x02 2. " RX_PSC_A1_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x02 1. " RX_PSC_A1_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RX_PSC_A1_0 ,RX enable" "Disabled,Enabled" line.word 0x04 "LANE2_RX_PSC_A2,Receiver A2 Power State Definition Register Lane 2" bitfld.word 0x04 15. " RX_PSC_A2_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x04 14. " RX_PSC_A2_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x04 13. " RX_PSC_A2_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x04 12. " RX_PSC_A2_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x04 11. " RX_PSC_A2_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x04 10. " RX_PSC_A2_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x04 9. " RX_PSC_A2_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x04 8. " RX_PSC_A2_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x04 7. " RX_PSC_A2_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " RX_PSC_A2_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x04 5. " RX_PSC_A2_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x04 4. " RX_PSC_A2_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x04 3. " RX_PSC_A2_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x04 2. " RX_PSC_A2_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x04 1. " RX_PSC_A2_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x04 0. " RX_PSC_A2_0 ,RX enable" "Disabled,Enabled" line.word 0x06 "LANE2_RX_PSC_A3,Receiver A3 Power State Definition Register Lane 2" bitfld.word 0x06 15. " RX_PSC_A3_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x06 14. " RX_PSC_A3_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x06 13. " RX_PSC_A3_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x06 12. " RX_PSC_A3_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x06 11. " RX_PSC_A3_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x06 10. " RX_PSC_A3_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x06 9. " RX_PSC_A3_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x06 8. " RX_PSC_A3_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x06 7. " RX_PSC_A3_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " RX_PSC_A3_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x06 5. " RX_PSC_A3_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x06 4. " RX_PSC_A3_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x06 3. " RX_PSC_A3_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x06 2. " RX_PSC_A3_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x06 1. " RX_PSC_A3_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " RX_PSC_A3_0 ,RX enable" "Disabled,Enabled" line.word 0x08 "LANE2_RX_PSC_A4,Receiver A4 Power State Definition Register Lane 2" bitfld.word 0x08 15. " RX_PSC_A4_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x08 14. " RX_PSC_A4_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x08 13. " RX_PSC_A4_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x08 12. " RX_PSC_A4_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x08 11. " RX_PSC_A4_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x08 10. " RX_PSC_A4_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x08 9. " RX_PSC_A4_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x08 8. " RX_PSC_A4_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x08 7. " RX_PSC_A4_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " RX_PSC_A4_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x08 5. " RX_PSC_A4_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x08 4. " RX_PSC_A4_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x08 3. " RX_PSC_A4_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x08 2. " RX_PSC_A4_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x08 1. " RX_PSC_A4_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " RX_PSC_A4_0 ,RX enable" "Disabled,Enabled" line.word 0x0A "LANE2_RX_PSC_A5,Receiver A5 Power State Definition Register Lane 2" bitfld.word 0x0A 15. " RX_PSC_A5_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x0A 14. " RX_PSC_A5_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x0A 13. " RX_PSC_A5_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 12. " RX_PSC_A5_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x0A 11. " RX_PSC_A5_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x0A 10. " RX_PSC_A5_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 9. " RX_PSC_A5_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x0A 8. " RX_PSC_A5_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x0A 7. " RX_PSC_A5_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 6. " RX_PSC_A5_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x0A 5. " RX_PSC_A5_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x0A 4. " RX_PSC_A5_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 3. " RX_PSC_A5_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x0A 2. " RX_PSC_A5_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x0A 1. " RX_PSC_A5_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 0. " RX_PSC_A5_0 ,RX enable" "Disabled,Enabled" line.word 0x0C "LANE2_RX_PSC_CAL,Receiver Calibration Power State Definition Register Lane 2" bitfld.word 0x0C 15. " RX_PSC_CAL_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x0C 14. " RX_PSC_CAL_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x0C 13. " RX_PSC_CAL_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 12. " RX_PSC_CAL_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x0C 11. " RX_PSC_CAL_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x0C 10. " RX_PSC_CAL_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 9. " RX_PSC_CAL_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x0C 8. " RX_PSC_CAL_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x0C 7. " RX_PSC_CAL_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " RX_PSC_CAL_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x0C 5. " RX_PSC_CAL_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x0C 4. " RX_PSC_CAL_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 3. " RX_PSC_CAL_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x0C 2. " RX_PSC_CAL_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x0C 1. " RX_PSC_CAL_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 0. " RX_PSC_CAL_0 ,RX enable" "Disabled,Enabled" line.word 0x0E "LANE2_RX_PSC_RDY,Receiver Ready Power State Definition Register Lane 2" bitfld.word 0x0E 15. " RX_PSC_RDY_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x0E 14. " RX_PSC_RDY_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x0E 13. " RX_PSC_RDY_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 12. " RX_PSC_RDY_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x0E 11. " RX_PSC_RDY_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x0E 10. " RX_PSC_RDY_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 9. " RX_PSC_RDY_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x0E 8. " RX_PSC_RDY_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x0E 7. " RX_PSC_RDY_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 6. " RX_PSC_RDY_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x0E 5. " RX_PSC_RDY_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x0E 4. " RX_PSC_RDY_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 3. " RX_PSC_RDY_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x0E 2. " RX_PSC_RDY_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x0E 1. " RX_PSC_RDY_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 0. " RX_PSC_RDY_0 ,RX enable" "Disabled,Enabled" textline " " group.word (0x8800+0x40)++0x0D line.word 0x00 "LANE2_RX_IQPI_ILL_CAL_CTRL,RX IQ PI ILL Calibration Control Register Lane 2" bitfld.word 0x00 15. " RX_IQPI_ILL_CAL_CTRL_15 ,Start ILL calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_IQPI_ILL_CAL_CTRL_15 ,ILL calibration process done" "Not done,Done" textline " " hexmask.word.byte 0x00 0.--7. 1. " RX_IQPI_ILL_CAL_CTRL_7_0 ,ILL calibration code" line.word 0x02 "LANE2_RX_IQPI_ILL_CAL_START,RX IQ PI ILL Calibration Start Point Register Lane 2" bitfld.word 0x02 12.--14. " RX_IQPI_ILL_CAL_START_14_12 ,ILL calibration initial step size control" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x02 0.--7. 1. " RX_IQPI_ILL_CAL_START_7_0 ,ILL calibration code starting point value" line.word 0x04 "LANE2_RX_IQPI_ILL_CAL_TCTRL,RX IQ PI ILL Calibration Timer Control Register Lane 2" bitfld.word 0x04 0.--2. " RX_IQPI_ILL_CAL_TCTRL_2_0 ,ILL calibration initial time scale control" "0,1,2,3,4,5,6,7" line.word 0x06 "LANE2_RX_IQPI_ILL_CAL_OVRD,RX IQ PI ILL Calibration Override Register Lane 2" bitfld.word 0x06 15. " RX_IQPI_ILL_CAL_OVRD_15 ,ILL calibration code override enable" "Disabled,Enabled" hexmask.word.byte 0x06 0.--7. 1. " RX_IQPI_ILL_CAL_OVRD_7_0 ,ILL calibration code override value" line.word 0x08 "LANE2_RX_IQPI_ILL_CAL_INIT_TMR,RX IQ PI ILL Calibration Initialization Timer Register Lane 2" hexmask.word 0x08 0.--11. 1. " RX_IQPI_ILL_CAL_INIT_TMR_11_0 ,Initialization wait timer value" line.word 0x0A "LANE2_RX_IQPI_ILL_CAL_ITER_TMR,RX IQ PI ILL Calibration Iteration Timer Register Lane 2" hexmask.word 0x0A 0.--11. 1. " RX_IQPI_ILL_CAL_ITER_TMR_11_0 ,Iteration wait timer value" line.word 0x0C "LANE2_RX_IQPI_ILL_LOCK_REFTMR_START,RX IQ PI ILL Lock Reference Timer Start Value Register Lane 2" hexmask.word 0x0C 0.--11. 1. " RX_IQPI_ILL_LOCK_REFTMR_START_11_0 ,ILL lock reference timer start value" group.word (0x8800+0x50)++0x07 line.word 0x00 "LANE2_RX_IQPI_ILL_LOCK_CALCNT_START_0,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 0 Register Lane 2" hexmask.word 0x00 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_0_11_0 ,ILL lock calibration counter start value" line.word 0x02 "LANE2_RX_IQPI_ILL_LOCK_CALCNT_START_1,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 1 Register Lane 2" hexmask.word 0x02 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_1_11_0 ,ILL lock calibration counter start value" line.word 0x04 "LANE2_RX_IQPI_ILL_LOCK_CALCNT_START_2,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 2 Register Lane 2" hexmask.word 0x04 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_2_11_0 ,ILL lock calibration counter start value" line.word 0x06 "LANE2_RX_IQPI_ILL_LOCK_CALCNT_START_3,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 3 Register Lane 2" hexmask.word 0x06 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_3_11_0 ,ILL lock calibration counter start value" group.word (0x8800+0x60)++0x0D line.word 0x00 "LANE2_RX_EPI_ILL_CAL_CTRL,RX E PI ILL Calibration Control Register Lane 2" bitfld.word 0x00 15. " RX_EPI_ILL_CAL_CTRL_15 ,Start ILL calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_EPI_ILL_CAL_CTRL_14 ,ILL calibration process done" "Not done,Done" textline " " hexmask.word.byte 0x00 0.--7. 1. " RX_EPI_ILL_CAL_CTRL_7_0 ,ILL calibration code" line.word 0x02 "LANE2_RX_EPI_ILL_CAL_START,RX E PI ILL Calibration Start Point Register Lane 2" bitfld.word 0x02 12.--14. " RX_EPI_ILL_CAL_START_14_12 ,ILL calibration initial step size control" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x02 0.--7. 1. " RX_EPI_ILL_CAL_START_7_0 ,ILL calibration code starting point value" line.word 0x04 "LANE2_RX_EPI_ILL_CAL_TCTRL,RX E PI ILL Calibration Timer Control Register Lane 2" bitfld.word 0x04 0.--2. " RX_EPI_ILL_CAL_TCTRL_2_0 ,ILL calibration initial time scale control" "0,1,2,3,4,5,6,7" line.word 0x06 "LANE2_RX_EPI_ILL_CAL_OVRD,RX E PI ILL Calibration Override Register Lane 2" bitfld.word 0x06 15. " RX_EPI_ILL_CAL_OVRD_15 ,ILL calibration code override enable" "Disabled,Enabled" hexmask.word.byte 0x06 0.--7. 1. " RX_EPI_ILL_CAL_OVRD_7_0 ,ILL calibration code override value" line.word 0x08 "LANE2_RX_EPI_ILL_CAL_INIT_TMR,RX E PI ILL Calibration Initialization Timer Register 2" hexmask.word 0x08 0.--11. 1. " RX_EPI_ILL_CAL_INIT_TMR_11_0 ,Initialization wait timer value" line.word 0x0A "LANE2_RX_EPI_ILL_CAL_ITER_TMR,RX E PI ILL Calibration Iteration Timer Register Lane 2" hexmask.word 0x0A 0.--11. 1. " RX_EPI_ILL_CAL_ITER_TMR_11_0 ,Iteration wait timer value" line.word 0x0C "LANE2_RX_EPI_ILL_LOCK_REFTMR_START,RX E PI ILL Lock Reference Timer Start Value Register Lane 2" hexmask.word 0x0C 0.--11. 1. " RX_EPI_ILL_LOCK_REFTMR_START_11_0 ,ILL lock reference timer start value" group.word (0x8800+0x70)++0x07 line.word 0x00 "LANE2_RX_EPI_ILL_LOCK_CALCNT_START_0,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 0 Register Lane 2" hexmask.word 0x00 0.--11. 1. " RX_EPI_ILL_LOCK_CALCNT_START_0_11_0 ,ILL lock calibration counter start value" line.word 0x02 "LANE2_RX_EPI_ILL_LOCK_CALCNT_START_1,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 1 Register Lane 2" hexmask.word 0x02 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_1_11_0 ,ILL lock calibration counter start value" line.word 0x04 "LANE2_RX_IQPI_ILL_LOCK_CALCNT_START_2,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 2 Register Lane 2" hexmask.word 0x04 0.--11. 1. " RX_EPI_ILL_LOCK_CALCNT_START_2_11_0 ,ILL lock calibration counter start value" line.word 0x06 "LANE2_RX_IQPI_ILL_LOCK_CALCNT_START_3,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 3 Register Lane 2" hexmask.word 0x06 0.--11. 1. " RX_EPI_ILL_LOCK_CALCNT_START_3_11_0 ,ILL lock calibration counter start value" group.word (0x8800+0x80)++0x0B line.word 0x00 "LANE2_RX_SDCAL0_CTRL,Signal Detect Calibration 0 Control Register Lane 2" bitfld.word 0x00 15. " RX_SDCAL0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SDCAL0_CTRL_14 ,Calibration process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " RX_EPI_ILL_CAL_CTRL_14 ,No analog calibration response" "Not responded,Responded" rbitfld.word 0x00 12. " RX_SDCAL0_CTRL_14 ,Current analog comparator response" "Not responded,Responded" textline " " bitfld.word 0x00 0.--3. " RX_SDCAL0_CTRL_3_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE2_RX_SDCAL0_OVRD,Signal Detect Calibration 0 Override Register Lane 2" bitfld.word 0x02 15. " RX_SDCAL0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " RX_SDCAL0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 0.--3. " RX_SDCAL0_OVRD_3_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "LANE2_RX_SDCAL0_START,Signal Detect Calibration 0 Start Register Lane 2" bitfld.word 0x04 15. " RX_SDCAL0_START_15 ,Calibration direction" "0,1" bitfld.word 0x04 0.--3. " RX_SDCAL0_START_3_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x06 "LANE2_RX_SDCAL0_TUNE,Signal Detect Calibration 0 Tune Register Lane 2" bitfld.word 0x06 0.--3. " RX_SDCAL0_TUNE_3_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "LANE2_RX_SDCAL0_INIT_TMR,Signal Detect Calibration 0 Initialization Timer Register Lane2" hexmask.word 0x08 0.--8. 1. " RX_SDCAL0_INIT_TMR_8_0 ,Initialization wait timer value" line.word 0x0A "LANE2_RX_SDCAL0_ITER_TMR,Signal Detect Calibration 0 Iteration Timer Register Lane 2" hexmask.word 0x0A 0.--8. 1. " RX_SDCAL0_ITER_TMR_8_0 ,Iteration wait timer value" group.word (0x8800+0x90)++0x0B line.word 0x00 "LANE2_RX_SDCAL1_CTRL,Signal Detect Calibration 1 Control Register Lane 2" bitfld.word 0x00 15. " RX_SDCAL1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SDCAL1_CTRL_14 ,Calibration process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " RX_SDCAL1_CTRL_13 ,No analog calibration response" "Not responded,Responded" rbitfld.word 0x00 12. " RX_SDCAL1_CTRL_12 ,Current analog comparator response" "Not responded,Responded" textline " " bitfld.word 0x00 0.--3. " RX_SDCAL1_CTRL_3_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE2_RX_SDCAL1_OVRD,Signal Detect Calibration 1 Override Register Lane 2" bitfld.word 0x02 15. " RX_SDCAL1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " RX_SDCAL1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 0.--3. " RX_SDCAL1_OVRD_3_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "LANE2_RX_SDCAL1_START,Signal Detect Calibration 1 Start Register Lane 2" bitfld.word 0x04 15. " RX_SDCAL1_START_15 ,Calibration direction" "0,1" bitfld.word 0x04 0.--3. " RX_SDCAL1_START_3_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x06 "LANE2_RX_SDCAL1_TUNE,Signal Detect Calibration 1 Tune Register Lane 2" bitfld.word 0x06 0.--3. " RX_SDCAL1_TUNE_3_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "LANE2_RX_SDCAL1_INIT_TMR,Signal Detect Calibration 1 Initialization Timer Register Lane 2" hexmask.word 0x08 0.--8. 1. " RX_SDCAL1_INIT_TMR_8_0 ,Initialization wait timer value" line.word 0x0A "LANE2_RX_SDCAL1_ITER_TMR,Signal Detect Calibration 1 Iteration Timer Register Lane 2" hexmask.word 0x0A 0.--8. 1. " RX_SDCAL1_ITER_TMR_8_0 ,Iteration wait timer value" group.word (0x8800+0xB0)++0x01 line.word 0x00 "LANE2_RX_SAMP_DAC_CTRL,Sampler Error DAC Control Register Lane 2" bitfld.word 0x00 0.--5. " RX_SAMP_DAC_CTRL_5_0 ,Sampler error DAC value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8800+0x100)++0x0B line.word 0x00 "LANE2_RX_CDRLF_CNFG,CDRLF Configuration Register Lane 2" rbitfld.word 0x00 15. " RX_CDRLF_CNFG_15 ,CDRLF fast phase lock locked detected" "Not detected,Detected" bitfld.word 0x00 14. " RX_CDRLF_CNFG_14 ,CDRLF fast phase lock diagnostic enable" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " RX_CDRLF_CNFG_13 ,CDRLF fast phase lock enable" "Disabled,Enabled" bitfld.word 0x00 12. " RX_CDRLF_CNFG_12 ,CDRLF fast frequency lock enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " RX_CDRLF_CNFG_11 ,CDRLF second order loop integrator max clear enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_CDRLF_CNFG_10 ,CDRLF reset on CDRLF PM accumulator max" "No reset,Reset" textline " " bitfld.word 0x00 9. " RX_CDRLF_CNFG_9 ,CDRLF freeze on electrical idle detect" "Not detected,Detected" bitfld.word 0x00 8. " RX_CDRLF_CNFG_8 ,CDRLF reset on electrical idle detect" "Not detected,Detected" textline " " bitfld.word 0x00 7. " RX_CDRLF_CNFG_7 ,CDRLF data filter enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " RX_CDRLF_CNFG_5_0 ,CDRLF second order loop integrator threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE2_RX_CDRLF_CNFG2,CDRLF Configuration Register 2 Lane 2" bitfld.word 0x02 4.--6. " RX_CDRLF_CNFG2_6 ,CDRLF diagnostic mode control" "0,1,2,3,4,5,6,7" bitfld.word 0x02 2. " RX_CDRLF_CNFG2_2 ,CDLRF reset hold" "Not held,Held" textline " " bitfld.word 0x02 1. " RX_CDRLF_CNFG2_1 ,CDRLF second order loop disable" "No,Yes" bitfld.word 0x02 0. " RX_CDRLF_CNFG2_0 ,CDRLF first order loop disable" "No,Yes" line.word 0x04 "LANE2_RX_CDRLF_MGN_DIAG,CDRLF Margin Diagnostic Register 2 Lane 2" bitfld.word 0x04 2. " RX_CDRLF_MGN_DIAG_2 ,CDRLF PI override down" "No override,Override" bitfld.word 0x04 1. " RX_CDRLF_MGN_DIAG_1 ,CDRLF PI override up" "No override,Override" textline " " bitfld.word 0x04 0. " RX_CDRLF_MGN_DIAG_0 ,CDRLF PI override enable" "Disabled,Enabled" line.word 0x06 "LANE2_RX_CDRLF_FPL_TMR0,CDRLF Fast Phase Lock Timer Value Register 0 Lane 2" bitfld.word 0x06 4.--7. " RX_CDRLF_FPL_TMR0_7_4 ,Fast phase lock timer accumulate state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x06 0.--3. " RX_CDRLF_FPL_TMR0_3_0 ,Fast phase lock timer delay state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "LANE2_RX_CDRLF_FPL_TMR1,CDRLF Fast Phase Lock Timer Value Register 1 Lane 2" bitfld.word 0x08 8.--11. " RX_CDRLF_FPL_TMR1_11_8 ,Fast phase lock timer trigger 1 state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x08 4.--7. " RX_CDRLF_FPL_TMR1_7_4 ,Fast phase lock timer trigger 2 state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x08 0.--3. " RX_CDRLF_FPL_TMR1_3_0 ,Fast phase lock timer trigger 3 state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0A "LANE2_RX_CDRLF_FFL_TMR,CDRLF Fast Frequency Lock Timer Value Register Lane 2" bitfld.word 0x0A 0.--5. " RX_CDRLF_FFL_TMR_5_0 ,Fast frequency lock step timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8800+0x110)++0x09 line.word 0x00 "LANE2_RX_CDRLF_FFL0_CTRL,CDRLF Fast Frequency Lock Step 0 Control Register Lane 2" bitfld.word 0x00 14.--15. " RX_CDRLF_FFL0_CTRL_15_14 ,FFL step 0 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x00 8.--12. " RX_CDRLF_FFL0_CTRL_12_8 ,FFL step 0 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x00 0.--4. " RX_CDRLF_FFL0_CTRL_4_0 ,FFL step 0 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x02 "LANE2_RX_CDRLF_FFL1_CTRL,CDRLF Fast Frequency Lock Step 1 Control Register Lane 2" bitfld.word 0x02 14.--15. " RX_CDRLF_FFL1_CTRL_15_14 ,FFL step 1 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x02 8.--12. " RX_CDRLF_FFL1_CTRL_12_8 ,FFL step 1 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x02 0.--4. " RX_CDRLF_FFL1_CTRL_4_0 ,FFL step 1 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE2_RX_CDRLF_FFL2_CTRL,CDRLF Fast Frequency Lock Step 2 Control Register Lane 2" bitfld.word 0x04 14.--15. " RX_CDRLF_FFL2_CTRL_15_14 ,FFL step 2 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x04 8.--12. " RX_CDRLF_FFL2_CTRL_12_8 ,FFL step 2 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x04 0.--4. " RX_CDRLF_FFL2_CTRL_4_0 ,FFL step 2 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "LANE2_RX_CDRLF_FFL3_CTRL,CDRLF Fast Frequency Lock Step 3 Control Register Lane 2" bitfld.word 0x06 14.--15. " RX_CDRLF_FFL3_CTRL_15_14 ,FFL step 3 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x06 8.--12. " RX_CDRLF_FFL3_CTRL_12_8 ,FFL step 3 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x06 0.--4. " RX_CDRLF_FFL3_CTRL_4_0 ,FFL step 3 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "LANE2_RX_CDRLF_FFL4_CTRL,CDRLF Fast Frequency Lock Step 4 Control Register Lane 2" bitfld.word 0x08 14.--15. " RX_CDRLF_FFL4_CTRL_15_14 ,FFL step 4 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x08 8.--12. " RX_CDRLF_FFL4_CTRL_12_8 ,FFL step 4 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x08 0.--4. " RX_CDRLF_FFL4_CTRL_4_0 ,FFL step 4 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (0x8800+0x120)++0x17 line.word 0x00 "LANE2_RX_SIGDET_HL_FILT_TMR,Receiver Signal Detect Filter High To Low Filter Timer Register Lane 2" hexmask.word 0x00 0.--9. 1. " RX_SIGDET_HL_FILT_TMR_9_0 ,Signal detect filter high to low filter timer value" line.word 0x02 "LANE2_RX_SIGDET_HL_DLY_TMR,Receiver Signal Detect Filter High To Low Delay Timer Register Lane 2" hexmask.word 0x02 0.--9. 1. " RX_SIGDET_HL_DLY_TMR_9_0 ,Signal detect filter high to low delay timer value" line.word 0x04 "LANE2_RX_SIGDET_HL_MIN_TMR,Receiver Signal Detect Filter High To Low Min Timer Register Lane 2" hexmask.word 0x04 0.--9. 1. " RX_SIGDET_HL_MIN_TMR_9_0 ,Signal detect filter high to low min timer value" line.word 0x06 "LANE2_RX_SIGDET_HL_MIN_TMR,Receiver Signal Detect Filter High To Low Init Timer Register Lane 2" hexmask.word 0x06 0.--9. 1. " RX_SIGDET_HL_INIT_TMR_9_0 ,Signal detect init timer value" line.word 0x08 "LANE2_RX_SIGDET_LH_FILT_TMR,Receiver Signal Detect Filter Low To High Filter Timer Register Lane 2" hexmask.word 0x08 0.--9. 1. " RX_SIGDET_LH_FILT_TMR_9_0 ,Signal detect filter low to high filter timer value" line.word 0x0A "LANE2_RX_SIGDET_LH_DLY_TMR,Receiver Signal Detect Filter Low To High Delay Timer Register Lane 2" hexmask.word 0x0A 0.--9. 1. " RX_SIGDET_LH_DLY_TMR_9_0 ,Signal detect filter low to high delay timer value" line.word 0x0C "LANE2_RX_SIGDET_LH_MIN_TMR,Receiver Signal Detect Filter Low To High Min Timer Register Lane 2" hexmask.word 0x0C 0.--9. 1. " RX_SIGDET_LH_MIN_TMR_9_0 ,Signal detect filter low to high min timer value" line.word 0x0E "LANE2_RX_SIGDET_LH_INIT_TMR,Receiver Signal Detect Filter Low To High Init Timer Register Lane 2" hexmask.word 0x0E 0.--9. 1. " RX_SIGDET_LH_INIT_TMR_9_0 ,Signal detect init timer value" line.word 0x10 "LANE2_RX_LFPSDET_FILT_TMR,Receiver LFPS Detect Filter Filter Timer Register Lane 2" hexmask.word 0x10 0.--9. 1. " RX_LFPSDET_FILT_TMR_9_0 ,LFPS detect filter timer value" line.word 0x12 "LANE2_RX_LFPSDET_DLY_TMR,Receiver LFPS Detect Filter Delay Timer Register Lane 2" hexmask.word 0x12 0.--9. 1. " RX_LFPSDET_DLY_TMR_9_0 ,LFPS detect filter delay timer value" line.word 0x14 "LANE2_RX_LFPSDET_MIN_TMR,Receiver LFPS Detect Min Timer Register Lane 2" hexmask.word 0x14 0.--9. 1. " RX_LFPSDET_MIN_TMR_9_0 ,LFPS detect min timer value" line.word 0x16 "LANE2_RX_LFPSDET_INIT_TMR,Receiver LFPS Detect Init Timer Register Lane 2" hexmask.word 0x16 0.--9. 1. " RX_LFPSDET_INIT_TMR_9_0 ,LFPS detect init timer value" group.word (0x8800+0x140)++0x01 line.word 0x00 "LANE2_RX_EYESURF_CTRL,Eye Surf Control Register Lane 2" bitfld.word 0x00 15. " RX_EYESURF_CTRL_15 ,Eye surf process enable" "Disabled,Enabled" rbitfld.word 0x00 14. " RX_EYESURF_CTRL_14 ,Eye surf process has completed" "Not completed,Completed" group.word (0x8800+0x148)++0x0B line.word 0x00 "LANE2_RX_EYESURF_TMR_DELLOW,Eye Surf Timer Delay Low Register Lane 2" line.word 0x02 "LANE2_RX_EYESURF_TMR_DELHIGH,Eye Surf Timer Delay High Register Lane 2" line.word 0x04 "LANE2_RX_EYESURF_TMR_TESTLOW,Eye Surf Timer Test Low Register Lane 2" line.word 0x06 "LANE2_RX_EYESURF_TMR_TESTHIGH,Eye Surf Timer Test High Register Lane 2" line.word 0x08 "LANE2_RX_EYESURF_NS_COORD,Eye Surf North South Test Point Coordinate Register Lane 2" bitfld.word 0x08 8. " RX_EYESURF_NS_COORD_8 ,Test point coordinate north south direction" "0,1" hexmask.word.byte 0x08 0.--6. 0x01 " RX_EYESURF_NS_COORD_6_0 ,Test point coordinate north south offset" line.word 0x0A "LANE2_RX_EYESURF_EW_COORD,Eye Surf East West Test Point Coordinate Register Lane 2" bitfld.word 0x0A 8. " RX_EYESURF_EW_COORD_8 ,Test point coordinate east west direction" "0,1" hexmask.word.byte 0x0A 0.--4. 0x01 " RX_EYESURF_EW_COORD_4_0 ,Test point coordinate east west offset" rgroup.word (0x8800+0x154)++0x01 line.word 0x00 "LANE2_RX_EYESURF_ERRCNT,Eye Surf Bit Error Count Register Lane 2" group.word (0x8800+0x160)++0x03 line.word 0x00 "LANE2_RX_BIST_CTRL,Receiver BIST Control Register Lane 2" bitfld.word 0x00 8.--11. " RX_BIST_CTRL_11_8 ,Receiver BIST mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4. " RX_BIST_CTRL_4 ,Receiver BIST error reset" "No reset,Reset" textline " " bitfld.word 0x00 1. " RX_BIST_CTRL_1 ,Receiver BIST user defined data FIFO clear" "No clear,Clear" bitfld.word 0x00 0. " RX_BIST_CTRL_0 ,Receiver BIST enable" "Disabled,Enabled" line.word 0x02 "LANE2_RX_BIST_SYNCCNT,Receiver BIST Sync Count Register Lane 2" wgroup.word (0x8800+0x164)++0x01 line.word 0x00 "LANE2_RX_BIST_UDDWR,Receiver BIST User Defined Data Write Register Lane 2" hexmask.word 0x00 0.--9. 1. " RX_BIST_UDDWR_9_0 ,Receiver BIST user defined data" rgroup.word (0x8800+0x166)++0x01 line.word 0x00 "LANE2_RX_BIST_ERRCNT,Receiver BIST Error Count Register Lane 2" group.word (0x8800+0x168)++0x05 line.word 0x00 "LANE2_XCVR_CMSMT_CLK_FREQ_MSMT_CTRL,Clock Frequency Measurement Control Register Lane 2" bitfld.word 0x00 15. " XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_15 ,Start test clock measurement" "Not started,Started" rbitfld.word 0x00 14. " XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_14 ,Test clock measurement done" "Not done,Done" line.word 0x02 "LANE2_XCVR_CMSMT_TEST_CLK_SEL,Test Clock Selection Register Lane 2" bitfld.word 0x02 0.--2. " XCVR_CMSMT_TEST_CLK_SEL_2_0 ,Test clock select" "0,1,2,3,4,5,6,7" line.word 0x04 "LANE2_XCVR_CMSMT_REF_CLK_TMR_VALUE,Reference Clock Timer Value Register Lane 2" hexmask.word 0x04 0.--11. 1. " XCVR_CMSMT_REF_CLK_TMR_VALUE_11_0 ,Reference clock timer value" rgroup.word (0x8800+0x16E)++0x01 line.word 0x00 "LANE2_XCVR_CMSMT_TEST_CLK_CNT_VALUE,Test Clock Counter Value Register Lane 2" hexmask.word 0x00 0.--11. 1. " XCVR_CMSMT_TEST_CLK_CNT_VALUE_11_0 ,Test clock counter value" group.word (0x8800+0x1C0)++0x15 line.word 0x00 "LANE2_RX_SLC_CTRL,RX Sampler Latch Calibration Control Register Lane 2" bitfld.word 0x00 15. " RX_SLC_CTRL_15 ,Start RX sampler latch calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SLC_CTRL_14 ,RX sampler latch calibration done" "Not done,Done" textline " " bitfld.word 0x00 13. " RX_SLC_CTRL_13 ,Analog calibration enable override" "Disabled,Enabled" bitfld.word 0x00 11. " RX_SLC_CTRL_11 ,I odd positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " RX_SLC_CTRL_10 ,Q odd positive calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 9. " RX_SLC_CTRL_9 ,E odd positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " RX_SLC_CTRL_8 ,I odd negative calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 7. " RX_SLC_CTRL_7 ,Q odd negative calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " RX_SLC_CTRL_6 ,E odd negative calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 5. " RX_SLC_CTRL_5 ,I even positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_SLC_CTRL_4 ,Q even positive calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 3. " RX_SLC_CTRL_3 ,E even positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " RX_SLC_CTRL_2 ,I even negative calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 1. " RX_SLC_CTRL_1 ,Q even negative calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RX_SLC_CTRL_0 ,E even negative calibration unit enable" "Disabled,Enabled" line.word 0x02 "LANE2_RX_SLC_EN_INIT_TMR,RX Sampler Latch Calibration Enable Initialization Timer Value Register Lane 2" bitfld.word 0x02 0.--5. " RX_SLC_EN_INIT_TMR_5_0 ,RX sampler latch calibration enable initialization timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE2_RX_SLC_CU_INIT_TMR,RX Sampler Latch Calibration Unit Initialization Timer Value Register Lane 2" bitfld.word 0x04 0.--5. " RX_SLC_CU_INIT_TMR_5_0 ,RX sampler latch calibration unit initialization timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x06 "LANE2_RX_SLC_CU_ITER_TMR,RX Sampler Latch Calibration Unit Iteration Timer Value Register Lane 2" bitfld.word 0x06 0.--5. " RX_SLC_CU_ITER_TMR_5_0 ,RX sampler latch calibration unit iteration timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "LANE2_RX_SLC_IE_MASK,RX Sampler Latch Calibration I Even Data Mask Register Lane 2" bitfld.word 0x08 9. " RX_SLC_IE_MASK_9 ,I even data mask 9" "Not masked,Masked" bitfld.word 0x08 8. " RX_SLC_IE_MASK_8 ,I even data mask 8" "Not masked,Masked" textline " " bitfld.word 0x08 7. " RX_SLC_IE_MASK_7 ,I even data mask 7" "Not masked,Masked" bitfld.word 0x08 6. " RX_SLC_IE_MASK_6 ,I even data mask 6" "Not masked,Masked" textline " " bitfld.word 0x08 5. " RX_SLC_IE_MASK_5 ,I even data mask 5" "Not masked,Masked" bitfld.word 0x08 4. " RX_SLC_IE_MASK_4 ,I even data mask 4" "Not masked,Masked" textline " " bitfld.word 0x08 3. " RX_SLC_IE_MASK_3 ,I even data mask 3" "Not masked,Masked" bitfld.word 0x08 2. " RX_SLC_IE_MASK_2 ,I even data mask 2" "Not masked,Masked" textline " " bitfld.word 0x08 1. " RX_SLC_IE_MASK_1 ,I even data mask 1" "Not masked,Masked" bitfld.word 0x08 0. " RX_SLC_IE_MASK_0 ,I even data mask 0" "Not masked,Masked" line.word 0x0A "LANE2_RX_SLC_IO_MASK,RX Sampler Latch Calibration I Odd Data Mask Register Lane 2" bitfld.word 0x0A 9. " RX_SLC_IO_MASK_9 ,I odd data mask 9" "Not masked,Masked" bitfld.word 0x0A 8. " RX_SLC_IO_MASK_8 ,I odd data mask 8" "Not masked,Masked" textline " " bitfld.word 0x0A 7. " RX_SLC_IO_MASK_7 ,I odd data mask 7" "Not masked,Masked" bitfld.word 0x0A 6. " RX_SLC_IO_MASK_6 ,I odd data mask 6" "Not masked,Masked" textline " " bitfld.word 0x0A 5. " RX_SLC_IO_MASK_5 ,I odd data mask 5" "Not masked,Masked" bitfld.word 0x0A 4. " RX_SLC_IO_MASK_4 ,I odd data mask 4" "Not masked,Masked" textline " " bitfld.word 0x0A 3. " RX_SLC_IO_MASK_3 ,I odd data mask 3" "Not masked,Masked" bitfld.word 0x0A 2. " RX_SLC_IO_MASK_2 ,I odd data mask 2" "Not masked,Masked" textline " " bitfld.word 0x0A 1. " RX_SLC_IO_MASK_1 ,I odd data mask 1" "Not masked,Masked" bitfld.word 0x0A 0. " RX_SLC_IO_MASK_0 ,I odd data mask 0" "Not masked,Masked" line.word 0x0C "LANE2_RX_SLC_QE_MASK,RX Sampler Latch Calibration Q Even Data Mask Register Lane 2" bitfld.word 0x0C 9. " RX_SLC_QE_MASK_9 ,Q even data mask 9" "Not masked,Masked" bitfld.word 0x0C 8. " RX_SLC_QE_MASK_8 ,Q even data mask 8" "Not masked,Masked" textline " " bitfld.word 0x0C 7. " RX_SLC_QE_MASK_7 ,Q even data mask 7" "Not masked,Masked" bitfld.word 0x0C 6. " RX_SLC_QE_MASK_6 ,Q even data mask 6" "Not masked,Masked" textline " " bitfld.word 0x0C 5. " RX_SLC_QE_MASK_5 ,Q even data mask 5" "Not masked,Masked" bitfld.word 0x0C 4. " RX_SLC_QE_MASK_4 ,Q even data mask 4" "Not masked,Masked" textline " " bitfld.word 0x0C 3. " RX_SLC_QE_MASK_3 ,Q even data mask 3" "Not masked,Masked" bitfld.word 0x0C 2. " RX_SLC_QE_MASK_2 ,Q even data mask 2" "Not masked,Masked" textline " " bitfld.word 0x0C 1. " RX_SLC_QE_MASK_1 ,Q even data mask 1" "Not masked,Masked" bitfld.word 0x0C 0. " RX_SLC_QE_MASK_0 ,Q even data mask 0" "Not masked,Masked" line.word 0x0E "LANE2_RX_SLC_QO_MASK,RX Sampler Latch Calibration Q Odd Data Mask Register Lane 2" bitfld.word 0x0E 9. " RX_SLC_QO_MASK_9 ,Q odd data mask 9" "Not masked,Masked" bitfld.word 0x0E 8. " RX_SLC_QO_MASK_8 ,Q odd data mask 8" "Not masked,Masked" textline " " bitfld.word 0x0E 7. " RX_SLC_QO_MASK_7 ,Q odd data mask 7" "Not masked,Masked" bitfld.word 0x0E 6. " RX_SLC_QO_MASK_6 ,Q odd data mask 6" "Not masked,Masked" textline " " bitfld.word 0x0E 5. " RX_SLC_QO_MASK_5 ,Q odd data mask 5" "Not masked,Masked" bitfld.word 0x0E 4. " RX_SLC_QO_MASK_4 ,Q odd data mask 4" "Not masked,Masked" textline " " bitfld.word 0x0E 3. " RX_SLC_QO_MASK_3 ,Q odd data mask 3" "Not masked,Masked" bitfld.word 0x0E 2. " RX_SLC_QO_MASK_2 ,Q odd data mask 2" "Not masked,Masked" textline " " bitfld.word 0x0E 1. " RX_SLC_QO_MASK_1 ,Q odd data mask 1" "Not masked,Masked" bitfld.word 0x0E 0. " RX_SLC_QO_MASK_0 ,Q odd data mask 0" "Not masked,Masked" line.word 0x10 "LANE2_RX_SLC_EE_MASK,RX Sampler Latch Calibration E Even Data Mask Register Lane 2" bitfld.word 0x10 9. " RX_SLC_EE_MASK_9 ,E even data mask 9" "Not masked,Masked" bitfld.word 0x10 8. " RX_SLC_EE_MASK_8 ,E even data mask 8" "Not masked,Masked" textline " " bitfld.word 0x10 7. " RX_SLC_EE_MASK_7 ,E even data mask 7" "Not masked,Masked" bitfld.word 0x10 6. " RX_SLC_EE_MASK_6 ,E even data mask 6" "Not masked,Masked" textline " " bitfld.word 0x10 5. " RX_SLC_EE_MASK_5 ,E even data mask 5" "Not masked,Masked" bitfld.word 0x10 4. " RX_SLC_EE_MASK_4 ,E even data mask 4" "Not masked,Masked" textline " " bitfld.word 0x10 3. " RX_SLC_EE_MASK_3 ,E even data mask 3" "Not masked,Masked" bitfld.word 0x10 2. " RX_SLC_EE_MASK_2 ,E even data mask 2" "Not masked,Masked" textline " " bitfld.word 0x10 1. " RX_SLC_EE_MASK_1 ,E even data mask 1" "Not masked,Masked" bitfld.word 0x10 0. " RX_SLC_EE_MASK_0 ,E even data mask 0" "Not masked,Masked" line.word 0x12 "LANE2_RX_SLC_EO_MASK,RX Sampler Latch Calibration E Odd Data Mask Register Lane 2" bitfld.word 0x12 9. " RX_SLC_EO_MASK_9 ,E odd data mask 9" "Not masked,Masked" bitfld.word 0x12 8. " RX_SLC_EO_MASK_8 ,E odd data mask 8" "Not masked,Masked" textline " " bitfld.word 0x12 7. " RX_SLC_EO_MASK_7 ,E odd data mask 7" "Not masked,Masked" bitfld.word 0x12 6. " RX_SLC_EO_MASK_6 ,E odd data mask 6" "Not masked,Masked" textline " " bitfld.word 0x12 5. " RX_SLC_EO_MASK_5 ,E odd data mask 5" "Not masked,Masked" bitfld.word 0x12 4. " RX_SLC_EO_MASK_4 ,E odd data mask 4" "Not masked,Masked" textline " " bitfld.word 0x12 3. " RX_SLC_EO_MASK_3 ,E odd data mask 3" "Not masked,Masked" bitfld.word 0x12 2. " RX_SLC_EO_MASK_2 ,E odd data mask 2" "Not masked,Masked" textline " " bitfld.word 0x12 1. " RX_SLC_EO_MASK_1 ,E odd data mask 1" "Not masked,Masked" bitfld.word 0x12 0. " RX_SLC_EO_MASK_0 ,E odd data mask 0" "Not masked,Masked" line.word 0x14 "LANE2_RX_SLC_DATA_THR,RX Sampler Latch Calibration Data Threshold Register Lane 2" bitfld.word 0x14 0.--3. " RX_SLC_DATA_THR_3_0 ,Data threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word (0x8800+0x200)++0xCB line.word 0x00 "LANE2_RX_SLC_IOP0_CTRL,RX Sampler Latch I Odd Positive 0 Calibration Unit Control Register Lane 2" bitfld.word 0x00 15. " RX_SLC_IOP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SLC_IOP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x00 13. " RX_SLC_IOP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x00 12. " RX_SLC_IOP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x00 0.--5. " RX_SLC_IOP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE2_RX_SLC_IOP0_OVRD,RX Sampler Latch I Odd Positive 0 Calibration Unit Override Register Lane 2" bitfld.word 0x02 15. " RX_SLC_IOP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " RX_SLC_IOP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 0.--5. " RX_SLC_IOP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE2_RX_SLC_IOP0_START,RX Sampler Latch I Odd Positive 0 Calibration Unit Start Register Lane 2" bitfld.word 0x04 15. " RX_SLC_IOP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x04 0.--5. " RX_SLC_IOP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x06 "LANE2_RX_SLC_IOP0_TUNE,RX Sampler Latch I Odd Positive 0 Calibration Unit Tune Register Lane 2" bitfld.word 0x06 0.--5. " RX_SLC_IOP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "LANE2_RX_SLC_IOP1_CTRL,RX Sampler Latch I Odd Positive 1 Calibration Unit Control Register Lane 2" bitfld.word 0x08 15. " RX_SLC_IOP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x08 14. " RX_SLC_IOP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x08 13. " RX_SLC_IOP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x08 12. " RX_SLC_IOP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x08 0.--5. " RX_SLC_IOP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0A "LANE2_RX_SLC_IOP1_OVRD,RX Sampler Latch I Odd Positive 1 Calibration Unit Override Register Lane 2" bitfld.word 0x0A 15. " RX_SLC_IOP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x0A 14. " RX_SLC_IOP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x0A 0.--5. " RX_SLC_IOP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0C "LANE2_RX_SLC_IOP1_START,RX Sampler Latch I Odd Positive 1 Calibration Unit Start Register Lane 2" bitfld.word 0x0C 15. " RX_SLC_IOP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x0C 0.--5. " RX_SLC_IOP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0E "LANE2_RX_SLC_IOP1_TUNE,RX Sampler Latch I Odd Positive 1 Calibration Unit Tune Register Lane 2" bitfld.word 0x0E 0.--5. " RX_SLC_IOP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x10 "LANE2_RX_SLC_QOP0_CTRL,RX Sampler Latch Q Odd Positive 0 Calibration Unit Control Register Lane 2" bitfld.word 0x10 15. " RX_SLC_QOP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x10 14. " RX_SLC_QOP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x10 13. " RX_SLC_QOP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x10 12. " RX_SLC_QOP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x10 0.--5. " RX_SLC_QOP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x12 "LANE2_RX_SLC_QOP0_OVRD,RX Sampler Latch Q Odd Positive 0 Calibration Unit Override Register Lane 2" bitfld.word 0x12 15. " RX_SLC_QOP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x12 14. " RX_SLC_QOP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x12 0.--5. " RX_SLC_QOP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x14 "LANE2_RX_SLC_QOP0_START,RX Sampler Latch Q Odd Positive 0 Calibration Unit Start Register Lane 2" bitfld.word 0x14 15. " RX_SLC_QOP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x14 0.--5. " RX_SLC_QOP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x16 "LANE2_RX_SLC_QOP0_TUNE,RX Sampler Latch Q Odd Positive 0 Calibration Unit Tune Register Lane 2" bitfld.word 0x16 0.--5. " RX_SLC_QOP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x18 "LANE2_RX_SLC_QOP1_CTRL,RX Sampler Latch Q Odd Positive 1 Calibration Unit Control Register Lane 2" bitfld.word 0x18 15. " RX_SLC_QOP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x18 14. " RX_SLC_QOP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x18 13. " RX_SLC_QOP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x18 12. " RX_SLC_QOP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x18 0.--5. " RX_SLC_QOP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x1A "LANE2_RX_SLC_QOP1_OVRD,RX Sampler Latch Q Odd Positive 1 Calibration Unit Override Register Lane 2" bitfld.word 0x1A 15. " RX_SLC_QOP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x1A 14. " RX_SLC_QOP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x1A 0.--5. " RX_SLC_QOP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x1C "LANE2_RX_SLC_QOP1_START,RX Sampler Latch Q Odd Positive 1 Calibration Unit Start Register Lane 2" bitfld.word 0x1C 15. " RX_SLC_QOP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x1C 0.--5. " RX_SLC_QOP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x1E "LANE2_RX_SLC_QOP1_TUNE,RX Sampler Latch Q Odd Positive 1 Calibration Unit Tune Register Lane 2" bitfld.word 0x1E 0.--5. " RX_SLC_QOP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x20 "LANE2_RX_SLC_EOP0_CTRL,RX Sampler Latch E Odd Positive 0 Calibration Unit Control Register Lane 2" bitfld.word 0x20 15. " RX_SLC_EOP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x20 14. " RX_SLC_EOP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x20 13. " RX_SLC_EOP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x20 12. " RX_SLC_EOP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x20 0.--5. " RX_SLC_EOP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x22 "LANE2_RX_SLC_EOP0_OVRD,RX Sampler Latch E Odd Positive 0 Calibration Unit Override Register Lane 2" bitfld.word 0x22 15. " RX_SLC_EOP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x22 14. " RX_SLC_EOP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x22 0.--5. " RX_SLC_EOP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x24 "LANE2_RX_SLC_EOP0_START,RX Sampler Latch E Odd Positive 0 Calibration Unit Start Register Lane 2" bitfld.word 0x24 15. " RX_SLC_EOP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x24 0.--5. " RX_SLC_EOP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x26 "LANE2_RX_SLC_EOP0_TUNE,RX Sampler Latch E Odd Positive 0 Calibration Unit Tune Register Lane 2" bitfld.word 0x26 0.--5. " RX_SLC_EOP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x28 "LANE2_RX_SLC_EOP1_CTRL,RX Sampler Latch E Odd Positive 1 Calibration Unit Control Register Lane 2" bitfld.word 0x28 15. " RX_SLC_EOP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x28 14. " RX_SLC_EOP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x28 13. " RX_SLC_EOP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x28 12. " RX_SLC_EOP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x28 0.--5. " RX_SLC_EOP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x2A "LANE2_RX_SLC_EOP1_OVRD,RX Sampler Latch E Odd Positive 1 Calibration Unit Override Register Lane 2" bitfld.word 0x2A 15. " RX_SLC_EOP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x2A 14. " RX_SLC_EOP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x2A 0.--5. " RX_SLC_EOP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x2C "LANE2_RX_SLC_EOP1_START,RX Sampler Latch E Odd Positive 1 Calibration Unit Start Register Lane 2" bitfld.word 0x2C 15. " RX_SLC_EOP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x2C 0.--5. " RX_SLC_EOP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x2E "LANE2_RX_SLC_EOP1_TUNE,RX Sampler Latch E Odd Positive 1 Calibration Unit Tune Register Lane 2" bitfld.word 0x2E 0.--5. " RX_SLC_EOP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x30 "LANE2_RX_SLC_ION0_CTRL,RX Sampler Latch I Odd Negative 0 Calibration Unit Control Register Lane 2" bitfld.word 0x30 15. " RX_SLC_ION0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x30 14. " RX_SLC_ION0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x30 13. " RX_SLC_ION0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x30 12. " RX_SLC_ION0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x30 0.--5. " RX_SLC_ION0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x32 "LANE2_RX_SLC_ION0_OVRD,RX Sampler Latch I Odd Negative 0 Calibration Unit Override Register Lane 2" bitfld.word 0x32 15. " RX_SLC_ION0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x32 14. " RX_SLC_ION0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x32 0.--5. " RX_SLC_ION0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x34 "LANE2_RX_SLC_ION0_START,RX Sampler Latch I Odd Negative 0 Calibration Unit Start Register Lane 2" bitfld.word 0x34 15. " RX_SLC_ION0_START_15 ,Calibration direction" "0,1" bitfld.word 0x34 0.--5. " RX_SLC_ION0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x36 "LANE2_RX_SLC_ION0_TUNE,RX Sampler Latch I Odd Negative 0 Calibration Unit Tune Register Lane 2" bitfld.word 0x36 0.--5. " RX_SLC_ION0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x38 "LANE2_RX_SLC_ION1_CTRL,RX Sampler Latch I Odd Negative 1 Calibration Unit Control Register Lane 2" bitfld.word 0x38 15. " RX_SLC_ION1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x38 14. " RX_SLC_ION1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x38 13. " RX_SLC_ION1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x38 12. " RX_SLC_ION1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x38 0.--5. " RX_SLC_ION1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x3A "LANE2_RX_SLC_ION1_OVRD,RX Sampler Latch I Odd Negative 1 Calibration Unit Override Register Lane 2" bitfld.word 0x3A 15. " RX_SLC_ION1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x3A 14. " RX_SLC_ION1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x3A 0.--5. " RX_SLC_ION1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x3C "LANE2_RX_SLC_ION1_START,RX Sampler Latch I Odd Negative 1 Calibration Unit Start Register Lane 2" bitfld.word 0x3C 15. " RX_SLC_ION1_START_15 ,Calibration direction" "0,1" bitfld.word 0x3C 0.--5. " RX_SLC_ION1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x3E "LANE2_RX_SLC_ION1_TUNE,RX Sampler Latch I Odd Negative 1 Calibration Unit Tune Register Lane 2" bitfld.word 0x3E 0.--5. " RX_SLC_ION1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x40 "LANE2_RX_SLC_QON0_CTRL,RX Sampler Latch Q Odd Negative 0 Calibration Unit Control Register Lane 2" bitfld.word 0x40 15. " RX_SLC_QON0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x40 14. " RX_SLC_QON0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x40 13. " RX_SLC_QON0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x40 12. " RX_SLC_QON0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x40 0.--5. " RX_SLC_QON0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x42 "LANE2_RX_SLC_QON0_OVRD,RX Sampler Latch Q Odd Negative 0 Calibration Unit Override Register Lane 2" bitfld.word 0x42 15. " RX_SLC_QON0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x42 14. " RX_SLC_QON0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x42 0.--5. " RX_SLC_QON0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x44 "LANE2_RX_SLC_QON0_START,RX Sampler Latch Q Odd Negative 0 Calibration Unit Start Register Lane 2" bitfld.word 0x44 15. " RX_SLC_QON0_START_15 ,Calibration direction" "0,1" bitfld.word 0x44 0.--5. " RX_SLC_QON0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x46 "LANE2_RX_SLC_QON0_TUNE,RX Sampler Latch Q Odd Negative 0 Calibration Unit Tune Register Lane 2" bitfld.word 0x46 0.--5. " RX_SLC_QON0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x48 "LANE2_RX_SLC_QON1_CTRL,RX Sampler Latch Q Odd Negative 1 Calibration Unit Control Register Lane 2" bitfld.word 0x48 15. " RX_SLC_QON1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x48 14. " RX_SLC_QON1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x48 13. " RX_SLC_QON1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x48 12. " RX_SLC_QON1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x48 0.--5. " RX_SLC_QON1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x4A "LANE2_RX_SLC_QON1_OVRD,RX Sampler Latch Q Odd Negative 1 Calibration Unit Override Register Lane 2" bitfld.word 0x4A 15. " RX_SLC_QON1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x4A 14. " RX_SLC_QON1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x4A 0.--5. " RX_SLC_QON1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x4C "LANE2_RX_SLC_QON1_START,RX Sampler Latch Q Odd Negative 1 Calibration Unit Start Register Lane 2" bitfld.word 0x4C 15. " RX_SLC_QON1_START_15 ,Calibration direction" "0,1" bitfld.word 0x4C 0.--5. " RX_SLC_QON1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x4E "LANE2_RX_SLC_QON1_TUNE,RX Sampler Latch Q Odd Negative 1 Calibration Unit Tune Register Lane 2" bitfld.word 0x4E 0.--5. " RX_SLC_QON1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x50 "LANE2_RX_SLC_EON0_CTRL,RX Sampler Latch E Odd Negative 0 Calibration Unit Control Register Lane 2" bitfld.word 0x50 15. " RX_SLC_EON0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x50 14. " RX_SLC_EON0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x50 13. " RX_SLC_EON0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x50 12. " RX_SLC_EON0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x50 0.--5. " RX_SLC_EON0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x52 "LANE2_RX_SLC_EON0_OVRD,RX Sampler Latch E Odd Negative 0 Calibration Unit Override Register Lane 2" bitfld.word 0x52 15. " RX_SLC_EON0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x52 14. " RX_SLC_EON0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x52 0.--5. " RX_SLC_EON0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x54 "LANE2_RX_SLC_EON0_START,RX Sampler Latch E Odd Negative 0 Calibration Unit Start Register Lane 2" bitfld.word 0x54 15. " RX_SLC_EON0_START_15 ,Calibration direction" "0,1" bitfld.word 0x54 0.--5. " RX_SLC_EON0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x56 "LANE2_RX_SLC_EON0_TUNE,RX Sampler Latch E Odd Negative 0 Calibration Unit Tune Register Lane 2" bitfld.word 0x56 0.--5. " RX_SLC_EON0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x58 "LANE2_RX_SLC_EON1_CTRL,RX Sampler Latch E Odd Negative 1 Calibration Unit Control Register Lane 2" bitfld.word 0x58 15. " RX_SLC_EON1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x58 14. " RX_SLC_EON1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x58 13. " RX_SLC_EON1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x58 12. " RX_SLC_EON1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x58 0.--5. " RX_SLC_EON1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x5A "LANE2_RX_SLC_EON1_OVRD,RX Sampler Latch E Odd Negative 1 Calibration Unit Override Register Lane 2" bitfld.word 0x5A 15. " RX_SLC_EON1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x5A 14. " RX_SLC_EON1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x5A 0.--5. " RX_SLC_EON1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x5C "LANE2_RX_SLC_EON1_START,RX Sampler Latch E Odd Negative 1 Calibration Unit Start Register Lane 2" bitfld.word 0x5C 15. " RX_SLC_EON1_START_15 ,Calibration direction" "0,1" bitfld.word 0x5C 0.--5. " RX_SLC_EON1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x5E "LANE2_RX_SLC_EON1_TUNE,RX Sampler Latch E Odd Negative 1 Calibration Unit Tune Register Lane 2" bitfld.word 0x5E 0.--5. " RX_SLC_EON1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x60 "LANE2_RX_SLC_IEP0_CTRL,RX Sampler Latch I Even Positive 0 Calibration Unit Control Register Lane 2" bitfld.word 0x60 15. " RX_SLC_IEP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x60 14. " RX_SLC_IEP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x60 13. " RX_SLC_IEP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x60 12. " RX_SLC_IEP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x60 0.--5. " RX_SLC_IEP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x62 "LANE2_RX_SLC_IEP0_OVRD,RX Sampler Latch I Even Positive 0 Calibration Unit Override Register Lane 2" bitfld.word 0x62 15. " RX_SLC_IEP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x62 14. " RX_SLC_IEP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x62 0.--5. " RX_SLC_IEP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x64 "LANE2_RX_SLC_IEP0_START,RX Sampler Latch I Even Positive 0 Calibration Unit Start Register Lane 2" bitfld.word 0x64 15. " RX_SLC_IEP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x64 0.--5. " RX_SLC_IEP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x66 "LANE2_RX_SLC_IEP0_TUNE,RX Sampler Latch I Even Positive 0 Calibration Unit Tune Register Lane 2" bitfld.word 0x66 0.--5. " RX_SLC_IEP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x68 "LANE2_RX_SLC_IEP1_CTRL,RX Sampler Latch I Even Positive 1 Calibration Unit Control Register Lane 2" bitfld.word 0x68 15. " RX_SLC_IEP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x68 14. " RX_SLC_IEP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x68 13. " RX_SLC_IEP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x68 12. " RX_SLC_IEP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x68 0.--5. " RX_SLC_IEP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x6A "LANE2_RX_SLC_IEP1_OVRD,RX Sampler Latch I Even Positive 1 Calibration Unit Override Register Lane 2" bitfld.word 0x6A 15. " RX_SLC_IEP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x6A 14. " RX_SLC_IEP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x6A 0.--5. " RX_SLC_IEP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x6C "LANE2_RX_SLC_IEP1_START,RX Sampler Latch I Even Positive 1 Calibration Unit Start Register Lane 2" bitfld.word 0x6C 15. " RX_SLC_IEP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x6C 0.--5. " RX_SLC_IEP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x6E "LANE2_RX_SLC_IEP1_TUNE,RX Sampler Latch I Even Positive 1 Calibration Unit Tune Register Lane 2" bitfld.word 0x6E 0.--5. " RX_SLC_IEP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x70 "LANE2_RX_SLC_QEP0_CTRL,RX Sampler Latch Q Even Positive 0 Calibration Unit Control Register Lane 2" bitfld.word 0x70 15. " RX_SLC_QEP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x70 14. " RX_SLC_QEP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x70 13. " RX_SLC_QEP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x70 12. " RX_SLC_QEP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x70 0.--5. " RX_SLC_QEP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x72 "LANE2_RX_SLC_QEP0_OVRD,RX Sampler Latch Q Even Positive 0 Calibration Unit Override Register Lane 2" bitfld.word 0x72 15. " RX_SLC_QEP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x72 14. " RX_SLC_QEP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x72 0.--5. " RX_SLC_QEP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x74 "LANE2_RX_SLC_QEP0_START,RX Sampler Latch Q Even Positive 0 Calibration Unit Start Register Lane 2" bitfld.word 0x74 15. " RX_SLC_QEP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x74 0.--5. " RX_SLC_QEP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x76 "LANE2_RX_SLC_QEP0_TUNE,RX Sampler Latch Q Even Positive 0 Calibration Unit Tune Register Lane 2" bitfld.word 0x76 0.--5. " RX_SLC_QEP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x78 "LANE2_RX_SLC_QEP1_CTRL,RX Sampler Latch Q Even Positive 1 Calibration Unit Control Register Lane 2" bitfld.word 0x78 15. " RX_SLC_QEP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x78 14. " RX_SLC_QEP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x78 13. " RX_SLC_QEP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x78 12. " RX_SLC_QEP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x78 0.--5. " RX_SLC_QEP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x7A "LANE2_RX_SLC_QEP1_OVRD,RX Sampler Latch Q Even Positive 1 Calibration Unit Override Register Lane 2" bitfld.word 0x7A 15. " RX_SLC_QEP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x7A 14. " RX_SLC_QEP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x7A 0.--5. " RX_SLC_QEP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x7C "LANE2_RX_SLC_QEP1_START,RX Sampler Latch Q Even Positive 1 Calibration Unit Start Register Lane 2" bitfld.word 0x7C 15. " RX_SLC_QEP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x7C 0.--5. " RX_SLC_QEP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x7E "LANE2_RX_SLC_QEP1_TUNE,RX Sampler Latch Q Even Positive 1 Calibration Unit Tune Register Lane2" bitfld.word 0x7E 0.--5. " RX_SLC_QEP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x80 "LANE2_RX_SLC_EEP0_CTRL,RX Sampler Latch E Even Positive 0 Calibration Unit Control Register Lane 2" bitfld.word 0x80 15. " RX_SLC_EEP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x80 14. " RX_SLC_EEP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x80 13. " RX_SLC_EEP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x80 12. " RX_SLC_EEP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x80 0.--5. " RX_SLC_EEP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x82 "LANE2_RX_SLC_EEP0_OVRD,RX Sampler Latch E Even Positive 0 Calibration Unit Override Register Lane 2" bitfld.word 0x82 15. " RX_SLC_EEP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x82 14. " RX_SLC_EEP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x82 0.--5. " RX_SLC_EEP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x84 "LANE2_RX_SLC_EEP0_START,RX Sampler Latch E Even Positive 0 Calibration Unit Start Register Lane 2" bitfld.word 0x84 15. " RX_SLC_EEP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x84 0.--5. " RX_SLC_EEP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x86 "LANE2_RX_SLC_EEP0_TUNE,RX Sampler Latch E Even Positive 0 Calibration Unit Tune Register Lane2" bitfld.word 0x86 0.--5. " RX_SLC_EEP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x88 "LANE2_RX_SLC_EEP1_CTRL,RX Sampler Latch E Even Positive 1 Calibration Unit Control Register Lane 2" bitfld.word 0x88 15. " RX_SLC_EEP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x88 14. " RX_SLC_EEP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x88 13. " RX_SLC_EEP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x88 12. " RX_SLC_EEP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x88 0.--5. " RX_SLC_EEP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x8A "LANE2_RX_SLC_EEP1_OVRD,RX Sampler Latch E Even Positive 1 Calibration Unit Override Register Lane 2" bitfld.word 0x8A 15. " RX_SLC_EEP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x8A 14. " RX_SLC_EEP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x8A 0.--5. " RX_SLC_EEP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x8C "LANE2_RX_SLC_EEP1_START,RX Sampler Latch E Even Positive 1 Calibration Unit Start Register Lane 2" bitfld.word 0x8C 15. " RX_SLC_EEP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x8C 0.--5. " RX_SLC_EEP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x8E "LANE2_RX_SLC_EEP1_TUNE,RX Sampler Latch E Even Positive 1 Calibration Unit Tune Register Lane 2" bitfld.word 0x8E 0.--5. " RX_SLC_EEP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x90 "LANE2_RX_SLC_IEN0_CTRL,RX Sampler Latch I Even Negative 0 Calibration Unit Control Register Lane 2" bitfld.word 0x90 15. " RX_SLC_IEN0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x90 14. " RX_SLC_IEN0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x90 13. " RX_SLC_IEN0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x90 12. " RX_SLC_IEN0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x90 0.--5. " RX_SLC_IEN0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x92 "LANE2_RX_SLC_IEN0_OVRD,RX Sampler Latch I Even Negative 0 Calibration Unit Override Register Lane 2" bitfld.word 0x92 15. " RX_SLC_IEN0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x92 14. " RX_SLC_IEN0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x92 0.--5. " RX_SLC_IEN0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x94 "LANE2_RX_SLC_IEN0_START,RX Sampler Latch I Even Negative 0 Calibration Unit Start Register Lane 2" bitfld.word 0x94 15. " RX_SLC_IEN0_START_15 ,Calibration direction" "0,1" bitfld.word 0x94 0.--5. " RX_SLC_IEN0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x96 "LANE2_RX_SLC_IEN0_TUNE,RX Sampler Latch I Even Negative 0 Calibration Unit Tune Register Lane 2" bitfld.word 0x96 0.--5. " RX_SLC_IEN0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x98 "LANE2_RX_SLC_IEN1_CTRL,RX Sampler Latch I Even Negative 1 Calibration Unit Control Register Lane 2" bitfld.word 0x98 15. " RX_SLC_IEN1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x98 14. " RX_SLC_IEN1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x98 13. " RX_SLC_IEN1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x98 12. " RX_SLC_IEN1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x98 0.--5. " RX_SLC_IEN1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x9A "LANE2_RX_SLC_IEN1_OVRD,RX Sampler Latch I Even Negative 1 Calibration Unit Override Register Lane 2" bitfld.word 0x9A 15. " RX_SLC_IEN1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x9A 14. " RX_SLC_IEN1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x9A 0.--5. " RX_SLC_IEN1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x9C "LANE2_RX_SLC_IEN1_START,RX Sampler Latch I Even Negative 1 Calibration Unit Start Register Lane 2" bitfld.word 0x9C 15. " RX_SLC_IEN1_START_15 ,Calibration direction" "0,1" bitfld.word 0x9C 0.--5. " RX_SLC_IEN1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x9E "LANE2_RX_SLC_IEN1_TUNE,RX Sampler Latch I Even Negative 1 Calibration Unit Tune Register Lane 2" bitfld.word 0x9E 0.--5. " RX_SLC_IEN1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA0 "LANE2_RX_SLC_QEN0_CTRL,RX Sampler Latch Q Even Negative 0 Calibration Unit Control Register Lane 2" bitfld.word 0xA0 15. " RX_SLC_QEN0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xA0 14. " RX_SLC_QEN0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xA0 13. " RX_SLC_QEN0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xA0 12. " RX_SLC_QEN0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xA0 0.--5. " RX_SLC_QEN0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA2 "LANE2_RX_SLC_QEN0_OVRD,RX Sampler Latch Q Even Negative 0 Calibration Unit Override Register Lane 2" bitfld.word 0xA2 15. " RX_SLC_QEN0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xA2 14. " RX_SLC_QEN0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xA2 0.--5. " RX_SLC_QEN0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA4 "LANE2_RX_SLC_QEN0_START,RX Sampler Latch Q Even Negative 0 Calibration Unit Start Register Lane 2" bitfld.word 0xA4 15. " RX_SLC_QEN0_START_15 ,Calibration direction" "0,1" bitfld.word 0xA4 0.--5. " RX_SLC_QEN0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA6 "LANE2_RX_SLC_QEN0_TUNE,RX Sampler Latch Q Even Negative 0 Calibration Unit Tune Register Lane 2" bitfld.word 0xA6 0.--5. " RX_SLC_QEN0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA8 "LANE2_RX_SLC_QEN1_CTRL,RX Sampler Latch Q Even Negative 1 Calibration Unit Control Register Lane 2" bitfld.word 0xA8 15. " RX_SLC_QEN1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xA8 14. " RX_SLC_QEN1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xA8 13. " RX_SLC_QEN1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xA8 12. " RX_SLC_QEN1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xA8 0.--5. " RX_SLC_QEN1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xAA "LANE2_RX_SLC_QEN1_OVRD,RX Sampler Latch Q Even Negative 1 Calibration Unit Override Register Lane 2" bitfld.word 0xAA 15. " RX_SLC_QEN1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xAA 14. " RX_SLC_QEN1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xAA 0.--5. " RX_SLC_QEN1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xAC "LANE2_RX_SLC_QEN1_START,RX Sampler Latch Q Even Negative 1 Calibration Unit Start Register Lane 2" bitfld.word 0xAC 15. " RX_SLC_QEN1_START_15 ,Calibration direction" "0,1" bitfld.word 0xAC 0.--5. " RX_SLC_QEN1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xAE "LANE2_RX_SLC_QEN1_TUNE,RX Sampler Latch Q Even Negative 1 Calibration Unit Tune Register Lane 2" bitfld.word 0xAE 0.--5. " RX_SLC_QEN1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB0 "LANE2_RX_SLC_EEN0_CTRL,RX Sampler Latch E Even Negative 0 Calibration Unit Control Register Lane 2" bitfld.word 0xB0 15. " RX_SLC_EEN0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xB0 14. " RX_SLC_EEN0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xB0 13. " RX_SLC_EEN0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xB0 12. " RX_SLC_EEN0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xB0 0.--5. " RX_SLC_EEN0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB2 "LANE2_RX_SLC_EEN0_OVRD,RX Sampler Latch E Even Negative 0 Calibration Unit Override Register Lane 2" bitfld.word 0xB2 15. " RX_SLC_EEN0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xB2 14. " RX_SLC_EEN0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xB2 0.--5. " RX_SLC_EEN0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB4 "LANE2_RX_SLC_EEN0_START,RX Sampler Latch E Even Negative 0 Calibration Unit Start Register Lane 2" bitfld.word 0xB4 15. " RX_SLC_EEN0_START_15 ,Calibration direction" "0,1" bitfld.word 0xB4 0.--5. " RX_SLC_EEN0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB6 "LANE2_RX_SLC_EEN0_TUNE,RX Sampler Latch E Even Negative 0 Calibration Unit Tune Register 2" bitfld.word 0xB6 0.--5. " RX_SLC_EEN0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB8 "LANE2_RX_SLC_EEN1_CTRL,RX Sampler Latch E Even Negative 1 Calibration Unit Control Register Lane 2" bitfld.word 0xB8 15. " RX_SLC_EEN1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xB8 14. " RX_SLC_EEN1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xB8 13. " RX_SLC_EEN1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xB8 12. " RX_SLC_EEN1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xB8 0.--5. " RX_SLC_EEN1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xBA "LANE2_RX_SLC_EEN1_OVRD,RX Sampler Latch E Even Negative 1 Calibration Unit Override Register Lane 2" bitfld.word 0xBA 15. " RX_SLC_EEN1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xBA 14. " RX_SLC_EEN1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xBA 0.--5. " RX_SLC_EEN1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xBC "LANE2_RX_SLC_EEN1_START,RX Sampler Latch E Even Negative 1 Calibration Unit Start Register Lane 2" bitfld.word 0xBC 15. " RX_SLC_EEN1_START_15 ,Calibration direction" "0,1" bitfld.word 0xBC 0.--5. " RX_SLC_EEN1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xBE "LANE2_RX_SLC_EEN1_TUNE,RX Sampler Latch E Even Negative 1 Calibration Unit Tune Register Lane 2" bitfld.word 0xBE 0.--5. " RX_SLC_EEN1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xC0 "LANE2_RX_REE_U3GCSM_CTRL,REE USB 3 General Control State Machine Control Register Lane 2" bitfld.word 0xC0 1. " RX_REE_U3GCSM_CTRL_1 ,Force run equalization" "Not forced,Forced" bitfld.word 0xC0 0. " RX_REE_U3GCSM_CTRL_0 ,General control state machine function enable" "Disabled,Enabled" line.word 0xC2 "LANE2_RX_REE_U3GCSM_EQENM_PH1,REE USB 3 General Control State Machine Phase 1 Equalization Enable Mask Register Lane 2" bitfld.word 0xC2 14. " RX_REE_U3GCSM_EQENM_PH1_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0xC2 9. " RX_REE_U3GCSM_EQENM_PH1_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0xC2 8. " RX_REE_U3GCSM_EQENM_PH1_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0xC2 7. " RX_REE_U3GCSM_EQENM_PH1_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0xC2 6. " RX_REE_U3GCSM_EQENM_PH1_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0xC2 5. " RX_REE_U3GCSM_EQENM_PH1_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0xC2 2. " RX_REE_U3GCSM_EQENM_PH1_2 ,RX tap 3" "0,1" bitfld.word 0xC2 1. " RX_REE_U3GCSM_EQENM_PH1_1 ,RX tap 2" "0,1" textline " " bitfld.word 0xC2 0. " RX_REE_U3GCSM_EQENM_PH1_0 ,RX tap 1" "0,1" line.word 0xC4 "LANE2_RX_REE_U3GCSM_EQENM_PH2,REE USB 3 General Control State Machine Phase 2 Equalization Enable Mask Register Lane 2" bitfld.word 0xC4 14. " RX_REE_U3GCSM_EQENM_PH2_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0xC4 9. " RX_REE_U3GCSM_EQENM_PH2_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0xC4 8. " RX_REE_U3GCSM_EQENM_PH2_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0xC4 7. " RX_REE_U3GCSM_EQENM_PH2_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0xC4 6. " RX_REE_U3GCSM_EQENM_PH2_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0xC4 5. " RX_REE_U3GCSM_EQENM_PH2_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0xC4 2. " RX_REE_U3GCSM_EQENM_PH2_2 ,RX tap 3" "0,1" bitfld.word 0xC4 1. " RX_REE_U3GCSM_EQENM_PH2_1 ,RX tap 2" "0,1" textline " " bitfld.word 0xC4 0. " RX_REE_U3GCSM_EQENM_PH2_0 ,RX tap 1" "0,1" line.word 0xC6 "LANE2_RX_REE_U3GCSM_START_TMR,REE USB 3 General Control State Machine Start Timer Value Register Lane 2" line.word 0xC8 "LANE2_RX_REE_U3GCSM_RUN_PH1_TMR,REE USB 3 General Control State Machine Run Phase 1 Timer Value Register Lane 2" line.word 0xCA "LANE2_RX_REE_U3GCSM_RUN_PH2_TMR,REE USB 3 General Control State Machine Run Phase 2 Timer Value Register Lane 2" group.word (0x8800+0xD0)++0x0B line.word 0x00 "LANE2_RX_REE_G2GCSM_CTRL,REE PCIe Gen 2 General Control State Machine Control Register Lane 2" bitfld.word 0x00 1. " RX_REE_G2GCSM_CTRL_1 ,Force run equalization" "Not forced,Forced" bitfld.word 0x00 0. " RX_REE_G2GCSM_CTRL_0 ,General control state machine function enable" "Disabled,Enabled" line.word 0x02 "LANE2_RX_REE_G2GCSM_EQENM_PH1,REE PCIe Gen 2 General Control State Machine Phase 1 Equalization Enable Mask Register Lane 2" bitfld.word 0x02 14. " RX_REE_G2GCSM_EQENM_PH1_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x02 9. " RX_REE_G2GCSM_EQENM_PH1_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x02 8. " RX_REE_G2GCSM_EQENM_PH1_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x02 7. " RX_REE_G2GCSM_EQENM_PH1_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x02 6. " RX_REE_G2GCSM_EQENM_PH1_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x02 5. " RX_REE_G2GCSM_EQENM_PH1_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x02 2. " RX_REE_G2GCSM_EQENM_PH1_2 ,RX tap 3" "0,1" bitfld.word 0x02 1. " RX_REE_G2GCSM_EQENM_PH1_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x02 0. " RX_REE_G2GCSM_EQENM_PH1_0 ,RX tap 1" "0,1" line.word 0x04 "LANE2_RX_REE_G2GCSM_EQENM_PH2,REE USB 2 General Control State Machine Phase 2 Equalization Enable Mask Register Lane 2" bitfld.word 0x04 14. " RX_REE_G2GCSM_EQENM_PH2_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x04 9. " RX_REE_G2GCSM_EQENM_PH2_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x04 8. " RX_REE_G2GCSM_EQENM_PH2_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x04 7. " RX_REE_G2GCSM_EQENM_PH2_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x04 6. " RX_REE_G2GCSM_EQENM_PH2_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x04 5. " RX_REE_G2GCSM_EQENM_PH2_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x04 2. " RX_REE_G2GCSM_EQENM_PH2_2 ,RX tap 3" "0,1" bitfld.word 0x04 1. " RX_REE_G2GCSM_EQENM_PH2_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x04 0. " RX_REE_G2GCSM_EQENM_PH2_0 ,RX tap 1" "0,1" line.word 0x06 "LANE2_RX_REE_G2GCSM_START_TMR,REE PCIe Gen 2 General Control State Machine Start Timer Value Register Lane 2" line.word 0x08 "LANE2_RX_REE_G2GCSM_RUN_PH1_TMR,REE PCIe Gen 2 General Control State Machine Run Phase 1 Timer Value Register Lane 2" line.word 0x0A "LANE2_RX_REE_G2GCSM_RUN_PH2_TMR,REE PCIe Gen 2 General Control State Machine Run Phase 2 Timer Value Register Lane 2" group.word (0x8800+0xF0)++0x0B line.word 0x00 "LANE2_RX_REE_PERGCSM_CTRL,REE Periodic General Control State Machine Control Register Lane 2" bitfld.word 0x00 1. " RX_REE_PERGCSM_CTRL_1 ,Force run equalization" "Not forced,Forced" bitfld.word 0x00 0. " RX_REE_PERGCSM_CTRL_0 ,General control state machine function enable" "Disabled,Enabled" line.word 0x02 "LANE2_RX_REE_PERGCSM_EQENM_PH1,REE Periodic General Control State Machine Phase 1 Equalization Enable Mask Register Lane 2" bitfld.word 0x02 14. " RX_REE_PERGCSM_EQENM_PH1_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x02 9. " RX_REE_PERGCSM_EQENM_PH1_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x02 8. " RX_REE_PERGCSM_EQENM_PH1_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x02 7. " RX_REE_PERGCSM_EQENM_PH1_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x02 6. " RX_REE_PERGCSM_EQENM_PH1_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x02 5. " RX_REE_PERGCSM_EQENM_PH1_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x02 2. " RX_REE_PERGCSM_EQENM_PH1_2 ,RX tap 3" "0,1" bitfld.word 0x02 1. " RX_REE_PERGCSM_EQENM_PH1_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x02 0. " RX_REE_PERGCSM_EQENM_PH1_0 ,RX tap 1" "0,1" line.word 0x04 "LANE2_RX_REE_PERGCSM_EQENM_PH2,REE Periodic General Control State Machine Phase 2 Equalization Enable Mask Register Lane 2" bitfld.word 0x04 14. " RX_REE_PERGCSM_EQENM_PH2_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x04 9. " RX_REE_PERGCSM_EQENM_PH2_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x04 8. " RX_REE_PERGCSM_EQENM_PH2_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x04 7. " RX_REE_PERGCSM_EQENM_PH2_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x04 6. " RX_REE_PERGCSM_EQENM_PH2_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x04 5. " RX_REE_PERGCSM_EQENM_PH2_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x04 2. " RX_REE_PERGCSM_EQENM_PH2_2 ,RX tap 3" "0,1" bitfld.word 0x04 1. " RX_REE_PERGCSM_EQENM_PH2_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x04 0. " RX_REE_PERGCSM_EQENM_PH2_0 ,RX tap 1" "0,1" line.word 0x06 "LANE2_RX_REE_PERGCSM_START_TMR,REE Periodic General Control State Machine Start Timer Value Register Lane 2" line.word 0x08 "LANE2_RX_REE_PERGCSM_RUN_PH1_TMR,REE Periodic General Control State Machine Run Phase 1 Timer Value Register Lane 2" line.word 0x0A "LANE2_RX_REE_PERGCSM_RUN_PH2_TMR,REE Periodic General Control State Machine Run Phase 2 Timer Value Register Lane 2" group.word (0x8800+0x100)++0x05 line.word 0x00 "LANE2_RX_REE_TAP1_CTRL,REE Tap 1 Control Register Lane 2" bitfld.word 0x00 11. " RX_REE_TAP1_CTRL_11 ,Tap coefficient combinational logic zero crossing enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_REE_TAP1_CTRL_10 ,Tap coefficient combinational logic non zero crossing enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_REE_TAP1_CTRL_9 ,Tap coefficient combinational logic bit 0 only enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_REE_TAP1_CTRL_8 ,Receiver DFE tap coefficient disable" "No,Yes" textline " " bitfld.word 0x00 4.--6. " RX_REE_TAP1_CTRL_6_4 ,Tap integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_TAP1_CTRL_3_0 ,Tap sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE2_RX_REE_TAP1_OVRD,REE Tap 1 Override Register Lane 2" bitfld.word 0x02 7. " RX_REE_TAP1_OVRD_7 ,Tap override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_TAP1_OVRD_5_0 ,Tap override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE2_RX_REE_TAP1_DIAG,REE Tap 1 Diagnostics Register Lane 2" bitfld.word 0x04 14. " RX_REE_TAP1_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_TAP1_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_TAP1_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_TAP1_DIAG_5_0 ,Current tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8800+0x108)++0x05 line.word 0x00 "LANE2_RX_REE_TAP2_CTRL,REE Tap 2 Control Register Lane 2" bitfld.word 0x00 11. " RX_REE_TAP2_CTRL_11 ,Tap coefficient combinational logic zero crossing enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_REE_TAP2_CTRL_10 ,Tap coefficient combinational logic non zero crossing enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_REE_TAP2_CTRL_9 ,Tap coefficient combinational logic bit 0 only enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_REE_TAP2_CTRL_8 ,Receiver DFE tap coefficient disable" "No,Yes" textline " " bitfld.word 0x00 4.--6. " RX_REE_TAP2_CTRL_6_4 ,Tap integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_TAP2_CTRL_3_0 ,Tap sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE2_RX_REE_TAP2_OVRD,REE Tap 2 Override Register Lane 2" bitfld.word 0x02 7. " RX_REE_TAP2_OVRD_7 ,Tap override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_TAP2_OVRD_5_0 ,Tap override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE2_RX_REE_TAP2_DIAG,REE Tap 2 Diagnostics Register Lane 2" bitfld.word 0x04 14. " RX_REE_TAP2_DIAG_14 ,Voter override neg" "No override,Override" bitfld.word 0x04 13. " RX_REE_TAP2_DIAG_13 ,Voter override pos" "0,1" textline " " bitfld.word 0x04 12. " RX_REE_TAP2_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_TAP2_DIAG_5_0 ,Current tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8800+0x110)++0x05 line.word 0x00 "LANE2_RX_REE_TAP3_CTRL,REE Tap 3 Control Register Lane 2" bitfld.word 0x00 11. " RX_REE_TAP3_CTRL_11 ,Tap coefficient combinational logic zero crossing enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_REE_TAP3_CTRL_10 ,Tap coefficient combinational logic non zero crossing enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_REE_TAP3_CTRL_9 ,Tap coefficient combinational logic bit 0 only enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_REE_TAP3_CTRL_8 ,Receiver DFE tap coefficient disable" "No,Yes" textline " " bitfld.word 0x00 4.--6. " RX_REE_TAP3_CTRL_6_4 ,Tap integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_TAP3_CTRL_3_0 ,Tap sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE2_RX_REE_TAP3_OVRD,REE Tap 3 Override Register Lane 2" bitfld.word 0x02 7. " RX_REE_TAP3_OVRD_7 ,Tap override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_TAP3_OVRD_5_0 ,Tap override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE2_RX_REE_TAP3_DIAG,REE Tap 3 Diagnostics Register Lane 2" bitfld.word 0x04 14. " RX_REE_TAP3_DIAG_14 ,Voter override neg" "No override,Override" bitfld.word 0x04 13. " RX_REE_TAP3_DIAG_13 ,Voter override pos" "0,1" textline " " bitfld.word 0x04 12. " RX_REE_TAP3_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_TAP3_DIAG_5_0 ,Current tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8800+0x128)++0x01 line.word 0x00 "LANE2_RX_REE_ANAENSM_DEL_TMR,REE Analog Enable Control State Machine Delay Timer Value Register Lane 2" group.word (0x8800+0x130)++0x0D line.word 0x00 "LANE2_RX_REE_PEAK_CTRL,REE Peaking Amp Control Register Lane 2" bitfld.word 0x00 11. " RX_REE_PEAK_CTRL_11 ,Peaking amp feedback path enable" "Disabled,Enabled" bitfld.word 0x00 8.--10. " RX_REE_PEAK_CTRL_10_8 ,Peaking amp feedback scaler value" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 4.--6. " RX_REE_PEAK_CTRL_6_4 ,Peaking amp integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_PEAK_CTRL_3_0 ,Peaking amp sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE2_RX_REE_PEAK_CODE_CTRL,REE Peaking Amp Code Control Register Lane 2" bitfld.word 0x02 8.--13. " RX_REE_PEAK_CODE_CTRL_13_8 ,Peaking amp code maximum value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x02 0.--5. " RX_REE_PEAK_CODE_CTRL_5_0 ,Peaking amp initial code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE2_RX_REE_PEAK_UTHR,REE Peaking Amp Upper Threshold Register Lane 2" hexmask.word 0x04 0.--8. 1. " RX_REE_PEAK_UTHR_8_0 ,Peaking amp algorithm upper threshold" line.word 0x06 "LANE2_RX_REE_PEAK_LTHR,REE Peaking Amp Lower Threshold Register Lane 2" hexmask.word 0x06 0.--8. 1. " RX_REE_PEAK_LTHR_8_0 ,Peaking amp algorithm lower threshold" line.word 0x08 "LANE2_RX_REE_PEAK_IOVRD,REE Peaking Amp Input Override Register Lane 2" bitfld.word 0x08 15. " RX_REE_PEAK_IOVRD_15 ,Peaking amp tap accumulator input override enable" "Disabled,Enabled" hexmask.word.byte 0x08 0.--7. 1. " RX_REE_PEAK_IOVRD_7_0 ,Peaking amp tap accumulator input override" line.word 0x0A "LANE2_RX_REE_PEAK_COVRD,REE Peaking Amp Code Override Register Lane 2" bitfld.word 0x0A 15. " RX_REE_PEAK_COVRD_15 ,Peaking amp code override enable" "Disabled,Enabled" bitfld.word 0x0A 0.--5. " RX_REE_PEAK_COVRD_5_0 ,Peaking amp code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0C "LANE2_RX_REE_PEAK_DIAG,REE Peaking Amp Diagnostics Register Lane 2" bitfld.word 0x0C 14. " RX_REE_PEAK_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x0C 13. " RX_REE_PEAK_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x0C 12. " RX_REE_PEAK_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x0C 0.--5. " RX_REE_TAP3_DIAG_5_0 ,Current peaking amp integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8800+0x140)++0x07 line.word 0x00 "LANE2_RX_REE_ATTEN_CTRL,REE Attenuation Control Register Lane 2" bitfld.word 0x00 0.--4. " RX_REE_ATTEN_CTRL_4_0 ,Receiver DFE attenuation maximum value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x02 "LANE2_RX_REE_ATTEN_THR,REE Attenuation Threshold Register Lane 2" bitfld.word 0x02 8.--12. " RX_REE_ATTEN_THR_12_8 ,Attenuation high threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--4. " RX_REE_ATTEN_THR_4_0 ,Attenuation low threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE2_RX_REE_ATTEN_CNT,REE Attenuation Counter Register Lane 2" line.word 0x06 "LANE2_RX_REE_ATTEN_OVRD,REE Attenuation Override Register Lane 2" bitfld.word 0x06 8. " RX_REE_ATTEN_OVRD_8 ,Attenuation override enable" "Disabled,Enabled" bitfld.word 0x06 0.--4. " RX_REE_ATTEN_OVRD_4_0 ,Attenuation override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word (0x8800+0x148)++0x01 line.word 0x00 "LANE2_RX_REE_ATTEN_DIAG,REE Attenuation Diagnostics Register Lane 2" bitfld.word 0x00 0.--4. " RX_REE_ATTEN_DIAG_4_0 ,Current attenuation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (0x8800+0x150)++0x05 line.word 0x00 "LANE2_RX_REE_LFEQ_CTRL,REE Low Frequency Equalizer Control Register Lane 2" bitfld.word 0x00 8. " RX_REE_LFEQ_CTRL_8 ,Receiver DFE coefficient disable" "No,Yes" bitfld.word 0x00 4.--6. " RX_REE_LFEQ_CTRL_6_4 ,Integrator accumulator scaler value" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 0.--3. " RX_REE_LFEQ_CTRL_3_0 ,Sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE2_RX_REE_LFEQ_OVRD,REE Low Frequency Equalizer Override Register Lane 2" bitfld.word 0x02 7. " RX_REE_LFEQ_OVRD_7 ,Override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_LFEQ_OVRD_5_0 ,Override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE2_RX_REE_LFEQ_DIAG,REE Low Frequency Equalizer Diagnostics Register Lane 2" bitfld.word 0x04 14. " RX_REE_LFEQ_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_LFEQ_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_LFEQ_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_LFEQ_DIAG_5_0 ,Current integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8800+0x158)++0x05 line.word 0x00 "LANE2_RX_REE_VGA_GAIN_CTRL,REE VGA Gain Control Register Lane 2" bitfld.word 0x00 8.--12. " RX_REE_VGA_GAIN_CTRL_12_8 ,VGA gain max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 4.--6. " RX_REE_VGA_GAIN_CTRL_6_4 ,VGA gain integrator accumulator scaler value" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 0.--3. " RX_REE_VGA_GAIN_CTRL_3_0 ,VGA gain sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE2_RX_REE_VGA_GAIN_OVRD,REE VGA Gain Override Register Lane 2" bitfld.word 0x02 15. " RX_REE_VGA_GAIN_OVRD_15 ,VGA gain target adjust override enable" "Disabled,Enabled" bitfld.word 0x02 8.--12. " RX_REE_VGA_GAIN_OVRD_12_8 ,VGA gain target adjust override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x02 7. " RX_REE_VGA_GAIN_OVRD_7 ,VGA gain override enable" "Disabled,Enabled" bitfld.word 0x02 0.--4. " RX_REE_VGA_GAIN_OVRD_4_0 ,VGA gain override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE2_RX_REE_VGA_GAIN_DIAG,REE VGA Gain Diagnostics Register Lane 2" bitfld.word 0x04 14. " RX_REE_VGA_GAIN_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_VGA_GAIN_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_VGA_GAIN_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_VGA_GAIN_DIAG_5_0 ,Current VGA gain integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.word (0x8800+0x15E)++0x01 line.word 0x00 "LANE2_RX_REE_VGA_GAIN_TGT_DIAG,REE VGA Gain Target Adjust Diagnostics Register Lane 2" bitfld.word 0x00 0.--4. " RX_REE_VGA_GAIN_TGT_DIAG_4_0 ,Current VGA gain integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (0x8800+0x160)++0x05 line.word 0x00 "LANE2_RX_REE_OFF_COR_CTRL,REE Offset Correction Control Register Lane 2" bitfld.word 0x00 4.--6. " RX_REE_OFF_COR_CTRL_6_4 ,Offset correction integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_OFF_COR_CTRL_3_0 ,Offset correction sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE2_RX_REE_OFF_COR_OVRD,REE Offset Correction Override Register Lane 2" bitfld.word 0x02 7. " RX_REE_OFF_COR_OVRD_7 ,Offset correction override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_OFF_COR_OVRD_5_0 ,Offset correction override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE2_RX_REE_OFF_COR_DIAG,REE Offset Correction Diagnostics Register Lane 2" bitfld.word 0x04 14. " RX_REE_OFF_COR_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_OFF_COR_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_OFF_COR_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_OFF_COR_DIAG_5_0 ,Current offset correction integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8800+0x170)++0x0D line.word 0x00 "LANE2_RX_REE_ADDR_CFG,REE Adder Configuration Register Lane 2" bitfld.word 0x00 2. " RX_REE_ADDR_CFG_2 ,RX peaking tap 3 adder enable" "Disabled,Enabled" bitfld.word 0x00 1. " RX_REE_ADDR_CFG_1 ,RX peaking tap 2 adder enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RX_REE_ADDR_CFG_0 ,RX peaking tap 1 adder enable" "Disabled,Enabled" line.word 0x02 "LANE2_RX_REE_ADDR_CFG,REE Tap 1 Clip Control Register Lane 2" bitfld.word 0x02 8.--10. " RX_REE_TAP1_CLIP_10_8 ,VGA target gain adjust multiplier" "0,1,2,3,4,5,6,7" bitfld.word 0x02 0.--4. " RX_REE_TAP1_CLIP_4_0 ,Threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE2_RX_REE_TAP2TON_CLIP,REE Taps 2 And 3 Clip Control Register Lane 2" bitfld.word 0x04 8.--10. " RX_REE_TAP2TON_CLIP_10_8 ,VGA target gain adjust multiplier" "0,1,2,3,4,5,6,7" bitfld.word 0x04 0.--4. " RX_REE_TAP2TON_CLIP_4_0 ,Threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "LANE2_RX_REE_CTRL_DATA_MASK,REE Control Data Mask Register Lane 2" rbitfld.word 0x06 14. " RX_REE_CTRL_DATA_MASK_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x06 9. " RX_REE_CTRL_DATA_MASK_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x06 8. " RX_REE_CTRL_DATA_MASK_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x06 7. " RX_REE_CTRL_DATA_MASK_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x06 6. " RX_REE_CTRL_DATA_MASK_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x06 5. " RX_REE_CTRL_DATA_MASK_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x06 2. " RX_REE_CTRL_DATA_MASK_2 ,RX tap 3" "0,1" bitfld.word 0x06 1. " RX_REE_CTRL_DATA_MASK_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x06 0. " RX_REE_CTRL_DATA_MASK_0 ,RX tap 1" "0,1" line.word 0x08 "LANE2_RX_REE_DIAG_CTRL,REE Diagnostic Control Register Lane 2" bitfld.word 0x08 6. " RX_REE_DIAG_CTRL_6 ,Hold periodic equalization while RX idle" "Not held,Held" bitfld.word 0x08 4. " RX_REE_DIAG_CTRL_4 ,Hold gen 2 equalization while RX idle" "Not held,Held" textline " " bitfld.word 0x08 1. " RX_REE_DIAG_CTRL_1 ,Force REE controller clock on" "Not forced,Forced" bitfld.word 0x08 0. " RX_REE_DIAG_CTRL_0 ,Force REE function clock on" "Not forced,Forced" line.word 0x0A "LANE2_RX_REE_SMGM_CTRL1,REE Control State Machine Gen Mode Control Register 1 Lane 2" bitfld.word 0x0A 15. " RX_REE_SMGM_CTRL1_15 ,REE periodic general control state machine E path enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 14. " RX_REE_SMGM_CTRL1_14 ,REE periodic general control state machine E path enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 13. " RX_REE_SMGM_CTRL1_13 ,REE periodic general control state machine E path enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 12. " RX_REE_SMGM_CTRL1_12 ,REE periodic general control state machine E path enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x0A 11. " RX_REE_SMGM_CTRL1_11 ,REE periodic general control state machine enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 10. " RX_REE_SMGM_CTRL1_10 ,REE periodic general control state machine enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 9. " RX_REE_SMGM_CTRL1_9 ,REE periodic general control state machine enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 8. " RX_REE_SMGM_CTRL1_8 ,REE periodic general control state machine enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x0A 7. " RX_REE_SMGM_CTRL1_7 ,REE Gen 2 general control state machine E path enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 6. " RX_REE_SMGM_CTRL1_6 ,REE Gen 2 general control state machine E path enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 5. " RX_REE_SMGM_CTRL1_5 ,REE Gen 2 general control state machine E path enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 4. " RX_REE_SMGM_CTRL1_4 ,REE Gen 2 general control state machine E path enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x0A 3. " RX_REE_SMGM_CTRL1_3 ,REE Gen 2 general control state machine enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 2. " RX_REE_SMGM_CTRL1_2 ,REE Gen 2 general control state machine enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 1. " RX_REE_SMGM_CTRL1_1 ,REE Gen 2 general control state machine enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 0. " RX_REE_SMGM_CTRL1_0 ,REE Gen 2 general control state machine enable standard mode 0" "Disabled,Enabled" line.word 0x0C "LANE2_RX_REE_SMGM_CTRL2,REE Control State Machine Gen Mode Control Register 2 Lane 2" bitfld.word 0x0C 0. " RX_REE_SMGM_CTRL2_0 ,REE USB 3 general control state machine E path enable" "Disabled,Enabled" group.word (0x8800+0x180)++0x13 line.word 0x00 "LANE2_RX_DIAG_ILL_CTRL,RX ILL Diagnostic Control Register Lane 2" bitfld.word 0x00 3. " RX_DIAG_ILL_CTRL_3 ,IQ PI ILL calibration enable override enable" "Disabled,Enabled" bitfld.word 0x00 2. " RX_DIAG_ILL_CTRL_2 ,IQ PI ILL calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " RX_DIAG_ILL_CTRL_1 ,E PI ILL calibration enable override enable" "Disabled,Enabled" bitfld.word 0x00 0. " RX_DIAG_ILL_CTRL_0 ,E PI ILL calibration enable override" "Disabled,Enabled" line.word 0x02 "LANE2_RX_DIAG_ILL_IQ_TRIM0,RX ILL IQ Trim 0 Register Lane 2" bitfld.word 0x02 12.--14. " RX_DIAG_ILL_IQ_TRIM0_14_12 ,Rx_diag_ill_iq_trim0_14_12" "0,1,2,3,4,5,6,7" bitfld.word 0x02 8.--10. " RX_DIAG_ILL_IQ_TRIM0_10_8 ,Rx_diag_ill_iq_trim0_10_8" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x02 6.--7. " RX_DIAG_ILL_IQ_TRIM0_7_6 ,Rx_diag_ill_iq_trim0_7_6" "0,1,2,3" bitfld.word 0x02 4.--5. " RX_DIAG_ILL_IQ_TRIM0_5_4 ,Rx_diag_ill_iq_trim0_5_4" "0,1,2,3" textline " " bitfld.word 0x02 2.--3. " RX_DIAG_ILL_IQ_TRIM0_3_2 ,Rx_diag_ill_iq_trim0_3_2" "0,1,2,3" bitfld.word 0x02 0.--1. " RX_DIAG_ILL_IQ_TRIM0_1_0 ,Rx_diag_ill_iq_trim0_1_0" "0,1,2,3" line.word 0x04 "LANE2_RX_DIAG_ILL_E_TRIM0,RX ILL E Trim 0 Register Lane 2" bitfld.word 0x04 12.--14. " RX_DIAG_ILL_E_TRIM0_14_12 ,Rx_diag_ill_e_trim0_14_12" "0,1,2,3,4,5,6,7" bitfld.word 0x04 8.--10. " RX_DIAG_ILL_E_TRIM0_10_8 ,Rx_diag_ill_e_trim0_10_8" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x04 6.--7. " RX_DIAG_ILL_E_TRIM0_7_6 ,Rx_diag_ill_e_trim0_7_6" "0,1,2,3" bitfld.word 0x04 4.--5. " RX_DIAG_ILL_E_TRIM0_5_4 ,Rx_diag_ill_e_trim0_5_4" "0,1,2,3" textline " " bitfld.word 0x04 2.--3. " RX_DIAG_ILL_E_TRIM0_3_2 ,Rx_diag_ill_e_trim0_3_2" "0,1,2,3" bitfld.word 0x04 0.--1. " RX_DIAG_ILL_E_TRIM0_1_0 ,Rx_diag_ill_e_trim0_1_0" "0,1,2,3" line.word 0x06 "LANE2_RX_DIAG_ILL_IQ_TRIM1,RX ILL IQ Trim 1 Register Lane 2" bitfld.word 0x06 4.--5. " RX_DIAG_ILL_IQ_TRIM1_5_4 ,Rx_diag_ill_iq_trim1_5_4" "0,1,2,3" bitfld.word 0x06 0.--2. " RX_DIAG_ILL_IQ_TRIM1_2_0 ,Rx_diag_ill_iq_trim1_2_0" "0,1,2,3,4,5,6,7" line.word 0x08 "LANE2_RX_DIAG_ILL_E_TRIM1,RX ILL E Trim 1 Register Lane 2" bitfld.word 0x08 4.--5. " RX_DIAG_ILL_E_TRIM1_5_4 ,Rx_diag_ill_e_trim1_5_4" "0,1,2,3" bitfld.word 0x08 0.--2. " RX_DIAG_ILL_E_TRIM1_2_0 ,Rx_diag_ill_e_trim1_2_0" "0,1,2,3,4,5,6,7" line.word 0x0A "LANE2_RX_DIAG_ILL_IQE_TRIM2,RX ILL IQ E Trim 2 Register Lane 2" bitfld.word 0x0A 14.--15. " RX_DIAG_ILL_IQE_TRIM2_15_14 ,Rx_diag_ill_iqe_trim2_15_14" "0,1,2,3" bitfld.word 0x0A 12.--13. " RX_DIAG_ILL_IQE_TRIM2_13_12 ,Rx_diag_ill_iqe_trim2_13_12" "0,1,2,3" textline " " bitfld.word 0x0A 10.--11. " RX_DIAG_ILL_IQE_TRIM2_11_10 ,Rx_diag_ill_iqe_trim2_11_10" "0,1,2,3" bitfld.word 0x0A 8.--9. " RX_DIAG_ILL_IQE_TRIM2_9_8 ,Rx_diag_ill_iqe_trim2_9_8" "0,1,2,3" textline " " bitfld.word 0x0A 6.--7. " RX_DIAG_ILL_IQE_TRIM2_7_6 ,Rx_diag_ill_iqe_trim2_7_6" "0,1,2,3" bitfld.word 0x0A 4.--5. " RX_DIAG_ILL_IQE_TRIM2_5_4 ,Rx_diag_ill_iqe_trim2_5_4" "0,1,2,3" textline " " bitfld.word 0x0A 2.--3. " RX_DIAG_ILL_IQE_TRIM2_3_2 ,Rx_diag_ill_iqe_trim2_3_2" "0,1,2,3" bitfld.word 0x0A 0.--1. " RX_DIAG_ILL_IQE_TRIM2_1_0 ,Rx_diag_ill_iqe_trim2_1_0" "0,1,2,3" line.word 0x0C "LANE2_RX_DIAG_ILL_IQE_TRIM3,RX ILL IQ E Trim 3 Register Lane 2" hexmask.word.byte 0x0C 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM3_15_8 ,Rx_diag_ill_iqe_trim3_15_8" hexmask.word.byte 0x0C 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM3_7_0 ,Rx_diag_ill_iqe_trim3_7_0" line.word 0x0E "LANE2_RX_DIAG_ILL_IQE_TRIM4,RX ILL IQ E Trim 4 Register Lane 2" hexmask.word.byte 0x0E 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM4_15_8 ,Rx_diag_ill_iqe_trim4_15_8" hexmask.word.byte 0x0E 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM4_7_0 ,Rx_diag_ill_iqe_trim4_7_0" line.word 0x10 "LANE2_RX_DIAG_ILL_IQE_TRIM5,RX ILL IQ E Trim 5 Register Lane 2" hexmask.word.byte 0x10 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM5_15_8 ,Rx_diag_ill_iqe_trim5_15_8" hexmask.word.byte 0x10 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM5_7_0 ,Rx_diag_ill_iqe_trim5_7_0" line.word 0x12 "LANE2_RX_DIAG_ILL_IQE_TRIM6,RX ILL IQ E Trim 6 Register Lane 2" hexmask.word.byte 0x12 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM6_15_8 ,Rx_diag_ill_iqe_trim6_15_8" hexmask.word.byte 0x12 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM6_7_0 ,Rx_diag_ill_iqe_trim6_7_0" group.word (0x8800+0x1A0)++0x11 line.word 0x00 "LANE2_RX_DIAG_DFE_AMP_TUNE,DFE Amp Fine Tuning Register Lane 2" bitfld.word 0x00 12.--14. " RX_DIAG_DFE_AMP_TUNE_14_12 ,DFE constant gm bias tune" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " RX_DIAG_DFE_AMP_TUNE_11 ,DFE VGA constant gm bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--10. " RX_DIAG_DFE_AMP_TUNE_10_8 ,DFE VGA amp current adjust" "0,1,2,3,4,5,6,7" bitfld.word 0x00 7. " RX_DIAG_DFE_AMP_TUNE_7 ,DFE peaking constant gm bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4.--6. " RX_DIAG_DFE_AMP_TUNE_6_4 ,DFE peaking amp current adjust" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " RX_DIAG_DFE_AMP_TUNE_3 ,DFE summing constant gm bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--2. " RX_DIAG_DFE_AMP_TUNE_2_0 ,DFE summing amp current adjust" "0,1,2,3,4,5,6,7" line.word 0x02 "LANE2_RX_DIAG_DFE_AMP_TUNE_2,DFE Amp Fine Tuning 2 Register Lane 2" bitfld.word 0x02 11. " RX_DIAG_DFE_AMP_TUNE_2_11 ,DFE low frequency equalizer constant gm bias enable" "Disabled,Enabled" bitfld.word 0x02 8.--10. " RX_DIAG_DFE_AMP_TUNE_2_10_8 ,DFE low frequency equalizer current adjust" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x02 7. " RX_DIAG_DFE_AMP_TUNE_2_7 ,Enable active inductors boost function in the peaking amp for high data rates" "Disabled,Enabled" bitfld.word 0x02 6. " RX_DIAG_DFE_AMP_TUNE_2_6 ,Enable active inductors boost function in stage 1 of the VGA for high data rates" "Disabled,Enabled" textline " " bitfld.word 0x02 5. " RX_DIAG_DFE_AMP_TUNE_2_5 ,Enable active inductors boost function in stage 2 of the VGA for high data rates" "Disabled,Enabled" bitfld.word 0x02 4. " RX_DIAG_DFE_AMP_TUNE_2_4 ,DFE RX tap 1 DAC range select" "0,1" textline " " bitfld.word 0x02 0.--1. " RX_DIAG_DFE_AMP_TUNE_2_1_0 ,DFE RX amp current adjust" "0,1,2,3" line.word 0x04 "LANE2_RX_DIAG_REE_DAC_CTRL,REE DAC Control Register Lane 2" bitfld.word 0x04 2. " RX_DIAG_REE_DAC_CTRL_2 ,DFE offset DAC enable" "Disabled,Enabled" bitfld.word 0x04 1. " RX_DIAG_REE_DAC_CTRL_1 ,DFE Offset DAC attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x04 0. " RX_DIAG_REE_DAC_CTRL_0 ,DFE DAC attenuation" "No attenuation,Attenuation" line.word 0x06 "LANE2_RX_DIAG_DFE_CTRL1,Receiver DFE Control Register 1 Lane 2" bitfld.word 0x06 15. " RX_DIAG_DFE_CTRL1_15 ,DFE tap 1 deserializer MUX select" "0,1" bitfld.word 0x06 7. " RX_DIAG_DFE_CTRL1_7 ,Receiver DFE low frequency equalization enable value standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " RX_DIAG_DFE_CTRL1_6 ,Receiver DFE low frequency equalization enable value standard mode 2" "Disabled,Enabled" bitfld.word 0x06 5. " RX_DIAG_DFE_CTRL1_5 ,Receiver DFE low frequency equalization enable value standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " RX_DIAG_DFE_CTRL1_4 ,Receiver DFE low frequency equalization enable value standard mode 0" "Disabled,Enabled" bitfld.word 0x06 3. " RX_DIAG_DFE_CTRL1_3 ,Receiver DFE equalization enable mask value standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x06 2. " RX_DIAG_DFE_CTRL1_2 ,Receiver DFE equalization enable mask value standard mode 2" "Disabled,Enabled" bitfld.word 0x06 1. " RX_DIAG_DFE_CTRL1_1 ,Receiver DFE equalization enable mask value standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " RX_DIAG_DFE_CTRL1_0 ,Receiver DFE equalization enable mask value standard mode 0" "Disabled,Enabled" line.word 0x08 "LANE2_RX_DIAG_DFE_CTRL2,Receiver DFE Control Register 2 Lane 2" bitfld.word 0x08 6.--7. " RX_DIAG_DFE_CTRL2_7_6 ,RX equalizer range select standard mode 3" "0,1,2,3" bitfld.word 0x08 4.--5. " RX_DIAG_DFE_CTRL2_5_4 ,RX equalizer range select standard mode 2" "0,1,2,3" textline " " bitfld.word 0x08 2.--3. " RX_DIAG_DFE_CTRL2_3_2 ,RX equalizer range select standard mode 1" "0,1,2,3" bitfld.word 0x08 0.--1. " RX_DIAG_DFE_CTRL2_1_0 ,RX equalizer range select standard mode 0" "0,1,2,3" line.word 0x0A "LANE2_RX_DIAG_DFE_CTRL3,Receiver DFE Control Register 3 Lane 2" bitfld.word 0x0A 12.--15. " RX_DIAG_DFE_CTRL3_15_12 ,RX DFE peaking resistor code select standard mode 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0A 8.--11. " RX_DIAG_DFE_CTRL3_11_8 ,RX DFE peaking resistor code select standard mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x0A 4.--7. " RX_DIAG_DFE_CTRL3_7_4 ,RX DFE peaking resistor code select standard mode 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0A 0.--3. " RX_DIAG_DFE_CTRL3_3_0 ,RX DFE peaking resistor code select standard mode 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0C "LANE2_RX_DIAG_NQST_CTRL,Nyquist Control Register Lane 2" bitfld.word 0x0C 12.--15. " RX_DIAG_NQST_CTRL_15_12 ,RX nyquist select value standard mode 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0C 8.--11. " RX_DIAG_NQST_CTRL_11_8 ,RX nyquist select value standard mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x0C 4.--7. " RX_DIAG_NQST_CTRL_7_4 ,RX nyquist select value standard mode 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0C 0.--3. " RX_DIAG_NQST_CTRL_3_0 ,RX nyquist select value standard mode 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0E "LANE2_RX_DIAG_LFEQ_TUNE,Low Frequency Equalizer Tuning Register Lane 2" bitfld.word 0x0E 6.--7. " RX_DIAG_LFEQ_TUNE_7_6 ,RX low frequency equalization zero frequency value standard mode 3" "0,1,2,3" bitfld.word 0x0E 4.--5. " RX_DIAG_LFEQ_TUNE_5_4 ,RX low frequency equalization zero frequency value standard mode 2" "0,1,2,3" textline " " bitfld.word 0x0E 2.--3. " RX_DIAG_LFEQ_TUNE_3_2 ,RX low frequency equalization zero frequency value standard mode 1" "0,1,2,3" bitfld.word 0x0E 0.--1. " RX_DIAG_LFEQ_TUNE_1_0 ,RX low frequency equalization zero frequency value standard mode 0" "0,1,2,3" line.word 0x10 "LANE2_RX_DIAG_RXCTRL,RX Control Register Lane 2" bitfld.word 0x10 15. " RX_DIAG_RXCTRL_15 ,RX deserializer clock invert" "Not inverted,Inverted" bitfld.word 0x10 11. " RX_DIAG_RXCTRL_11 ,PI output clock divider enable standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x10 10. " RX_DIAG_RXCTRL_10 ,PI output clock divider enable standard mode 2" "Disabled,Enabled" bitfld.word 0x10 9. " RX_DIAG_RXCTRL_9 ,PI output clock divider enable standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x10 8. " RX_DIAG_RXCTRL_8 ,PI output clock divider enable standard mode 0" "Disabled,Enabled" bitfld.word 0x10 7. " RX_DIAG_RXCTRL_7 ,Receiver CML to CMOS rate select value standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x10 6. " RX_DIAG_RXCTRL_6 ,Receiver CML to CMOS rate select value standard mode 2" "Disabled,Enabled" bitfld.word 0x10 5. " RX_DIAG_RXCTRL_5 ,Receiver CML to CMOS rate select value standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x10 4. " RX_DIAG_RXCTRL_4 ,Receiver CML to CMOS rate select value standard mode 0" "Disabled,Enabled" bitfld.word 0x10 3. " RX_DIAG_RXCTRL_3 ,RX interface sub-rate standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x10 2. " RX_DIAG_RXCTRL_2 ,RX interface sub-rate standard mode 2" "Disabled,Enabled" bitfld.word 0x10 1. " RX_DIAG_RXCTRL_1 ,RX interface sub-rate standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x10 0. " RX_DIAG_RXCTRL_0 ,RX interface sub-rate standard mode 0" "Disabled,Enabled" rgroup.word (0x8800+0x1B2)++0x01 line.word 0x00 "LANE2_RX_DIAG_RST_DIAG,Receiver Control Reset Diagnostic Register Lane 2" bitfld.word 0x00 8. " RX_DIAG_RST_DIAG_8 ,Current state of the rxda_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 7. " RX_DIAG_RST_DIAG_7 ,Current state of the rx_dig_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 6. " RX_DIAG_RST_DIAG_6 ,Current state of the rxda_cdrlf_reset_n reset" "No reset,Reset" bitfld.word 0x00 5. " RX_DIAG_RST_DIAG_5 ,Current state of the rx_ree_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 4. " RX_DIAG_RST_DIAG_4 ,Current state of the rx_lfps_det_filter_reset_n reset" "No reset,Reset" bitfld.word 0x00 3. " RX_DIAG_RST_DIAG_3 ,Current state of the rx_epi_ill_cal_lock_det_clk_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 2. " RX_DIAG_RST_DIAG_2 ,Current state of the rx_epi_ill_cal_ref_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 1. " RX_DIAG_RST_DIAG_1 ,Current state of the rx_iqpi_ill_cal_lock_det_clk_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 0. " RX_DIAG_RST_DIAG_0 ,Current state of the rx_iqpi_ill_cal_ref_clk_reset_n reset" "No reset,Reset" group.word (0x8800+0x1B8)++0x05 line.word 0x00 "LANE2_RX_DIAG_SIGDET_TUNE,RX Signal Detect Tuning And Control Register Lane 2" bitfld.word 0x00 12.--13. " RX_DIAG_SIGDET_TUNE_13_12 ,Signal detect filter function select" "0,1,2,3" bitfld.word 0x00 4.--5. " RX_DIAG_SIGDET_TUNE_5_4 ,Signal definition to be provided by the analog team" "0,1,2,3" textline " " bitfld.word 0x00 0.--3. " RX_DIAG_SIGDET_TUNE_3_0 ,Signal detect level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE2_RX_DIAG_LFPSDET_TUNE,RX LFPS Detect Tuning And Control Register Lane 2" hexmask.word.byte 0x02 8.--15. 1. " RX_DIAG_LFPSDET_TUNE_15_8 ,Signal definition to be provided by the analog team" hexmask.word.byte 0x02 0.--7. 1. " RX_DIAG_LFPSDET_TUNE_7_0 ,LFPS detect level" line.word 0x04 "LANE2_RX_DIAG_SD_TEST,Signal Detect Test Register Lane 2" bitfld.word 0x04 3. " RX_DIAG_SD_TEST_3 ,LFPS detected low test bit" "Not detected,Detected" bitfld.word 0x04 2. " RX_DIAG_SD_TEST_2 ,LFPS detected high test bit" "Not detected,Detected" textline " " bitfld.word 0x04 1. " RX_DIAG_SD_TEST_1 ,Signal detected low test bit" "Not detected,Detected" bitfld.word 0x04 0. " RX_DIAG_SD_TEST_0 ,Signal detected high test bit" "Not detected,Detected" group.word (0x8800+0x1C0)++0x03 line.word 0x00 "LANE2_RX_DIAG_SAMP_CTRL,RX Sampler Diagnostic Control Register Lane 2" bitfld.word 0x00 0. " RX_DIAG_SAMP_CTRL_0 ,Analog sampler" "0,1" line.word 0x02 "LANE2_RX_DIAG_SC2C_DELAY,RX Sampler CML TO CMOS Enable Delay Register Lane 2" hexmask.word 0x02 0.--9. 1. " RX_DIAG_SC2C_DELAY_9_0 ,Sampler CML to CMOS enable delay" group.word (0x8800+0x1C8)++0x03 line.word 0x00 "LANE2_RX_DIAG_MPHY_CTRL_1,MPHY Control Register 1 Lane 2" bitfld.word 0x00 14. " RX_DIAG_MPHY_CTRL_1_14 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x00 13. " RX_DIAG_MPHY_CTRL_1_13 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x00 12. " RX_DIAG_MPHY_CTRL_1_12 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x00 8.--9. " RX_DIAG_MPHY_CTRL_1_9_8 ,Signal definition to be provided by the analog team" "0,1,2,3" textline " " bitfld.word 0x00 0.--5. " RX_DIAG_MPHY_CTRL_1_5_0 ,Signal definition to be provided by the analog team" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE2_RX_DIAG_MPHY_CTRL_2,MPHY Control Register 2 Lane 2" rbitfld.word 0x02 10. " RX_DIAG_MPHY_CTRL_2_10 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 9. " RX_DIAG_MPHY_CTRL_2_9 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x02 8. " RX_DIAG_MPHY_CTRL_2_8 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 7. " RX_DIAG_MPHY_CTRL_2_7 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x02 6. " RX_DIAG_MPHY_CTRL_2_6 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 5. " RX_DIAG_MPHY_CTRL_2_5 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x02 4. " RX_DIAG_MPHY_CTRL_2_4 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 0.--1. " RX_DIAG_MPHY_CTRL_2_1_0 ,Signal definition to be provided by the analog team" "0,1,2,3" group.word (0x8800+0x1D0)++0x03 line.word 0x00 "LANE2_RX_DIAG_LPBK_CTRL,RX Loopback Controller Register Lane 2" bitfld.word 0x00 4. " RX_DIAG_LPBK_CTRL_4 ,Recovered clock loopback select" "0,1" bitfld.word 0x00 0.--3. " RX_DIAG_LPBK_CTRL_3_0 ,Attenuation settings" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE2_RX_DIAG_ECTRL_OVRD,RX Extra Enable Control Override Register Lane2" bitfld.word 0x02 1. " RX_DIAG_ECTRL_OVRD_1 ,Sampler CML to CMOS enable override enable" "Disabled,Enabled" bitfld.word 0x02 0. " RX_DIAG_ECTRL_OVRD_0 ,Sampler CML to CMOS enable override" "Disabled,Enabled" group.word (0x8800+0x1E0)++0x0F line.word 0x00 "LANE2_RX_DIAG_CML2CMOS_BTRIM,CML To CMOS Bias Trim Register Lane 2" bitfld.word 0x00 12.--14. " RX_DIAG_CML2CMOS_BTRIM_14_12 ,CML to CMOS IQ bias sink current trim" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--10. " RX_DIAG_CML2CMOS_BTRIM_10_8 ,CML to CMOS IQ bias source current trim" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 4.--6. " RX_DIAG_CML2CMOS_BTRIM_6_4 ,CML to CMOS E bias sink current trim" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--2. " RX_DIAG_CML2CMOS_BTRIM_2_0 ,CML to CMOS E bias source current trim" "0,1,2,3,4,5,6,7" line.word 0x02 "LANE2_RX_DIAG_BIAS_GEN_CTRL1,RX Bias Gen Control Register 1 Lane 2" bitfld.word 0x02 14.--15. " RX_DIAG_BIAS_GEN_CTRL1_15_14 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 12.--13. " RX_DIAG_BIAS_GEN_CTRL1_13_12 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 10.--11. " RX_DIAG_BIAS_GEN_CTRL1_11_10 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 8.--9. " RX_DIAG_BIAS_GEN_CTRL1_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 6.--7. " RX_DIAG_BIAS_GEN_CTRL1_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 4.--5. " RX_DIAG_BIAS_GEN_CTRL1_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 2.--3. " RX_DIAG_BIAS_GEN_CTRL1_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 0.--1. " RX_DIAG_BIAS_GEN_CTRL1_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x04 "LANE2_RX_DIAG_BIAS_GEN_CTRL2,RX Bias Gen Control Register 2 Lane 2" bitfld.word 0x04 14.--15. " RX_DIAG_BIAS_GEN_CTRL2_15_14 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 12.--13. " RX_DIAG_BIAS_GEN_CTRL2_13_12 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 10.--11. " RX_DIAG_BIAS_GEN_CTRL2_11_10 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 8.--9. " RX_DIAG_BIAS_GEN_CTRL2_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 6.--7. " RX_DIAG_BIAS_GEN_CTRL2_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 4.--5. " RX_DIAG_BIAS_GEN_CTRL2_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 2.--3. " RX_DIAG_BIAS_GEN_CTRL2_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 0.--1. " RX_DIAG_BIAS_GEN_CTRL2_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x06 "LANE2_RX_DIAG_BIAS_GEN_CTRL3,RX Bias Gen Control Register 3 Lane 2" bitfld.word 0x06 14.--15. " RX_DIAG_BIAS_GEN_CTRL3_15_14 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 12.--13. " RX_DIAG_BIAS_GEN_CTRL3_13_12 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 10.--11. " RX_DIAG_BIAS_GEN_CTRL3_11_10 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 8.--9. " RX_DIAG_BIAS_GEN_CTRL3_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 6.--7. " RX_DIAG_BIAS_GEN_CTRL3_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 4.--5. " RX_DIAG_BIAS_GEN_CTRL3_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 2.--3. " RX_DIAG_BIAS_GEN_CTRL3_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 0.--1. " RX_DIAG_BIAS_GEN_CTRL3_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x08 "LANE2_RX_DIAG_BIAS_GEN_CTRL4,RX Bias Gen Control Register 4 Lane 2" bitfld.word 0x08 15. " RX_DIAG_BIAS_GEN_CTRL4_15 ,Enable base unit on all the current outputs from the RX bias generation block" "Disabled,Enabled" bitfld.word 0x08 8.--9. " RX_DIAG_BIAS_GEN_CTRL4_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x08 6.--7. " RX_DIAG_BIAS_GEN_CTRL4_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x08 4.--5. " RX_DIAG_BIAS_GEN_CTRL4_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x08 2.--3. " RX_DIAG_BIAS_GEN_CTRL4_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x08 0.--1. " RX_DIAG_BIAS_GEN_CTRL4_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x0A "LANE2_RX_DIAG_BS_TM,RX Boundary Scan Test Mode Register" line.word 0x0C "LANE2_RX_DIAG_RXFE_TM1,RX Receiver Front End Test Mode Register 1 Lane 2" line.word 0x0E "LANE2_RX_DIAG_RXFE_TM2,RX Receiver Front End Test Mode Register 2 Lane 2" group.word 0x8C00++0x0F line.word 0x00 "LANE3_RX_PSC_A0,Receiver A0 Power State Definition Register Lane 3" bitfld.word 0x00 15. " RX_PSC_A0_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x00 14. " RX_PSC_A0_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x00 13. " RX_PSC_A0_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RX_PSC_A0_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x00 11. " RX_PSC_A0_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_PSC_A0_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_PSC_A0_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_PSC_A0_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x00 7. " RX_PSC_A0_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " RX_PSC_A0_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x00 5. " RX_PSC_A0_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x00 4. " RX_PSC_A0_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RX_PSC_A0_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x00 2. " RX_PSC_A0_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x00 1. " RX_PSC_A0_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RX_PSC_A0_0 ,RX enable" "Disabled,Enabled" line.word 0x02 "LANE3_RX_PSC_A1,Receiver A1 Power State Definition Register Lane 3" bitfld.word 0x02 15. " RX_PSC_A1_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x02 14. " RX_PSC_A1_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x02 13. " RX_PSC_A1_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RX_PSC_A1_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x02 11. " RX_PSC_A1_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x02 10. " RX_PSC_A1_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RX_PSC_A1_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x02 8. " RX_PSC_A1_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x02 7. " RX_PSC_A1_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " RX_PSC_A1_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x02 5. " RX_PSC_A1_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x02 4. " RX_PSC_A1_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RX_PSC_A1_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x02 2. " RX_PSC_A1_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x02 1. " RX_PSC_A1_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RX_PSC_A1_0 ,RX enable" "Disabled,Enabled" line.word 0x04 "LANE3_RX_PSC_A2,Receiver A2 Power State Definition Register Lane 3" bitfld.word 0x04 15. " RX_PSC_A2_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x04 14. " RX_PSC_A2_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x04 13. " RX_PSC_A2_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x04 12. " RX_PSC_A2_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x04 11. " RX_PSC_A2_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x04 10. " RX_PSC_A2_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x04 9. " RX_PSC_A2_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x04 8. " RX_PSC_A2_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x04 7. " RX_PSC_A2_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " RX_PSC_A2_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x04 5. " RX_PSC_A2_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x04 4. " RX_PSC_A2_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x04 3. " RX_PSC_A2_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x04 2. " RX_PSC_A2_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x04 1. " RX_PSC_A2_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x04 0. " RX_PSC_A2_0 ,RX enable" "Disabled,Enabled" line.word 0x06 "LANE3_RX_PSC_A3,Receiver A3 Power State Definition Register Lane 3" bitfld.word 0x06 15. " RX_PSC_A3_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x06 14. " RX_PSC_A3_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x06 13. " RX_PSC_A3_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x06 12. " RX_PSC_A3_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x06 11. " RX_PSC_A3_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x06 10. " RX_PSC_A3_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x06 9. " RX_PSC_A3_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x06 8. " RX_PSC_A3_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x06 7. " RX_PSC_A3_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " RX_PSC_A3_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x06 5. " RX_PSC_A3_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x06 4. " RX_PSC_A3_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x06 3. " RX_PSC_A3_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x06 2. " RX_PSC_A3_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x06 1. " RX_PSC_A3_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " RX_PSC_A3_0 ,RX enable" "Disabled,Enabled" line.word 0x08 "LANE3_RX_PSC_A4,Receiver A4 Power State Definition Register Lane 3" bitfld.word 0x08 15. " RX_PSC_A4_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x08 14. " RX_PSC_A4_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x08 13. " RX_PSC_A4_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x08 12. " RX_PSC_A4_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x08 11. " RX_PSC_A4_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x08 10. " RX_PSC_A4_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x08 9. " RX_PSC_A4_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x08 8. " RX_PSC_A4_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x08 7. " RX_PSC_A4_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " RX_PSC_A4_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x08 5. " RX_PSC_A4_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x08 4. " RX_PSC_A4_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x08 3. " RX_PSC_A4_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x08 2. " RX_PSC_A4_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x08 1. " RX_PSC_A4_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " RX_PSC_A4_0 ,RX enable" "Disabled,Enabled" line.word 0x0A "LANE3_RX_PSC_A5,Receiver A5 Power State Definition Register Lane 3" bitfld.word 0x0A 15. " RX_PSC_A5_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x0A 14. " RX_PSC_A5_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x0A 13. " RX_PSC_A5_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 12. " RX_PSC_A5_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x0A 11. " RX_PSC_A5_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x0A 10. " RX_PSC_A5_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 9. " RX_PSC_A5_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x0A 8. " RX_PSC_A5_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x0A 7. " RX_PSC_A5_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 6. " RX_PSC_A5_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x0A 5. " RX_PSC_A5_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x0A 4. " RX_PSC_A5_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 3. " RX_PSC_A5_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x0A 2. " RX_PSC_A5_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x0A 1. " RX_PSC_A5_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x0A 0. " RX_PSC_A5_0 ,RX enable" "Disabled,Enabled" line.word 0x0C "LANE3_RX_PSC_CAL,Receiver Calibration Power State Definition Register Lane 3" bitfld.word 0x0C 15. " RX_PSC_CAL_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x0C 14. " RX_PSC_CAL_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x0C 13. " RX_PSC_CAL_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 12. " RX_PSC_CAL_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x0C 11. " RX_PSC_CAL_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x0C 10. " RX_PSC_CAL_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 9. " RX_PSC_CAL_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x0C 8. " RX_PSC_CAL_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x0C 7. " RX_PSC_CAL_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " RX_PSC_CAL_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x0C 5. " RX_PSC_CAL_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x0C 4. " RX_PSC_CAL_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 3. " RX_PSC_CAL_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x0C 2. " RX_PSC_CAL_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x0C 1. " RX_PSC_CAL_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 0. " RX_PSC_CAL_0 ,RX enable" "Disabled,Enabled" line.word 0x0E "LANE3_RX_PSC_RDY,Receiver Ready Power State Definition Register Lane 3" bitfld.word 0x0E 15. " RX_PSC_RDY_15 ,RX LFPS / signal detect filter mode" "0,1" bitfld.word 0x0E 14. " RX_PSC_RDY_14 ,RX squelch enable" "Disabled,Enabled" bitfld.word 0x0E 13. " RX_PSC_RDY_13 ,RX LFPS detect enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 12. " RX_PSC_RDY_12 ,RX signal detect extend valid" "Not valid,Valid" bitfld.word 0x0E 11. " RX_PSC_RDY_11 ,RX signal detect filter enable" "Disabled,Enabled" bitfld.word 0x0E 10. " RX_PSC_RDY_10 ,RX LFPS detect filter enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 9. " RX_PSC_RDY_9 ,RX clock enable" "Disabled,Enabled" bitfld.word 0x0E 8. " RX_PSC_RDY_8 ,RX signal detect enable" "Disabled,Enabled" bitfld.word 0x0E 7. " RX_PSC_RDY_7 ,RX equalization enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 6. " RX_PSC_RDY_6 ,RX sampler enable" "Disabled,Enabled" bitfld.word 0x0E 5. " RX_PSC_RDY_5 ,RX CDRLF enable" "Disabled,Enabled" bitfld.word 0x0E 4. " RX_PSC_RDY_4 ,RX bias enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 3. " RX_PSC_RDY_3 ,RX DFE equalization enable" "Disabled,Enabled" bitfld.word 0x0E 2. " RX_PSC_RDY_2 ,RX PI enable" "Disabled,Enabled" bitfld.word 0x0E 1. " RX_PSC_RDY_1 ,RX e path enable" "Disabled,Enabled" textline " " bitfld.word 0x0E 0. " RX_PSC_RDY_0 ,RX enable" "Disabled,Enabled" textline " " group.word (0x8C00+0x40)++0x0D line.word 0x00 "LANE3_RX_IQPI_ILL_CAL_CTRL,RX IQ PI ILL Calibration Control Register Lane 3" bitfld.word 0x00 15. " RX_IQPI_ILL_CAL_CTRL_15 ,Start ILL calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_IQPI_ILL_CAL_CTRL_15 ,ILL calibration process done" "Not done,Done" textline " " hexmask.word.byte 0x00 0.--7. 1. " RX_IQPI_ILL_CAL_CTRL_7_0 ,ILL calibration code" line.word 0x02 "LANE3_RX_IQPI_ILL_CAL_START,RX IQ PI ILL Calibration Start Point Register Lane 3" bitfld.word 0x02 12.--14. " RX_IQPI_ILL_CAL_START_14_12 ,ILL calibration initial step size control" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x02 0.--7. 1. " RX_IQPI_ILL_CAL_START_7_0 ,ILL calibration code starting point value" line.word 0x04 "LANE3_RX_IQPI_ILL_CAL_TCTRL,RX IQ PI ILL Calibration Timer Control Register Lane 3" bitfld.word 0x04 0.--2. " RX_IQPI_ILL_CAL_TCTRL_2_0 ,ILL calibration initial time scale control" "0,1,2,3,4,5,6,7" line.word 0x06 "LANE3_RX_IQPI_ILL_CAL_OVRD,RX IQ PI ILL Calibration Override Register Lane 3" bitfld.word 0x06 15. " RX_IQPI_ILL_CAL_OVRD_15 ,ILL calibration code override enable" "Disabled,Enabled" hexmask.word.byte 0x06 0.--7. 1. " RX_IQPI_ILL_CAL_OVRD_7_0 ,ILL calibration code override value" line.word 0x08 "LANE3_RX_IQPI_ILL_CAL_INIT_TMR,RX IQ PI ILL Calibration Initialization Timer Register Lane 3" hexmask.word 0x08 0.--11. 1. " RX_IQPI_ILL_CAL_INIT_TMR_11_0 ,Initialization wait timer value" line.word 0x0A "LANE3_RX_IQPI_ILL_CAL_ITER_TMR,RX IQ PI ILL Calibration Iteration Timer Register Lane 3" hexmask.word 0x0A 0.--11. 1. " RX_IQPI_ILL_CAL_ITER_TMR_11_0 ,Iteration wait timer value" line.word 0x0C "LANE3_RX_IQPI_ILL_LOCK_REFTMR_START,RX IQ PI ILL Lock Reference Timer Start Value Register Lane 3" hexmask.word 0x0C 0.--11. 1. " RX_IQPI_ILL_LOCK_REFTMR_START_11_0 ,ILL lock reference timer start value" group.word (0x8C00+0x50)++0x07 line.word 0x00 "LANE3_RX_IQPI_ILL_LOCK_CALCNT_START_0,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 0 Register Lane 3" hexmask.word 0x00 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_0_11_0 ,ILL lock calibration counter start value" line.word 0x02 "LANE3_RX_IQPI_ILL_LOCK_CALCNT_START_1,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 1 Register Lane 3" hexmask.word 0x02 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_1_11_0 ,ILL lock calibration counter start value" line.word 0x04 "LANE3_RX_IQPI_ILL_LOCK_CALCNT_START_2,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 2 Register Lane 3" hexmask.word 0x04 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_2_11_0 ,ILL lock calibration counter start value" line.word 0x06 "LANE3_RX_IQPI_ILL_LOCK_CALCNT_START_3,RX IQ PI ILL Lock Calibration Counter Start Value Standard Mode 3 Register Lane 3" hexmask.word 0x06 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_3_11_0 ,ILL lock calibration counter start value" group.word (0x8C00+0x60)++0x0D line.word 0x00 "LANE3_RX_EPI_ILL_CAL_CTRL,RX E PI ILL Calibration Control Register Lane 3" bitfld.word 0x00 15. " RX_EPI_ILL_CAL_CTRL_15 ,Start ILL calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_EPI_ILL_CAL_CTRL_14 ,ILL calibration process done" "Not done,Done" textline " " hexmask.word.byte 0x00 0.--7. 1. " RX_EPI_ILL_CAL_CTRL_7_0 ,ILL calibration code" line.word 0x02 "LANE3_RX_EPI_ILL_CAL_START,RX E PI ILL Calibration Start Point Register Lane 3" bitfld.word 0x02 12.--14. " RX_EPI_ILL_CAL_START_14_12 ,ILL calibration initial step size control" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x02 0.--7. 1. " RX_EPI_ILL_CAL_START_7_0 ,ILL calibration code starting point value" line.word 0x04 "LANE3_RX_EPI_ILL_CAL_TCTRL,RX E PI ILL Calibration Timer Control Register Lane 3" bitfld.word 0x04 0.--2. " RX_EPI_ILL_CAL_TCTRL_2_0 ,ILL calibration initial time scale control" "0,1,2,3,4,5,6,7" line.word 0x06 "LANE3_RX_EPI_ILL_CAL_OVRD,RX E PI ILL Calibration Override Register Lane 3" bitfld.word 0x06 15. " RX_EPI_ILL_CAL_OVRD_15 ,ILL calibration code override enable" "Disabled,Enabled" hexmask.word.byte 0x06 0.--7. 1. " RX_EPI_ILL_CAL_OVRD_7_0 ,ILL calibration code override value" line.word 0x08 "LANE3_RX_EPI_ILL_CAL_INIT_TMR,RX E PI ILL Calibration Initialization Timer Register 3" hexmask.word 0x08 0.--11. 1. " RX_EPI_ILL_CAL_INIT_TMR_11_0 ,Initialization wait timer value" line.word 0x0A "LANE3_RX_EPI_ILL_CAL_ITER_TMR,RX E PI ILL Calibration Iteration Timer Register Lane 3" hexmask.word 0x0A 0.--11. 1. " RX_EPI_ILL_CAL_ITER_TMR_11_0 ,Iteration wait timer value" line.word 0x0C "LANE3_RX_EPI_ILL_LOCK_REFTMR_START,RX E PI ILL Lock Reference Timer Start Value Register Lane 3" hexmask.word 0x0C 0.--11. 1. " RX_EPI_ILL_LOCK_REFTMR_START_11_0 ,ILL lock reference timer start value" group.word (0x8C00+0x70)++0x07 line.word 0x00 "LANE3_RX_EPI_ILL_LOCK_CALCNT_START_0,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 0 Register Lane 3" hexmask.word 0x00 0.--11. 1. " RX_EPI_ILL_LOCK_CALCNT_START_0_11_0 ,ILL lock calibration counter start value" line.word 0x02 "LANE3_RX_EPI_ILL_LOCK_CALCNT_START_1,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 1 Register Lane 3" hexmask.word 0x02 0.--11. 1. " RX_IQPI_ILL_LOCK_CALCNT_START_1_11_0 ,ILL lock calibration counter start value" line.word 0x04 "LANE3_RX_IQPI_ILL_LOCK_CALCNT_START_2,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 2 Register Lane 3" hexmask.word 0x04 0.--11. 1. " RX_EPI_ILL_LOCK_CALCNT_START_2_11_0 ,ILL lock calibration counter start value" line.word 0x06 "LANE3_RX_IQPI_ILL_LOCK_CALCNT_START_3,RX E PI ILL Lock Calibration Counter Start Value Standard Mode 3 Register Lane 3" hexmask.word 0x06 0.--11. 1. " RX_EPI_ILL_LOCK_CALCNT_START_3_11_0 ,ILL lock calibration counter start value" group.word (0x8C00+0x80)++0x0B line.word 0x00 "LANE3_RX_SDCAL0_CTRL,Signal Detect Calibration 0 Control Register Lane 3" bitfld.word 0x00 15. " RX_SDCAL0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SDCAL0_CTRL_14 ,Calibration process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " RX_EPI_ILL_CAL_CTRL_14 ,No analog calibration response" "Not responded,Responded" rbitfld.word 0x00 12. " RX_SDCAL0_CTRL_14 ,Current analog comparator response" "Not responded,Responded" textline " " bitfld.word 0x00 0.--3. " RX_SDCAL0_CTRL_3_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE3_RX_SDCAL0_OVRD,Signal Detect Calibration 0 Override Register Lane 3" bitfld.word 0x02 15. " RX_SDCAL0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " RX_SDCAL0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 0.--3. " RX_SDCAL0_OVRD_3_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "LANE3_RX_SDCAL0_START,Signal Detect Calibration 0 Start Register Lane 3" bitfld.word 0x04 15. " RX_SDCAL0_START_15 ,Calibration direction" "0,1" bitfld.word 0x04 0.--3. " RX_SDCAL0_START_3_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x06 "LANE3_RX_SDCAL0_TUNE,Signal Detect Calibration 0 Tune Register Lane 3" bitfld.word 0x06 0.--3. " RX_SDCAL0_TUNE_3_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "LANE3_RX_SDCAL0_INIT_TMR,Signal Detect Calibration 0 Initialization Timer Register Lane3" hexmask.word 0x08 0.--8. 1. " RX_SDCAL0_INIT_TMR_8_0 ,Initialization wait timer value" line.word 0x0A "LANE3_RX_SDCAL0_ITER_TMR,Signal Detect Calibration 0 Iteration Timer Register Lane 3" hexmask.word 0x0A 0.--8. 1. " RX_SDCAL0_ITER_TMR_8_0 ,Iteration wait timer value" group.word (0x8C00+0x90)++0x0B line.word 0x00 "LANE3_RX_SDCAL1_CTRL,Signal Detect Calibration 1 Control Register Lane 3" bitfld.word 0x00 15. " RX_SDCAL1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SDCAL1_CTRL_14 ,Calibration process done" "Not done,Done" textline " " rbitfld.word 0x00 13. " RX_SDCAL1_CTRL_13 ,No analog calibration response" "Not responded,Responded" rbitfld.word 0x00 12. " RX_SDCAL1_CTRL_12 ,Current analog comparator response" "Not responded,Responded" textline " " bitfld.word 0x00 0.--3. " RX_SDCAL1_CTRL_3_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE3_RX_SDCAL1_OVRD,Signal Detect Calibration 1 Override Register Lane 3" bitfld.word 0x02 15. " RX_SDCAL1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " RX_SDCAL1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 0.--3. " RX_SDCAL1_OVRD_3_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "LANE3_RX_SDCAL1_START,Signal Detect Calibration 1 Start Register Lane 3" bitfld.word 0x04 15. " RX_SDCAL1_START_15 ,Calibration direction" "0,1" bitfld.word 0x04 0.--3. " RX_SDCAL1_START_3_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x06 "LANE3_RX_SDCAL1_TUNE,Signal Detect Calibration 1 Tune Register Lane 3" bitfld.word 0x06 0.--3. " RX_SDCAL1_TUNE_3_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "LANE3_RX_SDCAL1_INIT_TMR,Signal Detect Calibration 1 Initialization Timer Register Lane 3" hexmask.word 0x08 0.--8. 1. " RX_SDCAL1_INIT_TMR_8_0 ,Initialization wait timer value" line.word 0x0A "LANE3_RX_SDCAL1_ITER_TMR,Signal Detect Calibration 1 Iteration Timer Register Lane 3" hexmask.word 0x0A 0.--8. 1. " RX_SDCAL1_ITER_TMR_8_0 ,Iteration wait timer value" group.word (0x8C00+0xB0)++0x01 line.word 0x00 "LANE3_RX_SAMP_DAC_CTRL,Sampler Error DAC Control Register Lane 3" bitfld.word 0x00 0.--5. " RX_SAMP_DAC_CTRL_5_0 ,Sampler error DAC value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8C00+0x100)++0x0B line.word 0x00 "LANE3_RX_CDRLF_CNFG,CDRLF Configuration Register Lane 3" rbitfld.word 0x00 15. " RX_CDRLF_CNFG_15 ,CDRLF fast phase lock locked detected" "Not detected,Detected" bitfld.word 0x00 14. " RX_CDRLF_CNFG_14 ,CDRLF fast phase lock diagnostic enable" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " RX_CDRLF_CNFG_13 ,CDRLF fast phase lock enable" "Disabled,Enabled" bitfld.word 0x00 12. " RX_CDRLF_CNFG_12 ,CDRLF fast frequency lock enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " RX_CDRLF_CNFG_11 ,CDRLF second order loop integrator max clear enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_CDRLF_CNFG_10 ,CDRLF reset on CDRLF PM accumulator max" "No reset,Reset" textline " " bitfld.word 0x00 9. " RX_CDRLF_CNFG_9 ,CDRLF freeze on electrical idle detect" "Not detected,Detected" bitfld.word 0x00 8. " RX_CDRLF_CNFG_8 ,CDRLF reset on electrical idle detect" "Not detected,Detected" textline " " bitfld.word 0x00 7. " RX_CDRLF_CNFG_7 ,CDRLF data filter enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " RX_CDRLF_CNFG_5_0 ,CDRLF second order loop integrator threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE3_RX_CDRLF_CNFG2,CDRLF Configuration Register 2 Lane 3" bitfld.word 0x02 4.--6. " RX_CDRLF_CNFG2_6 ,CDRLF diagnostic mode control" "0,1,2,3,4,5,6,7" bitfld.word 0x02 2. " RX_CDRLF_CNFG2_2 ,CDLRF reset hold" "Not held,Held" textline " " bitfld.word 0x02 1. " RX_CDRLF_CNFG2_1 ,CDRLF second order loop disable" "No,Yes" bitfld.word 0x02 0. " RX_CDRLF_CNFG2_0 ,CDRLF first order loop disable" "No,Yes" line.word 0x04 "LANE3_RX_CDRLF_MGN_DIAG,CDRLF Margin Diagnostic Register 2 Lane 3" bitfld.word 0x04 2. " RX_CDRLF_MGN_DIAG_2 ,CDRLF PI override down" "No override,Override" bitfld.word 0x04 1. " RX_CDRLF_MGN_DIAG_1 ,CDRLF PI override up" "No override,Override" textline " " bitfld.word 0x04 0. " RX_CDRLF_MGN_DIAG_0 ,CDRLF PI override enable" "Disabled,Enabled" line.word 0x06 "LANE3_RX_CDRLF_FPL_TMR0,CDRLF Fast Phase Lock Timer Value Register 0 Lane 3" bitfld.word 0x06 4.--7. " RX_CDRLF_FPL_TMR0_7_4 ,Fast phase lock timer accumulate state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x06 0.--3. " RX_CDRLF_FPL_TMR0_3_0 ,Fast phase lock timer delay state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "LANE3_RX_CDRLF_FPL_TMR1,CDRLF Fast Phase Lock Timer Value Register 1 Lane 3" bitfld.word 0x08 8.--11. " RX_CDRLF_FPL_TMR1_11_8 ,Fast phase lock timer trigger 1 state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x08 4.--7. " RX_CDRLF_FPL_TMR1_7_4 ,Fast phase lock timer trigger 2 state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x08 0.--3. " RX_CDRLF_FPL_TMR1_3_0 ,Fast phase lock timer trigger 3 state time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0A "LANE3_RX_CDRLF_FFL_TMR,CDRLF Fast Frequency Lock Timer Value Register Lane 3" bitfld.word 0x0A 0.--5. " RX_CDRLF_FFL_TMR_5_0 ,Fast frequency lock step timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8C00+0x110)++0x09 line.word 0x00 "LANE3_RX_CDRLF_FFL0_CTRL,CDRLF Fast Frequency Lock Step 0 Control Register Lane 3" bitfld.word 0x00 14.--15. " RX_CDRLF_FFL0_CTRL_15_14 ,FFL step 0 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x00 8.--12. " RX_CDRLF_FFL0_CTRL_12_8 ,FFL step 0 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x00 0.--4. " RX_CDRLF_FFL0_CTRL_4_0 ,FFL step 0 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x02 "LANE3_RX_CDRLF_FFL1_CTRL,CDRLF Fast Frequency Lock Step 1 Control Register Lane 3" bitfld.word 0x02 14.--15. " RX_CDRLF_FFL1_CTRL_15_14 ,FFL step 1 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x02 8.--12. " RX_CDRLF_FFL1_CTRL_12_8 ,FFL step 1 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x02 0.--4. " RX_CDRLF_FFL1_CTRL_4_0 ,FFL step 1 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE3_RX_CDRLF_FFL2_CTRL,CDRLF Fast Frequency Lock Step 2 Control Register Lane 3" bitfld.word 0x04 14.--15. " RX_CDRLF_FFL2_CTRL_15_14 ,FFL step 2 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x04 8.--12. " RX_CDRLF_FFL2_CTRL_12_8 ,FFL step 2 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x04 0.--4. " RX_CDRLF_FFL2_CTRL_4_0 ,FFL step 2 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "LANE3_RX_CDRLF_FFL3_CTRL,CDRLF Fast Frequency Lock Step 3 Control Register Lane 3" bitfld.word 0x06 14.--15. " RX_CDRLF_FFL3_CTRL_15_14 ,FFL step 3 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x06 8.--12. " RX_CDRLF_FFL3_CTRL_12_8 ,FFL step 3 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x06 0.--4. " RX_CDRLF_FFL3_CTRL_4_0 ,FFL step 3 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "LANE3_RX_CDRLF_FFL4_CTRL,CDRLF Fast Frequency Lock Step 4 Control Register Lane 3" bitfld.word 0x08 14.--15. " RX_CDRLF_FFL4_CTRL_15_14 ,FFL step 4 CDRLF second order loop integrator scaler" "0,1,2,3" bitfld.word 0x08 8.--12. " RX_CDRLF_FFL4_CTRL_12_8 ,FFL step 4 CDRLF second order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x08 0.--4. " RX_CDRLF_FFL4_CTRL_4_0 ,FFL step 4 CDRLF first order loop sigma delta update rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (0x8C00+0x120)++0x17 line.word 0x00 "LANE3_RX_SIGDET_HL_FILT_TMR,Receiver Signal Detect Filter High To Low Filter Timer Register Lane 3" hexmask.word 0x00 0.--9. 1. " RX_SIGDET_HL_FILT_TMR_9_0 ,Signal detect filter high to low filter timer value" line.word 0x02 "LANE3_RX_SIGDET_HL_DLY_TMR,Receiver Signal Detect Filter High To Low Delay Timer Register Lane 3" hexmask.word 0x02 0.--9. 1. " RX_SIGDET_HL_DLY_TMR_9_0 ,Signal detect filter high to low delay timer value" line.word 0x04 "LANE3_RX_SIGDET_HL_MIN_TMR,Receiver Signal Detect Filter High To Low Min Timer Register Lane 3" hexmask.word 0x04 0.--9. 1. " RX_SIGDET_HL_MIN_TMR_9_0 ,Signal detect filter high to low min timer value" line.word 0x06 "LANE3_RX_SIGDET_HL_MIN_TMR,Receiver Signal Detect Filter High To Low Init Timer Register Lane 3" hexmask.word 0x06 0.--9. 1. " RX_SIGDET_HL_INIT_TMR_9_0 ,Signal detect init timer value" line.word 0x08 "LANE3_RX_SIGDET_LH_FILT_TMR,Receiver Signal Detect Filter Low To High Filter Timer Register Lane 3" hexmask.word 0x08 0.--9. 1. " RX_SIGDET_LH_FILT_TMR_9_0 ,Signal detect filter low to high filter timer value" line.word 0x0A "LANE3_RX_SIGDET_LH_DLY_TMR,Receiver Signal Detect Filter Low To High Delay Timer Register Lane 3" hexmask.word 0x0A 0.--9. 1. " RX_SIGDET_LH_DLY_TMR_9_0 ,Signal detect filter low to high delay timer value" line.word 0x0C "LANE3_RX_SIGDET_LH_MIN_TMR,Receiver Signal Detect Filter Low To High Min Timer Register Lane 3" hexmask.word 0x0C 0.--9. 1. " RX_SIGDET_LH_MIN_TMR_9_0 ,Signal detect filter low to high min timer value" line.word 0x0E "LANE3_RX_SIGDET_LH_INIT_TMR,Receiver Signal Detect Filter Low To High Init Timer Register Lane 3" hexmask.word 0x0E 0.--9. 1. " RX_SIGDET_LH_INIT_TMR_9_0 ,Signal detect init timer value" line.word 0x10 "LANE3_RX_LFPSDET_FILT_TMR,Receiver LFPS Detect Filter Filter Timer Register Lane 3" hexmask.word 0x10 0.--9. 1. " RX_LFPSDET_FILT_TMR_9_0 ,LFPS detect filter timer value" line.word 0x12 "LANE3_RX_LFPSDET_DLY_TMR,Receiver LFPS Detect Filter Delay Timer Register Lane 3" hexmask.word 0x12 0.--9. 1. " RX_LFPSDET_DLY_TMR_9_0 ,LFPS detect filter delay timer value" line.word 0x14 "LANE3_RX_LFPSDET_MIN_TMR,Receiver LFPS Detect Min Timer Register Lane 3" hexmask.word 0x14 0.--9. 1. " RX_LFPSDET_MIN_TMR_9_0 ,LFPS detect min timer value" line.word 0x16 "LANE3_RX_LFPSDET_INIT_TMR,Receiver LFPS Detect Init Timer Register Lane 3" hexmask.word 0x16 0.--9. 1. " RX_LFPSDET_INIT_TMR_9_0 ,LFPS detect init timer value" group.word (0x8C00+0x140)++0x01 line.word 0x00 "LANE3_RX_EYESURF_CTRL,Eye Surf Control Register Lane 3" bitfld.word 0x00 15. " RX_EYESURF_CTRL_15 ,Eye surf process enable" "Disabled,Enabled" rbitfld.word 0x00 14. " RX_EYESURF_CTRL_14 ,Eye surf process has completed" "Not completed,Completed" group.word (0x8C00+0x148)++0x0B line.word 0x00 "LANE3_RX_EYESURF_TMR_DELLOW,Eye Surf Timer Delay Low Register Lane 3" line.word 0x02 "LANE3_RX_EYESURF_TMR_DELHIGH,Eye Surf Timer Delay High Register Lane 3" line.word 0x04 "LANE3_RX_EYESURF_TMR_TESTLOW,Eye Surf Timer Test Low Register Lane 3" line.word 0x06 "LANE3_RX_EYESURF_TMR_TESTHIGH,Eye Surf Timer Test High Register Lane 3" line.word 0x08 "LANE3_RX_EYESURF_NS_COORD,Eye Surf North South Test Point Coordinate Register Lane 3" bitfld.word 0x08 8. " RX_EYESURF_NS_COORD_8 ,Test point coordinate north south direction" "0,1" hexmask.word.byte 0x08 0.--6. 0x01 " RX_EYESURF_NS_COORD_6_0 ,Test point coordinate north south offset" line.word 0x0A "LANE3_RX_EYESURF_EW_COORD,Eye Surf East West Test Point Coordinate Register Lane 3" bitfld.word 0x0A 8. " RX_EYESURF_EW_COORD_8 ,Test point coordinate east west direction" "0,1" hexmask.word.byte 0x0A 0.--4. 0x01 " RX_EYESURF_EW_COORD_4_0 ,Test point coordinate east west offset" rgroup.word (0x8C00+0x154)++0x01 line.word 0x00 "LANE3_RX_EYESURF_ERRCNT,Eye Surf Bit Error Count Register Lane 3" group.word (0x8C00+0x160)++0x03 line.word 0x00 "LANE3_RX_BIST_CTRL,Receiver BIST Control Register Lane 3" bitfld.word 0x00 8.--11. " RX_BIST_CTRL_11_8 ,Receiver BIST mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4. " RX_BIST_CTRL_4 ,Receiver BIST error reset" "No reset,Reset" textline " " bitfld.word 0x00 1. " RX_BIST_CTRL_1 ,Receiver BIST user defined data FIFO clear" "No clear,Clear" bitfld.word 0x00 0. " RX_BIST_CTRL_0 ,Receiver BIST enable" "Disabled,Enabled" line.word 0x02 "LANE3_RX_BIST_SYNCCNT,Receiver BIST Sync Count Register Lane 3" wgroup.word (0x8C00+0x164)++0x01 line.word 0x00 "LANE3_RX_BIST_UDDWR,Receiver BIST User Defined Data Write Register Lane 3" hexmask.word 0x00 0.--9. 1. " RX_BIST_UDDWR_9_0 ,Receiver BIST user defined data" rgroup.word (0x8C00+0x166)++0x01 line.word 0x00 "LANE3_RX_BIST_ERRCNT,Receiver BIST Error Count Register Lane 3" group.word (0x8C00+0x168)++0x05 line.word 0x00 "LANE3_XCVR_CMSMT_CLK_FREQ_MSMT_CTRL,Clock Frequency Measurement Control Register Lane 3" bitfld.word 0x00 15. " XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_15 ,Start test clock measurement" "Not started,Started" rbitfld.word 0x00 14. " XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_14 ,Test clock measurement done" "Not done,Done" line.word 0x02 "LANE3_XCVR_CMSMT_TEST_CLK_SEL,Test Clock Selection Register Lane 3" bitfld.word 0x02 0.--2. " XCVR_CMSMT_TEST_CLK_SEL_2_0 ,Test clock select" "0,1,2,3,4,5,6,7" line.word 0x04 "LANE3_XCVR_CMSMT_REF_CLK_TMR_VALUE,Reference Clock Timer Value Register Lane 3" hexmask.word 0x04 0.--11. 1. " XCVR_CMSMT_REF_CLK_TMR_VALUE_11_0 ,Reference clock timer value" rgroup.word (0x8C00+0x16E)++0x01 line.word 0x00 "LANE3_XCVR_CMSMT_TEST_CLK_CNT_VALUE,Test Clock Counter Value Register Lane 3" hexmask.word 0x00 0.--11. 1. " XCVR_CMSMT_TEST_CLK_CNT_VALUE_11_0 ,Test clock counter value" group.word (0x8C00+0x1C0)++0x15 line.word 0x00 "LANE3_RX_SLC_CTRL,RX Sampler Latch Calibration Control Register Lane 3" bitfld.word 0x00 15. " RX_SLC_CTRL_15 ,Start RX sampler latch calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SLC_CTRL_14 ,RX sampler latch calibration done" "Not done,Done" textline " " bitfld.word 0x00 13. " RX_SLC_CTRL_13 ,Analog calibration enable override" "Disabled,Enabled" bitfld.word 0x00 11. " RX_SLC_CTRL_11 ,I odd positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " RX_SLC_CTRL_10 ,Q odd positive calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 9. " RX_SLC_CTRL_9 ,E odd positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " RX_SLC_CTRL_8 ,I odd negative calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 7. " RX_SLC_CTRL_7 ,Q odd negative calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " RX_SLC_CTRL_6 ,E odd negative calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 5. " RX_SLC_CTRL_5 ,I even positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_SLC_CTRL_4 ,Q even positive calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 3. " RX_SLC_CTRL_3 ,E even positive calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " RX_SLC_CTRL_2 ,I even negative calibration unit enable" "Disabled,Enabled" bitfld.word 0x00 1. " RX_SLC_CTRL_1 ,Q even negative calibration unit enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RX_SLC_CTRL_0 ,E even negative calibration unit enable" "Disabled,Enabled" line.word 0x02 "LANE3_RX_SLC_EN_INIT_TMR,RX Sampler Latch Calibration Enable Initialization Timer Value Register Lane 3" bitfld.word 0x02 0.--5. " RX_SLC_EN_INIT_TMR_5_0 ,RX sampler latch calibration enable initialization timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE3_RX_SLC_CU_INIT_TMR,RX Sampler Latch Calibration Unit Initialization Timer Value Register Lane 3" bitfld.word 0x04 0.--5. " RX_SLC_CU_INIT_TMR_5_0 ,RX sampler latch calibration unit initialization timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x06 "LANE3_RX_SLC_CU_ITER_TMR,RX Sampler Latch Calibration Unit Iteration Timer Value Register Lane 3" bitfld.word 0x06 0.--5. " RX_SLC_CU_ITER_TMR_5_0 ,RX sampler latch calibration unit iteration timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "LANE3_RX_SLC_IE_MASK,RX Sampler Latch Calibration I Even Data Mask Register Lane 3" bitfld.word 0x08 9. " RX_SLC_IE_MASK_9 ,I even data mask 9" "Not masked,Masked" bitfld.word 0x08 8. " RX_SLC_IE_MASK_8 ,I even data mask 8" "Not masked,Masked" textline " " bitfld.word 0x08 7. " RX_SLC_IE_MASK_7 ,I even data mask 7" "Not masked,Masked" bitfld.word 0x08 6. " RX_SLC_IE_MASK_6 ,I even data mask 6" "Not masked,Masked" textline " " bitfld.word 0x08 5. " RX_SLC_IE_MASK_5 ,I even data mask 5" "Not masked,Masked" bitfld.word 0x08 4. " RX_SLC_IE_MASK_4 ,I even data mask 4" "Not masked,Masked" textline " " bitfld.word 0x08 3. " RX_SLC_IE_MASK_3 ,I even data mask 3" "Not masked,Masked" bitfld.word 0x08 2. " RX_SLC_IE_MASK_2 ,I even data mask 2" "Not masked,Masked" textline " " bitfld.word 0x08 1. " RX_SLC_IE_MASK_1 ,I even data mask 1" "Not masked,Masked" bitfld.word 0x08 0. " RX_SLC_IE_MASK_0 ,I even data mask 0" "Not masked,Masked" line.word 0x0A "LANE3_RX_SLC_IO_MASK,RX Sampler Latch Calibration I Odd Data Mask Register Lane 3" bitfld.word 0x0A 9. " RX_SLC_IO_MASK_9 ,I odd data mask 9" "Not masked,Masked" bitfld.word 0x0A 8. " RX_SLC_IO_MASK_8 ,I odd data mask 8" "Not masked,Masked" textline " " bitfld.word 0x0A 7. " RX_SLC_IO_MASK_7 ,I odd data mask 7" "Not masked,Masked" bitfld.word 0x0A 6. " RX_SLC_IO_MASK_6 ,I odd data mask 6" "Not masked,Masked" textline " " bitfld.word 0x0A 5. " RX_SLC_IO_MASK_5 ,I odd data mask 5" "Not masked,Masked" bitfld.word 0x0A 4. " RX_SLC_IO_MASK_4 ,I odd data mask 4" "Not masked,Masked" textline " " bitfld.word 0x0A 3. " RX_SLC_IO_MASK_3 ,I odd data mask 3" "Not masked,Masked" bitfld.word 0x0A 2. " RX_SLC_IO_MASK_2 ,I odd data mask 2" "Not masked,Masked" textline " " bitfld.word 0x0A 1. " RX_SLC_IO_MASK_1 ,I odd data mask 1" "Not masked,Masked" bitfld.word 0x0A 0. " RX_SLC_IO_MASK_0 ,I odd data mask 0" "Not masked,Masked" line.word 0x0C "LANE3_RX_SLC_QE_MASK,RX Sampler Latch Calibration Q Even Data Mask Register Lane 3" bitfld.word 0x0C 9. " RX_SLC_QE_MASK_9 ,Q even data mask 9" "Not masked,Masked" bitfld.word 0x0C 8. " RX_SLC_QE_MASK_8 ,Q even data mask 8" "Not masked,Masked" textline " " bitfld.word 0x0C 7. " RX_SLC_QE_MASK_7 ,Q even data mask 7" "Not masked,Masked" bitfld.word 0x0C 6. " RX_SLC_QE_MASK_6 ,Q even data mask 6" "Not masked,Masked" textline " " bitfld.word 0x0C 5. " RX_SLC_QE_MASK_5 ,Q even data mask 5" "Not masked,Masked" bitfld.word 0x0C 4. " RX_SLC_QE_MASK_4 ,Q even data mask 4" "Not masked,Masked" textline " " bitfld.word 0x0C 3. " RX_SLC_QE_MASK_3 ,Q even data mask 3" "Not masked,Masked" bitfld.word 0x0C 2. " RX_SLC_QE_MASK_2 ,Q even data mask 2" "Not masked,Masked" textline " " bitfld.word 0x0C 1. " RX_SLC_QE_MASK_1 ,Q even data mask 1" "Not masked,Masked" bitfld.word 0x0C 0. " RX_SLC_QE_MASK_0 ,Q even data mask 0" "Not masked,Masked" line.word 0x0E "LANE3_RX_SLC_QO_MASK,RX Sampler Latch Calibration Q Odd Data Mask Register Lane 3" bitfld.word 0x0E 9. " RX_SLC_QO_MASK_9 ,Q odd data mask 9" "Not masked,Masked" bitfld.word 0x0E 8. " RX_SLC_QO_MASK_8 ,Q odd data mask 8" "Not masked,Masked" textline " " bitfld.word 0x0E 7. " RX_SLC_QO_MASK_7 ,Q odd data mask 7" "Not masked,Masked" bitfld.word 0x0E 6. " RX_SLC_QO_MASK_6 ,Q odd data mask 6" "Not masked,Masked" textline " " bitfld.word 0x0E 5. " RX_SLC_QO_MASK_5 ,Q odd data mask 5" "Not masked,Masked" bitfld.word 0x0E 4. " RX_SLC_QO_MASK_4 ,Q odd data mask 4" "Not masked,Masked" textline " " bitfld.word 0x0E 3. " RX_SLC_QO_MASK_3 ,Q odd data mask 3" "Not masked,Masked" bitfld.word 0x0E 2. " RX_SLC_QO_MASK_2 ,Q odd data mask 2" "Not masked,Masked" textline " " bitfld.word 0x0E 1. " RX_SLC_QO_MASK_1 ,Q odd data mask 1" "Not masked,Masked" bitfld.word 0x0E 0. " RX_SLC_QO_MASK_0 ,Q odd data mask 0" "Not masked,Masked" line.word 0x10 "LANE3_RX_SLC_EE_MASK,RX Sampler Latch Calibration E Even Data Mask Register Lane 3" bitfld.word 0x10 9. " RX_SLC_EE_MASK_9 ,E even data mask 9" "Not masked,Masked" bitfld.word 0x10 8. " RX_SLC_EE_MASK_8 ,E even data mask 8" "Not masked,Masked" textline " " bitfld.word 0x10 7. " RX_SLC_EE_MASK_7 ,E even data mask 7" "Not masked,Masked" bitfld.word 0x10 6. " RX_SLC_EE_MASK_6 ,E even data mask 6" "Not masked,Masked" textline " " bitfld.word 0x10 5. " RX_SLC_EE_MASK_5 ,E even data mask 5" "Not masked,Masked" bitfld.word 0x10 4. " RX_SLC_EE_MASK_4 ,E even data mask 4" "Not masked,Masked" textline " " bitfld.word 0x10 3. " RX_SLC_EE_MASK_3 ,E even data mask 3" "Not masked,Masked" bitfld.word 0x10 2. " RX_SLC_EE_MASK_2 ,E even data mask 2" "Not masked,Masked" textline " " bitfld.word 0x10 1. " RX_SLC_EE_MASK_1 ,E even data mask 1" "Not masked,Masked" bitfld.word 0x10 0. " RX_SLC_EE_MASK_0 ,E even data mask 0" "Not masked,Masked" line.word 0x12 "LANE3_RX_SLC_EO_MASK,RX Sampler Latch Calibration E Odd Data Mask Register Lane 3" bitfld.word 0x12 9. " RX_SLC_EO_MASK_9 ,E odd data mask 9" "Not masked,Masked" bitfld.word 0x12 8. " RX_SLC_EO_MASK_8 ,E odd data mask 8" "Not masked,Masked" textline " " bitfld.word 0x12 7. " RX_SLC_EO_MASK_7 ,E odd data mask 7" "Not masked,Masked" bitfld.word 0x12 6. " RX_SLC_EO_MASK_6 ,E odd data mask 6" "Not masked,Masked" textline " " bitfld.word 0x12 5. " RX_SLC_EO_MASK_5 ,E odd data mask 5" "Not masked,Masked" bitfld.word 0x12 4. " RX_SLC_EO_MASK_4 ,E odd data mask 4" "Not masked,Masked" textline " " bitfld.word 0x12 3. " RX_SLC_EO_MASK_3 ,E odd data mask 3" "Not masked,Masked" bitfld.word 0x12 2. " RX_SLC_EO_MASK_2 ,E odd data mask 2" "Not masked,Masked" textline " " bitfld.word 0x12 1. " RX_SLC_EO_MASK_1 ,E odd data mask 1" "Not masked,Masked" bitfld.word 0x12 0. " RX_SLC_EO_MASK_0 ,E odd data mask 0" "Not masked,Masked" line.word 0x14 "LANE3_RX_SLC_DATA_THR,RX Sampler Latch Calibration Data Threshold Register Lane 3" bitfld.word 0x14 0.--3. " RX_SLC_DATA_THR_3_0 ,Data threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word (0x8C00+0x200)++0xCB line.word 0x00 "LANE3_RX_SLC_IOP0_CTRL,RX Sampler Latch I Odd Positive 0 Calibration Unit Control Register Lane 3" bitfld.word 0x00 15. " RX_SLC_IOP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x00 14. " RX_SLC_IOP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x00 13. " RX_SLC_IOP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x00 12. " RX_SLC_IOP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x00 0.--5. " RX_SLC_IOP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE3_RX_SLC_IOP0_OVRD,RX Sampler Latch I Odd Positive 0 Calibration Unit Override Register Lane 3" bitfld.word 0x02 15. " RX_SLC_IOP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x02 14. " RX_SLC_IOP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x02 0.--5. " RX_SLC_IOP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE3_RX_SLC_IOP0_START,RX Sampler Latch I Odd Positive 0 Calibration Unit Start Register Lane 3" bitfld.word 0x04 15. " RX_SLC_IOP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x04 0.--5. " RX_SLC_IOP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x06 "LANE3_RX_SLC_IOP0_TUNE,RX Sampler Latch I Odd Positive 0 Calibration Unit Tune Register Lane 3" bitfld.word 0x06 0.--5. " RX_SLC_IOP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "LANE3_RX_SLC_IOP1_CTRL,RX Sampler Latch I Odd Positive 1 Calibration Unit Control Register Lane 3" bitfld.word 0x08 15. " RX_SLC_IOP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x08 14. " RX_SLC_IOP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x08 13. " RX_SLC_IOP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x08 12. " RX_SLC_IOP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x08 0.--5. " RX_SLC_IOP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0A "LANE3_RX_SLC_IOP1_OVRD,RX Sampler Latch I Odd Positive 1 Calibration Unit Override Register Lane 3" bitfld.word 0x0A 15. " RX_SLC_IOP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x0A 14. " RX_SLC_IOP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x0A 0.--5. " RX_SLC_IOP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0C "LANE3_RX_SLC_IOP1_START,RX Sampler Latch I Odd Positive 1 Calibration Unit Start Register Lane 3" bitfld.word 0x0C 15. " RX_SLC_IOP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x0C 0.--5. " RX_SLC_IOP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0E "LANE3_RX_SLC_IOP1_TUNE,RX Sampler Latch I Odd Positive 1 Calibration Unit Tune Register Lane 3" bitfld.word 0x0E 0.--5. " RX_SLC_IOP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x10 "LANE3_RX_SLC_QOP0_CTRL,RX Sampler Latch Q Odd Positive 0 Calibration Unit Control Register Lane 3" bitfld.word 0x10 15. " RX_SLC_QOP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x10 14. " RX_SLC_QOP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x10 13. " RX_SLC_QOP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x10 12. " RX_SLC_QOP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x10 0.--5. " RX_SLC_QOP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x12 "LANE3_RX_SLC_QOP0_OVRD,RX Sampler Latch Q Odd Positive 0 Calibration Unit Override Register Lane 3" bitfld.word 0x12 15. " RX_SLC_QOP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x12 14. " RX_SLC_QOP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x12 0.--5. " RX_SLC_QOP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x14 "LANE3_RX_SLC_QOP0_START,RX Sampler Latch Q Odd Positive 0 Calibration Unit Start Register Lane 3" bitfld.word 0x14 15. " RX_SLC_QOP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x14 0.--5. " RX_SLC_QOP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x16 "LANE3_RX_SLC_QOP0_TUNE,RX Sampler Latch Q Odd Positive 0 Calibration Unit Tune Register Lane 3" bitfld.word 0x16 0.--5. " RX_SLC_QOP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x18 "LANE3_RX_SLC_QOP1_CTRL,RX Sampler Latch Q Odd Positive 1 Calibration Unit Control Register Lane 3" bitfld.word 0x18 15. " RX_SLC_QOP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x18 14. " RX_SLC_QOP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x18 13. " RX_SLC_QOP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x18 12. " RX_SLC_QOP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x18 0.--5. " RX_SLC_QOP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x1A "LANE3_RX_SLC_QOP1_OVRD,RX Sampler Latch Q Odd Positive 1 Calibration Unit Override Register Lane 3" bitfld.word 0x1A 15. " RX_SLC_QOP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x1A 14. " RX_SLC_QOP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x1A 0.--5. " RX_SLC_QOP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x1C "LANE3_RX_SLC_QOP1_START,RX Sampler Latch Q Odd Positive 1 Calibration Unit Start Register Lane 3" bitfld.word 0x1C 15. " RX_SLC_QOP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x1C 0.--5. " RX_SLC_QOP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x1E "LANE3_RX_SLC_QOP1_TUNE,RX Sampler Latch Q Odd Positive 1 Calibration Unit Tune Register Lane 3" bitfld.word 0x1E 0.--5. " RX_SLC_QOP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x20 "LANE3_RX_SLC_EOP0_CTRL,RX Sampler Latch E Odd Positive 0 Calibration Unit Control Register Lane 3" bitfld.word 0x20 15. " RX_SLC_EOP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x20 14. " RX_SLC_EOP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x20 13. " RX_SLC_EOP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x20 12. " RX_SLC_EOP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x20 0.--5. " RX_SLC_EOP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x22 "LANE3_RX_SLC_EOP0_OVRD,RX Sampler Latch E Odd Positive 0 Calibration Unit Override Register Lane 3" bitfld.word 0x22 15. " RX_SLC_EOP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x22 14. " RX_SLC_EOP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x22 0.--5. " RX_SLC_EOP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x24 "LANE3_RX_SLC_EOP0_START,RX Sampler Latch E Odd Positive 0 Calibration Unit Start Register Lane 3" bitfld.word 0x24 15. " RX_SLC_EOP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x24 0.--5. " RX_SLC_EOP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x26 "LANE3_RX_SLC_EOP0_TUNE,RX Sampler Latch E Odd Positive 0 Calibration Unit Tune Register Lane 3" bitfld.word 0x26 0.--5. " RX_SLC_EOP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x28 "LANE3_RX_SLC_EOP1_CTRL,RX Sampler Latch E Odd Positive 1 Calibration Unit Control Register Lane 3" bitfld.word 0x28 15. " RX_SLC_EOP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x28 14. " RX_SLC_EOP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x28 13. " RX_SLC_EOP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x28 12. " RX_SLC_EOP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x28 0.--5. " RX_SLC_EOP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x2A "LANE3_RX_SLC_EOP1_OVRD,RX Sampler Latch E Odd Positive 1 Calibration Unit Override Register Lane 3" bitfld.word 0x2A 15. " RX_SLC_EOP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x2A 14. " RX_SLC_EOP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x2A 0.--5. " RX_SLC_EOP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x2C "LANE3_RX_SLC_EOP1_START,RX Sampler Latch E Odd Positive 1 Calibration Unit Start Register Lane 3" bitfld.word 0x2C 15. " RX_SLC_EOP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x2C 0.--5. " RX_SLC_EOP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x2E "LANE3_RX_SLC_EOP1_TUNE,RX Sampler Latch E Odd Positive 1 Calibration Unit Tune Register Lane 3" bitfld.word 0x2E 0.--5. " RX_SLC_EOP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x30 "LANE3_RX_SLC_ION0_CTRL,RX Sampler Latch I Odd Negative 0 Calibration Unit Control Register Lane 3" bitfld.word 0x30 15. " RX_SLC_ION0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x30 14. " RX_SLC_ION0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x30 13. " RX_SLC_ION0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x30 12. " RX_SLC_ION0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x30 0.--5. " RX_SLC_ION0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x32 "LANE3_RX_SLC_ION0_OVRD,RX Sampler Latch I Odd Negative 0 Calibration Unit Override Register Lane 3" bitfld.word 0x32 15. " RX_SLC_ION0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x32 14. " RX_SLC_ION0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x32 0.--5. " RX_SLC_ION0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x34 "LANE3_RX_SLC_ION0_START,RX Sampler Latch I Odd Negative 0 Calibration Unit Start Register Lane 3" bitfld.word 0x34 15. " RX_SLC_ION0_START_15 ,Calibration direction" "0,1" bitfld.word 0x34 0.--5. " RX_SLC_ION0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x36 "LANE3_RX_SLC_ION0_TUNE,RX Sampler Latch I Odd Negative 0 Calibration Unit Tune Register Lane 3" bitfld.word 0x36 0.--5. " RX_SLC_ION0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x38 "LANE3_RX_SLC_ION1_CTRL,RX Sampler Latch I Odd Negative 1 Calibration Unit Control Register Lane 3" bitfld.word 0x38 15. " RX_SLC_ION1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x38 14. " RX_SLC_ION1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x38 13. " RX_SLC_ION1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x38 12. " RX_SLC_ION1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x38 0.--5. " RX_SLC_ION1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x3A "LANE3_RX_SLC_ION1_OVRD,RX Sampler Latch I Odd Negative 1 Calibration Unit Override Register Lane 3" bitfld.word 0x3A 15. " RX_SLC_ION1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x3A 14. " RX_SLC_ION1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x3A 0.--5. " RX_SLC_ION1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x3C "LANE3_RX_SLC_ION1_START,RX Sampler Latch I Odd Negative 1 Calibration Unit Start Register Lane 3" bitfld.word 0x3C 15. " RX_SLC_ION1_START_15 ,Calibration direction" "0,1" bitfld.word 0x3C 0.--5. " RX_SLC_ION1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x3E "LANE3_RX_SLC_ION1_TUNE,RX Sampler Latch I Odd Negative 1 Calibration Unit Tune Register Lane 3" bitfld.word 0x3E 0.--5. " RX_SLC_ION1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x40 "LANE3_RX_SLC_QON0_CTRL,RX Sampler Latch Q Odd Negative 0 Calibration Unit Control Register Lane 3" bitfld.word 0x40 15. " RX_SLC_QON0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x40 14. " RX_SLC_QON0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x40 13. " RX_SLC_QON0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x40 12. " RX_SLC_QON0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x40 0.--5. " RX_SLC_QON0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x42 "LANE3_RX_SLC_QON0_OVRD,RX Sampler Latch Q Odd Negative 0 Calibration Unit Override Register Lane 3" bitfld.word 0x42 15. " RX_SLC_QON0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x42 14. " RX_SLC_QON0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x42 0.--5. " RX_SLC_QON0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x44 "LANE3_RX_SLC_QON0_START,RX Sampler Latch Q Odd Negative 0 Calibration Unit Start Register Lane 3" bitfld.word 0x44 15. " RX_SLC_QON0_START_15 ,Calibration direction" "0,1" bitfld.word 0x44 0.--5. " RX_SLC_QON0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x46 "LANE3_RX_SLC_QON0_TUNE,RX Sampler Latch Q Odd Negative 0 Calibration Unit Tune Register Lane 3" bitfld.word 0x46 0.--5. " RX_SLC_QON0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x48 "LANE3_RX_SLC_QON1_CTRL,RX Sampler Latch Q Odd Negative 1 Calibration Unit Control Register Lane 3" bitfld.word 0x48 15. " RX_SLC_QON1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x48 14. " RX_SLC_QON1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x48 13. " RX_SLC_QON1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x48 12. " RX_SLC_QON1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x48 0.--5. " RX_SLC_QON1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x4A "LANE3_RX_SLC_QON1_OVRD,RX Sampler Latch Q Odd Negative 1 Calibration Unit Override Register Lane 3" bitfld.word 0x4A 15. " RX_SLC_QON1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x4A 14. " RX_SLC_QON1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x4A 0.--5. " RX_SLC_QON1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x4C "LANE3_RX_SLC_QON1_START,RX Sampler Latch Q Odd Negative 1 Calibration Unit Start Register Lane 3" bitfld.word 0x4C 15. " RX_SLC_QON1_START_15 ,Calibration direction" "0,1" bitfld.word 0x4C 0.--5. " RX_SLC_QON1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x4E "LANE3_RX_SLC_QON1_TUNE,RX Sampler Latch Q Odd Negative 1 Calibration Unit Tune Register Lane 3" bitfld.word 0x4E 0.--5. " RX_SLC_QON1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x50 "LANE3_RX_SLC_EON0_CTRL,RX Sampler Latch E Odd Negative 0 Calibration Unit Control Register Lane 3" bitfld.word 0x50 15. " RX_SLC_EON0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x50 14. " RX_SLC_EON0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x50 13. " RX_SLC_EON0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x50 12. " RX_SLC_EON0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x50 0.--5. " RX_SLC_EON0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x52 "LANE3_RX_SLC_EON0_OVRD,RX Sampler Latch E Odd Negative 0 Calibration Unit Override Register Lane 3" bitfld.word 0x52 15. " RX_SLC_EON0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x52 14. " RX_SLC_EON0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x52 0.--5. " RX_SLC_EON0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x54 "LANE3_RX_SLC_EON0_START,RX Sampler Latch E Odd Negative 0 Calibration Unit Start Register Lane 3" bitfld.word 0x54 15. " RX_SLC_EON0_START_15 ,Calibration direction" "0,1" bitfld.word 0x54 0.--5. " RX_SLC_EON0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x56 "LANE3_RX_SLC_EON0_TUNE,RX Sampler Latch E Odd Negative 0 Calibration Unit Tune Register Lane 3" bitfld.word 0x56 0.--5. " RX_SLC_EON0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x58 "LANE3_RX_SLC_EON1_CTRL,RX Sampler Latch E Odd Negative 1 Calibration Unit Control Register Lane 3" bitfld.word 0x58 15. " RX_SLC_EON1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x58 14. " RX_SLC_EON1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x58 13. " RX_SLC_EON1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x58 12. " RX_SLC_EON1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x58 0.--5. " RX_SLC_EON1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x5A "LANE3_RX_SLC_EON1_OVRD,RX Sampler Latch E Odd Negative 1 Calibration Unit Override Register Lane 3" bitfld.word 0x5A 15. " RX_SLC_EON1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x5A 14. " RX_SLC_EON1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x5A 0.--5. " RX_SLC_EON1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x5C "LANE3_RX_SLC_EON1_START,RX Sampler Latch E Odd Negative 1 Calibration Unit Start Register Lane 3" bitfld.word 0x5C 15. " RX_SLC_EON1_START_15 ,Calibration direction" "0,1" bitfld.word 0x5C 0.--5. " RX_SLC_EON1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x5E "LANE3_RX_SLC_EON1_TUNE,RX Sampler Latch E Odd Negative 1 Calibration Unit Tune Register Lane 3" bitfld.word 0x5E 0.--5. " RX_SLC_EON1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x60 "LANE3_RX_SLC_IEP0_CTRL,RX Sampler Latch I Even Positive 0 Calibration Unit Control Register Lane 3" bitfld.word 0x60 15. " RX_SLC_IEP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x60 14. " RX_SLC_IEP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x60 13. " RX_SLC_IEP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x60 12. " RX_SLC_IEP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x60 0.--5. " RX_SLC_IEP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x62 "LANE3_RX_SLC_IEP0_OVRD,RX Sampler Latch I Even Positive 0 Calibration Unit Override Register Lane 3" bitfld.word 0x62 15. " RX_SLC_IEP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x62 14. " RX_SLC_IEP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x62 0.--5. " RX_SLC_IEP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x64 "LANE3_RX_SLC_IEP0_START,RX Sampler Latch I Even Positive 0 Calibration Unit Start Register Lane 3" bitfld.word 0x64 15. " RX_SLC_IEP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x64 0.--5. " RX_SLC_IEP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x66 "LANE3_RX_SLC_IEP0_TUNE,RX Sampler Latch I Even Positive 0 Calibration Unit Tune Register Lane 3" bitfld.word 0x66 0.--5. " RX_SLC_IEP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x68 "LANE3_RX_SLC_IEP1_CTRL,RX Sampler Latch I Even Positive 1 Calibration Unit Control Register Lane 3" bitfld.word 0x68 15. " RX_SLC_IEP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x68 14. " RX_SLC_IEP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x68 13. " RX_SLC_IEP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x68 12. " RX_SLC_IEP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x68 0.--5. " RX_SLC_IEP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x6A "LANE3_RX_SLC_IEP1_OVRD,RX Sampler Latch I Even Positive 1 Calibration Unit Override Register Lane 3" bitfld.word 0x6A 15. " RX_SLC_IEP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x6A 14. " RX_SLC_IEP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x6A 0.--5. " RX_SLC_IEP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x6C "LANE3_RX_SLC_IEP1_START,RX Sampler Latch I Even Positive 1 Calibration Unit Start Register Lane 3" bitfld.word 0x6C 15. " RX_SLC_IEP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x6C 0.--5. " RX_SLC_IEP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x6E "LANE3_RX_SLC_IEP1_TUNE,RX Sampler Latch I Even Positive 1 Calibration Unit Tune Register Lane 3" bitfld.word 0x6E 0.--5. " RX_SLC_IEP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x70 "LANE3_RX_SLC_QEP0_CTRL,RX Sampler Latch Q Even Positive 0 Calibration Unit Control Register Lane 3" bitfld.word 0x70 15. " RX_SLC_QEP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x70 14. " RX_SLC_QEP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x70 13. " RX_SLC_QEP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x70 12. " RX_SLC_QEP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x70 0.--5. " RX_SLC_QEP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x72 "LANE3_RX_SLC_QEP0_OVRD,RX Sampler Latch Q Even Positive 0 Calibration Unit Override Register Lane 3" bitfld.word 0x72 15. " RX_SLC_QEP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x72 14. " RX_SLC_QEP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x72 0.--5. " RX_SLC_QEP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x74 "LANE3_RX_SLC_QEP0_START,RX Sampler Latch Q Even Positive 0 Calibration Unit Start Register Lane 3" bitfld.word 0x74 15. " RX_SLC_QEP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x74 0.--5. " RX_SLC_QEP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x76 "LANE3_RX_SLC_QEP0_TUNE,RX Sampler Latch Q Even Positive 0 Calibration Unit Tune Register Lane 3" bitfld.word 0x76 0.--5. " RX_SLC_QEP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x78 "LANE3_RX_SLC_QEP1_CTRL,RX Sampler Latch Q Even Positive 1 Calibration Unit Control Register Lane 3" bitfld.word 0x78 15. " RX_SLC_QEP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x78 14. " RX_SLC_QEP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x78 13. " RX_SLC_QEP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x78 12. " RX_SLC_QEP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x78 0.--5. " RX_SLC_QEP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x7A "LANE3_RX_SLC_QEP1_OVRD,RX Sampler Latch Q Even Positive 1 Calibration Unit Override Register Lane 3" bitfld.word 0x7A 15. " RX_SLC_QEP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x7A 14. " RX_SLC_QEP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x7A 0.--5. " RX_SLC_QEP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x7C "LANE3_RX_SLC_QEP1_START,RX Sampler Latch Q Even Positive 1 Calibration Unit Start Register Lane 3" bitfld.word 0x7C 15. " RX_SLC_QEP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x7C 0.--5. " RX_SLC_QEP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x7E "LANE3_RX_SLC_QEP1_TUNE,RX Sampler Latch Q Even Positive 1 Calibration Unit Tune Register Lane3" bitfld.word 0x7E 0.--5. " RX_SLC_QEP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x80 "LANE3_RX_SLC_EEP0_CTRL,RX Sampler Latch E Even Positive 0 Calibration Unit Control Register Lane 3" bitfld.word 0x80 15. " RX_SLC_EEP0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x80 14. " RX_SLC_EEP0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x80 13. " RX_SLC_EEP0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x80 12. " RX_SLC_EEP0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x80 0.--5. " RX_SLC_EEP0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x82 "LANE3_RX_SLC_EEP0_OVRD,RX Sampler Latch E Even Positive 0 Calibration Unit Override Register Lane 3" bitfld.word 0x82 15. " RX_SLC_EEP0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x82 14. " RX_SLC_EEP0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x82 0.--5. " RX_SLC_EEP0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x84 "LANE3_RX_SLC_EEP0_START,RX Sampler Latch E Even Positive 0 Calibration Unit Start Register Lane 3" bitfld.word 0x84 15. " RX_SLC_EEP0_START_15 ,Calibration direction" "0,1" bitfld.word 0x84 0.--5. " RX_SLC_EEP0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x86 "LANE3_RX_SLC_EEP0_TUNE,RX Sampler Latch E Even Positive 0 Calibration Unit Tune Register Lane3" bitfld.word 0x86 0.--5. " RX_SLC_EEP0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x88 "LANE3_RX_SLC_EEP1_CTRL,RX Sampler Latch E Even Positive 1 Calibration Unit Control Register Lane 3" bitfld.word 0x88 15. " RX_SLC_EEP1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x88 14. " RX_SLC_EEP1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x88 13. " RX_SLC_EEP1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x88 12. " RX_SLC_EEP1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x88 0.--5. " RX_SLC_EEP1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x8A "LANE3_RX_SLC_EEP1_OVRD,RX Sampler Latch E Even Positive 1 Calibration Unit Override Register Lane 3" bitfld.word 0x8A 15. " RX_SLC_EEP1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x8A 14. " RX_SLC_EEP1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x8A 0.--5. " RX_SLC_EEP1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x8C "LANE3_RX_SLC_EEP1_START,RX Sampler Latch E Even Positive 1 Calibration Unit Start Register Lane 3" bitfld.word 0x8C 15. " RX_SLC_EEP1_START_15 ,Calibration direction" "0,1" bitfld.word 0x8C 0.--5. " RX_SLC_EEP1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x8E "LANE3_RX_SLC_EEP1_TUNE,RX Sampler Latch E Even Positive 1 Calibration Unit Tune Register Lane 3" bitfld.word 0x8E 0.--5. " RX_SLC_EEP1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x90 "LANE3_RX_SLC_IEN0_CTRL,RX Sampler Latch I Even Negative 0 Calibration Unit Control Register Lane 3" bitfld.word 0x90 15. " RX_SLC_IEN0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x90 14. " RX_SLC_IEN0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x90 13. " RX_SLC_IEN0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x90 12. " RX_SLC_IEN0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x90 0.--5. " RX_SLC_IEN0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x92 "LANE3_RX_SLC_IEN0_OVRD,RX Sampler Latch I Even Negative 0 Calibration Unit Override Register Lane 3" bitfld.word 0x92 15. " RX_SLC_IEN0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x92 14. " RX_SLC_IEN0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x92 0.--5. " RX_SLC_IEN0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x94 "LANE3_RX_SLC_IEN0_START,RX Sampler Latch I Even Negative 0 Calibration Unit Start Register Lane 3" bitfld.word 0x94 15. " RX_SLC_IEN0_START_15 ,Calibration direction" "0,1" bitfld.word 0x94 0.--5. " RX_SLC_IEN0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x96 "LANE3_RX_SLC_IEN0_TUNE,RX Sampler Latch I Even Negative 0 Calibration Unit Tune Register Lane 3" bitfld.word 0x96 0.--5. " RX_SLC_IEN0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x98 "LANE3_RX_SLC_IEN1_CTRL,RX Sampler Latch I Even Negative 1 Calibration Unit Control Register Lane 3" bitfld.word 0x98 15. " RX_SLC_IEN1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0x98 14. " RX_SLC_IEN1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0x98 13. " RX_SLC_IEN1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0x98 12. " RX_SLC_IEN1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0x98 0.--5. " RX_SLC_IEN1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x9A "LANE3_RX_SLC_IEN1_OVRD,RX Sampler Latch I Even Negative 1 Calibration Unit Override Register Lane 3" bitfld.word 0x9A 15. " RX_SLC_IEN1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0x9A 14. " RX_SLC_IEN1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x9A 0.--5. " RX_SLC_IEN1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x9C "LANE3_RX_SLC_IEN1_START,RX Sampler Latch I Even Negative 1 Calibration Unit Start Register Lane 3" bitfld.word 0x9C 15. " RX_SLC_IEN1_START_15 ,Calibration direction" "0,1" bitfld.word 0x9C 0.--5. " RX_SLC_IEN1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x9E "LANE3_RX_SLC_IEN1_TUNE,RX Sampler Latch I Even Negative 1 Calibration Unit Tune Register Lane 3" bitfld.word 0x9E 0.--5. " RX_SLC_IEN1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA0 "LANE3_RX_SLC_QEN0_CTRL,RX Sampler Latch Q Even Negative 0 Calibration Unit Control Register Lane 3" bitfld.word 0xA0 15. " RX_SLC_QEN0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xA0 14. " RX_SLC_QEN0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xA0 13. " RX_SLC_QEN0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xA0 12. " RX_SLC_QEN0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xA0 0.--5. " RX_SLC_QEN0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA2 "LANE3_RX_SLC_QEN0_OVRD,RX Sampler Latch Q Even Negative 0 Calibration Unit Override Register Lane 3" bitfld.word 0xA2 15. " RX_SLC_QEN0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xA2 14. " RX_SLC_QEN0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xA2 0.--5. " RX_SLC_QEN0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA4 "LANE3_RX_SLC_QEN0_START,RX Sampler Latch Q Even Negative 0 Calibration Unit Start Register Lane 3" bitfld.word 0xA4 15. " RX_SLC_QEN0_START_15 ,Calibration direction" "0,1" bitfld.word 0xA4 0.--5. " RX_SLC_QEN0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA6 "LANE3_RX_SLC_QEN0_TUNE,RX Sampler Latch Q Even Negative 0 Calibration Unit Tune Register Lane 3" bitfld.word 0xA6 0.--5. " RX_SLC_QEN0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xA8 "LANE3_RX_SLC_QEN1_CTRL,RX Sampler Latch Q Even Negative 1 Calibration Unit Control Register Lane 3" bitfld.word 0xA8 15. " RX_SLC_QEN1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xA8 14. " RX_SLC_QEN1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xA8 13. " RX_SLC_QEN1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xA8 12. " RX_SLC_QEN1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xA8 0.--5. " RX_SLC_QEN1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xAA "LANE3_RX_SLC_QEN1_OVRD,RX Sampler Latch Q Even Negative 1 Calibration Unit Override Register Lane 3" bitfld.word 0xAA 15. " RX_SLC_QEN1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xAA 14. " RX_SLC_QEN1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xAA 0.--5. " RX_SLC_QEN1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xAC "LANE3_RX_SLC_QEN1_START,RX Sampler Latch Q Even Negative 1 Calibration Unit Start Register Lane 3" bitfld.word 0xAC 15. " RX_SLC_QEN1_START_15 ,Calibration direction" "0,1" bitfld.word 0xAC 0.--5. " RX_SLC_QEN1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xAE "LANE3_RX_SLC_QEN1_TUNE,RX Sampler Latch Q Even Negative 1 Calibration Unit Tune Register Lane 3" bitfld.word 0xAE 0.--5. " RX_SLC_QEN1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB0 "LANE3_RX_SLC_EEN0_CTRL,RX Sampler Latch E Even Negative 0 Calibration Unit Control Register Lane 3" bitfld.word 0xB0 15. " RX_SLC_EEN0_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xB0 14. " RX_SLC_EEN0_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xB0 13. " RX_SLC_EEN0_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xB0 12. " RX_SLC_EEN0_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xB0 0.--5. " RX_SLC_EEN0_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB2 "LANE3_RX_SLC_EEN0_OVRD,RX Sampler Latch E Even Negative 0 Calibration Unit Override Register Lane 3" bitfld.word 0xB2 15. " RX_SLC_EEN0_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xB2 14. " RX_SLC_EEN0_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xB2 0.--5. " RX_SLC_EEN0_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB4 "LANE3_RX_SLC_EEN0_START,RX Sampler Latch E Even Negative 0 Calibration Unit Start Register Lane 3" bitfld.word 0xB4 15. " RX_SLC_EEN0_START_15 ,Calibration direction" "0,1" bitfld.word 0xB4 0.--5. " RX_SLC_EEN0_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB6 "LANE3_RX_SLC_EEN0_TUNE,RX Sampler Latch E Even Negative 0 Calibration Unit Tune Register 3" bitfld.word 0xB6 0.--5. " RX_SLC_EEN0_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xB8 "LANE3_RX_SLC_EEN1_CTRL,RX Sampler Latch E Even Negative 1 Calibration Unit Control Register Lane 3" bitfld.word 0xB8 15. " RX_SLC_EEN1_CTRL_15 ,Start calibration" "Not started,Started" rbitfld.word 0xB8 14. " RX_SLC_EEN1_CTRL_14 ,Calibration done" "Not done,Done" textline " " rbitfld.word 0xB8 13. " RX_SLC_EEN1_CTRL_13 ,No calibration response" "Not responded,Responded" rbitfld.word 0xB8 12. " RX_SLC_EEN1_CTRL_12 ,Current comparator response" "Not responded,Responded" textline " " rbitfld.word 0xB8 0.--5. " RX_SLC_EEN1_CTRL_5_0 ,Calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xBA "LANE3_RX_SLC_EEN1_OVRD,RX Sampler Latch E Even Negative 1 Calibration Unit Override Register Lane 3" bitfld.word 0xBA 15. " RX_SLC_EEN1_OVRD_15 ,Calibration code override enable" "Disabled,Enabled" bitfld.word 0xBA 14. " RX_SLC_EEN1_OVRD_14 ,Analog calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0xBA 0.--5. " RX_SLC_EEN1_OVRD_5_0 ,Calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xBC "LANE3_RX_SLC_EEN1_START,RX Sampler Latch E Even Negative 1 Calibration Unit Start Register Lane 3" bitfld.word 0xBC 15. " RX_SLC_EEN1_START_15 ,Calibration direction" "0,1" bitfld.word 0xBC 0.--5. " RX_SLC_EEN1_START_5_0 ,Start calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xBE "LANE3_RX_SLC_EEN1_TUNE,RX Sampler Latch E Even Negative 1 Calibration Unit Tune Register Lane 3" bitfld.word 0xBE 0.--5. " RX_SLC_EEN1_TUNE_5_0 ,Calibration tune value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0xC0 "LANE3_RX_REE_U3GCSM_CTRL,REE USB 3 General Control State Machine Control Register Lane 3" bitfld.word 0xC0 1. " RX_REE_U3GCSM_CTRL_1 ,Force run equalization" "Not forced,Forced" bitfld.word 0xC0 0. " RX_REE_U3GCSM_CTRL_0 ,General control state machine function enable" "Disabled,Enabled" line.word 0xC2 "LANE3_RX_REE_U3GCSM_EQENM_PH1,REE USB 3 General Control State Machine Phase 1 Equalization Enable Mask Register Lane 3" bitfld.word 0xC2 14. " RX_REE_U3GCSM_EQENM_PH1_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0xC2 9. " RX_REE_U3GCSM_EQENM_PH1_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0xC2 8. " RX_REE_U3GCSM_EQENM_PH1_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0xC2 7. " RX_REE_U3GCSM_EQENM_PH1_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0xC2 6. " RX_REE_U3GCSM_EQENM_PH1_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0xC2 5. " RX_REE_U3GCSM_EQENM_PH1_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0xC2 2. " RX_REE_U3GCSM_EQENM_PH1_2 ,RX tap 3" "0,1" bitfld.word 0xC2 1. " RX_REE_U3GCSM_EQENM_PH1_1 ,RX tap 2" "0,1" textline " " bitfld.word 0xC2 0. " RX_REE_U3GCSM_EQENM_PH1_0 ,RX tap 1" "0,1" line.word 0xC4 "LANE3_RX_REE_U3GCSM_EQENM_PH2,REE USB 3 General Control State Machine Phase 2 Equalization Enable Mask Register Lane 3" bitfld.word 0xC4 14. " RX_REE_U3GCSM_EQENM_PH2_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0xC4 9. " RX_REE_U3GCSM_EQENM_PH2_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0xC4 8. " RX_REE_U3GCSM_EQENM_PH2_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0xC4 7. " RX_REE_U3GCSM_EQENM_PH2_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0xC4 6. " RX_REE_U3GCSM_EQENM_PH2_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0xC4 5. " RX_REE_U3GCSM_EQENM_PH2_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0xC4 2. " RX_REE_U3GCSM_EQENM_PH2_2 ,RX tap 3" "0,1" bitfld.word 0xC4 1. " RX_REE_U3GCSM_EQENM_PH2_1 ,RX tap 2" "0,1" textline " " bitfld.word 0xC4 0. " RX_REE_U3GCSM_EQENM_PH2_0 ,RX tap 1" "0,1" line.word 0xC6 "LANE3_RX_REE_U3GCSM_START_TMR,REE USB 3 General Control State Machine Start Timer Value Register Lane 3" line.word 0xC8 "LANE3_RX_REE_U3GCSM_RUN_PH1_TMR,REE USB 3 General Control State Machine Run Phase 1 Timer Value Register Lane 3" line.word 0xCA "LANE3_RX_REE_U3GCSM_RUN_PH2_TMR,REE USB 3 General Control State Machine Run Phase 2 Timer Value Register Lane 3" group.word (0x8C00+0xD0)++0x0B line.word 0x00 "LANE3_RX_REE_G2GCSM_CTRL,REE PCIe Gen 2 General Control State Machine Control Register Lane 3" bitfld.word 0x00 1. " RX_REE_G2GCSM_CTRL_1 ,Force run equalization" "Not forced,Forced" bitfld.word 0x00 0. " RX_REE_G2GCSM_CTRL_0 ,General control state machine function enable" "Disabled,Enabled" line.word 0x02 "LANE3_RX_REE_G2GCSM_EQENM_PH1,REE PCIe Gen 2 General Control State Machine Phase 1 Equalization Enable Mask Register Lane 3" bitfld.word 0x02 14. " RX_REE_G2GCSM_EQENM_PH1_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x02 9. " RX_REE_G2GCSM_EQENM_PH1_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x02 8. " RX_REE_G2GCSM_EQENM_PH1_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x02 7. " RX_REE_G2GCSM_EQENM_PH1_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x02 6. " RX_REE_G2GCSM_EQENM_PH1_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x02 5. " RX_REE_G2GCSM_EQENM_PH1_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x02 2. " RX_REE_G2GCSM_EQENM_PH1_2 ,RX tap 3" "0,1" bitfld.word 0x02 1. " RX_REE_G2GCSM_EQENM_PH1_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x02 0. " RX_REE_G2GCSM_EQENM_PH1_0 ,RX tap 1" "0,1" line.word 0x04 "LANE3_RX_REE_G2GCSM_EQENM_PH2,REE USB 2 General Control State Machine Phase 2 Equalization Enable Mask Register Lane 3" bitfld.word 0x04 14. " RX_REE_G2GCSM_EQENM_PH2_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x04 9. " RX_REE_G2GCSM_EQENM_PH2_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x04 8. " RX_REE_G2GCSM_EQENM_PH2_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x04 7. " RX_REE_G2GCSM_EQENM_PH2_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x04 6. " RX_REE_G2GCSM_EQENM_PH2_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x04 5. " RX_REE_G2GCSM_EQENM_PH2_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x04 2. " RX_REE_G2GCSM_EQENM_PH2_2 ,RX tap 3" "0,1" bitfld.word 0x04 1. " RX_REE_G2GCSM_EQENM_PH2_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x04 0. " RX_REE_G2GCSM_EQENM_PH2_0 ,RX tap 1" "0,1" line.word 0x06 "LANE3_RX_REE_G2GCSM_START_TMR,REE PCIe Gen 2 General Control State Machine Start Timer Value Register Lane 3" line.word 0x08 "LANE3_RX_REE_G2GCSM_RUN_PH1_TMR,REE PCIe Gen 2 General Control State Machine Run Phase 1 Timer Value Register Lane 3" line.word 0x0A "LANE3_RX_REE_G2GCSM_RUN_PH2_TMR,REE PCIe Gen 2 General Control State Machine Run Phase 2 Timer Value Register Lane 3" group.word (0x8C00+0xF0)++0x0B line.word 0x00 "LANE3_RX_REE_PERGCSM_CTRL,REE Periodic General Control State Machine Control Register Lane 3" bitfld.word 0x00 1. " RX_REE_PERGCSM_CTRL_1 ,Force run equalization" "Not forced,Forced" bitfld.word 0x00 0. " RX_REE_PERGCSM_CTRL_0 ,General control state machine function enable" "Disabled,Enabled" line.word 0x02 "LANE3_RX_REE_PERGCSM_EQENM_PH1,REE Periodic General Control State Machine Phase 1 Equalization Enable Mask Register Lane 3" bitfld.word 0x02 14. " RX_REE_PERGCSM_EQENM_PH1_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x02 9. " RX_REE_PERGCSM_EQENM_PH1_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x02 8. " RX_REE_PERGCSM_EQENM_PH1_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x02 7. " RX_REE_PERGCSM_EQENM_PH1_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x02 6. " RX_REE_PERGCSM_EQENM_PH1_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x02 5. " RX_REE_PERGCSM_EQENM_PH1_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x02 2. " RX_REE_PERGCSM_EQENM_PH1_2 ,RX tap 3" "0,1" bitfld.word 0x02 1. " RX_REE_PERGCSM_EQENM_PH1_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x02 0. " RX_REE_PERGCSM_EQENM_PH1_0 ,RX tap 1" "0,1" line.word 0x04 "LANE3_RX_REE_PERGCSM_EQENM_PH2,REE Periodic General Control State Machine Phase 2 Equalization Enable Mask Register Lane 3" bitfld.word 0x04 14. " RX_REE_PERGCSM_EQENM_PH2_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x04 9. " RX_REE_PERGCSM_EQENM_PH2_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x04 8. " RX_REE_PERGCSM_EQENM_PH2_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x04 7. " RX_REE_PERGCSM_EQENM_PH2_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x04 6. " RX_REE_PERGCSM_EQENM_PH2_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x04 5. " RX_REE_PERGCSM_EQENM_PH2_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x04 2. " RX_REE_PERGCSM_EQENM_PH2_2 ,RX tap 3" "0,1" bitfld.word 0x04 1. " RX_REE_PERGCSM_EQENM_PH2_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x04 0. " RX_REE_PERGCSM_EQENM_PH2_0 ,RX tap 1" "0,1" line.word 0x06 "LANE3_RX_REE_PERGCSM_START_TMR,REE Periodic General Control State Machine Start Timer Value Register Lane 3" line.word 0x08 "LANE3_RX_REE_PERGCSM_RUN_PH1_TMR,REE Periodic General Control State Machine Run Phase 1 Timer Value Register Lane 3" line.word 0x0A "LANE3_RX_REE_PERGCSM_RUN_PH2_TMR,REE Periodic General Control State Machine Run Phase 2 Timer Value Register Lane 3" group.word (0x8C00+0x100)++0x05 line.word 0x00 "LANE3_RX_REE_TAP1_CTRL,REE Tap 1 Control Register Lane 3" bitfld.word 0x00 11. " RX_REE_TAP1_CTRL_11 ,Tap coefficient combinational logic zero crossing enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_REE_TAP1_CTRL_10 ,Tap coefficient combinational logic non zero crossing enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_REE_TAP1_CTRL_9 ,Tap coefficient combinational logic bit 0 only enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_REE_TAP1_CTRL_8 ,Receiver DFE tap coefficient disable" "No,Yes" textline " " bitfld.word 0x00 4.--6. " RX_REE_TAP1_CTRL_6_4 ,Tap integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_TAP1_CTRL_3_0 ,Tap sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE3_RX_REE_TAP1_OVRD,REE Tap 1 Override Register Lane 3" bitfld.word 0x02 7. " RX_REE_TAP1_OVRD_7 ,Tap override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_TAP1_OVRD_5_0 ,Tap override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE3_RX_REE_TAP1_DIAG,REE Tap 1 Diagnostics Register Lane 3" bitfld.word 0x04 14. " RX_REE_TAP1_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_TAP1_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_TAP1_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_TAP1_DIAG_5_0 ,Current tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8C00+0x108)++0x05 line.word 0x00 "LANE3_RX_REE_TAP2_CTRL,REE Tap 2 Control Register Lane 3" bitfld.word 0x00 11. " RX_REE_TAP2_CTRL_11 ,Tap coefficient combinational logic zero crossing enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_REE_TAP2_CTRL_10 ,Tap coefficient combinational logic non zero crossing enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_REE_TAP2_CTRL_9 ,Tap coefficient combinational logic bit 0 only enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_REE_TAP2_CTRL_8 ,Receiver DFE tap coefficient disable" "No,Yes" textline " " bitfld.word 0x00 4.--6. " RX_REE_TAP2_CTRL_6_4 ,Tap integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_TAP2_CTRL_3_0 ,Tap sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE3_RX_REE_TAP2_OVRD,REE Tap 2 Override Register Lane 3" bitfld.word 0x02 7. " RX_REE_TAP2_OVRD_7 ,Tap override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_TAP2_OVRD_5_0 ,Tap override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE3_RX_REE_TAP2_DIAG,REE Tap 2 Diagnostics Register Lane 3" bitfld.word 0x04 14. " RX_REE_TAP2_DIAG_14 ,Voter override neg" "No override,Override" bitfld.word 0x04 13. " RX_REE_TAP2_DIAG_13 ,Voter override pos" "0,1" textline " " bitfld.word 0x04 12. " RX_REE_TAP2_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_TAP2_DIAG_5_0 ,Current tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8C00+0x110)++0x05 line.word 0x00 "LANE3_RX_REE_TAP3_CTRL,REE Tap 3 Control Register Lane 3" bitfld.word 0x00 11. " RX_REE_TAP3_CTRL_11 ,Tap coefficient combinational logic zero crossing enable" "Disabled,Enabled" bitfld.word 0x00 10. " RX_REE_TAP3_CTRL_10 ,Tap coefficient combinational logic non zero crossing enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RX_REE_TAP3_CTRL_9 ,Tap coefficient combinational logic bit 0 only enable" "Disabled,Enabled" bitfld.word 0x00 8. " RX_REE_TAP3_CTRL_8 ,Receiver DFE tap coefficient disable" "No,Yes" textline " " bitfld.word 0x00 4.--6. " RX_REE_TAP3_CTRL_6_4 ,Tap integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_TAP3_CTRL_3_0 ,Tap sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE3_RX_REE_TAP3_OVRD,REE Tap 3 Override Register Lane 3" bitfld.word 0x02 7. " RX_REE_TAP3_OVRD_7 ,Tap override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_TAP3_OVRD_5_0 ,Tap override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE3_RX_REE_TAP3_DIAG,REE Tap 3 Diagnostics Register Lane 3" bitfld.word 0x04 14. " RX_REE_TAP3_DIAG_14 ,Voter override neg" "No override,Override" bitfld.word 0x04 13. " RX_REE_TAP3_DIAG_13 ,Voter override pos" "0,1" textline " " bitfld.word 0x04 12. " RX_REE_TAP3_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_TAP3_DIAG_5_0 ,Current tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8C00+0x128)++0x01 line.word 0x00 "LANE3_RX_REE_ANAENSM_DEL_TMR,REE Analog Enable Control State Machine Delay Timer Value Register Lane 3" group.word (0x8C00+0x130)++0x0D line.word 0x00 "LANE3_RX_REE_PEAK_CTRL,REE Peaking Amp Control Register Lane 3" bitfld.word 0x00 11. " RX_REE_PEAK_CTRL_11 ,Peaking amp feedback path enable" "Disabled,Enabled" bitfld.word 0x00 8.--10. " RX_REE_PEAK_CTRL_10_8 ,Peaking amp feedback scaler value" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 4.--6. " RX_REE_PEAK_CTRL_6_4 ,Peaking amp integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_PEAK_CTRL_3_0 ,Peaking amp sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE3_RX_REE_PEAK_CODE_CTRL,REE Peaking Amp Code Control Register Lane 3" bitfld.word 0x02 8.--13. " RX_REE_PEAK_CODE_CTRL_13_8 ,Peaking amp code maximum value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x02 0.--5. " RX_REE_PEAK_CODE_CTRL_5_0 ,Peaking amp initial code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE3_RX_REE_PEAK_UTHR,REE Peaking Amp Upper Threshold Register Lane 3" hexmask.word 0x04 0.--8. 1. " RX_REE_PEAK_UTHR_8_0 ,Peaking amp algorithm upper threshold" line.word 0x06 "LANE3_RX_REE_PEAK_LTHR,REE Peaking Amp Lower Threshold Register Lane 3" hexmask.word 0x06 0.--8. 1. " RX_REE_PEAK_LTHR_8_0 ,Peaking amp algorithm lower threshold" line.word 0x08 "LANE3_RX_REE_PEAK_IOVRD,REE Peaking Amp Input Override Register Lane 3" bitfld.word 0x08 15. " RX_REE_PEAK_IOVRD_15 ,Peaking amp tap accumulator input override enable" "Disabled,Enabled" hexmask.word.byte 0x08 0.--7. 1. " RX_REE_PEAK_IOVRD_7_0 ,Peaking amp tap accumulator input override" line.word 0x0A "LANE3_RX_REE_PEAK_COVRD,REE Peaking Amp Code Override Register Lane 3" bitfld.word 0x0A 15. " RX_REE_PEAK_COVRD_15 ,Peaking amp code override enable" "Disabled,Enabled" bitfld.word 0x0A 0.--5. " RX_REE_PEAK_COVRD_5_0 ,Peaking amp code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x0C "LANE3_RX_REE_PEAK_DIAG,REE Peaking Amp Diagnostics Register Lane 3" bitfld.word 0x0C 14. " RX_REE_PEAK_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x0C 13. " RX_REE_PEAK_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x0C 12. " RX_REE_PEAK_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x0C 0.--5. " RX_REE_TAP3_DIAG_5_0 ,Current peaking amp integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8C00+0x140)++0x07 line.word 0x00 "LANE3_RX_REE_ATTEN_CTRL,REE Attenuation Control Register Lane 3" bitfld.word 0x00 0.--4. " RX_REE_ATTEN_CTRL_4_0 ,Receiver DFE attenuation maximum value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x02 "LANE3_RX_REE_ATTEN_THR,REE Attenuation Threshold Register Lane 3" bitfld.word 0x02 8.--12. " RX_REE_ATTEN_THR_12_8 ,Attenuation high threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--4. " RX_REE_ATTEN_THR_4_0 ,Attenuation low threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE3_RX_REE_ATTEN_CNT,REE Attenuation Counter Register Lane 3" line.word 0x06 "LANE3_RX_REE_ATTEN_OVRD,REE Attenuation Override Register Lane 3" bitfld.word 0x06 8. " RX_REE_ATTEN_OVRD_8 ,Attenuation override enable" "Disabled,Enabled" bitfld.word 0x06 0.--4. " RX_REE_ATTEN_OVRD_4_0 ,Attenuation override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word (0x8C00+0x148)++0x01 line.word 0x00 "LANE3_RX_REE_ATTEN_DIAG,REE Attenuation Diagnostics Register Lane 3" bitfld.word 0x00 0.--4. " RX_REE_ATTEN_DIAG_4_0 ,Current attenuation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (0x8C00+0x150)++0x05 line.word 0x00 "LANE3_RX_REE_LFEQ_CTRL,REE Low Frequency Equalizer Control Register Lane 3" bitfld.word 0x00 8. " RX_REE_LFEQ_CTRL_8 ,Receiver DFE coefficient disable" "No,Yes" bitfld.word 0x00 4.--6. " RX_REE_LFEQ_CTRL_6_4 ,Integrator accumulator scaler value" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 0.--3. " RX_REE_LFEQ_CTRL_3_0 ,Sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE3_RX_REE_LFEQ_OVRD,REE Low Frequency Equalizer Override Register Lane 3" bitfld.word 0x02 7. " RX_REE_LFEQ_OVRD_7 ,Override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_LFEQ_OVRD_5_0 ,Override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE3_RX_REE_LFEQ_DIAG,REE Low Frequency Equalizer Diagnostics Register Lane 3" bitfld.word 0x04 14. " RX_REE_LFEQ_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_LFEQ_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_LFEQ_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_LFEQ_DIAG_5_0 ,Current integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8C00+0x158)++0x05 line.word 0x00 "LANE3_RX_REE_VGA_GAIN_CTRL,REE VGA Gain Control Register Lane 3" bitfld.word 0x00 8.--12. " RX_REE_VGA_GAIN_CTRL_12_8 ,VGA gain max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 4.--6. " RX_REE_VGA_GAIN_CTRL_6_4 ,VGA gain integrator accumulator scaler value" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 0.--3. " RX_REE_VGA_GAIN_CTRL_3_0 ,VGA gain sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE3_RX_REE_VGA_GAIN_OVRD,REE VGA Gain Override Register Lane 3" bitfld.word 0x02 15. " RX_REE_VGA_GAIN_OVRD_15 ,VGA gain target adjust override enable" "Disabled,Enabled" bitfld.word 0x02 8.--12. " RX_REE_VGA_GAIN_OVRD_12_8 ,VGA gain target adjust override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x02 7. " RX_REE_VGA_GAIN_OVRD_7 ,VGA gain override enable" "Disabled,Enabled" bitfld.word 0x02 0.--4. " RX_REE_VGA_GAIN_OVRD_4_0 ,VGA gain override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE3_RX_REE_VGA_GAIN_DIAG,REE VGA Gain Diagnostics Register Lane 3" bitfld.word 0x04 14. " RX_REE_VGA_GAIN_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_VGA_GAIN_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_VGA_GAIN_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_VGA_GAIN_DIAG_5_0 ,Current VGA gain integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.word (0x8C00+0x15E)++0x01 line.word 0x00 "LANE3_RX_REE_VGA_GAIN_TGT_DIAG,REE VGA Gain Target Adjust Diagnostics Register Lane 3" bitfld.word 0x00 0.--4. " RX_REE_VGA_GAIN_TGT_DIAG_4_0 ,Current VGA gain integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (0x8C00+0x160)++0x05 line.word 0x00 "LANE3_RX_REE_OFF_COR_CTRL,REE Offset Correction Control Register Lane 3" bitfld.word 0x00 4.--6. " RX_REE_OFF_COR_CTRL_6_4 ,Offset correction integrator accumulator scaler value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " RX_REE_OFF_COR_CTRL_3_0 ,Offset correction sigma delta accumulator scaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE3_RX_REE_OFF_COR_OVRD,REE Offset Correction Override Register Lane 3" bitfld.word 0x02 7. " RX_REE_OFF_COR_OVRD_7 ,Offset correction override enable" "Disabled,Enabled" bitfld.word 0x02 0.--5. " RX_REE_OFF_COR_OVRD_5_0 ,Offset correction override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x04 "LANE3_RX_REE_OFF_COR_DIAG,REE Offset Correction Diagnostics Register Lane 3" bitfld.word 0x04 14. " RX_REE_OFF_COR_DIAG_14 ,Voter override neg" "Not activated,Activated" bitfld.word 0x04 13. " RX_REE_OFF_COR_DIAG_13 ,Voter override pos" "Not activated,Activated" textline " " bitfld.word 0x04 12. " RX_REE_OFF_COR_DIAG_12 ,Voter override enable" "Disabled,Enabled" bitfld.word 0x04 0.--5. " RX_REE_OFF_COR_DIAG_5_0 ,Current offset correction integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word (0x8C00+0x170)++0x0D line.word 0x00 "LANE3_RX_REE_ADDR_CFG,REE Adder Configuration Register Lane 3" bitfld.word 0x00 2. " RX_REE_ADDR_CFG_2 ,RX peaking tap 3 adder enable" "Disabled,Enabled" bitfld.word 0x00 1. " RX_REE_ADDR_CFG_1 ,RX peaking tap 2 adder enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RX_REE_ADDR_CFG_0 ,RX peaking tap 1 adder enable" "Disabled,Enabled" line.word 0x02 "LANE3_RX_REE_ADDR_CFG,REE Tap 1 Clip Control Register Lane 3" bitfld.word 0x02 8.--10. " RX_REE_TAP1_CLIP_10_8 ,VGA target gain adjust multiplier" "0,1,2,3,4,5,6,7" bitfld.word 0x02 0.--4. " RX_REE_TAP1_CLIP_4_0 ,Threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "LANE3_RX_REE_TAP2TON_CLIP,REE Taps 2 And 3 Clip Control Register Lane 3" bitfld.word 0x04 8.--10. " RX_REE_TAP2TON_CLIP_10_8 ,VGA target gain adjust multiplier" "0,1,2,3,4,5,6,7" bitfld.word 0x04 0.--4. " RX_REE_TAP2TON_CLIP_4_0 ,Threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "LANE3_RX_REE_CTRL_DATA_MASK,REE Control Data Mask Register Lane 3" rbitfld.word 0x06 14. " RX_REE_CTRL_DATA_MASK_14 ,Ignore 1010 controller" "Not ignored,Ignored" bitfld.word 0x06 9. " RX_REE_CTRL_DATA_MASK_9 ,RX attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x06 8. " RX_REE_CTRL_DATA_MASK_8 ,RX VGA gain" "Not gained,Gained" bitfld.word 0x06 7. " RX_REE_CTRL_DATA_MASK_7 ,RX offset correction coefficient" "Not corrected,Corrected" textline " " bitfld.word 0x06 6. " RX_REE_CTRL_DATA_MASK_6 ,RX peaking amp gain" "Not gained,Gained" bitfld.word 0x06 5. " RX_REE_CTRL_DATA_MASK_5 ,RX low frequency equalizer adaptive control" "0,1" textline " " bitfld.word 0x06 2. " RX_REE_CTRL_DATA_MASK_2 ,RX tap 3" "0,1" bitfld.word 0x06 1. " RX_REE_CTRL_DATA_MASK_1 ,RX tap 2" "0,1" textline " " bitfld.word 0x06 0. " RX_REE_CTRL_DATA_MASK_0 ,RX tap 1" "0,1" line.word 0x08 "LANE3_RX_REE_DIAG_CTRL,REE Diagnostic Control Register Lane 3" bitfld.word 0x08 6. " RX_REE_DIAG_CTRL_6 ,Hold periodic equalization while RX idle" "Not held,Held" bitfld.word 0x08 4. " RX_REE_DIAG_CTRL_4 ,Hold gen 2 equalization while RX idle" "Not held,Held" textline " " bitfld.word 0x08 1. " RX_REE_DIAG_CTRL_1 ,Force REE controller clock on" "Not forced,Forced" bitfld.word 0x08 0. " RX_REE_DIAG_CTRL_0 ,Force REE function clock on" "Not forced,Forced" line.word 0x0A "LANE3_RX_REE_SMGM_CTRL1,REE Control State Machine Gen Mode Control Register 1 Lane 3" bitfld.word 0x0A 15. " RX_REE_SMGM_CTRL1_15 ,REE periodic general control state machine E path enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 14. " RX_REE_SMGM_CTRL1_14 ,REE periodic general control state machine E path enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 13. " RX_REE_SMGM_CTRL1_13 ,REE periodic general control state machine E path enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 12. " RX_REE_SMGM_CTRL1_12 ,REE periodic general control state machine E path enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x0A 11. " RX_REE_SMGM_CTRL1_11 ,REE periodic general control state machine enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 10. " RX_REE_SMGM_CTRL1_10 ,REE periodic general control state machine enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 9. " RX_REE_SMGM_CTRL1_9 ,REE periodic general control state machine enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 8. " RX_REE_SMGM_CTRL1_8 ,REE periodic general control state machine enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x0A 7. " RX_REE_SMGM_CTRL1_7 ,REE Gen 2 general control state machine E path enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 6. " RX_REE_SMGM_CTRL1_6 ,REE Gen 2 general control state machine E path enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 5. " RX_REE_SMGM_CTRL1_5 ,REE Gen 2 general control state machine E path enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 4. " RX_REE_SMGM_CTRL1_4 ,REE Gen 2 general control state machine E path enable standard mode 0" "Disabled,Enabled" textline " " bitfld.word 0x0A 3. " RX_REE_SMGM_CTRL1_3 ,REE Gen 2 general control state machine enable standard mode 3" "Disabled,Enabled" bitfld.word 0x0A 2. " RX_REE_SMGM_CTRL1_2 ,REE Gen 2 general control state machine enable standard mode 2" "Disabled,Enabled" textline " " bitfld.word 0x0A 1. " RX_REE_SMGM_CTRL1_1 ,REE Gen 2 general control state machine enable standard mode 1" "Disabled,Enabled" bitfld.word 0x0A 0. " RX_REE_SMGM_CTRL1_0 ,REE Gen 2 general control state machine enable standard mode 0" "Disabled,Enabled" line.word 0x0C "LANE3_RX_REE_SMGM_CTRL2,REE Control State Machine Gen Mode Control Register 2 Lane 3" bitfld.word 0x0C 0. " RX_REE_SMGM_CTRL2_0 ,REE USB 3 general control state machine E path enable" "Disabled,Enabled" group.word (0x8C00+0x180)++0x13 line.word 0x00 "LANE3_RX_DIAG_ILL_CTRL,RX ILL Diagnostic Control Register Lane 3" bitfld.word 0x00 3. " RX_DIAG_ILL_CTRL_3 ,IQ PI ILL calibration enable override enable" "Disabled,Enabled" bitfld.word 0x00 2. " RX_DIAG_ILL_CTRL_2 ,IQ PI ILL calibration enable override" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " RX_DIAG_ILL_CTRL_1 ,E PI ILL calibration enable override enable" "Disabled,Enabled" bitfld.word 0x00 0. " RX_DIAG_ILL_CTRL_0 ,E PI ILL calibration enable override" "Disabled,Enabled" line.word 0x02 "LANE3_RX_DIAG_ILL_IQ_TRIM0,RX ILL IQ Trim 0 Register Lane 3" bitfld.word 0x02 12.--14. " RX_DIAG_ILL_IQ_TRIM0_14_12 ,Rx_diag_ill_iq_trim0_14_12" "0,1,2,3,4,5,6,7" bitfld.word 0x02 8.--10. " RX_DIAG_ILL_IQ_TRIM0_10_8 ,Rx_diag_ill_iq_trim0_10_8" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x02 6.--7. " RX_DIAG_ILL_IQ_TRIM0_7_6 ,Rx_diag_ill_iq_trim0_7_6" "0,1,2,3" bitfld.word 0x02 4.--5. " RX_DIAG_ILL_IQ_TRIM0_5_4 ,Rx_diag_ill_iq_trim0_5_4" "0,1,2,3" textline " " bitfld.word 0x02 2.--3. " RX_DIAG_ILL_IQ_TRIM0_3_2 ,Rx_diag_ill_iq_trim0_3_2" "0,1,2,3" bitfld.word 0x02 0.--1. " RX_DIAG_ILL_IQ_TRIM0_1_0 ,Rx_diag_ill_iq_trim0_1_0" "0,1,2,3" line.word 0x04 "LANE3_RX_DIAG_ILL_E_TRIM0,RX ILL E Trim 0 Register Lane 3" bitfld.word 0x04 12.--14. " RX_DIAG_ILL_E_TRIM0_14_12 ,Rx_diag_ill_e_trim0_14_12" "0,1,2,3,4,5,6,7" bitfld.word 0x04 8.--10. " RX_DIAG_ILL_E_TRIM0_10_8 ,Rx_diag_ill_e_trim0_10_8" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x04 6.--7. " RX_DIAG_ILL_E_TRIM0_7_6 ,Rx_diag_ill_e_trim0_7_6" "0,1,2,3" bitfld.word 0x04 4.--5. " RX_DIAG_ILL_E_TRIM0_5_4 ,Rx_diag_ill_e_trim0_5_4" "0,1,2,3" textline " " bitfld.word 0x04 2.--3. " RX_DIAG_ILL_E_TRIM0_3_2 ,Rx_diag_ill_e_trim0_3_2" "0,1,2,3" bitfld.word 0x04 0.--1. " RX_DIAG_ILL_E_TRIM0_1_0 ,Rx_diag_ill_e_trim0_1_0" "0,1,2,3" line.word 0x06 "LANE3_RX_DIAG_ILL_IQ_TRIM1,RX ILL IQ Trim 1 Register Lane 3" bitfld.word 0x06 4.--5. " RX_DIAG_ILL_IQ_TRIM1_5_4 ,Rx_diag_ill_iq_trim1_5_4" "0,1,2,3" bitfld.word 0x06 0.--2. " RX_DIAG_ILL_IQ_TRIM1_2_0 ,Rx_diag_ill_iq_trim1_2_0" "0,1,2,3,4,5,6,7" line.word 0x08 "LANE3_RX_DIAG_ILL_E_TRIM1,RX ILL E Trim 1 Register Lane 3" bitfld.word 0x08 4.--5. " RX_DIAG_ILL_E_TRIM1_5_4 ,Rx_diag_ill_e_trim1_5_4" "0,1,2,3" bitfld.word 0x08 0.--2. " RX_DIAG_ILL_E_TRIM1_2_0 ,Rx_diag_ill_e_trim1_2_0" "0,1,2,3,4,5,6,7" line.word 0x0A "LANE3_RX_DIAG_ILL_IQE_TRIM2,RX ILL IQ E Trim 2 Register Lane 3" bitfld.word 0x0A 14.--15. " RX_DIAG_ILL_IQE_TRIM2_15_14 ,Rx_diag_ill_iqe_trim2_15_14" "0,1,2,3" bitfld.word 0x0A 12.--13. " RX_DIAG_ILL_IQE_TRIM2_13_12 ,Rx_diag_ill_iqe_trim2_13_12" "0,1,2,3" textline " " bitfld.word 0x0A 10.--11. " RX_DIAG_ILL_IQE_TRIM2_11_10 ,Rx_diag_ill_iqe_trim2_11_10" "0,1,2,3" bitfld.word 0x0A 8.--9. " RX_DIAG_ILL_IQE_TRIM2_9_8 ,Rx_diag_ill_iqe_trim2_9_8" "0,1,2,3" textline " " bitfld.word 0x0A 6.--7. " RX_DIAG_ILL_IQE_TRIM2_7_6 ,Rx_diag_ill_iqe_trim2_7_6" "0,1,2,3" bitfld.word 0x0A 4.--5. " RX_DIAG_ILL_IQE_TRIM2_5_4 ,Rx_diag_ill_iqe_trim2_5_4" "0,1,2,3" textline " " bitfld.word 0x0A 2.--3. " RX_DIAG_ILL_IQE_TRIM2_3_2 ,Rx_diag_ill_iqe_trim2_3_2" "0,1,2,3" bitfld.word 0x0A 0.--1. " RX_DIAG_ILL_IQE_TRIM2_1_0 ,Rx_diag_ill_iqe_trim2_1_0" "0,1,2,3" line.word 0x0C "LANE3_RX_DIAG_ILL_IQE_TRIM3,RX ILL IQ E Trim 3 Register Lane 3" hexmask.word.byte 0x0C 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM3_15_8 ,Rx_diag_ill_iqe_trim3_15_8" hexmask.word.byte 0x0C 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM3_7_0 ,Rx_diag_ill_iqe_trim3_7_0" line.word 0x0E "LANE3_RX_DIAG_ILL_IQE_TRIM4,RX ILL IQ E Trim 4 Register Lane 3" hexmask.word.byte 0x0E 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM4_15_8 ,Rx_diag_ill_iqe_trim4_15_8" hexmask.word.byte 0x0E 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM4_7_0 ,Rx_diag_ill_iqe_trim4_7_0" line.word 0x10 "LANE3_RX_DIAG_ILL_IQE_TRIM5,RX ILL IQ E Trim 5 Register Lane 3" hexmask.word.byte 0x10 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM5_15_8 ,Rx_diag_ill_iqe_trim5_15_8" hexmask.word.byte 0x10 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM5_7_0 ,Rx_diag_ill_iqe_trim5_7_0" line.word 0x12 "LANE3_RX_DIAG_ILL_IQE_TRIM6,RX ILL IQ E Trim 6 Register Lane 3" hexmask.word.byte 0x12 8.--15. 1. " RX_DIAG_ILL_IQE_TRIM6_15_8 ,Rx_diag_ill_iqe_trim6_15_8" hexmask.word.byte 0x12 0.--7. 1. " RX_DIAG_ILL_IQE_TRIM6_7_0 ,Rx_diag_ill_iqe_trim6_7_0" group.word (0x8C00+0x1A0)++0x11 line.word 0x00 "LANE3_RX_DIAG_DFE_AMP_TUNE,DFE Amp Fine Tuning Register Lane 3" bitfld.word 0x00 12.--14. " RX_DIAG_DFE_AMP_TUNE_14_12 ,DFE constant gm bias tune" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " RX_DIAG_DFE_AMP_TUNE_11 ,DFE VGA constant gm bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--10. " RX_DIAG_DFE_AMP_TUNE_10_8 ,DFE VGA amp current adjust" "0,1,2,3,4,5,6,7" bitfld.word 0x00 7. " RX_DIAG_DFE_AMP_TUNE_7 ,DFE peaking constant gm bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4.--6. " RX_DIAG_DFE_AMP_TUNE_6_4 ,DFE peaking amp current adjust" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " RX_DIAG_DFE_AMP_TUNE_3 ,DFE summing constant gm bias enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--2. " RX_DIAG_DFE_AMP_TUNE_2_0 ,DFE summing amp current adjust" "0,1,2,3,4,5,6,7" line.word 0x02 "LANE3_RX_DIAG_DFE_AMP_TUNE_2,DFE Amp Fine Tuning 2 Register Lane 3" bitfld.word 0x02 11. " RX_DIAG_DFE_AMP_TUNE_2_11 ,DFE low frequency equalizer constant gm bias enable" "Disabled,Enabled" bitfld.word 0x02 8.--10. " RX_DIAG_DFE_AMP_TUNE_2_10_8 ,DFE low frequency equalizer current adjust" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x02 7. " RX_DIAG_DFE_AMP_TUNE_2_7 ,Enable active inductors boost function in the peaking amp for high data rates" "Disabled,Enabled" bitfld.word 0x02 6. " RX_DIAG_DFE_AMP_TUNE_2_6 ,Enable active inductors boost function in stage 1 of the VGA for high data rates" "Disabled,Enabled" textline " " bitfld.word 0x02 5. " RX_DIAG_DFE_AMP_TUNE_2_5 ,Enable active inductors boost function in stage 2 of the VGA for high data rates" "Disabled,Enabled" bitfld.word 0x02 4. " RX_DIAG_DFE_AMP_TUNE_2_4 ,DFE RX tap 1 DAC range select" "0,1" textline " " bitfld.word 0x02 0.--1. " RX_DIAG_DFE_AMP_TUNE_2_1_0 ,DFE RX amp current adjust" "0,1,2,3" line.word 0x04 "LANE3_RX_DIAG_REE_DAC_CTRL,REE DAC Control Register Lane 3" bitfld.word 0x04 2. " RX_DIAG_REE_DAC_CTRL_2 ,DFE offset DAC enable" "Disabled,Enabled" bitfld.word 0x04 1. " RX_DIAG_REE_DAC_CTRL_1 ,DFE Offset DAC attenuation" "No attenuation,Attenuation" textline " " bitfld.word 0x04 0. " RX_DIAG_REE_DAC_CTRL_0 ,DFE DAC attenuation" "No attenuation,Attenuation" line.word 0x06 "LANE3_RX_DIAG_DFE_CTRL1,Receiver DFE Control Register 1 Lane 3" bitfld.word 0x06 15. " RX_DIAG_DFE_CTRL1_15 ,DFE tap 1 deserializer MUX select" "0,1" bitfld.word 0x06 7. " RX_DIAG_DFE_CTRL1_7 ,Receiver DFE low frequency equalization enable value standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " RX_DIAG_DFE_CTRL1_6 ,Receiver DFE low frequency equalization enable value standard mode 2" "Disabled,Enabled" bitfld.word 0x06 5. " RX_DIAG_DFE_CTRL1_5 ,Receiver DFE low frequency equalization enable value standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " RX_DIAG_DFE_CTRL1_4 ,Receiver DFE low frequency equalization enable value standard mode 0" "Disabled,Enabled" bitfld.word 0x06 3. " RX_DIAG_DFE_CTRL1_3 ,Receiver DFE equalization enable mask value standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x06 2. " RX_DIAG_DFE_CTRL1_2 ,Receiver DFE equalization enable mask value standard mode 2" "Disabled,Enabled" bitfld.word 0x06 1. " RX_DIAG_DFE_CTRL1_1 ,Receiver DFE equalization enable mask value standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " RX_DIAG_DFE_CTRL1_0 ,Receiver DFE equalization enable mask value standard mode 0" "Disabled,Enabled" line.word 0x08 "LANE3_RX_DIAG_DFE_CTRL2,Receiver DFE Control Register 2 Lane 3" bitfld.word 0x08 6.--7. " RX_DIAG_DFE_CTRL2_7_6 ,RX equalizer range select standard mode 3" "0,1,2,3" bitfld.word 0x08 4.--5. " RX_DIAG_DFE_CTRL2_5_4 ,RX equalizer range select standard mode 2" "0,1,2,3" textline " " bitfld.word 0x08 2.--3. " RX_DIAG_DFE_CTRL2_3_2 ,RX equalizer range select standard mode 1" "0,1,2,3" bitfld.word 0x08 0.--1. " RX_DIAG_DFE_CTRL2_1_0 ,RX equalizer range select standard mode 0" "0,1,2,3" line.word 0x0A "LANE3_RX_DIAG_DFE_CTRL3,Receiver DFE Control Register 3 Lane 3" bitfld.word 0x0A 12.--15. " RX_DIAG_DFE_CTRL3_15_12 ,RX DFE peaking resistor code select standard mode 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0A 8.--11. " RX_DIAG_DFE_CTRL3_11_8 ,RX DFE peaking resistor code select standard mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x0A 4.--7. " RX_DIAG_DFE_CTRL3_7_4 ,RX DFE peaking resistor code select standard mode 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0A 0.--3. " RX_DIAG_DFE_CTRL3_3_0 ,RX DFE peaking resistor code select standard mode 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0C "LANE3_RX_DIAG_NQST_CTRL,Nyquist Control Register Lane 3" bitfld.word 0x0C 12.--15. " RX_DIAG_NQST_CTRL_15_12 ,RX nyquist select value standard mode 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0C 8.--11. " RX_DIAG_NQST_CTRL_11_8 ,RX nyquist select value standard mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x0C 4.--7. " RX_DIAG_NQST_CTRL_7_4 ,RX nyquist select value standard mode 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0C 0.--3. " RX_DIAG_NQST_CTRL_3_0 ,RX nyquist select value standard mode 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0E "LANE3_RX_DIAG_LFEQ_TUNE,Low Frequency Equalizer Tuning Register Lane 3" bitfld.word 0x0E 6.--7. " RX_DIAG_LFEQ_TUNE_7_6 ,RX low frequency equalization zero frequency value standard mode 3" "0,1,2,3" bitfld.word 0x0E 4.--5. " RX_DIAG_LFEQ_TUNE_5_4 ,RX low frequency equalization zero frequency value standard mode 2" "0,1,2,3" textline " " bitfld.word 0x0E 2.--3. " RX_DIAG_LFEQ_TUNE_3_2 ,RX low frequency equalization zero frequency value standard mode 1" "0,1,2,3" bitfld.word 0x0E 0.--1. " RX_DIAG_LFEQ_TUNE_1_0 ,RX low frequency equalization zero frequency value standard mode 0" "0,1,2,3" line.word 0x10 "LANE3_RX_DIAG_RXCTRL,RX Control Register Lane 3" bitfld.word 0x10 15. " RX_DIAG_RXCTRL_15 ,RX deserializer clock invert" "Not inverted,Inverted" bitfld.word 0x10 11. " RX_DIAG_RXCTRL_11 ,PI output clock divider enable standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x10 10. " RX_DIAG_RXCTRL_10 ,PI output clock divider enable standard mode 2" "Disabled,Enabled" bitfld.word 0x10 9. " RX_DIAG_RXCTRL_9 ,PI output clock divider enable standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x10 8. " RX_DIAG_RXCTRL_8 ,PI output clock divider enable standard mode 0" "Disabled,Enabled" bitfld.word 0x10 7. " RX_DIAG_RXCTRL_7 ,Receiver CML to CMOS rate select value standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x10 6. " RX_DIAG_RXCTRL_6 ,Receiver CML to CMOS rate select value standard mode 2" "Disabled,Enabled" bitfld.word 0x10 5. " RX_DIAG_RXCTRL_5 ,Receiver CML to CMOS rate select value standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x10 4. " RX_DIAG_RXCTRL_4 ,Receiver CML to CMOS rate select value standard mode 0" "Disabled,Enabled" bitfld.word 0x10 3. " RX_DIAG_RXCTRL_3 ,RX interface sub-rate standard mode 3" "Disabled,Enabled" textline " " bitfld.word 0x10 2. " RX_DIAG_RXCTRL_2 ,RX interface sub-rate standard mode 2" "Disabled,Enabled" bitfld.word 0x10 1. " RX_DIAG_RXCTRL_1 ,RX interface sub-rate standard mode 1" "Disabled,Enabled" textline " " bitfld.word 0x10 0. " RX_DIAG_RXCTRL_0 ,RX interface sub-rate standard mode 0" "Disabled,Enabled" rgroup.word (0x8C00+0x1B2)++0x01 line.word 0x00 "LANE3_RX_DIAG_RST_DIAG,Receiver Control Reset Diagnostic Register Lane 3" bitfld.word 0x00 8. " RX_DIAG_RST_DIAG_8 ,Current state of the rxda_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 7. " RX_DIAG_RST_DIAG_7 ,Current state of the rx_dig_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 6. " RX_DIAG_RST_DIAG_6 ,Current state of the rxda_cdrlf_reset_n reset" "No reset,Reset" bitfld.word 0x00 5. " RX_DIAG_RST_DIAG_5 ,Current state of the rx_ree_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 4. " RX_DIAG_RST_DIAG_4 ,Current state of the rx_lfps_det_filter_reset_n reset" "No reset,Reset" bitfld.word 0x00 3. " RX_DIAG_RST_DIAG_3 ,Current state of the rx_epi_ill_cal_lock_det_clk_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 2. " RX_DIAG_RST_DIAG_2 ,Current state of the rx_epi_ill_cal_ref_clk_reset_n reset" "No reset,Reset" bitfld.word 0x00 1. " RX_DIAG_RST_DIAG_1 ,Current state of the rx_iqpi_ill_cal_lock_det_clk_reset_n reset" "No reset,Reset" textline " " bitfld.word 0x00 0. " RX_DIAG_RST_DIAG_0 ,Current state of the rx_iqpi_ill_cal_ref_clk_reset_n reset" "No reset,Reset" group.word (0x8C00+0x1B8)++0x05 line.word 0x00 "LANE3_RX_DIAG_SIGDET_TUNE,RX Signal Detect Tuning And Control Register Lane 3" bitfld.word 0x00 12.--13. " RX_DIAG_SIGDET_TUNE_13_12 ,Signal detect filter function select" "0,1,2,3" bitfld.word 0x00 4.--5. " RX_DIAG_SIGDET_TUNE_5_4 ,Signal definition to be provided by the analog team" "0,1,2,3" textline " " bitfld.word 0x00 0.--3. " RX_DIAG_SIGDET_TUNE_3_0 ,Signal detect level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE3_RX_DIAG_LFPSDET_TUNE,RX LFPS Detect Tuning And Control Register Lane 3" hexmask.word.byte 0x02 8.--15. 1. " RX_DIAG_LFPSDET_TUNE_15_8 ,Signal definition to be provided by the analog team" hexmask.word.byte 0x02 0.--7. 1. " RX_DIAG_LFPSDET_TUNE_7_0 ,LFPS detect level" line.word 0x04 "LANE3_RX_DIAG_SD_TEST,Signal Detect Test Register Lane 3" bitfld.word 0x04 3. " RX_DIAG_SD_TEST_3 ,LFPS detected low test bit" "Not detected,Detected" bitfld.word 0x04 2. " RX_DIAG_SD_TEST_2 ,LFPS detected high test bit" "Not detected,Detected" textline " " bitfld.word 0x04 1. " RX_DIAG_SD_TEST_1 ,Signal detected low test bit" "Not detected,Detected" bitfld.word 0x04 0. " RX_DIAG_SD_TEST_0 ,Signal detected high test bit" "Not detected,Detected" group.word (0x8C00+0x1C0)++0x03 line.word 0x00 "LANE3_RX_DIAG_SAMP_CTRL,RX Sampler Diagnostic Control Register Lane 3" bitfld.word 0x00 0. " RX_DIAG_SAMP_CTRL_0 ,Analog sampler" "0,1" line.word 0x02 "LANE3_RX_DIAG_SC2C_DELAY,RX Sampler CML TO CMOS Enable Delay Register Lane 3" hexmask.word 0x02 0.--9. 1. " RX_DIAG_SC2C_DELAY_9_0 ,Sampler CML to CMOS enable delay" group.word (0x8C00+0x1C8)++0x03 line.word 0x00 "LANE3_RX_DIAG_MPHY_CTRL_1,MPHY Control Register 1 Lane 3" bitfld.word 0x00 14. " RX_DIAG_MPHY_CTRL_1_14 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x00 13. " RX_DIAG_MPHY_CTRL_1_13 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x00 12. " RX_DIAG_MPHY_CTRL_1_12 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x00 8.--9. " RX_DIAG_MPHY_CTRL_1_9_8 ,Signal definition to be provided by the analog team" "0,1,2,3" textline " " bitfld.word 0x00 0.--5. " RX_DIAG_MPHY_CTRL_1_5_0 ,Signal definition to be provided by the analog team" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x02 "LANE3_RX_DIAG_MPHY_CTRL_2,MPHY Control Register 2 Lane 3" rbitfld.word 0x02 10. " RX_DIAG_MPHY_CTRL_2_10 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 9. " RX_DIAG_MPHY_CTRL_2_9 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x02 8. " RX_DIAG_MPHY_CTRL_2_8 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 7. " RX_DIAG_MPHY_CTRL_2_7 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x02 6. " RX_DIAG_MPHY_CTRL_2_6 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 5. " RX_DIAG_MPHY_CTRL_2_5 ,Signal definition to be provided by the analog team" "0,1" textline " " bitfld.word 0x02 4. " RX_DIAG_MPHY_CTRL_2_4 ,Signal definition to be provided by the analog team" "0,1" bitfld.word 0x02 0.--1. " RX_DIAG_MPHY_CTRL_2_1_0 ,Signal definition to be provided by the analog team" "0,1,2,3" group.word (0x8C00+0x1D0)++0x03 line.word 0x00 "LANE3_RX_DIAG_LPBK_CTRL,RX Loopback Controller Register Lane 3" bitfld.word 0x00 4. " RX_DIAG_LPBK_CTRL_4 ,Recovered clock loopback select" "0,1" bitfld.word 0x00 0.--3. " RX_DIAG_LPBK_CTRL_3_0 ,Attenuation settings" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "LANE3_RX_DIAG_ECTRL_OVRD,RX Extra Enable Control Override Register Lane3" bitfld.word 0x02 1. " RX_DIAG_ECTRL_OVRD_1 ,Sampler CML to CMOS enable override enable" "Disabled,Enabled" bitfld.word 0x02 0. " RX_DIAG_ECTRL_OVRD_0 ,Sampler CML to CMOS enable override" "Disabled,Enabled" group.word (0x8C00+0x1E0)++0x0F line.word 0x00 "LANE3_RX_DIAG_CML2CMOS_BTRIM,CML To CMOS Bias Trim Register Lane 3" bitfld.word 0x00 12.--14. " RX_DIAG_CML2CMOS_BTRIM_14_12 ,CML to CMOS IQ bias sink current trim" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--10. " RX_DIAG_CML2CMOS_BTRIM_10_8 ,CML to CMOS IQ bias source current trim" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 4.--6. " RX_DIAG_CML2CMOS_BTRIM_6_4 ,CML to CMOS E bias sink current trim" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--2. " RX_DIAG_CML2CMOS_BTRIM_2_0 ,CML to CMOS E bias source current trim" "0,1,2,3,4,5,6,7" line.word 0x02 "LANE3_RX_DIAG_BIAS_GEN_CTRL1,RX Bias Gen Control Register 1 Lane 3" bitfld.word 0x02 14.--15. " RX_DIAG_BIAS_GEN_CTRL1_15_14 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 12.--13. " RX_DIAG_BIAS_GEN_CTRL1_13_12 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 10.--11. " RX_DIAG_BIAS_GEN_CTRL1_11_10 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 8.--9. " RX_DIAG_BIAS_GEN_CTRL1_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 6.--7. " RX_DIAG_BIAS_GEN_CTRL1_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 4.--5. " RX_DIAG_BIAS_GEN_CTRL1_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x02 2.--3. " RX_DIAG_BIAS_GEN_CTRL1_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x02 0.--1. " RX_DIAG_BIAS_GEN_CTRL1_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x04 "LANE3_RX_DIAG_BIAS_GEN_CTRL2,RX Bias Gen Control Register 2 Lane 3" bitfld.word 0x04 14.--15. " RX_DIAG_BIAS_GEN_CTRL2_15_14 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 12.--13. " RX_DIAG_BIAS_GEN_CTRL2_13_12 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 10.--11. " RX_DIAG_BIAS_GEN_CTRL2_11_10 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 8.--9. " RX_DIAG_BIAS_GEN_CTRL2_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 6.--7. " RX_DIAG_BIAS_GEN_CTRL2_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 4.--5. " RX_DIAG_BIAS_GEN_CTRL2_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x04 2.--3. " RX_DIAG_BIAS_GEN_CTRL2_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x04 0.--1. " RX_DIAG_BIAS_GEN_CTRL2_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x06 "LANE3_RX_DIAG_BIAS_GEN_CTRL3,RX Bias Gen Control Register 3 Lane 3" bitfld.word 0x06 14.--15. " RX_DIAG_BIAS_GEN_CTRL3_15_14 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 12.--13. " RX_DIAG_BIAS_GEN_CTRL3_13_12 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 10.--11. " RX_DIAG_BIAS_GEN_CTRL3_11_10 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 8.--9. " RX_DIAG_BIAS_GEN_CTRL3_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 6.--7. " RX_DIAG_BIAS_GEN_CTRL3_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 4.--5. " RX_DIAG_BIAS_GEN_CTRL3_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x06 2.--3. " RX_DIAG_BIAS_GEN_CTRL3_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x06 0.--1. " RX_DIAG_BIAS_GEN_CTRL3_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x08 "LANE3_RX_DIAG_BIAS_GEN_CTRL4,RX Bias Gen Control Register 4 Lane 3" bitfld.word 0x08 15. " RX_DIAG_BIAS_GEN_CTRL4_15 ,Enable base unit on all the current outputs from the RX bias generation block" "Disabled,Enabled" bitfld.word 0x08 8.--9. " RX_DIAG_BIAS_GEN_CTRL4_9_8 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x08 6.--7. " RX_DIAG_BIAS_GEN_CTRL4_7_6 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x08 4.--5. " RX_DIAG_BIAS_GEN_CTRL4_5_4 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" textline " " bitfld.word 0x08 2.--3. " RX_DIAG_BIAS_GEN_CTRL4_3_2 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" bitfld.word 0x08 0.--1. " RX_DIAG_BIAS_GEN_CTRL4_1_0 ,Current programmability on the biasgen current supplying block xxx" "0,1,2,3" line.word 0x0A "LANE3_RX_DIAG_BS_TM,RX Boundary Scan Test Mode Register" line.word 0x0C "LANE3_RX_DIAG_RXFE_TM1,RX Receiver Front End Test Mode Register 1 Lane 3" line.word 0x0E "LANE3_RX_DIAG_RXFE_TM2,RX Receiver Front End Test Mode Register 2 Lane 3" textline " " group.word 0xC010++0x03 line.word 0x00 "PHY_HDP_MODE_CTL,HDP Mode Control Register" bitfld.word 0x00 15. " PHY_HDP_MODE_CTL_15 ,PHY HDP lane disable" "No,Yes" bitfld.word 0x00 14. " PHY_HDP_MODE_CTL_14 ,PHY HDP lane disable" "No,Yes" textline " " bitfld.word 0x00 13. " PHY_HDP_MODE_CTL_13 ,PHY HDP lane disable" "No,Yes" bitfld.word 0x00 12. " PHY_HDP_MODE_CTL_12 ,PHY HDP lane disable" "No,Yes" textline " " bitfld.word 0x00 4.--7. " PHY_HDP_MODE_CTL_7_4 ,HDP power state acknowledgment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PHY_HDP_MODE_CTL_3_0 ,HDP power state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "PHY_HDP_CLK_CTL,HDP Clock Control Register" bitfld.word 0x02 12.--15. " PHY_HDP_CLK_CTL_15_12 ,DP PLL data rate 1 clock divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x02 8.--11. " PHY_HDP_CLK_CTL_11_8 ,DP PLL data rate 0 clock divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x02 3. " PHY_HDP_CLK_CTL_3 ,HDP PLL clock enable acknowledge" "Disabled,Enabled" bitfld.word 0x02 2. " PHY_HDP_CLK_CTL_2 ,HDP PLL clock enable" "Disabled,Enabled" textline " " bitfld.word 0x02 1. " PHY_HDP_CLK_CTL_1 ,HDP PLL ready" "Not ready,Ready" bitfld.word 0x02 0. " PHY_HDP_CLK_CTL_0 ,HDP PLL enable" "Disabled,Enabled" rgroup.word 0xC01E++0x01 line.word 0x00 "PHY_STS,PHY Status Register" bitfld.word 0x00 15. " PHY_STS_15 ,PHY APB access timeout" "No timed out,Timed out" group.word 0xC020++0x01 line.word 0x00 "PHY_ISO_CMN_CTRL,PHY Common Control Signal Isolation Register" bitfld.word 0x00 0. " PHY_ISO_CMN_CTRL_0 ,Drives phy_reset_n PHY input when in PHY and PMA isolation modes" "Not drove,Drove" group.word (0xC400+0x10)++0x01 line.word 0x00 "LANE0_PHY_HDP_TX_CTL,HDP Lane Configuration Register 0" bitfld.word 0x00 4.--5. " PHY_HDP_TX_CTL_5_4 ,Tx voltage level" "Level 0,Level 1,Level 2,Level 3" bitfld.word 0x00 0.--1. " PHY_HDP_TX_CTL_1_0 ,Tx De-emphasis setting" "Level 0,Level 1,Level 2,Level 3" group.word (0xC400+0x38)++0x03 line.word 0x00 "LANE0_PHY_DP_ISO_TX_DATA_LO,DP Tx Data Low Isolation Register 0" line.word 0x02 "LANE0_PHY_DP_ISO_TX_DATA_HI,DP Tx Data High Isolation Register 0" bitfld.word 0x02 0.--3. " PHY_DP_ISO_TX_DATA_HI_3_0 ,Drives phy_pma_tx_data_ln_XX[19:16] PHY input for the associated lane when in PHY isolation modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word (0xC440+0x10)++0x01 line.word 0x00 "LANE1_PHY_HDP_TX_CTL,HDP Lane Configuration Register 1" bitfld.word 0x00 4.--5. " PHY_HDP_TX_CTL_5_4 ,Tx voltage level" "Level 0,Level 1,Level 2,Level 3" bitfld.word 0x00 0.--1. " PHY_HDP_TX_CTL_1_0 ,Tx De-emphasis setting" "Level 0,Level 1,Level 2,Level 3" group.word (0xC440+0x38)++0x03 line.word 0x00 "LANE1_PHY_DP_ISO_TX_DATA_LO,DP Tx Data Low Isolation Register 1" line.word 0x02 "LANE1_PHY_DP_ISO_TX_DATA_HI,DP Tx Data High Isolation Register 1" bitfld.word 0x02 0.--3. " PHY_DP_ISO_TX_DATA_HI_3_0 ,Drives phy_pma_tx_data_ln_XX[19:16] PHY input for the associated lane when in PHY isolation modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word (0xC480+0x10)++0x01 line.word 0x00 "LANE2_PHY_HDP_TX_CTL,HDP Lane Configuration Register 2" bitfld.word 0x00 4.--5. " PHY_HDP_TX_CTL_5_4 ,Tx voltage level" "Level 0,Level 1,Level 2,Level 3" bitfld.word 0x00 0.--1. " PHY_HDP_TX_CTL_1_0 ,Tx De-emphasis setting" "Level 0,Level 1,Level 2,Level 3" group.word (0xC480+0x38)++0x03 line.word 0x00 "LANE2_PHY_DP_ISO_TX_DATA_LO,DP Tx Data Low Isolation Register 2" line.word 0x02 "LANE2_PHY_DP_ISO_TX_DATA_HI,DP Tx Data High Isolation Register 2" bitfld.word 0x02 0.--3. " PHY_DP_ISO_TX_DATA_HI_3_0 ,Drives phy_pma_tx_data_ln_XX[19:16] PHY input for the associated lane when in PHY isolation modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word (0xC4C0+0x10)++0x01 line.word 0x00 "LANE3_PHY_HDP_TX_CTL,HDP Lane Configuration Register 3" bitfld.word 0x00 4.--5. " PHY_HDP_TX_CTL_5_4 ,Tx voltage level" "Level 0,Level 1,Level 2,Level 3" bitfld.word 0x00 0.--1. " PHY_HDP_TX_CTL_1_0 ,Tx De-emphasis setting" "Level 0,Level 1,Level 2,Level 3" group.word (0xC4C0+0x38)++0x03 line.word 0x00 "LANE3_PHY_DP_ISO_TX_DATA_LO,DP Tx Data Low Isolation Register 3" line.word 0x02 "LANE3_PHY_DP_ISO_TX_DATA_HI,DP Tx Data High Isolation Register 3" bitfld.word 0x02 0.--3. " PHY_DP_ISO_TX_DATA_HI_3_0 ,Drives phy_pma_tx_data_ln_XX[19:16] PHY input for the associated lane when in PHY isolation modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC800++0x01 line.word 0x00 "PHY_PMA_CMN_CTRL1,PMA Common Control1 Register" bitfld.word 0x00 14.--15. " PHY_PMA_CMN_CTRL1_15_14 ,Drives cmn_ref_clk_ana_div PMA input" "0,1,2,3" bitfld.word 0x00 12.--13. " PHY_PMA_CMN_CTRL1_13_12 ,Drives cmn_ref_clk_dig_div PMA input" "0,1,2,3" textline " " bitfld.word 0x00 10.--11. " PHY_PMA_CMN_CTRL1_11_10 ,Drives cmn_psm_clk_dig_div PMA input" "0,1,2,3" bitfld.word 0x00 4.--6. " PHY_PMA_CMN_CTRL1_6_4 ,Drives cmn_ref_clk_sel PMA input" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x00 3. " PHY_PMA_CMN_CTRL1_3 ,Drives cmn_ref_clk_rcv_en PMA input" "Not drove,Drove" rbitfld.word 0x00 2. " PHY_PMA_CMN_CTRL1_2 ,Current value of cmn_macro_suspend_ack PMA output" "0,1" textline " " rbitfld.word 0x00 1. " PHY_PMA_CMN_CTRL1_1 ,Current value of cmn_refclk_active PMA output" "0,1" rbitfld.word 0x00 0. " PHY_PMA_CMN_CTRL1_0 ,Current value of cmn_ready PMA output" "0,1" rgroup.word 0xC802++0x05 line.word 0x00 "PHY_PMA_CMN_CTRL2,PMA Common Control2 Register" bitfld.word 0x00 6. " PHY_PMA_CMN_CTRL2_6 ,Current value of cmn_pll0_locked PMA output" "0,1" bitfld.word 0x00 4. " PHY_PMA_CMN_CTRL2_4 ,Current value of cmn_pll0_clk_datart_en_ack PMA output" "0,1" textline " " bitfld.word 0x00 2. " PHY_PMA_CMN_CTRL2_2 ,Current value of cmn_pll0_disabled PMA output" "0,1" bitfld.word 0x00 0. " PHY_PMA_CMN_CTRL2_0 ,Current value of cmn_pll0_ready PMA output" "0,1" line.word 0x02 "PHY_PMA_SSM_STATE,PMA SSM Current State Register" hexmask.word 0x02 0.--8. 1. " PHY_PMA_SSM_STATE_8_0 ,Current state of the PMA startup state machine" line.word 0x04 "PHY_PMA_ISO_PLL_SM_STATE,PMA PLL State Machine Current State Register" hexmask.word 0x04 0.--11. 1. " PHY_PMA_ISO_PLL_SM_STATE_11_0 ,Current value of cmn_pllsm0_state[11:0]" group.word 0xC820++0x05 line.word 0x00 "PHY_PMA_ISO_CMN_CTRL,PMA Common Control Signal Isolation Register" rbitfld.word 0x00 7. " PHY_PMA_ISO_CMN_CTRL_7 ,Current value of cmn_clock_stop_ack PMA output" "0,1" bitfld.word 0x00 6. " PHY_PMA_ISO_CMN_CTRL_6 ,Drives cmn_clock_stop_req PMA input when in PMA isolation mode" "Not drove,Drove" textline " " rbitfld.word 0x00 5. " PHY_PMA_ISO_CMN_CTRL_5 ,Current value of cmn_macro_pwr_en_ack PMA output" "0,1" bitfld.word 0x00 4. " PHY_PMA_ISO_CMN_CTRL_4 ,Drives cmn_macro_pwr_en PMA input when in PHY macro and PMA isolation modes" "Not drove,Drove" textline " " bitfld.word 0x00 3. " PHY_PMA_ISO_CMN_CTRL_3 ,Drives cmn_refclk_disable PMA input when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x00 2. " PHY_PMA_ISO_CMN_CTRL_2 ,Drives macro_suspend_req PMA input when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x00 1. " PHY_PMA_ISO_CMN_CTRL_1 ,Drives cmn_macro_en PMA input when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x00 0. " PHY_PMA_ISO_CMN_CTRL_0 ,Drives cmn_reset_n PMA input when in PMA isolation mode" "Not drove,Drove" line.word 0x02 "PHY_PMA_ISO_PLL_CTRL0,PMA PLL Control0 Isolation Register" bitfld.word 0x02 2. " PHY_PMA_ISO_PLL_CTRL0_2 ,Drives cmn_pll0_clk_datart_en PMA input when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x02 0. " PHY_PMA_ISO_PLL_CTRL0_0 ,Drives cmn_pll0_en PMA input when in PMA isolation mode" "Not drove,Drove" line.word 0x04 "PHY_PMA_ISO_PLL_CTRL1,PMA PLL Control1 Isolation Register" bitfld.word 0x04 4.--7. " PHY_PMA_ISO_PLL_CTRL1_7_4 ,Drives cmn_pll0_clk_datart1_div PMA input when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x04 0.--3. " PHY_PMA_ISO_PLL_CTRL1_3_0 ,Drives cmn_pll0_clk_datart0_div PMA input when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.w(ad:0x00080000+0xC83E)&0x8000)==0x8000)) group.word 0xC83E++0x01 line.word 0x00 "PHY_PMA_ISOLATION_CTRL,Isolation Control Register" bitfld.word 0x00 15. " PMA_ISOLATION_CTRL_15 ,PMA isolation enable" "Disabled,Enabled" bitfld.word 0x00 14. " PMA_ISOLATION_CTRL_14 ,PMA common isolation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " PHY_PMA_ISOLATION_CTRL_12 ,PHY/PMA isolation mode select" "PHY,PMA" bitfld.word 0x00 7. " PMA_ISOLATION_CTRL_7 ,PMA lane 7 isolation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " PMA_ISOLATION_CTRL_6 ,PMA lane 6 isolation enable" "Disabled,Enabled" bitfld.word 0x00 5. " PMA_ISOLATION_CTRL_5 ,PMA lane 5 isolation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " PMA_ISOLATION_CTRL_4 ,PMA lane 4 isolation enable" "Disabled,Enabled" bitfld.word 0x00 3. " PMA_ISOLATION_CTRL_3 ,PMA lane 3 isolation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " PMA_ISOLATION_CTRL_2 ,PMA lane 2 isolation enable" "Disabled,Enabled" bitfld.word 0x00 1. " PMA_ISOLATION_CTRL_1 ,PMA lane 1 isolation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " PMA_ISOLATION_CTRL_0 ,PMA lane 0 isolation enable" "Disabled,Enabled" else group.word 0xC83E++0x01 line.word 0x00 "PHY_PMA_ISOLATION_CTRL,Isolation Control Register" bitfld.word 0x00 15. " PHY_ISOLATION_CTRL_15 ,PHY isolation enable" "Disabled,Enabled" bitfld.word 0x00 14. " PHY_ISOLATION_CTRL_14 ,PHY common isolation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PHY_ISOLATION_CTRL_7 ,PHY lane 7 isolation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " PHY_ISOLATION_CTRL_6 ,PHY lane 6 isolation enable" "Disabled,Enabled" bitfld.word 0x00 5. " PHY_ISOLATION_CTRL_5 ,PHY lane 5 isolation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " PHY_ISOLATION_CTRL_4 ,PHY lane 4 isolation enable" "Disabled,Enabled" bitfld.word 0x00 3. " PHY_ISOLATION_CTRL_3 ,PHY lane 3 isolation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " PHY_ISOLATION_CTRL_2 ,PHY lane 2 isolation enable" "Disabled,Enabled" bitfld.word 0x00 1. " PHY_ISOLATION_CTRL_1 ,PHY lane 1 isolation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " PHY_ISOLATION_CTRL_0 ,PHY lane 0 isolation enable" "Disabled,Enabled" endif group.word 0xCC00++0x03 line.word 0x00 "LANE0_PHY_PMA_XCVR_CTRL,PMA Transceiver Control Register 0" rbitfld.word 0x00 10. " PHY_PMA_XCVR_CTRL_10 ,Current value of xcvr_lane_en_ack PMA output for the associated lane" "0,1" bitfld.word 0x00 8. " PHY_PMA_XCVR_CTRL_8 ,Drives the tx_differential_invert PMA input for the associated lane" "Not drove,Drove" textline " " rbitfld.word 0x00 3. " PHY_PMA_XCVR_CTRL_3 ,Current value of rx_bist_status_ln_{nnn} PMA output for the associated lane" "0,1" rbitfld.word 0x00 2. " PHY_PMA_XCVR_CTRL_2 ,Current value of rx_bist_err_toggle_ln_{nnn} PMA output for the associated lane" "0,1" textline " " rbitfld.word 0x00 1. " PHY_PMA_XCVR_CTRL_1 ,Current value of rx_bist_sync_ln_{nnn} PMA output for the associated lane" "0,1" line.word 0x02 "LANE0_PHY_PMA_XCVR_LPBK,PMA Loopback Control Register 0" bitfld.word 0x02 8. " PHY_PMA_XCVR_LPBK_8 ,Drives the tx_bist_hold PMA input for all lanes in the associated link" "Not drove,Drove" bitfld.word 0x02 5. " PHY_PMA_XCVR_LPBK_5 ,Drives the txrx_fe_parallel_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" textline " " bitfld.word 0x02 4. " PHY_PMA_XCVR_LPBK_4 ,Drives the txrx_ne_parallel_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" bitfld.word 0x02 3. " PHY_PMA_XCVR_LPBK_3 ,Drives the txrx_recovered_clk_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" textline " " bitfld.word 0x02 2. " PHY_PMA_XCVR_LPBK_2 ,Drives the txrx_line_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" bitfld.word 0x02 1. " PHY_PMA_XCVR_LPBK_1 ,Drives the txrx_isi_gen_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" textline " " bitfld.word 0x02 0. " PHY_PMA_XCVR_LPBK_0 ,Drives the txrx_serial_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" rgroup.word (0xCC00+0x08)++0x03 line.word 0x00 "LANE0_PHY_PMA_PSM_STATE_LO,PMA PSM Current State Lower Register 0" line.word 0x02 "LANE0_PHY_PMA_PSM_STATE_HI,PMA PSM Current State Higher Register 0" hexmask.word.byte 0x02 0.--7. 1. " PHY_PMA_PSM_STATE_HI_7_0 ,Current state of the PMA power state machine" group.word (0xCC00+0x20)++0x0B line.word 0x00 "LANE0_PHY_PMA_ISO_XCVR_CTRL,PMA Isolation Transceiver Control Register 0" rbitfld.word 0x00 15. " PHY_PMA_ISO_XCVR_CTRL_15 ,Current value of xcvr_pll_clk_en_ack PMA output for the associated lane" "0,1" bitfld.word 0x00 14. " PHY_PMA_ISO_XCVR_CTRL_14 ,Drives xcvr_pll_clk_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x00 13. " PHY_PMA_ISO_XCVR_CTRL_13 ,Drives tx_lfps_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x00 12. " PHY_PMA_ISO_XCVR_CTRL_12 ,Drives tx_elec_idle PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " rbitfld.word 0x00 11. " PHY_PMA_ISO_XCVR_CTRL_11 ,Current value of xcvr_psm_ready PMA output for the associated lane" "0,1" rbitfld.word 0x00 10. " PHY_PMA_ISO_XCVR_CTRL_10 ,Current value of tx_rcv_detected PMA output for the associated lane when in PMA isolation mode" "0,1" textline " " rbitfld.word 0x00 9. " PHY_PMA_ISO_XCVR_CTRL_9 ,Current value of tx_rcv_detect_done PMA output for the associated lane" "0,1" bitfld.word 0x00 8. " PHY_PMA_ISO_XCVR_CTRL_8 ,Drives tx_rcv_detect_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x00 5. " PHY_PMA_ISO_XCVR_CTRL_5 ,Drives xcvr_link_reset_n PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x00 4. " PHY_PMA_ISO_XCVR_CTRL_4 ,Drives xcvr_lane_suspend PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x00 0. " PHY_PMA_ISO_XCVR_CTRL_0 ,Drives xcvr_lane_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" line.word 0x02 "LANE0_PHY_PMA_ISO_TX_CFG,PMA Isolation Configuration Register 0" bitfld.word 0x02 12.--13. " PHY_PMA_ISO_TX_CFG_13_12 ,Drives tx_deemphasis PMA input for the associated lane when in PMA isolation mode" "0,1,2,3" bitfld.word 0x02 8. " PHY_PMA_ISO_TX_CFG_8 ,Drives tx_low_power_swing_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x02 0.--2. " PHY_PMA_ISO_TX_CFG_2_0 ,Drives tx_vmargin PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7" line.word 0x04 "LANE0_PHY_PMA_ISO_LINK_MODE,PMA Isolation Mode Control Register 0" bitfld.word 0x04 15. " PHY_PMA_ISO_LINK_MODE_15 ,Drives tx_reset_n PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x04 12. " PHY_PMA_ISO_LINK_MODE_12 ,Drives the tx_high_z PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x04 4.--5. " PHY_PMA_ISO_LINK_MODE_5_4 ,Drives xcvr_standard_mode PMA input for the associated lane when in PMA isolation mode" "0,1,2,3" bitfld.word 0x04 0.--2. " PHY_PMA_ISO_LINK_MODE_2_0 ,Drives xcvr_data_width PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7" line.word 0x06 "LANE0_PHY_PMA_ISO_PWRST_CTRL,PMA Isolation Power State Control Register 0" bitfld.word 0x06 14. " PHY_PMA_ISO_PWRST_CTRL_14 ,Tx_cmn_mode_en_ext PMA input for the associated lane when in PMA isolation mode" "0,1" rbitfld.word 0x06 8.--13. " PHY_PMA_ISO_PWRST_CTRL_13_8 ,Current value of xcvr_power_state_ack PMA output for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x06 0.--5. " PHY_PMA_ISO_PWRST_CTRL_5_0 ,Drives xcvr_power_state_req PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "LANE0_PHY_PMA_ISO_TX_DATA_LO,PMA Transmit Low Data Isolation Register 0" line.word 0x0A "LANE0_PHY_PMA_ISO_TX_DATA_HI,PMA Transmit High Data Isolation Register 0" bitfld.word 0x0A 0.--3. " PHY_PMA_ISO_TX_DATA_HI_3_0 ,Drives tx_td[19:16] PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC40++0x03 line.word 0x00 "LANE1_PHY_PMA_XCVR_CTRL,PMA Transceiver Control Register 1" rbitfld.word 0x00 10. " PHY_PMA_XCVR_CTRL_10 ,Current value of xcvr_lane_en_ack PMA output for the associated lane" "0,1" bitfld.word 0x00 8. " PHY_PMA_XCVR_CTRL_8 ,Drives the tx_differential_invert PMA input for the associated lane" "Not drove,Drove" textline " " rbitfld.word 0x00 3. " PHY_PMA_XCVR_CTRL_3 ,Current value of rx_bist_status_ln_{nnn} PMA output for the associated lane" "0,1" rbitfld.word 0x00 2. " PHY_PMA_XCVR_CTRL_2 ,Current value of rx_bist_err_toggle_ln_{nnn} PMA output for the associated lane" "0,1" textline " " rbitfld.word 0x00 1. " PHY_PMA_XCVR_CTRL_1 ,Current value of rx_bist_sync_ln_{nnn} PMA output for the associated lane" "0,1" line.word 0x02 "LANE1_PHY_PMA_XCVR_LPBK,PMA Loopback Control Register 1" bitfld.word 0x02 8. " PHY_PMA_XCVR_LPBK_8 ,Drives the tx_bist_hold PMA input for all lanes in the associated link" "Not drove,Drove" bitfld.word 0x02 5. " PHY_PMA_XCVR_LPBK_5 ,Drives the txrx_fe_parallel_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" textline " " bitfld.word 0x02 4. " PHY_PMA_XCVR_LPBK_4 ,Drives the txrx_ne_parallel_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" bitfld.word 0x02 3. " PHY_PMA_XCVR_LPBK_3 ,Drives the txrx_recovered_clk_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" textline " " bitfld.word 0x02 2. " PHY_PMA_XCVR_LPBK_2 ,Drives the txrx_line_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" bitfld.word 0x02 1. " PHY_PMA_XCVR_LPBK_1 ,Drives the txrx_isi_gen_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" textline " " bitfld.word 0x02 0. " PHY_PMA_XCVR_LPBK_0 ,Drives the txrx_serial_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" rgroup.word (0xCC40+0x08)++0x03 line.word 0x00 "LANE1_PHY_PMA_PSM_STATE_LO,PMA PSM Current State Lower Register 1" line.word 0x02 "LANE1_PHY_PMA_PSM_STATE_HI,PMA PSM Current State Higher Register 1" hexmask.word.byte 0x02 0.--7. 1. " PHY_PMA_PSM_STATE_HI_7_0 ,Current state of the PMA power state machine" group.word (0xCC40+0x20)++0x0B line.word 0x00 "LANE1_PHY_PMA_ISO_XCVR_CTRL,PMA Isolation Transceiver Control Register 1" rbitfld.word 0x00 15. " PHY_PMA_ISO_XCVR_CTRL_15 ,Current value of xcvr_pll_clk_en_ack PMA output for the associated lane" "0,1" bitfld.word 0x00 14. " PHY_PMA_ISO_XCVR_CTRL_14 ,Drives xcvr_pll_clk_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x00 13. " PHY_PMA_ISO_XCVR_CTRL_13 ,Drives tx_lfps_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x00 12. " PHY_PMA_ISO_XCVR_CTRL_12 ,Drives tx_elec_idle PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " rbitfld.word 0x00 11. " PHY_PMA_ISO_XCVR_CTRL_11 ,Current value of xcvr_psm_ready PMA output for the associated lane" "0,1" rbitfld.word 0x00 10. " PHY_PMA_ISO_XCVR_CTRL_10 ,Current value of tx_rcv_detected PMA output for the associated lane when in PMA isolation mode" "0,1" textline " " rbitfld.word 0x00 9. " PHY_PMA_ISO_XCVR_CTRL_9 ,Current value of tx_rcv_detect_done PMA output for the associated lane" "0,1" bitfld.word 0x00 8. " PHY_PMA_ISO_XCVR_CTRL_8 ,Drives tx_rcv_detect_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x00 5. " PHY_PMA_ISO_XCVR_CTRL_5 ,Drives xcvr_link_reset_n PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x00 4. " PHY_PMA_ISO_XCVR_CTRL_4 ,Drives xcvr_lane_suspend PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x00 0. " PHY_PMA_ISO_XCVR_CTRL_0 ,Drives xcvr_lane_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" line.word 0x02 "LANE1_PHY_PMA_ISO_TX_CFG,PMA Isolation Configuration Register 1" bitfld.word 0x02 12.--13. " PHY_PMA_ISO_TX_CFG_13_12 ,Drives tx_deemphasis PMA input for the associated lane when in PMA isolation mode" "0,1,2,3" bitfld.word 0x02 8. " PHY_PMA_ISO_TX_CFG_8 ,Drives tx_low_power_swing_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x02 0.--2. " PHY_PMA_ISO_TX_CFG_2_0 ,Drives tx_vmargin PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7" line.word 0x04 "LANE1_PHY_PMA_ISO_LINK_MODE,PMA Isolation Mode Control Register 1" bitfld.word 0x04 15. " PHY_PMA_ISO_LINK_MODE_15 ,Drives tx_reset_n PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x04 12. " PHY_PMA_ISO_LINK_MODE_12 ,Drives the tx_high_z PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x04 4.--5. " PHY_PMA_ISO_LINK_MODE_5_4 ,Drives xcvr_standard_mode PMA input for the associated lane when in PMA isolation mode" "0,1,2,3" bitfld.word 0x04 0.--2. " PHY_PMA_ISO_LINK_MODE_2_0 ,Drives xcvr_data_width PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7" line.word 0x06 "LANE1_PHY_PMA_ISO_PWRST_CTRL,PMA Isolation Power State Control Register 1" bitfld.word 0x06 14. " PHY_PMA_ISO_PWRST_CTRL_14 ,Tx_cmn_mode_en_ext PMA input for the associated lane when in PMA isolation mode" "0,1" rbitfld.word 0x06 8.--13. " PHY_PMA_ISO_PWRST_CTRL_13_8 ,Current value of xcvr_power_state_ack PMA output for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x06 0.--5. " PHY_PMA_ISO_PWRST_CTRL_5_0 ,Drives xcvr_power_state_req PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "LANE1_PHY_PMA_ISO_TX_DATA_LO,PMA Transmit Low Data Isolation Register 1" line.word 0x0A "LANE1_PHY_PMA_ISO_TX_DATA_HI,PMA Transmit High Data Isolation Register 1" bitfld.word 0x0A 0.--3. " PHY_PMA_ISO_TX_DATA_HI_3_0 ,Drives tx_td[19:16] PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC80++0x03 line.word 0x00 "LANE2_PHY_PMA_XCVR_CTRL,PMA Transceiver Control Register 2" rbitfld.word 0x00 10. " PHY_PMA_XCVR_CTRL_10 ,Current value of xcvr_lane_en_ack PMA output for the associated lane" "0,1" bitfld.word 0x00 8. " PHY_PMA_XCVR_CTRL_8 ,Drives the tx_differential_invert PMA input for the associated lane" "Not drove,Drove" textline " " rbitfld.word 0x00 3. " PHY_PMA_XCVR_CTRL_3 ,Current value of rx_bist_status_ln_{nnn} PMA output for the associated lane" "0,1" rbitfld.word 0x00 2. " PHY_PMA_XCVR_CTRL_2 ,Current value of rx_bist_err_toggle_ln_{nnn} PMA output for the associated lane" "0,1" textline " " rbitfld.word 0x00 1. " PHY_PMA_XCVR_CTRL_1 ,Current value of rx_bist_sync_ln_{nnn} PMA output for the associated lane" "0,1" line.word 0x02 "LANE2_PHY_PMA_XCVR_LPBK,PMA Loopback Control Register 2" bitfld.word 0x02 8. " PHY_PMA_XCVR_LPBK_8 ,Drives the tx_bist_hold PMA input for all lanes in the associated link" "Not drove,Drove" bitfld.word 0x02 5. " PHY_PMA_XCVR_LPBK_5 ,Drives the txrx_fe_parallel_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" textline " " bitfld.word 0x02 4. " PHY_PMA_XCVR_LPBK_4 ,Drives the txrx_ne_parallel_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" bitfld.word 0x02 3. " PHY_PMA_XCVR_LPBK_3 ,Drives the txrx_recovered_clk_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" textline " " bitfld.word 0x02 2. " PHY_PMA_XCVR_LPBK_2 ,Drives the txrx_line_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" bitfld.word 0x02 1. " PHY_PMA_XCVR_LPBK_1 ,Drives the txrx_isi_gen_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" textline " " bitfld.word 0x02 0. " PHY_PMA_XCVR_LPBK_0 ,Drives the txrx_serial_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" rgroup.word (0xCC80+0x08)++0x03 line.word 0x00 "LANE2_PHY_PMA_PSM_STATE_LO,PMA PSM Current State Lower Register 2" line.word 0x02 "LANE2_PHY_PMA_PSM_STATE_HI,PMA PSM Current State Higher Register 2" hexmask.word.byte 0x02 0.--7. 1. " PHY_PMA_PSM_STATE_HI_7_0 ,Current state of the PMA power state machine" group.word (0xCC80+0x20)++0x0B line.word 0x00 "LANE2_PHY_PMA_ISO_XCVR_CTRL,PMA Isolation Transceiver Control Register 2" rbitfld.word 0x00 15. " PHY_PMA_ISO_XCVR_CTRL_15 ,Current value of xcvr_pll_clk_en_ack PMA output for the associated lane" "0,1" bitfld.word 0x00 14. " PHY_PMA_ISO_XCVR_CTRL_14 ,Drives xcvr_pll_clk_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x00 13. " PHY_PMA_ISO_XCVR_CTRL_13 ,Drives tx_lfps_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x00 12. " PHY_PMA_ISO_XCVR_CTRL_12 ,Drives tx_elec_idle PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " rbitfld.word 0x00 11. " PHY_PMA_ISO_XCVR_CTRL_11 ,Current value of xcvr_psm_ready PMA output for the associated lane" "0,1" rbitfld.word 0x00 10. " PHY_PMA_ISO_XCVR_CTRL_10 ,Current value of tx_rcv_detected PMA output for the associated lane when in PMA isolation mode" "0,1" textline " " rbitfld.word 0x00 9. " PHY_PMA_ISO_XCVR_CTRL_9 ,Current value of tx_rcv_detect_done PMA output for the associated lane" "0,1" bitfld.word 0x00 8. " PHY_PMA_ISO_XCVR_CTRL_8 ,Drives tx_rcv_detect_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x00 5. " PHY_PMA_ISO_XCVR_CTRL_5 ,Drives xcvr_link_reset_n PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x00 4. " PHY_PMA_ISO_XCVR_CTRL_4 ,Drives xcvr_lane_suspend PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x00 0. " PHY_PMA_ISO_XCVR_CTRL_0 ,Drives xcvr_lane_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" line.word 0x02 "LANE2_PHY_PMA_ISO_TX_CFG,PMA Isolation Configuration Register 2" bitfld.word 0x02 12.--13. " PHY_PMA_ISO_TX_CFG_13_12 ,Drives tx_deemphasis PMA input for the associated lane when in PMA isolation mode" "0,1,2,3" bitfld.word 0x02 8. " PHY_PMA_ISO_TX_CFG_8 ,Drives tx_low_power_swing_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x02 0.--2. " PHY_PMA_ISO_TX_CFG_2_0 ,Drives tx_vmargin PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7" line.word 0x04 "LANE2_PHY_PMA_ISO_LINK_MODE,PMA Isolation Mode Control Register 2" bitfld.word 0x04 15. " PHY_PMA_ISO_LINK_MODE_15 ,Drives tx_reset_n PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x04 12. " PHY_PMA_ISO_LINK_MODE_12 ,Drives the tx_high_z PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x04 4.--5. " PHY_PMA_ISO_LINK_MODE_5_4 ,Drives xcvr_standard_mode PMA input for the associated lane when in PMA isolation mode" "0,1,2,3" bitfld.word 0x04 0.--2. " PHY_PMA_ISO_LINK_MODE_2_0 ,Drives xcvr_data_width PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7" line.word 0x06 "LANE2_PHY_PMA_ISO_PWRST_CTRL,PMA Isolation Power State Control Register 2" bitfld.word 0x06 14. " PHY_PMA_ISO_PWRST_CTRL_14 ,Tx_cmn_mode_en_ext PMA input for the associated lane when in PMA isolation mode" "0,1" rbitfld.word 0x06 8.--13. " PHY_PMA_ISO_PWRST_CTRL_13_8 ,Current value of xcvr_power_state_ack PMA output for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x06 0.--5. " PHY_PMA_ISO_PWRST_CTRL_5_0 ,Drives xcvr_power_state_req PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "LANE2_PHY_PMA_ISO_TX_DATA_LO,PMA Transmit Low Data Isolation Register 2" line.word 0x0A "LANE2_PHY_PMA_ISO_TX_DATA_HI,PMA Transmit High Data Isolation Register 2" bitfld.word 0x0A 0.--3. " PHY_PMA_ISO_TX_DATA_HI_3_0 ,Drives tx_td[19:16] PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCCC0++0x03 line.word 0x00 "LANE3_PHY_PMA_XCVR_CTRL,PMA Transceiver Control Register 3" rbitfld.word 0x00 10. " PHY_PMA_XCVR_CTRL_10 ,Current value of xcvr_lane_en_ack PMA output for the associated lane" "0,1" bitfld.word 0x00 8. " PHY_PMA_XCVR_CTRL_8 ,Drives the tx_differential_invert PMA input for the associated lane" "Not drove,Drove" textline " " rbitfld.word 0x00 3. " PHY_PMA_XCVR_CTRL_3 ,Current value of rx_bist_status_ln_{nnn} PMA output for the associated lane" "0,1" rbitfld.word 0x00 2. " PHY_PMA_XCVR_CTRL_2 ,Current value of rx_bist_err_toggle_ln_{nnn} PMA output for the associated lane" "0,1" textline " " rbitfld.word 0x00 1. " PHY_PMA_XCVR_CTRL_1 ,Current value of rx_bist_sync_ln_{nnn} PMA output for the associated lane" "0,1" line.word 0x02 "LANE3_PHY_PMA_XCVR_LPBK,PMA Loopback Control Register 3" bitfld.word 0x02 8. " PHY_PMA_XCVR_LPBK_8 ,Drives the tx_bist_hold PMA input for all lanes in the associated link" "Not drove,Drove" bitfld.word 0x02 5. " PHY_PMA_XCVR_LPBK_5 ,Drives the txrx_fe_parallel_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" textline " " bitfld.word 0x02 4. " PHY_PMA_XCVR_LPBK_4 ,Drives the txrx_ne_parallel_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" bitfld.word 0x02 3. " PHY_PMA_XCVR_LPBK_3 ,Drives the txrx_recovered_clk_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" textline " " bitfld.word 0x02 2. " PHY_PMA_XCVR_LPBK_2 ,Drives the txrx_line_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" bitfld.word 0x02 1. " PHY_PMA_XCVR_LPBK_1 ,Drives the txrx_isi_gen_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" textline " " bitfld.word 0x02 0. " PHY_PMA_XCVR_LPBK_0 ,Drives the txrx_serial_lpbk_en_ln_{nnn} PMA input for the associated lane" "Not drove,Drove" rgroup.word (0xCCC0+0x08)++0x03 line.word 0x00 "LANE3_PHY_PMA_PSM_STATE_LO,PMA PSM Current State Lower Register 3" line.word 0x02 "LANE3_PHY_PMA_PSM_STATE_HI,PMA PSM Current State Higher Register 3" hexmask.word.byte 0x02 0.--7. 1. " PHY_PMA_PSM_STATE_HI_7_0 ,Current state of the PMA power state machine" group.word (0xCCC0+0x20)++0x0B line.word 0x00 "LANE3_PHY_PMA_ISO_XCVR_CTRL,PMA Isolation Transceiver Control Register 3" rbitfld.word 0x00 15. " PHY_PMA_ISO_XCVR_CTRL_15 ,Current value of xcvr_pll_clk_en_ack PMA output for the associated lane" "0,1" bitfld.word 0x00 14. " PHY_PMA_ISO_XCVR_CTRL_14 ,Drives xcvr_pll_clk_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x00 13. " PHY_PMA_ISO_XCVR_CTRL_13 ,Drives tx_lfps_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x00 12. " PHY_PMA_ISO_XCVR_CTRL_12 ,Drives tx_elec_idle PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " rbitfld.word 0x00 11. " PHY_PMA_ISO_XCVR_CTRL_11 ,Current value of xcvr_psm_ready PMA output for the associated lane" "0,1" rbitfld.word 0x00 10. " PHY_PMA_ISO_XCVR_CTRL_10 ,Current value of tx_rcv_detected PMA output for the associated lane when in PMA isolation mode" "0,1" textline " " rbitfld.word 0x00 9. " PHY_PMA_ISO_XCVR_CTRL_9 ,Current value of tx_rcv_detect_done PMA output for the associated lane" "0,1" bitfld.word 0x00 8. " PHY_PMA_ISO_XCVR_CTRL_8 ,Drives tx_rcv_detect_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x00 5. " PHY_PMA_ISO_XCVR_CTRL_5 ,Drives xcvr_link_reset_n PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x00 4. " PHY_PMA_ISO_XCVR_CTRL_4 ,Drives xcvr_lane_suspend PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x00 0. " PHY_PMA_ISO_XCVR_CTRL_0 ,Drives xcvr_lane_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" line.word 0x02 "LANE3_PHY_PMA_ISO_TX_CFG,PMA Isolation Configuration Register 3" bitfld.word 0x02 12.--13. " PHY_PMA_ISO_TX_CFG_13_12 ,Drives tx_deemphasis PMA input for the associated lane when in PMA isolation mode" "0,1,2,3" bitfld.word 0x02 8. " PHY_PMA_ISO_TX_CFG_8 ,Drives tx_low_power_swing_en PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x02 0.--2. " PHY_PMA_ISO_TX_CFG_2_0 ,Drives tx_vmargin PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7" line.word 0x04 "LANE3_PHY_PMA_ISO_LINK_MODE,PMA Isolation Mode Control Register 3" bitfld.word 0x04 15. " PHY_PMA_ISO_LINK_MODE_15 ,Drives tx_reset_n PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" bitfld.word 0x04 12. " PHY_PMA_ISO_LINK_MODE_12 ,Drives the tx_high_z PMA input for the associated lane when in PMA isolation mode" "Not drove,Drove" textline " " bitfld.word 0x04 4.--5. " PHY_PMA_ISO_LINK_MODE_5_4 ,Drives xcvr_standard_mode PMA input for the associated lane when in PMA isolation mode" "0,1,2,3" bitfld.word 0x04 0.--2. " PHY_PMA_ISO_LINK_MODE_2_0 ,Drives xcvr_data_width PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7" line.word 0x06 "LANE3_PHY_PMA_ISO_PWRST_CTRL,PMA Isolation Power State Control Register 3" bitfld.word 0x06 14. " PHY_PMA_ISO_PWRST_CTRL_14 ,Tx_cmn_mode_en_ext PMA input for the associated lane when in PMA isolation mode" "0,1" rbitfld.word 0x06 8.--13. " PHY_PMA_ISO_PWRST_CTRL_13_8 ,Current value of xcvr_power_state_ack PMA output for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x06 0.--5. " PHY_PMA_ISO_PWRST_CTRL_5_0 ,Drives xcvr_power_state_req PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.word 0x08 "LANE3_PHY_PMA_ISO_TX_DATA_LO,PMA Transmit Low Data Isolation Register 3" line.word 0x0A "LANE3_PHY_PMA_ISO_TX_DATA_HI,PMA Transmit High Data Isolation Register 3" bitfld.word 0x0A 0.--3. " PHY_PMA_ISO_TX_DATA_HI_3_0 ,Drives tx_td[19:16] PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end width 0x0B tree.end tree.open "MIPI_DSI (MIPI DSI Host Controller)" tree "MIPI_DSI_HOST" base ad:0x30A00000 width 50. rgroup.long 0x00++0x33 line.long 0x00 "MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES,MIPI DSI Host DSI Host Configuration Number Lanes" bitfld.long 0x00 0.--1. " DSI_HOST_CFG_NUM_LANES ,Number of active lanes that are to be used for transmitting data" "1 lane,2 lanes,3 lanes,4 lanes" line.long 0x04 "MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK,MIPI DSI Host DSI Host Configuration Noncontinuous Clock" bitfld.long 0x04 0. " DSI_HOST_CFG_NONCONTINUOUS_CLK ,Host controller into non-continuous MIPI clock mode" "Continuous,Noncontinuous" line.long 0x08 "MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE,MIPI DSI Host DSI Host Configuration T PRE" hexmask.long.byte 0x08 0.--6. 1. " DSI_HOST_CFG_T_PRE ,Number of byte clock periods that the controller will wait after enabling the clock lane for HS operation before enabling the data lanes for HS operation" line.long 0x0C "MIPI_DSI_HOST_DSI_HOST_CFG_T_POST,MIPI DSI Host DSI Host Configuration T Post" hexmask.long.byte 0x0C 0.--6. 1. " DSI_HOST_CFG_T_POST ,Number of byte clock periods to wait before putting the clock lane into LP mode after the data lanes have been detected to be in stop state" line.long 0x10 "MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP,MIPI DSI Host DSI Host Configuration TX GAP" hexmask.long.byte 0x10 0.--6. 1. " DSI_HOST_CFG_TX_GAP ,Number of byte clock periods that the controller will wait after the clock lane has been put into LP mode before enabling the clock lane for HS mode again" line.long 0x14 "MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP,MIPI DSI Host DSI Host Configuration Autoinsert EOTP" bitfld.long 0x14 0. " DSI_HOST_CFG_AUTOINSERT_EOTP ,Enable the host controller to automatically insert an EoTp short packet when switching from HS to LP" "Not auto-inserted,Auto-inserted" line.long 0x18 "MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP,MIPI DSI Host DSI Host Configuration TX GAP" hexmask.long.byte 0x18 0.--7. 1. " DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP ,DSI host controller to send extra end of transmission packets after the end of a packet" line.long 0x1C "MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT,MIPI DSI Host DSI Host Configuration HTX To Count" hexmask.long.tbyte 0x1C 0.--23. 1. " DSI_HOST_CFG_HTX_TO_COUNT ,Value of the DSI host high speed TX timeout count in clk_byte clock periods" line.long 0x20 "MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT,MIPI DSI Host DSI Host Configuration LRX H To Count" hexmask.long.tbyte 0x20 0.--23. 1. " DSI_HOST_CFG_LRX_H_TO_COUNT ,Value of the DSI host low power RX timeout count in clk_byte clock periods" line.long 0x24 "MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT,MIPI DSI Host DSI Host Configuration LRX H To Count" hexmask.long.tbyte 0x24 0.--23. 1. " DSI_HOST_CFG_BTA_H_TO_COUNT ,Value of the DSI host bus turn around (BTA) timeout in clk_byte clock periods" line.long 0x28 "MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP,MIPI DSI Host DSI Host Configuration TWAKEUP" hexmask.long.tbyte 0x28 0.--18. 1. " DSI_HOST_CFG_TWAKEUP ,DPHY Twakeup timing parameter" line.long 0x2C "MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT,MIPI DSI Host DSI Host Configuration Status Out" bitfld.long 0x2C 10. " CHECKSUM_ERROR ,Checksum error from peripheral error report" "No error,Error" bitfld.long 0x2C 9. " ECC_ERROR_MULTI_BIT ,ECC multi-bit error from peripheral error report" "No error,Error" textline " " bitfld.long 0x2C 8. " ECC_ERROR_MULTI_BIT ,ECC single bit error from peripheral error report" "No error,Error" bitfld.long 0x2C 7. " CONTENTION_DETECT ,Contention detection from peripheral error report" "No error,Error" textline " " bitfld.long 0x2C 6. " FALSE_CONTROL_ERROR ,False control error from peripheral error report" "No error,Error" bitfld.long 0x2C 5. " PERIPH_TIMEOUT_ERROR ,Peripheral timeout error from peripheral error report" "No error,Error" textline " " bitfld.long 0x2C 4. " LP_TX_SYNC_ERROR ,Low power transmit sync error from peripheral error report" "No error,Error" bitfld.long 0x2C 3. " ESCAPE_MODE_ENTRY_CMD_ERROR ,Escape mode entry command error from peripheral error report" "No error,Error" textline " " bitfld.long 0x2C 2. " EOT_SYNC_ERROR ,End of transmission sync error from peripheral error report" "No error,Error" bitfld.long 0x2C 1. " SOT_SYNC_ERROR ,Start of transmission sync error from peripheral error report" "No error,Error" textline " " bitfld.long 0x2C 0. " SOT_ERROR ,Start of transmission error from peripheral error report" "No error,Error" line.long 0x30 "MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS,MIPI DSI Host DSI Host RX Error Status" bitfld.long 0x30 10. " DSI_HOST_RX_ERROR_STATUS[6] ,Status register for host receive error detection (BTA timeout detected)" "Not detected,Detected" bitfld.long 0x30 9. " DSI_HOST_RX_ERROR_STATUS[5] ,Status register for host receive error detection (Reverse low power data receive timeout detected)" "Not detected,Detected" textline " " bitfld.long 0x30 8. " DSI_HOST_RX_ERROR_STATUS[4] ,Status register for host receive error detection (High speed forward TX timeout detected)" "Not detected,Detected" bitfld.long 0x30 7. " DSI_HOST_RX_ERROR_STATUS[3] ,Status register for host receive error detection (CRC error detected)" "Not detected,Detected" textline " " bitfld.long 0x30 2.--6. " DSI_HOST_RX_ERROR_STATUS[2] ,Status register for host receive error detection (Errored bit position for single bit ECC error)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 1. " DSI_HOST_RX_ERROR_STATUS[1] ,Status register for host receive error detection (ECC multi bit error detected)" "Not detected,Detected" textline " " bitfld.long 0x30 0. " DSI_HOST_RX_ERROR_STATUS[0] ,Status register for host receive error detection (ECC single bit error detected)" "Not detected,Detected" width 0x0B tree.end tree "MIPI_DSI_HOST_DPI_INTFC" base ad:0x30A00000 width 65. rgroup.long 0x200++0x43 line.long 0x00 "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Pixel Payload Size" hexmask.long.word 0x00 0.--15. 1. " DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE ,Maximum number of pixels that should be sent as one DSI packet" line.long 0x04 "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Pixel FIFO Send Level" hexmask.long.word 0x04 0.--15. 1. " DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL ,In order to optimize DSI utility the DPI bridge buffers a certain number of DPI pixels before initiating a DSI packet" line.long 0x08 "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Interface Color Coding" bitfld.long 0x08 0.--2. " DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING ,Distribution of RGB bits within the 24-bit d bus" "16-bit conf 1,16-bit conf 2,16-bit conf 3,18-bit conf 1,18-bit conf 2,24-bit,?..." line.long 0x0C "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Pixel Format" bitfld.long 0x0C 0.--1. " DSI_HOST_CFG_DPI_PIXEL_FORMAT ,DSI packet type of the pixels" "16-bit,18-bit,18-bit loosely packed,24-bit" line.long 0x10 "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY,MIPI DSI Host DPI INTFC DSI Host Configuration DPI VSYNC Polarity" bitfld.long 0x10 0. " DSI_HOST_CFG_DPI_VSYNC_POLARITY ,Polarity of dpi_vsync_input" "Active low,Active high" line.long 0x14 "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY,MIPI DSI Host DPI INTFC DSI Host Configuration DPI HSYNC Polarity" bitfld.long 0x14 0. " DSI_HOST_CFG_DPI_HSYNC_POLARITY ,Polarity of dpi_hsync_input" "Active low,Active high" line.long 0x18 "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Video Mode" bitfld.long 0x18 0.--1. " DSI_HOST_CFG_DPI_VIDEO_MODE ,DSI video mode that the host DPI module should generate packets for" "Non-Burst with sync pulses,Non-Burst with sync events,Burst,?..." line.long 0x1C "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI HFP" hexmask.long.word 0x1C 0.--15. 1. " DSI_HOST_CFG_DPI_HFP ,DSI packet payload size" line.long 0x20 "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI HBP" hexmask.long.word 0x20 0.--15. 1. " DSI_HOST_CFG_DPI_HBP ,DSI packet payload size" line.long 0x24 "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA,MIPI DSI Host DPI INTFC DSI Host Configuration DPI HSA" hexmask.long.word 0x24 0.--15. 1. " DSI_HOST_CFG_DPI_HSA ,DSI packet payload size" line.long 0x28 "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Enable MULT PKTS" bitfld.long 0x28 0. " DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS ,Multiple packets per video line" "Single packet,Two packets" line.long 0x2C "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI VBP" hexmask.long.byte 0x2C 0.--7. 1. " DSI_HOST_CFG_DPI_VBP ,Number of lines in the vertical back porch" line.long 0x30 "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI VFP" hexmask.long.byte 0x30 0.--7. 1. " DSI_HOST_CFG_DPI_VFP ,Number of lines in the vertical front porch" line.long 0x34 "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE,MIPI DSI Host DPI INTF DSI Host Configuration DPI BLLP Mode" bitfld.long 0x34 0. " DSI_HOST_CFG_DPI_BLLP_MODE ,Optimize bllp periods to low power mode when possible" "Blanking packets sent during BLLP periods,LP mode used for BLLP periods" line.long 0x38 "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Use Null PKT BLLP" bitfld.long 0x38 0. " DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP ,Type of blanking packet to be sent during bllp region" "Blanking packet used in BLLP region,Null packet used in BLLP region" line.long 0x3C "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Vactive" hexmask.long.word 0x3C 0.--13. 1. " DSI_HOST_CFG_DPI_VACTIVE ,Number of lines in the vertical active area" line.long 0x40 "MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC,MIPI DSI Host DPI INTFC DSI Host Configuration DPI VC" bitfld.long 0x40 0.--1. " DSI_HOST_CFG_DPI_VC ,Virtual channel (VC) of packets that will be sent to the receive packet interface" "0,1,2,3" width 0x0B tree.end tree "MIPI_DSI_HOST_APB_PKT_IF" base ad:0x30A00000 width 53. rgroup.long 0x280++0x2F line.long 0x00 "MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD,MIPI DSI Host APB PKT IF DSI Host TX Payload" line.long 0x04 "MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL,MIPI DSI Host APB PKT IF DSI Host PKT Control" bitfld.long 0x04 26. " DSI_HOST_PKT_CONTROL[5] ,Tx packet control (Perform BTA only/no packet Tx)" ",BTA only/No packet Tx" bitfld.long 0x04 25. " DSI_HOST_PKT_CONTROL[4] ,Tx packet control (Perform BTA after packet is sent)" ",Performed" textline " " bitfld.long 0x04 24. " DSI_HOST_PKT_CONTROL[3] ,Tx packet control (Lp or HS select)" "LP,HS" bitfld.long 0x04 18.--23. " DSI_HOST_PKT_CONTROL[2] ,Tx packet control (Packet header DSI data type)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 16.--17. " DSI_HOST_PKT_CONTROL[1] ,Tx packet control (Packet virtual channel)" "0,1,2,3" hexmask.long.word 0x04 0.--15. 1. " DSI_HOST_PKT_CONTROL[0] ,Tx packet control (Packet word count)" line.long 0x08 "MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET,MIPI DSI Host APB PKT IF DSI Host Send Packet" bitfld.long 0x08 0. " DSI_HOST_SEND_PACKET ,Tx send packet" "Not sent,Sent" line.long 0x0C "MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS,MIPI DSI Host APB PKT IF DSI PKT Status" bitfld.long 0x0C 8. " DSI_HOST_PKT_STATUS[8] ,Status of APB to packet interface (All rx packet payload data has been receive)" "Not received,Received" bitfld.long 0x0C 7. " DSI_HOST_PKT_STATUS[7] ,Status of APB to packet interface (Rx packet header has been received)" "Not received,Received" textline " " bitfld.long 0x0C 6. " DSI_HOST_PKT_STATUS[6] ,Status of APB to packet interface (Rx fifo underflow)" "No underflow,Underflow" bitfld.long 0x0C 5. " DSI_HOST_PKT_STATUS[5] ,Status of APB to packet interface (Rx fifo overflow)" "No overflow,Overflow" textline " " bitfld.long 0x0C 4. " DSI_HOST_PKT_STATUS[4] ,Status of APB to packet interface (Tx fifo underflow)" "No underflow,Underflow" bitfld.long 0x0C 3. " DSI_HOST_PKT_STATUS[3] ,Status of APB to packet interface (Tx fifo overflow)" "No overflow,Overflow" textline " " bitfld.long 0x0C 2. " DSI_HOST_PKT_STATUS[2] ,Status of APB to packet interface (Dphy direction)" "Tx had control,Rx has control" bitfld.long 0x0C 1. " DSI_HOST_PKT_STATUS[1] ,Status of APB to packet interface (Tx packet done)" "Not done,Done" textline " " bitfld.long 0x0C 0. " DSI_HOST_PKT_STATUS[0] ,Status of APB to packet interface (State machine not idle)" "Not idle,Idle" line.long 0x10 "MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL,MIPI DSI Host APB PKT IF DSI Host PKT FIFO WR Level" hexmask.long.word 0x10 0.--15. 1. " DSI_HOST_PKT_FIFO_WR_LEVEL ,Write level of APB to pkt interface fifo" line.long 0x14 "MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL,MIPI DSI Host APB PKT IF DSI Host PKT FIFO RD Level" hexmask.long.word 0x14 0.--15. 1. " DSI_HOST_PKT_FIFO_RD_LEVEL ,Read level of APB to pkt interface fifo" line.long 0x18 "MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD,MIPI DSI Host APB PKT IF DSI Host PKT RX Payload" line.long 0x1C "MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER,MIPI DSI Host APB PKT IF DSI Host PKT RX PKT Header" bitfld.long 0x1C 22.--23. " DSI_HOST_PKT_RX_PKT_HEADER[2] ,APB to pkt interface rx packet header (Virtual Channel)" "0,1,2,3" bitfld.long 0x1C 16.--21. " DSI_HOST_PKT_RX_PKT_HEADER[1] ,APB to pkt interface rx packet header (Data type)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x1C 0.--15. 1. " DSI_HOST_PKT_RX_PKT_HEADER[0] ,APB to pkt interface rx packet header (Word count)" line.long 0x20 "MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS,MIPI DSI Host APB PKT IF DSI Host Interrupt Status" bitfld.long 0x20 31. " DSI_HOST_IRQ_STATUS[12] ,Status of APB to packet interface (High speed tx timeout)" "No interrupt,Interrupt" bitfld.long 0x20 30. " DSI_HOST_IRQ_STATUS[11] ,Status of APB to packet interface (Low power rx timeout)" "No interrupt,Interrupt" textline " " bitfld.long 0x20 29. " DSI_HOST_IRQ_STATUS[10] ,Status of APB to packet interface (Host bta timeout)" "No interrupt,Interrupt" hexmask.long.tbyte 0x20 9.--28. 1. " DSI_HOST_IRQ_STATUS[9] ,Status of APB to packet interface (Map directory to dsi host controller status_out port bit descriptions)" textline " " bitfld.long 0x20 8. " DSI_HOST_IRQ_STATUS[8] ,Status of APB to packet interface (All rx packet payload data has been received)" "No interrupt,Interrupt" bitfld.long 0x20 7. " DSI_HOST_IRQ_STATUS[7] ,Status of APB to packet interface (Rx packet header has been received)" "No interrupt,Interrupt" textline " " bitfld.long 0x20 6. " DSI_HOST_IRQ_STATUS[6] ,Status of APB to packet interface (Rx fifo underflow)" "No interrupt,Interrupt" bitfld.long 0x20 5. " DSI_HOST_IRQ_STATUS[5] ,Status of APB to packet interface (Rx fifo overflow)" "No interrupt,Interrupt" textline " " bitfld.long 0x20 4. " DSI_HOST_IRQ_STATUS[4] ,Status of APB to packet interface (Tx fifo underflow)" "No interrupt,Interrupt" bitfld.long 0x20 3. " DSI_HOST_IRQ_STATUS[3] ,Status of APB to packet interface (Tx fifo overflow)" "No interrupt,Interrupt" textline " " bitfld.long 0x20 2. " DSI_HOST_IRQ_STATUS[2] ,Status of APB to packet interface (Dphy direction)" "No interrupt,Interrupt" bitfld.long 0x20 1. " DSI_HOST_IRQ_STATUS[1] ,Status of APB to packet interface (Tx packet done)" "No interrupt,Interrupt" textline " " bitfld.long 0x20 0. " DSI_HOST_IRQ_STATUS[0] ,Status of APB to packet interface (State machine not idle)" "No interrupt,Interrupt" line.long 0x24 "MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2,MIPI DSI Host APB PKT IF DSI Host Interrupt Status 2" bitfld.long 0x24 2. " DSI_HOST_IRQ_STATUS2[2] ,Status of APB to packet interface part 2 (Crc error)" "No interrupt,Interrupt" bitfld.long 0x24 1. " DSI_HOST_IRQ_STATUS2[1] ,Status of APB to packet interface part 2 (Multi bit ecc error)" "No interrupt,Interrupt" textline " " bitfld.long 0x24 0. " DSI_HOST_IRQ_STATUS2[0] ,Status of APB to packet interface part 2 (Single bit ecc error)" "No interrupt,Interrupt" line.long 0x28 "MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK,MIPI DSI Host APB PKT IF DSI Host Interrupt Mask" bitfld.long 0x28 31. " DSI_HOST_IRQ_MASK[12] ,Status of APB to packet interface (High speed tx timeout)" "Not masked,Masked" bitfld.long 0x28 30. " DSI_HOST_IRQ_MASK[11] ,Status of APB to packet interface (Low power rx timeout)" "Not masked,Masked" textline " " bitfld.long 0x28 29. " DSI_HOST_IRQ_MASK[10] ,Status of APB to packet interface (Host bta timeout)" "Not masked,Masked" hexmask.long.tbyte 0x28 9.--28. 1. " DSI_HOST_IRQ_MASK[9] ,Status of APB to packet interface (Map directory to dsi host controller status_out port bit descriptions)" textline " " bitfld.long 0x28 8. " DSI_HOST_IRQ_MASK[8] ,Status of APB to packet interface (All rx packet payload data has been received)" "Not masked,Masked" bitfld.long 0x28 7. " DSI_HOST_IRQ_MASK[7] ,Status of APB to packet interface (Rx packet header has been received)" "Not masked,Masked" textline " " bitfld.long 0x28 6. " DSI_HOST_IRQ_MASK[6] ,Status of APB to packet interface (Rx fifo underflow)" "Not masked,Masked" bitfld.long 0x28 5. " DSI_HOST_IRQ_MASK[5] ,Status of APB to packet interface (Rx fifo overflow)" "Not masked,Masked" textline " " bitfld.long 0x28 4. " DSI_HOST_IRQ_MASK[4] ,Status of APB to packet interface (Tx fifo underflow)" "Not masked,Masked" bitfld.long 0x28 3. " DSI_HOST_IRQ_MASK[3] ,Status of APB to packet interface (Tx fifo overflow)" "Not masked,Masked" textline " " bitfld.long 0x28 2. " DSI_HOST_IRQ_MASK[2] ,Status of APB to packet interface (Dphy direction)" "Not masked,Masked" bitfld.long 0x28 1. " DSI_HOST_IRQ_MASK[1] ,Status of APB to packet interface (Tx packet done)" "Not masked,Masked" textline " " bitfld.long 0x28 0. " DSI_HOST_IRQ_MASK[0] ,Status of APB to packet interface (State machine not idle)" "Not masked,Masked" line.long 0x2C "MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2,MIPI DSI Host APB PKT IF DSI Host Interrupt Mask 2" bitfld.long 0x2C 2. " DSI_HOST_IRQ_MASK2[2] ,Status of APB to packet interface part 2 (Crc error)" "Not masked,Masked" bitfld.long 0x2C 1. " DSI_HOST_IRQ_MASK2[1] ,Status of APB to packet interface part 2 (Multi bit ecc error)" "Not masked,Masked" textline " " bitfld.long 0x2C 0. " DSI_HOST_IRQ_MASK2[0] ,Status of APB to packet interface part 2 (Single bit ecc error)" "Not masked,Masked" width 0x0B tree.end tree "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC" base ad:0x30A00000 width 57. rgroup.long 0x300++0x47 line.long 0x00 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY,MIPI DSI Host FSL IP1 DPHY INTFC DPHY PD DPHY" bitfld.long 0x00 0. " DPHY_PD_DPHY ,DPHY PD_DPHY input control" "0,1" line.long 0x04 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE,MIPI DSI Host FSL IP1 DPHY INTFC DPHY M PRG HS PREPARE" bitfld.long 0x04 0.--1. " DPHY_M_PRG_HS_PREPARE ,DPHY m_PRG_HS_PREPARE input" "1,1.5,2,2.5" line.long 0x08 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE,MIPI DSI Host FSL IP1 DPHY INTFC DPHY MC PRG HS PREPARE" bitfld.long 0x08 0. " DPHY_MC_PRG_HS_PREPARE ,DPHY mc_PRG_HS_PREPARE input" "1,1.5" line.long 0x0C "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO,MIPI DSI Host FSL IP1 DPHY INTFC DPHY M PRG HS Zero" bitfld.long 0x0C 0.--4. " DPHY_M_PRG_HS_ZERO ,DPHY m_PRG_HS_ZERO input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO,MIPI DSI Host FSL IP1 DPHY INTFC DPHY MC PRG HS Zero" bitfld.long 0x10 0.--5. " DPHY_MC_PRG_HS_ZERO ,DPHY mc_PRG_HS_ZERO input" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL,MIPI DSI Host FSL IP1 DPHY INTFC DPH M PRG HS Trail" bitfld.long 0x14 0.--3. " DPHY_M_PRG_HS_TRAIL ,DPHY m_PRG_HS_TRAIL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL,MIPI DSI Host FSL IP1 DPHY INTFC DPHY MC PRG HS Trail" bitfld.long 0x18 0.--3. " DPHY_MC_PRG_HS_TRAIL ,DPHY mc_PRG_HS_TRAIL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL,MIPI DSI Host FSL IP1 DPHY INTFC DPHY PD PLL" bitfld.long 0x1C 0. " PD ,DPHY PD_PLL input" "0,1" line.long 0x20 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST,MIPI DSI Host FSL IP1 DPHY INTFC DPHY MC PRG HS Zero" bitfld.long 0x20 0.--5. " TST ,DPHY TST input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN,MIPI DSI Host FSL IP1 DPHY INTFC DPHY CN" bitfld.long 0x24 0.--4. " CN ,DPHY PLL input divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x28 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM,MIPI DSI Host FSL IP1 DPHY INTFC DPHY CM" hexmask.long.byte 0x28 0.--7. 1. " CM ,DPHY PLL feedback divider" line.long 0x2C "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO,MIPI DSI Host FSL IP1 DPHY INTFC DPHY CO" bitfld.long 0x2C 0.--1. " CO ,DPHY PLL output divider" "1,2,4,8" line.long 0x30 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK,MIPI DSI Host FSL IP1 DPHY INTFC DPHY Lock" bitfld.long 0x30 0. " LOCK ,DPHY PLL LOCK output" "0,1" line.long 0x34 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP,MIPI DSI Host FSL IP1 DPHY INTFC DPHY Lock BYP" bitfld.long 0x34 0. " DPHY_LOCK_BYP ,DPHY LOCK_BYP input" "0,1" line.long 0x38 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL,MIPI DSI Host FSL IP1 DPHY INTFC DPHY RTERM SEL" bitfld.long 0x38 0. " DPHY_RTERM_SEL ,DPHY RTERM_SEL input" "0,1" line.long 0x3C "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN,MIPI DSI Host FSL IP1 DPHY INTFC DPHY Auto PD EN" bitfld.long 0x3C 0. " DPHY_AUTO_PD_EN ,DPHY AUTO_PD_EN input" "0,1" line.long 0x40 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP,MIPI DSI Host FSL IP1 DPHY INTFC DPHY RXLPRP" bitfld.long 0x40 0.--1. " DPHY_RXLPRP ,DPHY RXLPRP input" "0,1,2,3" line.long 0x44 "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP,MIPI DSI Host FSL IP1 DPHY INTFC DPHY RXCDRP" bitfld.long 0x44 0.--1. " DPHY_RXCDRP ,DPHY RXCDRP input" "0,1,2,3" width 0x0B tree.end tree.end tree "MIPI_CSI (MIPI CSI Host Controller)" base ad:0x00000100 width 31. group.long 0x00++0x07 line.long 0x00 "CSI2RX_CFG_NUM_LANES,CSI2RX Configuration Number Lanes" bitfld.long 0x00 0.--1. " CSI2RX_CFG_NUM_LANES ,Number of active lanes that are to be used for receiving data" "1 lane,2 lanes,3 lanes,4 lanes" line.long 0x04 "CSI2RX_CFG_DISABLE_DATA_LANES,CSI2RX Configuration Disable Data Lanes" bitfld.long 0x04 0.--3. " CSI2RX_CFG_DISABLE_DATA_LANES ,DPHY Enable signal to deassert" "Data lane 0,Data lane 1,Data lane 2,Data lane 3,?..." rgroup.long 0x08++0x07 line.long 0x00 "CSI2RX_BIT_ERR,CSI2RX Bit Error" bitfld.long 0x00 1. " CSI2RX_BIT_ERR[1] ,First status event when either a one or two bit error occurs" "No error event captured,Two bit error event captured" bitfld.long 0x00 0. " CSI2RX_BIT_ERR[0] ,First status event when either a one or two bit error occurs" "No error,Error" textline " " line.long 0x04 "CSI2RX_IRQ_STATUS,CSI2RX Interrupt Status" bitfld.long 0x04 8. " CSI2RX_IRQ_MASK[8] ,CSI2 RX IRQ status 8" "No interrupt,Interrupt" bitfld.long 0x04 7. " [7] ,CSI2 RX IRQ status 7" "No interrupt,Interrupt" bitfld.long 0x04 6. " [6] ,CSI2 RX IRQ status 6" "No interrupt,Interrupt" bitfld.long 0x04 5. " [5] ,CSI2 RX IRQ status 5" "No interrupt,Interrupt" textline " " bitfld.long 0x04 4. " [4] ,CSI2 RX IRQ status 4" "No interrupt,Interrupt" bitfld.long 0x04 3. " [3] ,CSI2 RX IRQ status 3" "No interrupt,Interrupt" bitfld.long 0x04 2. " [2] ,CSI2 RX IRQ status 2" "No interrupt,Interrupt" bitfld.long 0x04 1. " [1] ,CSI2 RX IRQ status 1" "No interrupt,Interrupt" textline " " bitfld.long 0x04 0. " [0] ,CSI2 RX IRQ status 0" "No interrupt,Interrupt" group.long 0x10++0x03 line.long 0x00 "CSI2RX_IRQ_MASK,CSI2RX Interrupt Mask" bitfld.long 0x00 8. " CSI2RX_IRQ_MASK[8] ,CSI2 RX IRQ mask 8" "Unmasked,Masked" bitfld.long 0x00 7. " [7] ,CSI2 RX IRQ mask 7" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,CSI2 RX IRQ mask 6" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,CSI2 RX IRQ mask 5" "Unmasked,Masked" textline " " bitfld.long 0x00 4. " [4] ,CSI2 RX IRQ mask 4" "Unmasked,Masked" bitfld.long 0x00 3. " [3] ,CSI2 RX IRQ mask 3" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,CSI2 RX IRQ mask 2" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,CSI2 RX IRQ mask 1" "Unmasked,Masked" textline " " bitfld.long 0x00 0. " [0] ,CSI2 RX IRQ mask 0" "Unmasked,Masked" rgroup.long 0x14++0x17 line.long 0x00 "CSI2RX_ULPS_STATUS,CSI2RX ULPS Status" hexmask.long.word 0x00 0.--9. 1. " CSI2RX_ULPS_STATUS ,CSI2 RX ULPS status" line.long 0x04 "CSI2RX_PPI_ERRSOT_HS,CSI2RX PPI ErrSOT HS" bitfld.long 0x04 0.--3. " CSI2RX_PPI_ERRSOT_HS ,CSI2 RX DPHY PPI ErrSotHS captured status from the DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CSI2RX_PPI_ERRSOTSYNC_HS,CSI2RX PPI ErrSOTSync HS" bitfld.long 0x08 0.--3. " CSI2RX_PPI_ERRSOTSYNC_HS ,CSI2 RX DPHY PPI ErrSotSync_HS captured status from the DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "CSI2RX_PPI_ERRESC,CSI2RX PPI ErrESC" bitfld.long 0x0C 0.--3. " CSI2RX_PPI_ERRESC ,CSI2 RX DPHY PPI ErrEsc captured status from the DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "CSI2RX_PPI_ERRSYNCESC,CSI2RX PPI ErrSyncESC" bitfld.long 0x10 0.--3. " CSI2RX_PPI_ERRSYNCESC ,CSI2 RX DPHY PPI ErrSyncEsc captured status from the DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "CSI2RX_PPI_ERRCONTROL,CSI2RX PPI Error Control" bitfld.long 0x14 0.--3. " CSI2RX_PPI_ERRCONTROL ,CSI2 RX DPHY PPI ErrControl captured status from the DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C++0x07 line.long 0x00 "CSI2RX_CFG_DISABLE_PAYLOAD_0,CSI2RX Configuration Disable Payload 0" line.long 0x04 "CSI2RX_CFG_DISABLE_PAYLOAD_1,CSI2RX Configuration Disable Payload 1" hexmask.long.tbyte 0x04 0.--16. 1. " CSI2RX_CFG_DISABLE_PAYLOAD_1 ,CSI2 RX Controller cfg_diable_payload" width 0x0B tree.end tree.open "SPDIF (Sony/Philips Digital Interface)" tree "SPDIF1" base ad:0x30810000 width 8. group.long 0x00++0x07 line.long 0x00 "SCR,SPDIF Configuration Register" bitfld.long 0x00 23. " RXFIFO_CTRL ,Rx FIFO control" "Normal,Always read zero" bitfld.long 0x00 22. " RXFIFO_OFF_ON ,SPDIF Rx FIFO on/off" "On,Off" newline bitfld.long 0x00 21. " RXFIFO_RST ,Rx FIFO reset" "Normal,Reset" bitfld.long 0x00 19.--20. " RXFIFOFULL_SEL ,Rx FIFO full interrupt select" "1,4,8,16" newline bitfld.long 0x00 18. " RXAUTOSYNC ,Rx auto sync off/on" "Off,On" bitfld.long 0x00 17. " TXAUTOSYNC ,Tx auto sync off/on" "Off,On" newline bitfld.long 0x00 15.--16. " TXFIFOEMPTY_SEL ,Tx FIFO empty interrupt select" "1,4,8,16" bitfld.long 0x00 13. " LOW_POWER ,SPDIF low-power mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SOFT_RESET ,SPDIF software reset" "No reset,Reset" bitfld.long 0x00 10.--11. " TXFIFO_CTRL ,Tx FIFO control" "Digital zero,Normal,Reset,?..." newline bitfld.long 0x00 9. " DMA_RX_EN ,DMA receive request enable" "Disabled,Enabled" bitfld.long 0x00 8. " DMA_TX_EN ,DMA transmit request enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " VALCTRL ,Outgoing validity set/clear control" "Set,Clear" bitfld.long 0x00 2.--4. " TXSEL ,Tx select" "Off,SPDIFIN,,,,Normal,?..." newline bitfld.long 0x00 0.--1. " USRC_SEL ,USRC select" "No embedded,SPDIF,,Chip transmitter" line.long 0x04 "SRCD,Cdtext Control Register" bitfld.long 0x04 1. " USYNCMODE ,U sync mode" "Non-CD,CD" newline width 13. sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) if (((per.l(ad:0x30810000+0x08)&0x40)==0x40)) group.long 0x08++0x03 line.long 0x00 "SRPC,Phaseconfig Register" bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "Spdif_rxclk,Spdif_rxclk,Spdif_rxclk,Spdif_rxclk,Spdif_rxclk,REF_CLK_32K,Tx_clk,ASRC_CLK,SPDIF_EXT_CLK,ESAI_HCKT,Spdif_rxclk,Spdif_rxclk,MLB clock,MLB PHY clock,?..." rbitfld.long 0x00 6. " LOCK ,DPLL lock" "Unlocked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10),?..." else group.long 0x08++0x03 line.long 0x00 "SRPC,Phaseconfig Register" bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "REF_CLK_32K,Tx_clk,ASRC_EXT_CLK,SPDIF_EXT_CLK,ESAI_HCKT,REF_CLK_32K,Tx_clk,ASRC_CLK,SPDIF_EXT_CLK,ESAI_HCKT,MLB clock,MLB PHY clock,MLB clock,MLB PHY clock,?..." rbitfld.long 0x00 6. " LOCK ,DPLL lock" "Unlocked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10),?..." endif else if (((per.l(ad:0x30810000+0x08)&0x40)==0x40)) group.long 0x08++0x03 line.long 0x00 "SRPC,Phaseconfig Register" bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "Spdif_rxclk,Spdif_rxclk,,Spdif_rxclk,,REF_CLK_32K,Tx_clk,,SPDIF_EXT_CLK,?..." rbitfld.long 0x00 6. " LOCK ,DPLL lock" "Unlocked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10),?..." else group.long 0x08++0x03 line.long 0x00 "SRPC,Phaseconfig Register" bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "REF_CLK_32K,Tx_clk,,SPDIF_EXT_CLK,,REF_CLK_32K,Tx_clk,,SPDIF_EXT_CLK,?..." rbitfld.long 0x00 6. " LOCK ,DPLL lock" "Unlocked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10),?..." endif endif group.long 0x0C++0x03 line.long 0x00 "SIE,Interrupten Register" bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " TXUNOV ,SPDIF Tx FIFO under/overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " TXRESYN ,SPDIF Tx FIFO resync interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " URXFUL ,U channel receive register full" "Not full,Full" newline bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " QRXFUL ,Q channel receive register full" "Not full,Full" bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RXFIFOUNOV ,Rx FIFO underrun/overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " RXFIFORESYN ,Rx FIFO resync interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " TXEM ,SPDIF Tx FIFO empty" "Not empty,Empty" bitfld.long 0x00 0. " RXFIFOFUL ,SPDIF Rx FIFO full" "Not full,Full" rgroup.long 0x10++0x03 line.long 0x00 "SIS,Interruptstat Register" bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 19. " TXUNOV ,SPDIF Tx FIFO under/overrun interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 18. " TXRESYN ,SPDIF Tx FIFO resync interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 10. " URXFUL ,U channel receive register full" "Not full,Full" newline bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 8. " QRXFUL ,Q channel receive register full" "Not full,Full" bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 4. " RXFIFOUNOV ,Rx FIFO underrun/overrun interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 3. " RXFIFORESYN ,Rx FIFO resync interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " TXEM ,SPDIF Tx FIFO empty" "Not empty,Empty" bitfld.long 0x00 0. " RXFIFOFUL ,SPDIF Rx FIFO full" "Not full,Full" wgroup.long 0x10++0x03 line.long 0x00 "SIC,Interruptclear Register" bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt clear" "No clear,Clear" bitfld.long 0x00 19. " TXUNOV ,SPDIF Tx FIFO under/overrun interrupt status" "No clear,Clear" bitfld.long 0x00 18. " TXRESYN ,SPDIF Tx FIFO resync interrupt status" "No clear,Clear" bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel interrupt status" "No clear,Clear" newline bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt status" "No clear,Clear" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt status" "No clear,Clear" bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt status" "No clear,Clear" bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt status" "No clear,Clear" newline bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt status" "No clear,Clear" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt status" "No clear,Clear" bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt status" "No clear,Clear" bitfld.long 0x00 4. " RXFIFOUNOV ,Rx FIFO underrun/overrun interrupt status" "No clear,Clear" newline bitfld.long 0x00 3. " RXFIFORESYN ,Rx FIFO resync interrupt status" "No clear,Clear" bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt status" "No clear,Clear" rgroup.long 0x14++0x17 line.long 0x00 "SRL,Spdifrxleft Register" hexmask.long.tbyte 0x00 0.--23. 1. " RXDATALEFT ,Processor receive SPDIF data left" line.long 0x04 "SRR,Spdifrxright Register" hexmask.long.tbyte 0x04 0.--23. 1. " RXDATARIGHT ,Processor receive SPDIF data right" line.long 0x08 "SRCSH,Spdifrxcchannel_h Register" hexmask.long.tbyte 0x08 0.--23. 1. " RXCCHANNEL_H ,SPDIF receive C channel register contains first 24 bits of C channel without interpretation" line.long 0x0C "SRCSL,Spdifrxcchannel_l Register" hexmask.long.tbyte 0x0C 0.--23. 1. " RXCCHANNEL_L ,SPDIF receive C channel register contains next 24 bits of C channel without interpretation" line.long 0x10 "SRU,Uchannelrx Register" hexmask.long.tbyte 0x10 0.--23. 1. " RXUCHANNEL ,SPDIF receive U channel register contains next 3 U channel bytes" line.long 0x14 "SRQ,Qchannelrx Register" hexmask.long.tbyte 0x14 0.--23. 1. " RXQCHANNEL ,SPDIF receive Q channel register contains next 3 Q channel bytes" wgroup.long 0x2C++0x07 line.long 0x00 "STL,Spdiftxleft Register" hexmask.long.tbyte 0x00 0.--23. 1. " TXDATALEFT ,SPDIF transmit left channel data" line.long 0x04 "STR,Spdiftxright Register" hexmask.long.tbyte 0x04 0.--23. 1. " TXDATARIGHT ,SPDIF transmit right channel data" group.long 0x34++0x07 line.long 0x00 "STCSCH,Spdiftxcchannelcons_h Register" hexmask.long.tbyte 0x00 0.--23. 1. " TXCCHANNELCONS_H ,SPDIF transmit cons. C channel data contains first 24 bits without interpretation" line.long 0x04 "STCSCL,Spdiftxcchannelcons_l Register" hexmask.long.tbyte 0x04 0.--23. 1. " TXCCHANNELCONS_L ,SPDIF transmit cons. C channel data contains next 24 bits without interpretation" rgroup.long 0x44++0x03 line.long 0x00 "SRFM,Freqmeas Register" hexmask.long.tbyte 0x00 0.--23. 1. " FREQMEAS ,Frequency measurement data" sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) group.long 0x50++0x03 line.long 0x00 "STC,Spdiftxclk Register" hexmask.long.word 0x00 11.--19. 1. " SYSCLK_DF ,System clock divider factor" bitfld.long 0x00 8.--10. " TXCLK_SOURCE ,Tx clock source" "REF_CLK_32K input,Tx_clk input,ASRC_EXT_CLK input,SPDIF_EXT_CLK,ESAI_HCKT input,Ipg_clk input,MLB clock input,MLB PHY clock input" bitfld.long 0x00 7. " TX_ALL_CLK_EN ,SPDIF transfer clock enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " TXCLK_DF ,Divider factor" else group.long 0x50++0x03 line.long 0x00 "STC,Spdiftxclk Register" hexmask.long.word 0x00 11.--19. 1. " SYSCLK_DF ,System clock divider factor" bitfld.long 0x00 8.--10. " TXCLK_SOURCE ,Tx clock source" "REF_CLK_32K,Tx_clk,,SPDIF_EXT_CLK,,Ipg_clk,?..." bitfld.long 0x00 7. " TX_ALL_CLK_EN ,SPDIF transfer clock enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " TXCLK_DF ,Divider factor" endif width 0x0B tree.end tree "SPDIF2" base ad:0x308A0000 width 8. group.long 0x00++0x07 line.long 0x00 "SCR,SPDIF Configuration Register" bitfld.long 0x00 23. " RXFIFO_CTRL ,Rx FIFO control" "Normal,Always read zero" bitfld.long 0x00 22. " RXFIFO_OFF_ON ,SPDIF Rx FIFO on/off" "On,Off" newline bitfld.long 0x00 21. " RXFIFO_RST ,Rx FIFO reset" "Normal,Reset" bitfld.long 0x00 19.--20. " RXFIFOFULL_SEL ,Rx FIFO full interrupt select" "1,4,8,16" newline bitfld.long 0x00 18. " RXAUTOSYNC ,Rx auto sync off/on" "Off,On" bitfld.long 0x00 17. " TXAUTOSYNC ,Tx auto sync off/on" "Off,On" newline bitfld.long 0x00 15.--16. " TXFIFOEMPTY_SEL ,Tx FIFO empty interrupt select" "1,4,8,16" bitfld.long 0x00 13. " LOW_POWER ,SPDIF low-power mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SOFT_RESET ,SPDIF software reset" "No reset,Reset" bitfld.long 0x00 10.--11. " TXFIFO_CTRL ,Tx FIFO control" "Digital zero,Normal,Reset,?..." newline bitfld.long 0x00 9. " DMA_RX_EN ,DMA receive request enable" "Disabled,Enabled" bitfld.long 0x00 8. " DMA_TX_EN ,DMA transmit request enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " VALCTRL ,Outgoing validity set/clear control" "Set,Clear" bitfld.long 0x00 2.--4. " TXSEL ,Tx select" "Off,SPDIFIN,,,,Normal,?..." newline bitfld.long 0x00 0.--1. " USRC_SEL ,USRC select" "No embedded,SPDIF,,Chip transmitter" line.long 0x04 "SRCD,Cdtext Control Register" bitfld.long 0x04 1. " USYNCMODE ,U sync mode" "Non-CD,CD" newline width 13. sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) if (((per.l(ad:0x308A0000+0x08)&0x40)==0x40)) group.long 0x08++0x03 line.long 0x00 "SRPC,Phaseconfig Register" bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "Spdif_rxclk,Spdif_rxclk,Spdif_rxclk,Spdif_rxclk,Spdif_rxclk,REF_CLK_32K,Tx_clk,ASRC_CLK,SPDIF_EXT_CLK,ESAI_HCKT,Spdif_rxclk,Spdif_rxclk,MLB clock,MLB PHY clock,?..." rbitfld.long 0x00 6. " LOCK ,DPLL lock" "Unlocked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10),?..." else group.long 0x08++0x03 line.long 0x00 "SRPC,Phaseconfig Register" bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "REF_CLK_32K,Tx_clk,ASRC_EXT_CLK,SPDIF_EXT_CLK,ESAI_HCKT,REF_CLK_32K,Tx_clk,ASRC_CLK,SPDIF_EXT_CLK,ESAI_HCKT,MLB clock,MLB PHY clock,MLB clock,MLB PHY clock,?..." rbitfld.long 0x00 6. " LOCK ,DPLL lock" "Unlocked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10),?..." endif else if (((per.l(ad:0x308A0000+0x08)&0x40)==0x40)) group.long 0x08++0x03 line.long 0x00 "SRPC,Phaseconfig Register" bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "Spdif_rxclk,Spdif_rxclk,,Spdif_rxclk,,REF_CLK_32K,Tx_clk,,SPDIF_EXT_CLK,?..." rbitfld.long 0x00 6. " LOCK ,DPLL lock" "Unlocked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10),?..." else group.long 0x08++0x03 line.long 0x00 "SRPC,Phaseconfig Register" bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "REF_CLK_32K,Tx_clk,,SPDIF_EXT_CLK,,REF_CLK_32K,Tx_clk,,SPDIF_EXT_CLK,?..." rbitfld.long 0x00 6. " LOCK ,DPLL lock" "Unlocked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10),?..." endif endif group.long 0x0C++0x03 line.long 0x00 "SIE,Interrupten Register" bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " TXUNOV ,SPDIF Tx FIFO under/overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " TXRESYN ,SPDIF Tx FIFO resync interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " URXFUL ,U channel receive register full" "Not full,Full" newline bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " QRXFUL ,Q channel receive register full" "Not full,Full" bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RXFIFOUNOV ,Rx FIFO underrun/overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " RXFIFORESYN ,Rx FIFO resync interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " TXEM ,SPDIF Tx FIFO empty" "Not empty,Empty" bitfld.long 0x00 0. " RXFIFOFUL ,SPDIF Rx FIFO full" "Not full,Full" rgroup.long 0x10++0x03 line.long 0x00 "SIS,Interruptstat Register" bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 19. " TXUNOV ,SPDIF Tx FIFO under/overrun interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 18. " TXRESYN ,SPDIF Tx FIFO resync interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 10. " URXFUL ,U channel receive register full" "Not full,Full" newline bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 8. " QRXFUL ,Q channel receive register full" "Not full,Full" bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 4. " RXFIFOUNOV ,Rx FIFO underrun/overrun interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 3. " RXFIFORESYN ,Rx FIFO resync interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " TXEM ,SPDIF Tx FIFO empty" "Not empty,Empty" bitfld.long 0x00 0. " RXFIFOFUL ,SPDIF Rx FIFO full" "Not full,Full" wgroup.long 0x10++0x03 line.long 0x00 "SIC,Interruptclear Register" bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt clear" "No clear,Clear" bitfld.long 0x00 19. " TXUNOV ,SPDIF Tx FIFO under/overrun interrupt status" "No clear,Clear" bitfld.long 0x00 18. " TXRESYN ,SPDIF Tx FIFO resync interrupt status" "No clear,Clear" bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel interrupt status" "No clear,Clear" newline bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt status" "No clear,Clear" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt status" "No clear,Clear" bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt status" "No clear,Clear" bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt status" "No clear,Clear" newline bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt status" "No clear,Clear" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt status" "No clear,Clear" bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt status" "No clear,Clear" bitfld.long 0x00 4. " RXFIFOUNOV ,Rx FIFO underrun/overrun interrupt status" "No clear,Clear" newline bitfld.long 0x00 3. " RXFIFORESYN ,Rx FIFO resync interrupt status" "No clear,Clear" bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt status" "No clear,Clear" rgroup.long 0x14++0x17 line.long 0x00 "SRL,Spdifrxleft Register" hexmask.long.tbyte 0x00 0.--23. 1. " RXDATALEFT ,Processor receive SPDIF data left" line.long 0x04 "SRR,Spdifrxright Register" hexmask.long.tbyte 0x04 0.--23. 1. " RXDATARIGHT ,Processor receive SPDIF data right" line.long 0x08 "SRCSH,Spdifrxcchannel_h Register" hexmask.long.tbyte 0x08 0.--23. 1. " RXCCHANNEL_H ,SPDIF receive C channel register contains first 24 bits of C channel without interpretation" line.long 0x0C "SRCSL,Spdifrxcchannel_l Register" hexmask.long.tbyte 0x0C 0.--23. 1. " RXCCHANNEL_L ,SPDIF receive C channel register contains next 24 bits of C channel without interpretation" line.long 0x10 "SRU,Uchannelrx Register" hexmask.long.tbyte 0x10 0.--23. 1. " RXUCHANNEL ,SPDIF receive U channel register contains next 3 U channel bytes" line.long 0x14 "SRQ,Qchannelrx Register" hexmask.long.tbyte 0x14 0.--23. 1. " RXQCHANNEL ,SPDIF receive Q channel register contains next 3 Q channel bytes" wgroup.long 0x2C++0x07 line.long 0x00 "STL,Spdiftxleft Register" hexmask.long.tbyte 0x00 0.--23. 1. " TXDATALEFT ,SPDIF transmit left channel data" line.long 0x04 "STR,Spdiftxright Register" hexmask.long.tbyte 0x04 0.--23. 1. " TXDATARIGHT ,SPDIF transmit right channel data" group.long 0x34++0x07 line.long 0x00 "STCSCH,Spdiftxcchannelcons_h Register" hexmask.long.tbyte 0x00 0.--23. 1. " TXCCHANNELCONS_H ,SPDIF transmit cons. C channel data contains first 24 bits without interpretation" line.long 0x04 "STCSCL,Spdiftxcchannelcons_l Register" hexmask.long.tbyte 0x04 0.--23. 1. " TXCCHANNELCONS_L ,SPDIF transmit cons. C channel data contains next 24 bits without interpretation" rgroup.long 0x44++0x03 line.long 0x00 "SRFM,Freqmeas Register" hexmask.long.tbyte 0x00 0.--23. 1. " FREQMEAS ,Frequency measurement data" sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) group.long 0x50++0x03 line.long 0x00 "STC,Spdiftxclk Register" hexmask.long.word 0x00 11.--19. 1. " SYSCLK_DF ,System clock divider factor" bitfld.long 0x00 8.--10. " TXCLK_SOURCE ,Tx clock source" "REF_CLK_32K input,Tx_clk input,ASRC_EXT_CLK input,SPDIF_EXT_CLK,ESAI_HCKT input,Ipg_clk input,MLB clock input,MLB PHY clock input" bitfld.long 0x00 7. " TX_ALL_CLK_EN ,SPDIF transfer clock enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " TXCLK_DF ,Divider factor" else group.long 0x50++0x03 line.long 0x00 "STC,Spdiftxclk Register" hexmask.long.word 0x00 11.--19. 1. " SYSCLK_DF ,System clock divider factor" bitfld.long 0x00 8.--10. " TXCLK_SOURCE ,Tx clock source" "REF_CLK_32K,Tx_clk,,SPDIF_EXT_CLK,,Ipg_clk,?..." bitfld.long 0x00 7. " TX_ALL_CLK_EN ,SPDIF transfer clock enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " TXCLK_DF ,Divider factor" endif width 0x0B tree.end tree.end tree.open "SAI (Synchronous Audio Interface)" tree "SAI1" base ad:0x30010000 width 7. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 16.--19. " FRAME ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " FIFO ,FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DATALINE ,Number of datalines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x30010000+0x08)&0x80000000)==0x80000000))||(((per.l(ad:0x30010000+0x08)&0x40000)==0x00)) group.long 0x08++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" textline " " eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" textline " " rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" textline " " rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x0C++0x03 line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register" hexmask.long.byte 0x00 0.--6. 1. " TFW ,Transmit FIFO watermark" if (((per.l(ad:0x30010000+0x08)&0x80000000)==0x00)) group.long 0x10++0x03 line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x10++0x03 line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x14++0x03 line.long 0x00 "TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x00 31. " CFR[7] ,Channel 7 FIFO reset" "No effect,Reset" bitfld.long 0x00 30. " [6] ,Channel 6 FIFO reset" "No effect,Reset" bitfld.long 0x00 29. " [5] ,Channel 5 FIFO reset" "No effect,Reset" bitfld.long 0x00 28. " [4] ,Channel 4 FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 27. " [3] ,Channel 3 FIFO reset" "No effect,Reset" bitfld.long 0x00 26. " [2] ,Channel 2 FIFO reset" "No effect,Reset" bitfld.long 0x00 25. " [1] ,Channel 1 FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " [0] ,Channel 0 FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 23. " TCE[7] ,Transmit channel 7 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Transmit channel 6 enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Transmit channel 5 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Transmit channel 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Transmit channel 3 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Transmit channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Transmit channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Transmit channel 0 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x30010000+0x08)&0x80000000)==0x00)) group.long 0x18++0x07 line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 26.--27. " FCOMB ,FIFO combine mode" "Disabled,Enabled on FIFO reads,Enabled on FIFO writes,Enabled on FIFO reads/writes" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5. " CHMOD ,Channel mode" "TDM,Output" textline " " bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x18++0x07 line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 26.--27. " FCOMB ,FIFO combine mode" "Disabled,Enabled on FIFO reads,Enabled on FIFO writes,Enabled on FIFO reads/writes" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5. " CHMOD ,Channel mode" "TDM,Output" textline " " bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0x20++0x03 hide.long 0x00 "TDR0,SAI Transmit Data Register 0" in hgroup.long 0x24++0x03 hide.long 0x00 "TDR1,SAI Transmit Data Register 1" in hgroup.long 0x28++0x03 hide.long 0x00 "TDR2,SAI Transmit Data Register 2" in hgroup.long 0x2C++0x03 hide.long 0x00 "TDR3,SAI Transmit Data Register 3" in hgroup.long 0x30++0x03 hide.long 0x00 "TDR4,SAI Transmit Data Register 4" in hgroup.long 0x34++0x03 hide.long 0x00 "TDR5,SAI Transmit Data Register 5" in hgroup.long 0x38++0x03 hide.long 0x00 "TDR6,SAI Transmit Data Register 6" in hgroup.long 0x3C++0x03 hide.long 0x00 "TDR7,SAI Transmit Data Register 7" in rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0x44++0x03 line.long 0x00 "TFR1,SAI Transmit FIFO Register 1" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0x48++0x03 line.long 0x00 "TFR2,SAI Transmit FIFO Register 2" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0x4C++0x03 line.long 0x00 "TFR3,SAI Transmit FIFO Register 3" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0x50++0x03 line.long 0x00 "TFR4,SAI Transmit FIFO Register 4" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0x54++0x03 line.long 0x00 "TFR5,SAI Transmit FIFO Register 5" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0x58++0x03 line.long 0x00 "TFR6,SAI Transmit FIFO Register 6" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0x5C++0x03 line.long 0x00 "TFR7,SAI Transmit FIFO Register 7" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Unmasked,Masked" if (((per.l(ad:0x30010000+0x88)&0x80000000)==0x80000000))||(((per.l(ad:0x30010000+0x88)&0x40000)==0x00)) group.long 0x88++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" textline " " eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" textline " " rbitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x88++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" textline " " rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x8C++0x07 line.long 0x00 "RCR1,SAI Receive Configuration 1 Register" hexmask.long.byte 0x00 0.--6. 1. " RFW ,Receive FIFO watermark" if (((per.l(ad:0x30010000+0x88)&0x80000000)==0x00)) group.long 0x90++0x03 line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x90++0x03 line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x94++0x03 line.long 0x00 "RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x00 31. " CFR[7] ,Channel 7 FIFO reset" "No effect,Reset" bitfld.long 0x00 30. " [6] ,Channel 6 FIFO reset" "No effect,Reset" bitfld.long 0x00 29. " [5] ,Channel 5 FIFO reset" "No effect,Reset" bitfld.long 0x00 28. " [4] ,Channel 4 FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 27. " [3] ,Channel 3 FIFO reset" "No effect,Reset" bitfld.long 0x00 26. " [2] ,Channel 2 FIFO reset" "No effect,Reset" bitfld.long 0x00 25. " [1] ,Channel 1 FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " [0] ,Channel 0 FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 23. " RCE[7] ,Receive channel 7 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Receive channel 6 enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Receive channel 5 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Receive channel 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Receive channel 3 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Receive channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Receive channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Receive channel 0 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x30010000+0x88)&0x80000000)==0x00)) group.long 0x98++0x07 line.long 0x00 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 26.--27. " FCOMB ,FIFO combine mode" "Disabled,Enabled on FIFO reads,Enabled on FIFO writes,Enabled on FIFO reads/writes" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" textline " " bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x98++0x07 line.long 0x00 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 26.--27. " FCOMB ,FIFO combine mode" "Disabled,Enabled on FIFO reads,Enabled on FIFO writes,Enabled on FIFO reads/writes" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" textline " " bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,SAI Receive Data Register 0" in hgroup.long 0xA4++0x03 hide.long 0x00 "RDR1,SAI Receive Data Register 1" in hgroup.long 0xA8++0x03 hide.long 0x00 "RDR2,SAI Receive Data Register 2" in hgroup.long 0xAC++0x03 hide.long 0x00 "RDR3,SAI Receive Data Register 3" in hgroup.long 0xB0++0x03 hide.long 0x00 "RDR4,SAI Receive Data Register 4" in hgroup.long 0xB4++0x03 hide.long 0x00 "RDR5,SAI Receive Data Register 5" in hgroup.long 0xB8++0x03 hide.long 0x00 "RDR6,SAI Receive Data Register 6" in hgroup.long 0xBC++0x03 hide.long 0x00 "RDR7,SAI Receive Data Register 7" in rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO Register 0" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0xC4++0x03 line.long 0x00 "RFR1,SAI Receive FIFO Register 1" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0xC8++0x03 line.long 0x00 "RFR2,SAI Receive FIFO Register 2" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0xCC++0x03 line.long 0x00 "RFR3,SAI Receive FIFO Register 3" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0xD0++0x03 line.long 0x00 "RFR4,SAI Receive FIFO Register 4" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0xD4++0x03 line.long 0x00 "RFR5,SAI Receive FIFO Register 5" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0xD8++0x03 line.long 0x00 "RFR6,SAI Receive FIFO Register 6" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" rgroup.long 0xDC++0x03 line.long 0x00 "RFR7,SAI Receive FIFO Register 7" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM[31] ,Receive word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Receive word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Receive word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Receive word 28 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Receive word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Receive word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Receive word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Receive word 24 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Receive word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Receive word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Receive word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Receive word 20 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Receive word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Receive word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Receive word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Receive word 16 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Receive word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Receive word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Receive word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Receive word 12 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Receive word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Receive word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Receive word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Receive word 8 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Receive word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Receive word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Receive word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Receive word 4 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Receive word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Receive word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Receive word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Receive word 0 mask" "Unmasked,Masked" width 0x0B tree.end tree "SAI2" base ad:0x308B0000 width 7. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 16.--19. " FRAME ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " FIFO ,FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DATALINE ,Number of datalines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x308B0000+0x08)&0x80000000)==0x80000000))||(((per.l(ad:0x308B0000+0x08)&0x40000)==0x00)) group.long 0x08++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" textline " " eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" textline " " rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" textline " " rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x0C++0x03 line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register" hexmask.long.byte 0x00 0.--6. 1. " TFW ,Transmit FIFO watermark" if (((per.l(ad:0x308B0000+0x08)&0x80000000)==0x00)) group.long 0x10++0x03 line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x10++0x03 line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x14++0x03 line.long 0x00 "TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x00 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x308B0000+0x08)&0x80000000)==0x00)) group.long 0x18++0x07 line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5. " CHMOD ,Channel mode" "TDM,Output" textline " " bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x18++0x07 line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5. " CHMOD ,Channel mode" "TDM,Output" textline " " bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0x20++0x03 hide.long 0x00 "TDR0,SAI Transmit Data Register 0" in rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Unmasked,Masked" if (((per.l(ad:0x308B0000+0x88)&0x80000000)==0x80000000))||(((per.l(ad:0x308B0000+0x88)&0x40000)==0x00)) group.long 0x88++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" textline " " eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" textline " " rbitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x88++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" textline " " rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x8C++0x07 line.long 0x00 "RCR1,SAI Receive Configuration 1 Register" hexmask.long.byte 0x00 0.--6. 1. " RFW ,Receive FIFO watermark" if (((per.l(ad:0x308B0000+0x88)&0x80000000)==0x00)) group.long 0x90++0x03 line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x90++0x03 line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x94++0x03 line.long 0x00 "RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x00 16. " RCE ,Receive channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x308B0000+0x88)&0x80000000)==0x00)) group.long 0x98++0x07 line.long 0x00 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" textline " " bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x98++0x07 line.long 0x00 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" textline " " bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,SAI Receive Data Register 0" in rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO Register 0" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM[31] ,Receive word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Receive word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Receive word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Receive word 28 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Receive word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Receive word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Receive word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Receive word 24 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Receive word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Receive word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Receive word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Receive word 20 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Receive word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Receive word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Receive word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Receive word 16 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Receive word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Receive word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Receive word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Receive word 12 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Receive word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Receive word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Receive word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Receive word 8 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Receive word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Receive word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Receive word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Receive word 4 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Receive word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Receive word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Receive word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Receive word 0 mask" "Unmasked,Masked" width 0x0B tree.end tree "SAI3" base ad:0x308C0000 width 7. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 16.--19. " FRAME ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " FIFO ,FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DATALINE ,Number of datalines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x308C0000+0x08)&0x80000000)==0x80000000))||(((per.l(ad:0x308C0000+0x08)&0x40000)==0x00)) group.long 0x08++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" textline " " eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" textline " " rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" textline " " rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x0C++0x03 line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register" hexmask.long.byte 0x00 0.--6. 1. " TFW ,Transmit FIFO watermark" if (((per.l(ad:0x308C0000+0x08)&0x80000000)==0x00)) group.long 0x10++0x03 line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x10++0x03 line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x14++0x03 line.long 0x00 "TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x00 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x308C0000+0x08)&0x80000000)==0x00)) group.long 0x18++0x07 line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5. " CHMOD ,Channel mode" "TDM,Output" textline " " bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x18++0x07 line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5. " CHMOD ,Channel mode" "TDM,Output" textline " " bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0x20++0x03 hide.long 0x00 "TDR0,SAI Transmit Data Register 0" in rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Unmasked,Masked" if (((per.l(ad:0x308C0000+0x88)&0x80000000)==0x80000000))||(((per.l(ad:0x308C0000+0x88)&0x40000)==0x00)) group.long 0x88++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" textline " " eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" textline " " rbitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x88++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" textline " " rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x8C++0x07 line.long 0x00 "RCR1,SAI Receive Configuration 1 Register" hexmask.long.byte 0x00 0.--6. 1. " RFW ,Receive FIFO watermark" if (((per.l(ad:0x308C0000+0x88)&0x80000000)==0x00)) group.long 0x90++0x03 line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x90++0x03 line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x94++0x03 line.long 0x00 "RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x00 16. " RCE ,Receive channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x308C0000+0x88)&0x80000000)==0x00)) group.long 0x98++0x07 line.long 0x00 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" textline " " bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x98++0x07 line.long 0x00 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" textline " " bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,SAI Receive Data Register 0" in rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO Register 0" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM[31] ,Receive word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Receive word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Receive word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Receive word 28 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Receive word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Receive word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Receive word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Receive word 24 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Receive word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Receive word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Receive word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Receive word 20 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Receive word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Receive word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Receive word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Receive word 16 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Receive word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Receive word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Receive word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Receive word 12 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Receive word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Receive word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Receive word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Receive word 8 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Receive word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Receive word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Receive word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Receive word 4 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Receive word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Receive word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Receive word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Receive word 0 mask" "Unmasked,Masked" width 0x0B tree.end tree "SAI4" base ad:0x30050000 width 7. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 16.--19. " FRAME ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " FIFO ,FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DATALINE ,Number of datalines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x30050000+0x08)&0x80000000)==0x80000000))||(((per.l(ad:0x30050000+0x08)&0x40000)==0x00)) group.long 0x08++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" textline " " eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" textline " " rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" textline " " rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x0C++0x03 line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register" hexmask.long.byte 0x00 0.--6. 1. " TFW ,Transmit FIFO watermark" if (((per.l(ad:0x30050000+0x08)&0x80000000)==0x00)) group.long 0x10++0x03 line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x10++0x03 line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x14++0x03 line.long 0x00 "TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x00 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x30050000+0x08)&0x80000000)==0x00)) group.long 0x18++0x07 line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5. " CHMOD ,Channel mode" "TDM,Output" textline " " bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x18++0x07 line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5. " CHMOD ,Channel mode" "TDM,Output" textline " " bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0x20++0x03 hide.long 0x00 "TDR0,SAI Transmit Data Register 0" in rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Unmasked,Masked" if (((per.l(ad:0x30050000+0x88)&0x80000000)==0x80000000))||(((per.l(ad:0x30050000+0x88)&0x40000)==0x00)) group.long 0x88++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" textline " " eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" textline " " rbitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x88++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" textline " " rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x8C++0x07 line.long 0x00 "RCR1,SAI Receive Configuration 1 Register" hexmask.long.byte 0x00 0.--6. 1. " RFW ,Receive FIFO watermark" if (((per.l(ad:0x30050000+0x88)&0x80000000)==0x00)) group.long 0x90++0x03 line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x90++0x03 line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x94++0x03 line.long 0x00 "RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x00 16. " RCE ,Receive channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x30050000+0x88)&0x80000000)==0x00)) group.long 0x98++0x07 line.long 0x00 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" textline " " bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x98++0x07 line.long 0x00 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" textline " " bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,SAI Receive Data Register 0" in rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO Register 0" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM[31] ,Receive word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Receive word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Receive word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Receive word 28 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Receive word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Receive word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Receive word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Receive word 24 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Receive word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Receive word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Receive word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Receive word 20 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Receive word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Receive word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Receive word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Receive word 16 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Receive word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Receive word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Receive word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Receive word 12 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Receive word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Receive word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Receive word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Receive word 8 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Receive word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Receive word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Receive word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Receive word 4 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Receive word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Receive word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Receive word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Receive word 0 mask" "Unmasked,Masked" width 0x0B tree.end tree "SAI5" base ad:0x30040000 width 7. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 16.--19. " FRAME ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " FIFO ,FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DATALINE ,Number of datalines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x30040000+0x08)&0x80000000)==0x80000000))||(((per.l(ad:0x30040000+0x08)&0x40000)==0x00)) group.long 0x08++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" textline " " eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" textline " " rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" textline " " rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x0C++0x03 line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register" hexmask.long.byte 0x00 0.--6. 1. " TFW ,Transmit FIFO watermark" if (((per.l(ad:0x30040000+0x08)&0x80000000)==0x00)) group.long 0x10++0x03 line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x10++0x03 line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x14++0x03 line.long 0x00 "TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x00 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x30040000+0x08)&0x80000000)==0x00)) group.long 0x18++0x07 line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5. " CHMOD ,Channel mode" "TDM,Output" textline " " bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x18++0x07 line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5. " CHMOD ,Channel mode" "TDM,Output" textline " " bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0x20++0x03 hide.long 0x00 "TDR0,SAI Transmit Data Register 0" in rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Unmasked,Masked" if (((per.l(ad:0x30040000+0x88)&0x80000000)==0x80000000))||(((per.l(ad:0x30040000+0x88)&0x40000)==0x00)) group.long 0x88++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" textline " " eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" textline " " rbitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x88++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" textline " " rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x8C++0x07 line.long 0x00 "RCR1,SAI Receive Configuration 1 Register" hexmask.long.byte 0x00 0.--6. 1. " RFW ,Receive FIFO watermark" if (((per.l(ad:0x30040000+0x88)&0x80000000)==0x00)) group.long 0x90++0x03 line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x90++0x03 line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x94++0x03 line.long 0x00 "RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x00 16. " RCE ,Receive channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x30040000+0x88)&0x80000000)==0x00)) group.long 0x98++0x07 line.long 0x00 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" textline " " bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x98++0x07 line.long 0x00 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" textline " " bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,SAI Receive Data Register 0" in rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO Register 0" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM[31] ,Receive word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Receive word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Receive word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Receive word 28 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Receive word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Receive word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Receive word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Receive word 24 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Receive word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Receive word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Receive word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Receive word 20 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Receive word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Receive word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Receive word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Receive word 16 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Receive word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Receive word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Receive word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Receive word 12 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Receive word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Receive word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Receive word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Receive word 8 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Receive word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Receive word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Receive word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Receive word 4 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Receive word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Receive word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Receive word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Receive word 0 mask" "Unmasked,Masked" width 0x0B tree.end tree "SAI6" base ad:0x30030000 width 7. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 16.--19. " FRAME ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " FIFO ,FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DATALINE ,Number of datalines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x30030000+0x08)&0x80000000)==0x80000000))||(((per.l(ad:0x30030000+0x08)&0x40000)==0x00)) group.long 0x08++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" textline " " eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" textline " " rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" textline " " rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x0C++0x03 line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register" hexmask.long.byte 0x00 0.--6. 1. " TFW ,Transmit FIFO watermark" if (((per.l(ad:0x30030000+0x08)&0x80000000)==0x00)) group.long 0x10++0x03 line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x10++0x03 line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x14++0x03 line.long 0x00 "TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x00 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x30030000+0x08)&0x80000000)==0x00)) group.long 0x18++0x07 line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5. " CHMOD ,Channel mode" "TDM,Output" textline " " bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x18++0x07 line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5. " CHMOD ,Channel mode" "TDM,Output" textline " " bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0x20++0x03 hide.long 0x00 "TDR0,SAI Transmit Data Register 0" in rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Unmasked,Masked" if (((per.l(ad:0x30030000+0x88)&0x80000000)==0x80000000))||(((per.l(ad:0x30030000+0x88)&0x40000)==0x00)) group.long 0x88++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" textline " " eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" textline " " rbitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x88++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" textline " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" textline " " rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x8C++0x07 line.long 0x00 "RCR1,SAI Receive Configuration 1 Register" hexmask.long.byte 0x00 0.--6. 1. " RFW ,Receive FIFO watermark" if (((per.l(ad:0x30030000+0x88)&0x80000000)==0x00)) group.long 0x90++0x03 line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x90++0x03 line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x94++0x03 line.long 0x00 "RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x00 16. " RCE ,Receive channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x30030000+0x88)&0x80000000)==0x00)) group.long 0x98++0x07 line.long 0x00 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" textline " " bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x98++0x07 line.long 0x00 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" textline " " bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,SAI Receive Data Register 0" in rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO Register 0" hexmask.long.byte 0x00 16.--23. 1. " WFP ,Write FIFO pointer" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 0.--7. 1. " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM[31] ,Receive word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Receive word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Receive word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Receive word 28 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Receive word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Receive word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Receive word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Receive word 24 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Receive word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Receive word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Receive word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Receive word 20 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Receive word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Receive word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Receive word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Receive word 16 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Receive word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Receive word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Receive word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Receive word 12 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Receive word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Receive word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Receive word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Receive word 8 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Receive word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Receive word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Receive word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Receive word 4 mask" "Unmasked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Receive word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Receive word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Receive word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Receive word 0 mask" "Unmasked,Masked" width 0x0B tree.end tree.end tree.end tree.open "VPU (Video Processing Unit)" tree "VPU_G1" base ad:0x38300000 width 14. if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x00)) group.long 0x04++0x03 line.long 0x00 "SWREG1,Interrupt Register Decoder" bitfld.long 0x00 24. " SW_DEC_PIC_INF ,B slice detected" "Not detected,Detected" bitfld.long 0x00 18. " SW_DEC_TIMEOUT ,Interrupt status bit decoder timeout" "No timeout,Timeout" bitfld.long 0x00 16. " SW_DEC_ERROR_INT ,Interrupt status bit input stream error" "No error,Error" textline " " bitfld.long 0x00 15. " SW_DEC_ASO_INT ,Interrupt status bit ASO (Arbitrary Slice Ordering) detected" "No interrupt,Interrupt" bitfld.long 0x00 14. " SW_DEC_BUFFER_INT ,Interrupt status bit input buffer empty" "No interrupt,Interrupt" bitfld.long 0x00 13. " SW_DEC_BUS_INT ,Interrupt status bit bus" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " SW_DEC_RDY_INT ,Interrupt status bit decoder" "No interrupt,Interrupt" bitfld.long 0x00 8. " SW_DEC_IRQ ,Decoder IRQ" "No interrupt,Interrupt" bitfld.long 0x00 5. " SW_DEC_ABORT_E ,Abort decoding enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SW_DEC_IRQ_DIS ,Decoder IRQ disable" "No,Yes" bitfld.long 0x00 0. " SW_DEC_E ,Decoder enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x10000000)) if (((per.l(ad:0x38300000+0x0C)&0x2000000)==0x2000000)) group.long 0x04++0x03 line.long 0x00 "SWREG1,Interrupt Register Decoder" bitfld.long 0x00 18. " SW_DEC_TIMEOUT ,Interrupt status bit decoder timeout" "No timeout,Timeout" bitfld.long 0x00 16. " SW_DEC_ERROR_INT ,Interrupt status bit input stream error" "No error,Error" bitfld.long 0x00 14. " SW_DEC_BUFFER_INT ,Interrupt status bit input buffer empty" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " SW_DEC_BUS_INT ,Interrupt status bit bus" "No interrupt,Interrupt" bitfld.long 0x00 12. " SW_DEC_RDY_INT ,Interrupt status bit decoder" "No interrupt,Interrupt" bitfld.long 0x00 8. " SW_DEC_IRQ ,Decoder IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " SW_DEC_ABORT_E ,Abort decoding enable" "Disabled,Enabled" bitfld.long 0x00 4. " SW_DEC_IRQ_DIS ,Decoder IRQ disable" "No,Yes" bitfld.long 0x00 0. " SW_DEC_E ,Decoder enable" "Disabled,Enabled" else group.long 0x04++0x03 line.long 0x00 "SWREG1,Interrupt Register Decoder" bitfld.long 0x00 18. " SW_DEC_TIMEOUT ,Interrupt status bit decoder timeout" "No timeout,Timeout" bitfld.long 0x00 16. " SW_DEC_ERROR_INT ,Interrupt status bit input stream error" "No error,Error" bitfld.long 0x00 14. " SW_DEC_BUFFER_INT ,Interrupt status bit input buffer empty" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " SW_DEC_BUS_INT ,Interrupt status bit bus" "No interrupt,Interrupt" bitfld.long 0x00 12. " SW_DEC_RDY_INT ,Interrupt status bit decoder" "No interrupt,Interrupt" bitfld.long 0x00 8. " SW_DEC_IRQ ,Decoder IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " SW_DEC_ABORT_E ,Abort decoding enable" "Disabled,Enabled" bitfld.long 0x00 4. " SW_DEC_IRQ_DIS ,Decoder IRQ disable" "No,Yes" bitfld.long 0x00 0. " SW_DEC_E ,Decoder enable" "Disabled,Enabled" endif elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0xA0000000)) group.long 0x04++0x03 line.long 0x00 "SWREG1,Interrupt Register Decoder" bitfld.long 0x00 18. " SW_DEC_TIMEOUT ,Interrupt status bit decoder timeout" "No timeout,Timeout" bitfld.long 0x00 17. " SW_DEC_SLICE_INT ,Interrupt status bit dec_slice_decoded" "No interrupt,Interrupt" bitfld.long 0x00 16. " SW_DEC_ERROR_INT ,Interrupt status bit input stream error" "No error,Error" textline " " bitfld.long 0x00 15. " SW_DEC_ASO_INT ,Error detected in residual data" "No error,Error" bitfld.long 0x00 14. " SW_DEC_BUFFER_INT ,Interrupt status bit input buffer empty" "No interrupt,Interrupt" bitfld.long 0x00 13. " SW_DEC_BUS_INT ,Interrupt status bit bus" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " SW_DEC_RDY_INT ,Interrupt status bit decoder" "No interrupt,Interrupt" bitfld.long 0x00 8. " SW_DEC_IRQ ,Decoder IRQ" "No interrupt,Interrupt" bitfld.long 0x00 5. " SW_DEC_ABORT_E ,Abort decoding enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SW_DEC_IRQ_DIS ,Decoder IRQ disable" "No,Yes" bitfld.long 0x00 0. " SW_DEC_E ,Decoder enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x30000000)) group.long 0x04++0x03 line.long 0x00 "SWREG1,Interrupt Register Decoder" bitfld.long 0x00 18. " SW_DEC_TIMEOUT ,Interrupt status bit decoder timeout" "No timeout,Timeout" bitfld.long 0x00 17. " SW_DEC_SLICE_INT ,Interrupt status bit dec_slice_decoded" "No interrupt,Interrupt" bitfld.long 0x00 16. " SW_DEC_ERROR_INT ,Interrupt status bit input stream error" "No error,Error" textline " " bitfld.long 0x00 14. " SW_DEC_BUFFER_INT ,Interrupt status bit input buffer empty" "No interrupt,Interrupt" bitfld.long 0x00 13. " SW_DEC_BUS_INT ,Interrupt status bit bus" "No interrupt,Interrupt" bitfld.long 0x00 12. " SW_DEC_RDY_INT ,Interrupt status bit decoder" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " SW_DEC_IRQ ,Decoder IRQ" "No interrupt,Interrupt" bitfld.long 0x00 5. " SW_DEC_ABORT_E ,Abort decoding enable" "Disabled,Enabled" bitfld.long 0x00 4. " SW_DEC_IRQ_DIS ,Decoder IRQ disable" "No,Yes" textline " " bitfld.long 0x00 0. " SW_DEC_E ,Decoder enable" "Disabled,Enabled" else group.long 0x04++0x03 line.long 0x00 "SWREG1,Interrupt Register Decoder" bitfld.long 0x00 18. " SW_DEC_TIMEOUT ,Interrupt status bit decoder timeout" "No timeout,Timeout" bitfld.long 0x00 16. " SW_DEC_ERROR_INT ,Interrupt status bit input stream error" "No error,Error" bitfld.long 0x00 14. " SW_DEC_BUFFER_INT ,Interrupt status bit input buffer empty" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " SW_DEC_BUS_INT ,Interrupt status bit bus" "No interrupt,Interrupt" bitfld.long 0x00 12. " SW_DEC_RDY_INT ,Interrupt status bit decoder" "No interrupt,Interrupt" bitfld.long 0x00 8. " SW_DEC_IRQ ,Decoder IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " SW_DEC_ABORT_E ,Abort decoding enable" "Disabled,Enabled" bitfld.long 0x00 4. " SW_DEC_IRQ_DIS ,Decoder IRQ disable" "No,Yes" bitfld.long 0x00 0. " SW_DEC_E ,Decoder enable" "Disabled,Enabled" endif textline " " group.long 0x08++0x03 line.long 0x00 "SWREG2,Device Configuration Register Decoder" hexmask.long.byte 0x00 24.--31. 1. " SW_DEC_AXI_RD_ID ,Read ID used for decoder reading services in AXI bus (if connected to AXI)" bitfld.long 0x00 23. " SW_DEC_TIMEOUT_E ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SW_DEC_STRSWAP32_E ,Decoder input 32bit data swap for stream data" "Not swapped,Swapped" bitfld.long 0x00 21. " SW_DEC_STRENDIAN_E ,Decoder input endian mode for stream data" "Big endian,Little endian" textline " " bitfld.long 0x00 20. " SW_DEC_INSWAP32_E ,Decoder input 32bit data swap for other than stream data" "Not swapped,Swapped" bitfld.long 0x00 19. " SW_DEC_OUTSWAP32_E ,Decoder output 32bit data swap" "Not swapped,Swapped" textline " " bitfld.long 0x00 18. " SW_DEC_DATA_DISC_E ,Data discard enable" "Disabled,Enabled" bitfld.long 0x00 17. " SW_TILED_MODE_MSB ,Tiled mode MSB enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11.--16. " SW_DEC_LATENCY ,Decoder master interface additional latency" "No latency,Min 8 cycles of IDLE between services,Min 16 cycles of IDLE between services,Min 24 cycles of IDLE between services,Min 32 cycles of IDLE between services,Min 40 cycles of IDLE between services,Min 48 cycles of IDLE between services,Min 56 cycles of IDLE between services,Min 64 cycles of IDLE between services,Min 72 cycles of IDLE between services,Min 80 cycles of IDLE between services,Min 88 cycles of IDLE between services,Min 96 cycles of IDLE between services,Min 104 cycles of IDLE between services,Min 112 cycles of IDLE between services,Min 120 cycles of IDLE between services,Min 128 cycles of IDLE between services,Min 136 cycles of IDLE between services,Min 144 cycles of IDLE between services,Min 152 cycles of IDLE between services,Min 160 cycles of IDLE between services,Min 168 cycles of IDLE between services,Min 176 cycles of IDLE between services,Min 184 cycles of IDLE between services,Min 192 cycles of IDLE between services,Min 200 cycles of IDLE between services,Min 208 cycles of IDLE between services,Min 216 cycles of IDLE between services,Min 224 cycles of IDLE between services,Min 232 cycles of IDLE between services,Min 240 cycles of IDLE between services,Min 248 cycles of IDLE between services,Min 256 cycles of IDLE between services,Min 264 cycles of IDLE between services,Min 272 cycles of IDLE between services,Min 280 cycles of IDLE between services,Min 288 cycles of IDLE between services,Min 296 cycles of IDLE between services,Min 304 cycles of IDLE between services,Min 312 cycles of IDLE between services,Min 320 cycles of IDLE between services,Min 328 cycles of IDLE between services,Min 336 cycles of IDLE between services,Min 344 cycles of IDLE between services,Min 352 cycles of IDLE between services,Min 360 cycles of IDLE between services,Min 368 cycles of IDLE between services,Min 376 cycles of IDLE between services,Min 384 cycles of IDLE between services,Min 392 cycles of IDLE between services,Min 400 cycles of IDLE between services,Min 408 cycles of IDLE between services,Min 416 cycles of IDLE between services,Min 424 cycles of IDLE between services,Min 432 cycles of IDLE between services,Min 440 cycles of IDLE between services,Min 448 cycles of IDLE between services,Min 456 cycles of IDLE between services,Min 464 cycles of IDLE between services,Min 472 cycles of IDLE between services,Min 480 cycles of IDLE between services,Min 488 cycles of IDLE between services,Min 496 cycles of IDLE between services,Min 504 cycles of IDLE between services" bitfld.long 0x00 10. " SW_DEC_CLK_GATE_E ,Decoder dynamic clock gating enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " SW_DEC_IN_ENDIAN ,Decoder input endian mode for other than stream data" "Big endian,Little endian" bitfld.long 0x00 8. " SW_DEC_OUT_ENDIAN ,Decoder output endian mode" "Big endian,Little endian" textline " " bitfld.long 0x00 7. " SW_TILED_MODE_LSB ,Tiled mode LSB enable" "Disabled,Enabled" bitfld.long 0x00 6. " SW_DEC_ADV_PRE_DIS ,Advanced PREFETCH mode disable" "No,Yes" textline " " bitfld.long 0x00 5. " SW_DEC_SCMD_DIS ,AXI single command multiple data disable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " SW_DEC_MAX_BURST ,Maximum burst length for decoder bus transactions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x10000000)) if (((per.l(ad:0x38300000+0xE4)&0x800000)==0x800000)) if (((per.l(ad:0x38300000+0x0C)&0x400000)==0x400000)) group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 27. " SW_RLC_MODE_E ,RLC mode enable" "Disabled,Enabled" bitfld.long 0x00 26. " SW_SKIP_MODE ,Skip mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SW_DIVX3_E ,DIVX3 enable" "Disabled,Enabled" bitfld.long 0x00 24. " SW_PJPEG_E ,Progressive JPEG enable" "Disabled,Enabled" bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" textline " " bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" bitfld.long 0x00 21. " SW_PIC_B_E ,B picture enable for current picture" "I||P,BI||B" bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" textline " " bitfld.long 0x00 19. " SW_PIC_TOPFIELD_E ,Fields being decoded" "Bottom,Top" bitfld.long 0x00 18. " SW_FWD_INTERLACE_E ,Coding mode of forward reference picture" "Progressive,Interlaced" bitfld.long 0x00 17. " SW_SORENSON_E ,Sorenson SPARC enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SW_REF_TOPFIELD_E ,Field used as reference" "Bottom,Top" bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" textline " " bitfld.long 0x00 12. " SW_WEBP_ES_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" bitfld.long 0x00 11. " SW_REFTOPFIRST_E ,FWD reference field first decoded" "Bottom,Top" bitfld.long 0x00 10. " SW_SEQ_MBAFF_E ,Sequence includes MBAFF coded pictures" "Not included,Included" textline " " bitfld.long 0x00 9. " SW_PICORD_COUNT_E ,Picture order count table read enable" "Disabled,Enabled" bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" else group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 27. " SW_RLC_MODE_E ,RLC mode enable" "Disabled,Enabled" bitfld.long 0x00 26. " SW_SKIP_MODE ,Skip mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SW_DIVX3_E ,DIVX3 enable" "Disabled,Enabled" bitfld.long 0x00 24. " SW_PJPEG_E ,Progressive JPEG enable" "Disabled,Enabled" bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" textline " " bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" bitfld.long 0x00 21. " SW_PIC_B_E ,B picture enable for current picture" "I||P,BI||B" bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" textline " " bitfld.long 0x00 18. " SW_FWD_INTERLACE_E ,Coding mode of forward reference picture" "Progressive,Interlaced" bitfld.long 0x00 17. " SW_SORENSON_E ,Sorenson SPARC enable" "Disabled,Enabled" bitfld.long 0x00 16. " SW_REF_TOPFIELD_E ,Field used as reference" "Bottom,Top" textline " " bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" bitfld.long 0x00 12. " SW_WEBP_ES_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" textline " " bitfld.long 0x00 11. " SW_REFTOPFIRST_E ,FWD reference field first decoded" "Bottom,Top" bitfld.long 0x00 10. " SW_SEQ_MBAFF_E ,Sequence includes MBAFF coded pictures" "Not included,Included" bitfld.long 0x00 9. " SW_PICORD_COUNT_E ,Picture order count table read enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" endif else if (((per.l(ad:0x38300000+0x0C)&0x400000)==0x400000)) group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 27. " SW_RLC_MODE_E ,RLC mode enable" "Disabled,Enabled" bitfld.long 0x00 25. " SW_DIVX3_E ,DIVX3 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " SW_PJPEG_E ,Progressive JPEG enable" "Disabled,Enabled" bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" textline " " bitfld.long 0x00 21. " SW_PIC_B_E ,B picture enable for current picture" "I||P,BI||B" bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" bitfld.long 0x00 19. " SW_PIC_TOPFIELD_E ,Fields being decoded" "Bottom,Top" textline " " bitfld.long 0x00 18. " SW_FWD_INTERLACE_E ,Coding mode of forward reference picture" "Progressive,Interlaced" bitfld.long 0x00 17. " SW_SORENSON_E ,Sorenson SPARC enable" "Disabled,Enabled" bitfld.long 0x00 16. " SW_REF_TOPFIELD_E ,Field used as reference" "Bottom,Top" textline " " bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" bitfld.long 0x00 12. " SW_WEBP_ES_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" textline " " bitfld.long 0x00 11. " SW_REFTOPFIRST_E ,FWD reference field first decoded" "Bottom,Top" bitfld.long 0x00 10. " SW_SEQ_MBAFF_E ,Sequence includes MBAFF coded pictures" "Not included,Included" bitfld.long 0x00 9. " SW_PICORD_COUNT_E ,Picture order count table read enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" else group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 27. " SW_RLC_MODE_E ,RLC mode enable" "Disabled,Enabled" bitfld.long 0x00 25. " SW_DIVX3_E ,DIVX3 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " SW_PJPEG_E ,Progressive JPEG enable" "Disabled,Enabled" bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" textline " " bitfld.long 0x00 21. " SW_PIC_B_E ,B picture enable for current picture" "I||P,BI||B" bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" bitfld.long 0x00 18. " SW_FWD_INTERLACE_E ,Coding mode of forward reference picture" "Progressive,Interlaced" textline " " bitfld.long 0x00 17. " SW_SORENSON_E ,Sorenson SPARC enable" "Disabled,Enabled" bitfld.long 0x00 16. " SW_REF_TOPFIELD_E ,Field used as reference" "Bottom,Top" bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" textline " " bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" bitfld.long 0x00 12. " SW_WEBP_ES_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" bitfld.long 0x00 11. " SW_REFTOPFIRST_E ,FWD reference field first decoded" "Bottom,Top" textline " " bitfld.long 0x00 10. " SW_SEQ_MBAFF_E ,Sequence includes MBAFF coded pictures" "Not included,Included" bitfld.long 0x00 9. " SW_PICORD_COUNT_E ,Picture order count table read enable" "Disabled,Enabled" bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" endif endif elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 26. " SW_SKIP_MODE ,Skip mode enable" "Disabled,Enabled" bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" textline " " bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" bitfld.long 0x00 13. " SW_WEBP_E ,Webp enable" "Disabled,Enabled" bitfld.long 0x00 12. " SW_WEBP_ES_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" textline " " bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x00)) if (((per.l(ad:0x38300000+0x0C)&0x400000)==0x400000)) group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 27. " SW_RLC_MODE_E ,RLC mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" textline " " bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" bitfld.long 0x00 19. " SW_PIC_TOPFIELD_E ,Fields being decoded" "Bottom,Top" bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" textline " " bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" bitfld.long 0x00 13. " SW_MVC_E ,Multi view coding enable" "Disabled,Enabled" bitfld.long 0x00 12. " SW_WRITE_MVS_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" textline " " bitfld.long 0x00 10. " SW_SEQ_MBAFF_E ,Sequence includes MBAFF coded pictures" "Not included,Included" bitfld.long 0x00 9. " SW_PICORD_COUNT_E ,Picture order count table read enable" "Disabled,Enabled" bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" else group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 27. " SW_RLC_MODE_E ,RLC mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" textline " " bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" textline " " bitfld.long 0x00 13. " SW_MVC_E ,Multi view coding enable" "Disabled,Enabled" bitfld.long 0x00 12. " SW_WRITE_MVS_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" bitfld.long 0x00 10. " SW_SEQ_MBAFF_E ,Sequence includes MBAFF coded pictures" "Not included,Included" textline " " bitfld.long 0x00 9. " SW_PICORD_COUNT_E ,Picture order count table read enable" "Disabled,Enabled" bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" endif elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x20000000)) if (((per.l(ad:0x38300000+0x0C)&0x400000)==0x400000)) group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 27. " SW_RLC_MODE_E ,RLC mode enable" "Disabled,Enabled" bitfld.long 0x00 26. " SW_SKIP_MODE ,Skip mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SW_DIVX3_E ,DIVX3 enable" "Disabled,Enabled" bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" textline " " bitfld.long 0x00 21. " SW_PIC_B_E ,B picture enable for current picture" "I||P,BI||B" bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" bitfld.long 0x00 19. " SW_PIC_TOPFIELD_E ,Fields being decoded" "Bottom,Top" textline " " bitfld.long 0x00 18. " SW_FWD_INTERLACE_E ,Coding mode of forward reference picture" "Progressive,Interlaced" bitfld.long 0x00 17. " SW_SORENSON_E ,Sorenson SPARC enable" "Disabled,Enabled" bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" textline " " bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" bitfld.long 0x00 12. " SW_WRITE_MVS_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" else group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 27. " SW_RLC_MODE_E ,RLC mode enable" "Disabled,Enabled" bitfld.long 0x00 26. " SW_SKIP_MODE ,Skip mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SW_DIVX3_E ,DIVX3 enable" "Disabled,Enabled" bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" textline " " bitfld.long 0x00 21. " SW_PIC_B_E ,B picture enable for current picture" "I||P,BI||B" bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" bitfld.long 0x00 18. " SW_FWD_INTERLACE_E ,Coding mode of forward reference picture" "Progressive,Interlaced" textline " " bitfld.long 0x00 17. " SW_SORENSON_E ,Sorenson SPARC enable" "Disabled,Enabled" bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" textline " " bitfld.long 0x00 12. " SW_WRITE_MVS_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" endif elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x30000000)) group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 24. " SW_PJPEG_E ,Progressive JPEG enable" "Disabled,Enabled" bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" textline " " bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x40000000)) if (((per.l(ad:0x38300000+0x0C)&0x400000)==0x400000)) group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" textline " " bitfld.long 0x00 21. " SW_PIC_B_E ,B picture enable for current picture" "I||P,BI||B" bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" bitfld.long 0x00 19. " SW_PIC_TOPFIELD_E ,Fields being decoded" "Bottom,Top" textline " " bitfld.long 0x00 18. " SW_FWD_INTERLACE_E ,Coding mode of forward reference picture" "Progressive,Interlaced" bitfld.long 0x00 16. " SW_REF_TOPFIELD_E ,Field used as reference" "Bottom,Top" bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" textline " " bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" bitfld.long 0x00 13. " SW_PIC_FIXED_QUANT ,Quantization parameter fix" "Not fixed,Fixed" bitfld.long 0x00 12. " SW_WRITE_MVS_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" textline " " bitfld.long 0x00 11. " SW_REFTOPFIRST_E ,FWD reference field first decoded" "Bottom,Top" bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" else group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" textline " " bitfld.long 0x00 21. " SW_PIC_B_E ,B picture enable for current picture" "I||P,BI||B" bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" bitfld.long 0x00 18. " SW_FWD_INTERLACE_E ,Coding mode of forward reference picture" "Progressive,Interlaced" textline " " bitfld.long 0x00 16. " SW_REF_TOPFIELD_E ,Field used as reference" "Bottom,Top" bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" textline " " bitfld.long 0x00 13. " SW_PIC_FIXED_QUANT ,Quantization parameter fix" "Not fixed,Fixed" bitfld.long 0x00 12. " SW_WRITE_MVS_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" bitfld.long 0x00 11. " SW_REFTOPFIRST_E ,FWD reference field first decoded" "Bottom,Top" textline " " bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" endif elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x50000000||0x60000000))) if (((per.l(ad:0x38300000+0x0C)&0x400000)==0x400000)) group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" textline " " bitfld.long 0x00 21. " SW_PIC_B_E ,B picture enable for current picture" "I||P,BI||B" bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" bitfld.long 0x00 19. " SW_PIC_TOPFIELD_E ,Fields being decoded" "Bottom,Top" textline " " bitfld.long 0x00 18. " SW_FWD_INTERLACE_E ,Coding mode of forward reference picture" "Progressive,Interlaced" bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" textline " " bitfld.long 0x00 12. " SW_WRITE_MVS_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" else group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" textline " " bitfld.long 0x00 21. " SW_PIC_B_E ,B picture enable for current picture" "I||P,BI||B" bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" bitfld.long 0x00 18. " SW_FWD_INTERLACE_E ,Coding mode of forward reference picture" "Progressive,Interlaced" textline " " bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" bitfld.long 0x00 12. " SW_WRITE_MVS_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" textline " " bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" endif elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x70000000)) group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" textline " " bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" bitfld.long 0x00 12. " SW_WRITE_MVS_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x80000000)) group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" bitfld.long 0x00 21. " SW_PIC_B_E ,B picture enable for current picture" "I||P,BI||B" textline " " bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" bitfld.long 0x00 12. " SW_WRITE_MVS_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" textline " " bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0xB0000000)) if (((per.l(ad:0x38300000+0x0C)&0x400000)==0x400000)) group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 26. " SW_SKIP_MODE ,Skip mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" textline " " bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" bitfld.long 0x00 21. " SW_PIC_B_E ,B picture enable for current picture" "I||P,BI||B" bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" textline " " bitfld.long 0x00 19. " SW_PIC_TOPFIELD_E ,Fields being decoded" "Bottom,Top" bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" textline " " bitfld.long 0x00 13. " SW_PIC_FIXED_QUANT ,Quantization parameter fix" "Not fixed,Fixed" bitfld.long 0x00 12. " SW_WRITE_MVS_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" else group.long 0x0C++0x03 line.long 0x00 "SWREG3,Decoder Control Register 0" bitfld.long 0x00 28.--31. " SW_DEC_MODE ,Decoding mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG-2,MPEG-1,VP6,RV,VP7,VP8,AVS,?..." bitfld.long 0x00 26. " SW_SKIP_MODE ,Skip mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " SW_PIC_INTERLACE_E ,Coding mode of the current picture" "Progressive,Interlaced" textline " " bitfld.long 0x00 22. " SW_PIC_FIELDMODE_E ,Structure of the current picture" "Frame,Field" bitfld.long 0x00 21. " SW_PIC_B_E ,B picture enable for current picture" "I||P,BI||B" bitfld.long 0x00 20. " SW_PIC_INTER_E ,Picture type" "Iter type (P),Intra type (I)" textline " " bitfld.long 0x00 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" bitfld.long 0x00 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" bitfld.long 0x00 13. " SW_PIC_FIXED_QUANT ,Quantization parameter fix" "Not fixed,Fixed" textline " " bitfld.long 0x00 12. " SW_WRITE_MVS_E ,Direct mode motion vector write enable for current picture" "Disable,Enabled" bitfld.long 0x00 8. " SW_DEC_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_AXI_WR_ID ,ID used for decoder writing services in AXI bus" endif endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x00)) group.long 0x10++0x03 line.long 0x00 "SWREG4,Decoder Control Register 1" hexmask.long.word 0x00 23.--31. 1. " SW_PIC_MB_WIDTH ,Picture width in macro blocks" hexmask.long.byte 0x00 11.--18. 1. " SW_PIC_MB_HEIGHT_P ,Picture height in macro blocks" bitfld.long 0x00 0.--4. " SW_REF_FRAMES ,Maximum number of short and long term reference frames in decoded picture buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x20000000)) group.long 0x10++0x03 line.long 0x00 "SWREG4,Decoder Control Register 1" hexmask.long.word 0x00 23.--31. 1. " SW_PIC_MB_WIDTH ,Picture width in macro blocks" hexmask.long.byte 0x00 11.--18. 1. " SW_PIC_MB_HEIGHT_P ,Picture height in macro blocks" bitfld.long 0x00 6. " SW_ALT_SCAN_E ,Enable alternative vertical scan method for interlaced frames" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--4. " SW_REF_FRAMES ,Maximum number of short and long term reference frames in decoded picture buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x30000000||0x70000000||0x80000000||0x90000000||0xA0000000||0xB0000000))) group.long 0x10++0x03 line.long 0x00 "SWREG4,Decoder Control Register 1" hexmask.long.word 0x00 23.--31. 1. " SW_PIC_MB_WIDTH ,Picture width in macro blocks" hexmask.long.byte 0x00 11.--18. 1. " SW_PIC_MB_HEIGHT_P ,Picture height in macro blocks" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x40000000)) group.long 0x10++0x03 line.long 0x00 "SWREG4,Decoder Control Register 1" hexmask.long.word 0x00 23.--31. 1. " SW_PIC_MB_WIDTH ,Picture width in macro blocks" bitfld.long 0x00 19.--22. " SW_MB_WIDTH_OFF ,The amount of meaningful horizontal pixels in last MB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 11.--18. 1. " SW_PIC_MB_HEIGHT_P ,Picture height in macro blocks" textline " " bitfld.long 0x00 7.--10. " SW_MB_HEIGHT_OFF ,The amount of meaningful vertical pixels in last MB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " SW_REF_FRAMES ,Num_ref semantics" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x50000000||0x60000000))) group.long 0x10++0x03 line.long 0x00 "SWREG4,Decoder Control Register 1" hexmask.long.word 0x00 23.--31. 1. " SW_PIC_MB_WIDTH ,Picture width in macro blocks" hexmask.long.byte 0x00 11.--18. 1. " SW_PIC_MB_HEIGHT_P ,Picture height in macro blocks" bitfld.long 0x00 6. " SW_ALT_SCAN_E ,Enable alternative vertical scan method for interlaced frames" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "SWREG4,Decoder Control Register 1" hexmask.long.word 0x00 23.--31. 1. " SW_PIC_MB_WIDTH ,Picture width in macro blocks" bitfld.long 0x00 19.--22. " SW_MB_WIDTH_OFF ,The amount of meaningful horizontal pixels in last MB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 11.--18. 1. " SW_PIC_MB_HEIGHT_P ,Picture height in macro blocks" textline " " bitfld.long 0x00 7.--10. " SW_MB_HEIGHT_OFF ,The amount of meaningful vertical pixels in last MB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " SW_ALT_SCAN_E ,Enable alternative vertical scan method for interlaced frames" "Disabled,Enabled" bitfld.long 0x00 0.--4. " SW_REF_FRAMES ,Num_ref semantics" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x00)) group.long 0x14++0x03 line.long 0x00 "SWREG5,Decoder Control Register 2" bitfld.long 0x00 26.--31. " SW_STRM_START_BIT ,Stream start word where decoding can be started" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24. " SW_TYPE1_QUANT_E ,Scaling matrix enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " SW_CH_QP_OFFSET ,Chroma Qp filter offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 14.--18. " SW_CH_QP_OFFSET2 ,Chroma Qp filter offset for cr type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " SW_FIELDPIC_FLAG_E ,Flag for stream that field_pic_flag exists in stream" "Not occurred,Occurred" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x20000000)) group.long 0x14++0x03 line.long 0x00 "SWREG5,Decoder Control Register 2" bitfld.long 0x00 26.--31. " SW_STRM_START_BIT ,Stream start word where decoding can be started" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 25. " SW_SYNC_MARKER_E ,Sync markers enable" "Disabled,Enabled" bitfld.long 0x00 24. " SW_TYPE1_QUANT_E ,Scaling matrix enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19.--23. " SW_CH_QP_OFFSET ,Chroma Qp filter offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x30000000)) group.long 0x14++0x03 line.long 0x00 "SWREG5,Decoder Control Register 2" bitfld.long 0x00 26.--31. " SW_STRM_START_BIT ,Stream start word where decoding can be started" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 25. " SW_SYNC_MARKER_E ,Sync markers enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x40000000)) group.long 0x14++0x03 line.long 0x00 "SWREG5,Decoder Control Register 2" bitfld.long 0x00 26.--31. " SW_STRM_START_BIT ,Stream start word where decoding can be started" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 25. " SW_SYNC_MARKER_E ,Sync markers enable" "Disabled,Enabled" bitfld.long 0x00 24. " SW_DQ_PROFILE ,SW DQ profile" "0,1" textline " " bitfld.long 0x00 23. " SW_DQBI_LEVEL ,SW DQBI level" "0,1" bitfld.long 0x00 22. " SW_RANGE_RED_FRM_E ,SW range red FRM enable" "Disabled,Enabled" bitfld.long 0x00 20. " SW_FAST_UVMC_E ,SW fast UVMC enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " SW_TRANSDCTAB ,SW TRANSDCTAB" "0,1" bitfld.long 0x00 15.--16. " SW_TRANSACFRM ,SW TRANSACFRM" "0,1,2,3" bitfld.long 0x00 13.--14. " SW_TRANSACFRM2 ,SW TRANSACFRM2" "0,1,2,3" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x50000000||0x60000000))) group.long 0x14++0x03 line.long 0x00 "SWREG5,Decoder Control Register 2" bitfld.long 0x00 26.--31. " SW_STRM_START_BIT ,Stream start word where decoding can be started" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24. " SW_QSCALE_TYPE ,SW QSCALE type" "0,1" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x70000000)) group.long 0x14++0x03 line.long 0x00 "SWREG5,Decoder Control Register 2" bitfld.long 0x00 26.--31. " SW_STRM_START_BIT ,Stream start word where decoding can be started" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " SW_STRM1_START_BIT ,SW STRM1 start bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 17. " SW_HUFFMAN_E ,SW HUFFMAN enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SW_MULTISTREAM_E ,SW multi-stream enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x80000000||0xB0000000))) group.long 0x14++0x03 line.long 0x00 "SWREG5,Decoder Control Register 2" bitfld.long 0x00 26.--31. " SW_STRM_START_BIT ,Stream start word where decoding can be started" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0x14++0x03 line.long 0x00 "SWREG5,Decoder Control Register 2" bitfld.long 0x00 26.--31. " SW_STRM_START_BIT ,Stream start word where decoding can be started" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " SW_STRM1_START_BIT ,SW STRM1 start bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x10000000)) group.long 0x14++0x03 line.long 0x00 "SWREG5,Decoder Control Register 2" bitfld.long 0x00 26.--31. " SW_STRM_START_BIT ,Stream start word where decoding can be started" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 25. " SW_SYNC_MARKER_E ,Sync markers enable" "Disabled,Enabled" bitfld.long 0x00 24. " SW_TYPE1_QUANT_E ,Type 1 quantization enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19.--23. " SW_CH_QP_OFFSET ,Chroma Qp filter offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--18. " SW_CH_QP_OFFSET2 ,Chroma Qp filter offset for cr type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " SW_FIELDPIC_FLAG_E ,Flag for stream that field_pic_flag exists in stream" "Not occurred,Occurred" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) if (((per.l(ad:0x38300000+0x08)&0x20080)!=0x00)) group.long 0x18++0x03 line.long 0x00 "SWREG6,Decoder Control Register 3" bitfld.long 0x00 31. " SW_START_CODE_E ,Stream start code existence" "Start codes not contained,Start codes contained" bitfld.long 0x00 25.--30. " SW_INIT_QP ,Initial value for quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.tbyte 0x00 0.--23. 1. " SW_STREAM_LEN ,Amount of stream data bytes in input buffer" else group.long 0x18++0x03 line.long 0x00 "SWREG6,Decoder Control Register 3" bitfld.long 0x00 31. " SW_START_CODE_E ,Stream start code existence" "Start codes not contained,Start codes contained" bitfld.long 0x00 25.--30. " SW_INIT_QP ,Initial value for quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24. " SW_CH_8PIX_ILEAV_E ,Additional chrominance data format writing where decoder writes chrominance in group of 8 pixels of Cb and then corresponding 8 pixels of Cr" "Disabled,Enabled" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " SW_STREAM_LEN ,Amount of stream data bytes in input buffer" endif elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x20000000||0x40000000))) group.long 0x18++0x03 line.long 0x00 "SWREG6,Decoder Control Register 3" bitfld.long 0x00 31. " SW_START_CODE_E ,Stream start code existence" "Start codes not contained,Start codes contained" bitfld.long 0x00 25.--30. " SW_INIT_QP ,Initial value for quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.tbyte 0x00 0.--23. 1. " SW_STREAM_LEN ,Amount of stream data bytes in input buffer" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x30000000||0x80000000))) group.long 0x18++0x03 line.long 0x00 "SWREG6,Decoder Control Register 3" hexmask.long.tbyte 0x00 0.--23. 1. " SW_STREAM_LEN ,Amount of stream data bytes in input buffer" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x50000000||0x60000000||0x70000000||0xB0000000))) group.long 0x18++0x03 line.long 0x00 "SWREG6,Decoder Control Register 3" bitfld.long 0x00 25.--30. " SW_INIT_QP ,Initial value for quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.tbyte 0x00 0.--23. 1. " SW_STREAM_LEN ,Amount of stream data bytes in input buffer" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0x18++0x03 line.long 0x00 "SWREG6,Decoder Control Register 3" hexmask.long.byte 0x00 24.--31. 1. " SW_STREAM_LEN_EXT ,SW_STREAM_LEN_EXT" hexmask.long.tbyte 0x00 0.--23. 1. " SW_STREAM_LEN ,Amount of stream data bytes in input buffer" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0x1C++0x03 line.long 0x00 "SWREG7,Decoder Control Register 4" bitfld.long 0x00 31. " SW_CABAC_E ,CABAC enable" "Disabled,Enabled" bitfld.long 0x00 30. " SW_BLACKWHITE_E ,Sampling format" "4:2:0,4:0:0" bitfld.long 0x00 29. " SW_DIR_8X8_INFER_E ,Method to use to derive luma motion vectors in B_skip, B_Direct_16x16 and B_direct_8x8_inference_flag" "0,1" textline " " bitfld.long 0x00 28. " SW_WEIGHT_PRED_E ,Weighted prediction enable for P slices" "Disabled,Enabled" bitfld.long 0x00 26.--27. " SW_WEIGHT_BIPR_IDC ,Weighted prediction specification for B slices" "Default,Explicit,Implicit,?..." bitfld.long 0x00 25. " SW_AVS_H264_H_EXT ,Resolution extension to support 4k resolution for AVS/H264" "Not supported,Supported" textline " " bitfld.long 0x00 16.--20. " SW_FRAMENUM_LEN ,Bit length of frame_num in data stream RV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. " SW_FRAMENUM ,Current frame number" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x40000000)) group.long 0x1C++0x03 line.long 0x00 "SWREG7,Decoder Control Register 4" bitfld.long 0x00 31. " SW_BITPLANE0_E ,SW BITPLANE0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " SW_BITPLANE1_E ,SW BITPLANE1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SW_BITPLANE2_E ,SW BITPLANE2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SW_TTMBF ,SW TTMBF" "0,1" bitfld.long 0x00 14.--18. " SW_PQINDEX ,SW PQINDEX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 13. " SW_VC1_HEIGHT_EXT ,SW VC1 height EXT" "0,1" textline " " bitfld.long 0x00 12. " SW_BILIN_MC_E ,SW BILIN MC enable" "Disabled,Enabled" bitfld.long 0x00 11. " SW_UNIQP_E ,SW UNIQP enable" "Disabled,Enabled" bitfld.long 0x00 10. " SW_HALFQP_E ,SW HALFQP enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " SW_TTFRM ,SW TTFRM" "0,1,2,3" bitfld.long 0x00 7. " SW_2ND_BYTE_EMUL_E ,SW 2ND byte EMUL enable" "Disabled,Enabled" bitfld.long 0x00 6. " SW_DQUANT_E ,SW DQUANT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SW_VC1_ADV_E ,SW VC1 ADV enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x70000000)) group.long 0x1C++0x03 line.long 0x00 "SWREG7,Decoder Control Register 4" bitfld.long 0x00 12. " SW_BILIN_MC_E ,SW BILIN MC enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x80000000)) group.long 0x1C++0x03 line.long 0x00 "SWREG7,Decoder Control Register 4" bitfld.long 0x00 16.--20. " SW_FRAMENUM_LEN ,SW FRAMENUM LEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0x1C++0x03 line.long 0x00 "SWREG7,Decoder Control Register 4" bitfld.long 0x00 26.--31. " SW_DCT1_START_BIT ,SW DCT1 start bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--25. " SW_DCT2_START_BIT ,SW DCT2 start bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13. " SW_CH_MV_RES ,SW CH MV RES" "0,1" textline " " bitfld.long 0x00 12. " SW_BILIN_MC_E ,SW BILIN MC enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " SW_INIT_DC_MATCH0 ,SW INIT DC MATCH0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " SW_INIT_DC_MATCH1 ,SW INIT DC MATCH1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 5. " SW_VP7_VERSION ,SW VP7 version" "0,1" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0xB0000000)) group.long 0x1C++0x03 line.long 0x00 "SWREG7,Decoder Control Register 4" bitfld.long 0x00 25. " SW_AVS_H264_H_EXT ,SW AVS H264 H EXT" "0,1" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0x20++0x03 line.long 0x00 "SWREG8,Decoder Control Register 5" bitfld.long 0x00 31. " SW_CONST_INTRA_E ,Constrained intra prediction flag" "Not occurred,Occurred" bitfld.long 0x00 30. " SW_FILT_CTRL_PRES ,Extra variables controlling characteristics of the deblocking filter present in the slice header" "Not present,Present" bitfld.long 0x00 29. " SW_RDPIC_CNT_PRES ,Redundant_pic_cnt syntax elements present in the slice header" "Not present,Present" textline " " bitfld.long 0x00 28. " SW_8X8TRANS_FLAG_E ,8x8 transform flag enable for stream decoding" "Disabled,Enabled" hexmask.long.word 0x00 17.--27. 1. " SW_REFPIC_MK_LEN ,Length of decoded reference picture marking bits" bitfld.long 0x00 16. " SW_IDR_PIC_E ,IDR (instantaneous decoding refresh) picture flag" "Not occurred,Occurred" textline " " hexmask.long.word 0x00 0.--15. 1. " SW_IDR_PIC_ID ,IDR (instantaneous decoding refresh) picture" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x20000000)) group.long 0x20++0x03 line.long 0x00 "SWREG8,Decoder Control Register 5" bitfld.long 0x00 8. " SW_DIVX_IDCT_E ,SW DIVX IDCT enable" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SW_DIVX3_SLICE_SIZE ,SW DIVX3 slice size" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x40000000)) group.long 0x20++0x03 line.long 0x00 "SWREG8,Decoder Control Register 5" hexmask.long.byte 0x00 24.--31. 1. " SW_MV_SCALEFACTOR ,SW MV SCALEFACTOR" bitfld.long 0x00 19.--23. " SW_REF_DIST_FWD ,SW REF DIST FWD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--18. " SW_REF_DIST_BWD ,SW REF DIST BWD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x70000000)) group.long 0x20++0x03 line.long 0x00 "SWREG8,Decoder Control Register 5" bitfld.long 0x00 14.--17. " SW_LOOP_FILT_LIMIT ,SW loop FILT limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " SW_VARIANCE_TEST_E ,SW variance test enable" "0,1" bitfld.long 0x00 10.--12. " SW_MV_THRESHOLD ,SW MV threshold" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " SW_VAR_THRESHOLD ,SW VAR threshold" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x80000000)) group.long 0x20++0x03 line.long 0x00 "SWREG8,Decoder Control Register 5" bitfld.long 0x00 30.--31. " SW_RV_PROFILE ,SW RV profile" "0,1,2,3" bitfld.long 0x00 28.--29. " SW_RV_OSV_QUANT ,SW RV OSV QUANT" "0,1,2,3" hexmask.long.word 0x00 14.--27. 1. " SW_RV_FWD_SCALE ,SW RV FWD scale" hexmask.long.word 0x00 0.--13. 1. " SW_RV_BWD_SCALE ,SW RV BWD scale" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0x20++0x03 line.long 0x00 "SWREG8,Decoder Control Register 5" hexmask.long.word 0x00 16.--31. 1. " SW_INIT_DC_COMP0 ,SW INIT DC COMP0" hexmask.long.word 0x00 0.--15. 1. " SW_INIT_DC_COMP1 ,SW INIT DC COMP1" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0x24++0x03 line.long 0x00 "SWREG9,Decoder Control Register 6" hexmask.long.byte 0x00 24.--31. 1. " SW_PPS_ID ,Picture parameter set that is referred to in the slice header" bitfld.long 0x00 19.--23. " SW_REFIDX1_ACTIVE ,Maximum reference index that can be used while decoding inter predicted macro blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--18. " SW_REFIDX0_ACTIVE ,Maximum reference index that can be used while decoding inter predicted macro blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x00 0.--7. 1. " SW_POC_LENGTH ,Length of picture order count field in stream" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x20000000)) group.long 0x24++0x03 line.long 0x00 "SWREG9,Decoder Control Register 6" hexmask.long 0x00 2.--31. 1. " SW_MB_CTRL_BASE ,SW MB CTRL base" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x40000000)) group.long 0x24++0x03 line.long 0x00 "SWREG9,Decoder Control Register 6" bitfld.long 0x00 24. " SW_ICOMP0_E ,SW ICOMP0 enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " SW_ISCALE0 ,SW ISCALE0" hexmask.long.word 0x00 0.--15. 1. " SWISHIFT0 ,SWISHIFT0" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x70000000)) group.long 0x24++0x03 line.long 0x00 "SWREG9,Decoder Control Register 6" hexmask.long.tbyte 0x00 0.--23. 1. " SW_STREAM1_LEN ,SW STREAM1 LEN" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x80000000)) group.long 0x24++0x03 line.long 0x00 "SWREG9,Decoder Control Register 6" hexmask.long.word 0x00 0.--12. 1. " SW_PIC_SLICE_AM ,SW PIC slice AM" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0x24++0x03 line.long 0x00 "SWREG9,Decoder Control Register 6" hexmask.long 0x00 2.--31. 1. " SW_MB_CTRL_BASE ,SW MB CTRL base" bitfld.long 0x00 24.--27. " SW_COEFFS_PART_AM ,SW COEFFS PART AM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x00)) if (((per.l(ad:0x38300000+0x0C)&0x8000000)==0x00)) group.long 0x28++0x03 line.long 0x00 "SWREG10,H264 P Initial Fwd Ref Pic List Register (4-9)" hexmask.long 0x00 2.--31. 1. " SW_DIFF_MV_BASE ,SW_DIFF_MV_BASE" bitfld.long 0x00 25.--29. " SW_PINIT_RLIST_F9 ,Initial reference picture list for P forward picid 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " SW_PINIT_RLIST_F8 ,Initial reference picture list for P forward picid 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 15.--19. " SW_PINIT_RLIST_F7 ,Initial reference picture list for P forward picid 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " SW_PINIT_RLIST_F6 ,Initial reference picture list for P forward picid 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SW_PINIT_RLIST_F5 ,Initial reference picture list for P forward picid 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " SW_PINIT_RLIST_F4 ,Initial reference picture list for P forward picid 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x28++0x03 line.long 0x00 "SWREG10,Base Address For Differential Motion Vector Base Address" hexmask.long 0x00 2.--31. 1. " SW_DIFF_MV_BASE ,SW_DIFF_MV_BASE" bitfld.long 0x00 25.--29. " SW_PINIT_RLIST_F9 ,Initial reference picture list for P forward picid 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " SW_PINIT_RLIST_F8 ,Initial reference picture list for P forward picid 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 15.--19. " SW_PINIT_RLIST_F7 ,Initial reference picture list for P forward picid 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " SW_PINIT_RLIST_F6 ,Initial reference picture list for P forward picid 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SW_PINIT_RLIST_F5 ,Initial reference picture list for P forward picid 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " SW_PINIT_RLIST_F4 ,Initial reference picture list for P forward picid 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x20000000)) if (((per.l(ad:0x38300000+0x0C)&0x8000000)==0x00)) group.long 0x28++0x03 line.long 0x00 "SWREG10,SWREG10" hexmask.long 0x00 2.--31. 0x04 " SW_DIFF_MV_BASE ,SW DIFF MV base" else group.long 0x28++0x03 line.long 0x00 "SWREG10,Base Address For Differential Motion Vector Base Address" hexmask.long 0x00 2.--31. 0x04 " SW_DIFF_MV_BASE ,SW DIFF MV base" endif elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x40000000)) group.long 0x28++0x03 line.long 0x00 "SWREG10,VC-1 Intensity Control 1" bitfld.long 0x00 24. " SW_ICOMP1_E ,SW ICOMP1 enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " SW_ISCALE1 ,SW ISCALE1" hexmask.long.word 0x00 0.--15. 1. " SW_ISHIFT1 ,SW ISHIFT1" elif (((per.l(ad:0x38300000+0x0C)&0xF8000000)==(0x90000000||0xA0000000))) group.long 0x28++0x03 line.long 0x00 "SWREG10,VP7 And VP8 Segmentation Base Register" hexmask.long 0x00 2.--31. 0x04 " SW_SEGMENT_BASE ,SW segment base" bitfld.long 0x00 1. " SW_SEGMENT_UPD_E ,SW segment UPD enable" "Disabled,Enabled" bitfld.long 0x00 0. " SW_SEGMENT_E ,SW segment enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x10000000)) group.long 0x28++0x03 line.long 0x00 "SWREG10,SWREG10" bitfld.long 0x00 25.--29. " SW_PINIT_RLIST_F9 ,Initial reference picture list for P forward picid 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " SW_PINIT_RLIST_F8 ,Initial reference picture list for P forward picid 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " SW_PINIT_RLIST_F7 ,Initial reference picture list for P forward picid 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 10.--14. " SW_PINIT_RLIST_F6 ,Initial reference picture list for P forward picid 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SW_PINIT_RLIST_F5 ,Initial reference picture list for P forward picid 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " SW_PINIT_RLIT_F4 ,Initial reference picture list for P forward picid 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if (((per.l(ad:0x38300000+0x0C)&0xF8000000)==0x00)) if (((per.l(ad:0x38300000+0x0C)&0x8000000)==0x8000000)) group.long 0x2C++0x03 line.long 0x00 "SWREG11,H264 P Initial Fwd Ref Pic List Register (10-15)" hexmask.long 0x00 2.--31. 1. " SW_I4X4_OR_DC_BASE ,SW_I4X4_OR_DC_BASE" bitfld.long 0x00 25.--29. " SW_PINIT_RLIST_F15 ,Initial reference picture list for P forward picid 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " SW_PINIT_RLIST_F14 ,Initial reference picture list for P forward picid 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 15.--19. " SW_PINIT_RLIST_F13 ,Initial reference picture list for P forward picid 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " SW_PINIT_RLIST_F12 ,Initial reference picture list for P forward picid 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SW_PINIT_RLIST_F11 ,Initial reference picture list for P forward picid 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " SW_PINIT_RLIST_F10 ,Initial reference picture list for P forward picid 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x2C++0x03 line.long 0x00 "SWREG11,Decoder Control Register 7" hexmask.long 0x00 2.--31. 1. " SW_I4X4_OR_DC_BASE ,SW_I4X4_OR_DC_BASE" bitfld.long 0x00 25.--29. " SW_PINIT_RLIST_F15 ,Initial reference picture list for P forward picid 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " SW_PINIT_RLIST_F14 ,Initial reference picture list for P forward picid 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 15.--19. " SW_PINIT_RLIST_F13 ,Initial reference picture list for P forward picid 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " SW_PINIT_RLIST_F12 ,Initial reference picture list for P forward picid 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SW_PINIT_RLIST_F11 ,Initial reference picture list for P forward picid 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " SW_PINIT_RLIST_F10 ,Initial reference picture list for P forward picid 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x20000000)) if (((per.l(ad:0x38300000+0x0C)&0x8000000)==0x8000000)) group.long 0x2C++0x03 line.long 0x00 "SWREG11,SWREG11" hexmask.long 0x00 2.--31. 0x04 " SW_I4X4_OR_DC_BASE ,SW I4X4 or DC base" else group.long 0x2C++0x03 line.long 0x00 "SWREG11,Decoder Control Register 7" hexmask.long 0x00 2.--31. 0x04 " SW_I4X4_OR_DC_BASE ,SW I4X4 or DC base" endif elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x40000000)) group.long 0x2C++0x03 line.long 0x00 "SWREG11,VC-1 Intensity Control 2" bitfld.long 0x00 24. " SW_ICOMP2_E ,SW ICOMP2 enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " SW_ISCALE2 ,SW ISCALE2" hexmask.long.word 0x00 0.--15. 1. " SW_ISHIFT2 ,SW ISHIFT2" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0x2C++0x03 line.long 0x00 "SWREG11,VC-1 Intensity Control 2" bitfld.long 0x00 24.--29. " SW_DCT3_START_BIT ,SW DCT3 start bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " SW_DCT4_START_BIT ,SW DCT4 start bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " SW_DCT5_START_BIT ,SW DCT5 start bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6.--11. " SW_DCT6_START_BIT ,SW DCT6 start bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " SW_DCT7_START_BIT ,SW DCT7 start bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x10000000)) group.long 0x2C++0x03 line.long 0x00 "SWREG11,SWREG11" hexmask.long 0x00 2.--31. 1. " SW_I4X4_OR_DC_BASE ,SW I4X4 or DC base" bitfld.long 0x00 25.--29. " SW_PINIT_RLIST_F15 ,Initial reference picture list for P forward picid 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " SW_PINIT_RLIST_F14 ,Initial reference picture list for P forward picid 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 15.--19. " SW_PINIT_RLIST_F13 ,Initial reference picture list for P forward picid 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " SW_PINIT_RLIST_F12 ,Initial reference picture list for P forward picid 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SW_PINIT_RLIST_F11 ,Initial reference picture list for P forward picid 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " SW_PINIT_RLIST_F10 ,Initial reference picture list for P forward picid 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x20000000))) if (((per.l(ad:0x38300000+0x0C)&0x8000000)==0x8000000)) group.long 0x30++0x03 line.long 0x00 "SWREG12,Base Address For RLC Data" else group.long 0x30++0x03 line.long 0x00 "SWREG12,Stream Start Address/End Address" endif else group.long 0x30++0x03 line.long 0x00 "SWREG12,Stream Start Address/End Address" endif textline " " if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000||0x20000000||0x30000000||0x40000000||0xB0000000))) group.long 0x34++0x03 line.long 0x00 "SWREG13,Base Address For Decoded Picture / Base Address For JPEG Decoder Output Luminance Picture" hexmask.long 0x00 2.--31. 0x04 " SW_DEC_OUT_BASE ,Base address for (decoder output picture/output luminance picture)" bitfld.long 0x00 1. " SW_DPB_ILACE_MODE ,DPB ilaced mode" "Ilaced/progressive frames,Progressive frames/Separate fields" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x50000000||0x60000000||0x70000000||0x80000000||0x90000000||0xA0000000))) group.long 0x34++0x03 line.long 0x00 "SWREG13,Base Address For Decoded Picture / Base Address For JPEG Decoder Output Luminance Picture" hexmask.long 0x00 2.--31. 0x04 " SW_DEC_OUT_BASE ,Base address for (decoder output picture/output luminance picture)" endif textline " " if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000||0xB0000000))) group.long 0x38++0x03 line.long 0x00 "SWREG14,Base Address For Reference Picture Index 0 / Base Address For JPEG Decoder Output Chrominance Picture" hexmask.long 0x00 2.--31. 0x04 " SW_REFER0_BASE ,Base address for reference picture index 0" bitfld.long 0x00 1. " SW_REFER0_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x00 0. " SW_REFER0_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x20000000||0x40000000||0x50000000||0x60000000||0x70000000||0x80000000))) group.long 0x38++0x03 line.long 0x00 "SWREG14,Base Address For Reference Picture Index 0 / Base Address For JPEG Decoder Output Chrominance Picture" hexmask.long 0x00 2.--31. 0x04 " SW_REFER0_BASE ,Base address for reference picture index 0" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x30000000||0x90000000||0xA0000000))) group.long 0x38++0x03 line.long 0x00 "SWREG14,Base Address For Reference Picture Index 0 / Base Address For JPEG Decoder Output Chrominance Picture" hexmask.long 0x00 2.--31. 0x04 " SW_JPG_CH_OUT_BASE ,SW JPG CH out base" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000||0xB0000000))) group.long 0x3C++0x03 line.long 0x00 "SWREG15,Base Address For Reference Picture Index 1 / JPEG Control" hexmask.long 0x00 2.--31. 0x04 " SW_REFER1_BASE ,Base address for reference picture index 1" bitfld.long 0x00 1. " SW_REFER1_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x00 0. " SW_REFER1_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x20000000||0x40000000||0x50000000||0x60000000))) group.long 0x3C++0x03 line.long 0x00 "SWREG15,Base Address For Reference Picture Index 1 / JPEG Control" hexmask.long 0x00 2.--31. 0x04 " SW_REFER1_BASE ,Base address for reference picture index 1" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x30000000)) group.long 0x3C++0x03 line.long 0x00 "SWREG15,Base Address For Reference Picture Index 1 / JPEG Control" hexmask.long.byte 0x00 0.--7. 1. " SW_JPEG_SLICE_H ,SW JPEG slice H" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0x3C++0x03 line.long 0x00 "SWREG15,Base Address For Reference Picture Index 1 / JPEG Control" hexmask.long 0x00 2.--31. 0x04 " SW_REFER1_BASE ,Base address for reference picture index 1" hexmask.long.byte 0x00 0.--7. 1. " SW_JPEG_SLICE_H ,SW JPEG slice H" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000||0xB0000000))) group.long 0x40++0x07 line.long 0x00 "SWREG16,Base Address For Reference Picture Index 2 / List Of VLC Code Lengths In First JPEG AC Table" hexmask.long 0x00 2.--31. 0x04 " SW_REFER2_BASE ,Base address for reference picture index 2" bitfld.long 0x00 1. " SW_REFER2_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x00 0. " SW_REFER2_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" line.long 0x04 "SWREG17,Base Address For Reference Picture Index 3 / List Of VLC Code lengths In First JPEG AC Table" hexmask.long 0x04 2.--31. 0x04 " SW_REFER3_BASE ,Base address for reference picture index 3" bitfld.long 0x04 1. " SW_REFER3_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x04 0. " SW_REFER3_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x20000000||0x40000000||0x50000000||0x60000000))) group.long 0x40++0x07 line.long 0x00 "SWREG16,Base Address For Reference Picture Index 2 / List Of VLC Code Lengths In First JPEG AC Table" hexmask.long 0x00 2.--31. 0x04 " SW_REFER2_BASE ,Base address for reference picture index 2" line.long 0x04 "SWREG17,Base Address For Reference Picture Index 3 / List Of VLC Code lengths In First JPEG AC Table" hexmask.long 0x04 2.--31. 0x04 " SW_REFER3_BASE ,Base address for reference picture index 3" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x30000000)) group.long 0x40++0x07 line.long 0x00 "SWREG16,Base Address For Reference Picture Index 2 / List Of VLC Code Lengths In First JPEG AC Table" hexmask.long.byte 0x00 24.--30. 1. " SW_AC1_CODE6_CNT ,SW AC1 CODE6 CNT" bitfld.long 0x00 16.--21. " SW_AC1_CODE5_CNT ,SW AC1 CODE5 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11.--15. " SW_AC1_CODE4_CNT ,SW AC1 CODE4 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7.--10. " SW_AC1_CODE3_CNT ,SW AC1 CODE3 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3.--5. " SW_AC1_CODE2_CNT ,SW AC1 CODE2 CNT" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " SW_AC1_CODE1_CNT ,SW AC1 CODE1 CNT" "0,1,2,3" line.long 0x04 "SWREG17,Base Address For Reference Picture Index 3 / List Of VLC Code lengths In First JPEG AC Table" hexmask.long.byte 0x04 24.--30. 1. " SW_AC1_CODE10_CNT ,SW AC1 CODE10 CNT" hexmask.long.byte 0x04 16.--23. 1. " SW_AC1_CODE9_CNT ,SW AC1 CODE9 CNT" hexmask.long.byte 0x04 8.--15. 1. " SW_AC1_CODE8_CNT ,SW AC1 CODE8 CNT" textline " " hexmask.long.byte 0x04 0.--7. 1. " SW_AC1_CODE7_CNT ,SW AC1 CODE7 CNT" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0x48++0x03 line.long 0x00 "SWREG18,Base Address For Reference Picture Index 4" hexmask.long 0x00 2.--31. 0x04 " SW_REFER4_BASE ,Base address for reference picture index 4" bitfld.long 0x00 1. " SW_REFER4_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x00 0. " SW_REFER4_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x20000000)) group.long 0x48++0x03 line.long 0x00 "SWREG18,Base Address For Reference Picture Index 4" bitfld.long 0x00 19. " SW_ALT_SCAN_FLAG_E ,SW ALT scan flag enable" "Disabled,Enabled" bitfld.long 0x00 15.--18. " SW_FCODE_FWD_HOR ,SW FCODE FWD HOR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--10. " SW_FCODE_BWD_HOR ,SW FCODE BWD HOR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 2. " SW_MV_ACCURACY_FWD ,SW MV accuracy FWD" "0,1" bitfld.long 0x00 1. " SW_MPEG4_VC1_RC ,SW MPEG4 VC1 RC" "0,1" bitfld.long 0x00 0. " SW_PREV_ANC_TYPE ,SW PREV ANC type" "0,1" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x30000000)) group.long 0x48++0x03 line.long 0x00 "SWREG18,Base Address For Reference Picture Index 4" hexmask.long.byte 0x00 24.--31. 1. " SW_AC1_CODE14_CNT ,SW AC1 CODE14 CNT" hexmask.long.byte 0x00 16.--23. 1. " SW_AC1_CODE13_CNT ,SW AC1 CODE13 CNT" hexmask.long.byte 0x00 8.--15. 1. " SW_AC1_CODE12_CNT ,SW AC1 CODE12 CNT" textline " " hexmask.long.byte 0x00 0.--7. 1. " SW_AC1_CODE11_CNT ,SW AC1 CODE11 CNT" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x40000000)) group.long 0x48++0x03 line.long 0x00 "SWREG18,Base Address For Reference Picture Index 4" hexmask.long.word 0x00 16.--31. 1. " SW_PIC_HEADER_LEN ,SW PIC header length" bitfld.long 0x00 13. " SW_PIC_4MV_E ,SW PIC 4MV enable" "Disabled,Enabled" bitfld.long 0x00 11. " SW_RANGE_RED_REF_E ,SW range red REF enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9.--10. " SW_VC1_DIFMV_RANGE ,SW VC1 DIFMV range" "0,1,2,3" bitfld.long 0x00 6.--7. " SW_MV_RANGE ,SW MV range" "0,1,2,3" bitfld.long 0x00 5. " SW_OVERLAP_E ,SW overlap enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3.--4. " SW_OVERLAP_METHOD ,SW overlap method" "0,1,2,3" bitfld.long 0x00 2. " SW_MV_ACCURACY_FWD ,SW overlap enable" "Disabled,Enabled" bitfld.long 0x00 1. " SW_MPEG4_VC1_RC ,SW MPEG4 VC1 RC" "0,1" textline " " bitfld.long 0x00 0. " SW_PREV_ANC_TYPE ,SW PREV ANC type" "0,1" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x50000000||0x60000000))) group.long 0x48++0x03 line.long 0x00 "SWREG18,Base Address For Reference Picture Index 4" bitfld.long 0x00 19. " SW_ALT_SCAN_FLAG_E ,SW ALT scan flag enable" "Disabled,Enabled" bitfld.long 0x00 15.--18. " SW_FCODE_FWD_HOR ,SW FCODE FWD HOR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11.--14. " SW_FCODE_FWD_VER ,SW FCODE FWD VER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7.--10. " SW_FCODE_BWD_HOR ,SW FCODE BWD HOR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3.--6. " SW_FCODE_BWD_VER ,SW FCODE BWD VER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " SW_MV_ACCURACY_FWD ,SW MV ACCURACY FWD" "0,1" textline " " bitfld.long 0x00 1. " SW_MPEG4_VC1_RC ,SW MPEG4 VC1 RC" "0,1" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x70000000||0x90000000||0xA0000000))) group.long 0x48++0x03 line.long 0x00 "SWREG18,Base Address For Reference Picture Index 4" hexmask.long 0x00 2.--31. 0x04 " SW_REFER4_BASE ,Base address for reference picture index 4" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x80000000||0xB0000000))) group.long 0x48++0x03 line.long 0x00 "SWREG18,Base Address For Reference Picture Index 4" bitfld.long 0x00 0. " SW_PREV_ANC_TYPE ,SW PREV ANC type" "0,1" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0x4C++0x0B line.long 0x00 "SWREG19,Base Address For Reference Picture Index 5" hexmask.long 0x00 2.--31. 0x04 " SW_REFER5_BASE ,Base address for reference picture index 5" bitfld.long 0x00 1. " SW_REFER5_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x00 0. " SW_REFER5_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" line.long 0x04 "SWREG20,Base Address For Reference Picture Index 6" hexmask.long 0x04 2.--31. 0x04 " SW_REFER6_BASE ,Base address for reference picture index 6" bitfld.long 0x04 1. " SW_REFER6_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x04 0. " SW_REFER6_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" line.long 0x08 "SWREG21,Base Address For Reference Picture Index 7" hexmask.long 0x08 2.--31. 0x04 " SW_REFER7_BASE ,Base address for reference picture index 7" bitfld.long 0x08 1. " SW_REFER7_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x08 0. " SW_REFER7_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x20000000)) group.long 0x4C++0x0B line.long 0x00 "SWREG19,Base Address For Reference Picture Index 5" hexmask.long 0x00 0.--26. 1. " SW_TRB_PER_TRD_D0 ,SW TRB PER TRD D0" line.long 0x04 "SWREG20,Base Address For Reference Picture Index 6" hexmask.long 0x04 0.--26. 1. " SW_TRB_PER_TRD_DM1 ,SW TRB PER TRD DM1" line.long 0x08 "SWREG21,Base Address For Reference Picture Index 7" hexmask.long 0x08 0.--26. 1. " SW_TRB_PER_TRD_D1 ,SW TRB PER TRD D1" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x30000000)) group.long 0x4C++0x0B line.long 0x00 "SWREG19,Base Address For Reference Picture Index 5" bitfld.long 0x00 27.--31. " SW_AC2_CODE4_CNT ,SW AC2 CODE4 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23.--26. " SW_AC2_CODE3_CNT ,SW AC2 CODE3 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19.--21. " SW_AC2_CODE2_CNT ,SW AC2 CODE2 CNT" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 16.--17. " SW_AC2_CODE1_CNT ,SW AC2 CODE1 CNT" "0,1,2,3" hexmask.long.byte 0x00 8.--15. 1. " SW_AC1_CODE16_CNT ,SW AC1 CODE16 CNT" hexmask.long.byte 0x00 0.--7. 1. " SW_AC1_CODE15_CNT ,SW AC1 CODE15 CNT" line.long 0x04 "SWREG20,Base Address For Reference Picture Index 6" hexmask.long.byte 0x04 24.--31. 1. " SW_AC2_CODE8_CNT ,SW AC2 CODE8 CNT" hexmask.long.byte 0x04 16.--23. 1. " SW_AC2_CODE7_CNT ,SW AC2 CODE7 CNT" hexmask.long.byte 0x04 8.--14. 1. " SW_AC2_CODE6_CNT ,SW AC2 CODE6 CNT" textline " " bitfld.long 0x04 0.--5. " SW_AC2_CODE5_CNT ,SW AC2 CODE5 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "SWREG21,Base Address For Reference Picture Index 7" hexmask.long.byte 0x08 24.--31. 1. " SW_AC2_CODE12_CNT ,SW AC2 CODE12 CNT" hexmask.long.byte 0x08 16.--23. 1. " SW_AC2_CODE11_CNT ,SW AC2 CODE11 CNT" hexmask.long.byte 0x08 8.--15. 1. " SW_AC2_CODE10_CNT ,SW AC2 CODE10 CNT" textline " " hexmask.long.byte 0x08 0.--7. 1. " SW_AC2_CODE9_CNT ,SW AC2 CODE9 CNT" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x40000000)) group.long 0x4C++0x07 line.long 0x00 "SWREG19,Base Address For Reference Picture Index 5" bitfld.long 0x00 24. " SW_ICOMP3_E ,SW ICOMP3 enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " SW_ISCALE3 ,SW ISCALE3" hexmask.long.word 0x00 0.--15. 1. " SW_ISHIFT3 ,SW ISHIFT3" line.long 0x04 "SWREG20,Base Address For Reference Picture Index 6" bitfld.long 0x04 24. " SW_ICOMP4_E ,SW ICOMP4 enable" "Disabled,Enabled" hexmask.long.byte 0x04 16.--23. 1. " SW_ISCALE4 ,SW ISCALE4" hexmask.long.word 0x04 0.--15. 1. " SW_ISHIFT4 ,SW ISHIFT4" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x70000000||0x90000000||0xA0000000))) group.long 0x4C++0x0B line.long 0x00 "SWREG19,Base Address For Reference Picture Index 5" bitfld.long 0x00 24.--29. " SW_SCAN_MAP_1 ,SW scan map 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " SW_SCAN_MAP_2 ,SW scan map 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " SW_SCAN_MAP_3 ,SW scan map 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6.--11. " SW_SCAN_MAP_4 ,SW scan map 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " SW_SCAN_MAP_5 ,SW scan map 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "SWREG20,Base Address For Reference Picture Index 6" bitfld.long 0x04 24.--29. " SW_SCAN_MAP_6 ,SW scan map 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 18.--23. " SW_SCAN_MAP_7 ,SW scan map 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 12.--17. " SW_SCAN_MAP_8 ,SW scan map 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 6.--11. " SW_SCAN_MAP_9 ,SW scan map 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " SW_SCAN_MAP_10 ,SW scan map 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "SWREG21,Base Address For Reference Picture Index 7" bitfld.long 0x08 24.--29. " SW_SCAN_MAP_11 ,SW scan map 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 18.--23. " SW_SCAN_MAP_12 ,SW scan map 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 12.--17. " SW_SCAN_MAP_13 ,SW scan map 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x08 6.--11. " SW_SCAN_MAP_14 ,SW scan map 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW_SCAN_MAP_15 ,SW scan map 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0x58++0x13 line.long 0x00 "SWREG22,Base Address For Reference Picture Index 8" hexmask.long 0x00 2.--31. 0x04 " SW_REFER8_BASE ,Base address for reference picture index 8" bitfld.long 0x00 1. " SW_REFER8_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x00 0. " SW_REFER8_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" line.long 0x04 "SWREG23,Base Address For Reference Picture Index 9" hexmask.long 0x04 2.--31. 0x04 " SW_REFER9_BASE ,Base address for reference picture index 9" bitfld.long 0x04 1. " SW_REFER9_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x04 0. " SW_REFER9_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" line.long 0x08 "SWREG24,Base Address For Reference Picture Index 10" hexmask.long 0x08 2.--31. 0x04 " SW_REFER10_BASE ,Base address for reference picture index 10" bitfld.long 0x08 1. " SW_REFER10_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x08 0. " SW_REFER10_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" line.long 0x0C "SWREG25,Base Address For Reference Picture Index 11" hexmask.long 0x0C 2.--31. 0x04 " SW_REFER11_BASE ,Base address for reference picture index 11" bitfld.long 0x0C 1. " SW_REFER11_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x0C 0. " SW_REFER11_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" line.long 0x10 "SWREG26,Base Address For Reference Picture Index 12" hexmask.long 0x10 2.--31. 0x04 " SW_REFER12_BASE ,Base address for reference picture index 12" bitfld.long 0x10 1. " SW_REFER12_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x10 0. " SW_REFER12_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x30000000)) group.long 0x58++0x13 line.long 0x00 "SWREG22,Base Address For Reference Picture Index 8" hexmask.long.byte 0x00 24.--31. 1. " SW_AC2_CODE16_CNT ,SW AC2 CODE16 CNT" hexmask.long.byte 0x00 16.--23. 1. " SW_AC2_CODE15_CNT ,SW AC2 CODE15 CNT" hexmask.long.byte 0x00 8.--15. 1. " SW_AC2_CODE14_CNT ,SW AC2 CODE14 CNT" textline " " hexmask.long.byte 0x00 0.--7. 1. " SW_AC2_CODE13_CNT ,SW AC2 CODE13 CNT" line.long 0x04 "SWREG23,Base Address For Reference Picture Index 9" bitfld.long 0x04 28.--31. " SW_DC1_CODE8_CNT ,SW DC1 CODE8 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24.--27. " SW_DC1_CODE7_CNT ,SW DC1 CODE7 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " SW_DC1_CODE6_CNT ,SW DC1 CODE6 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 16.--19. " SW_DC1_CODE5_CNT ,SW DC1 CODE5 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " SW_DC1_CODE4_CNT ,SW DC1 CODE4 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " SW_DC1_CODE3_CNT ,SW DC1 CODE3 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 4.--6. " SW_DC1_CODE2_CNT ,SW DC1 CODE2 CNT" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--1. " SW_DC1_CODE1_CNT ,SW DC1 CODE1 CNT" "0,1,2,3" line.long 0x08 "SWREG24,Base Address For Reference Picture Index 10" bitfld.long 0x08 28.--31. " SW_DC1_CODE16_CNT ,SW DC1 CODE16 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. " SW_DC1_CODE15_CNT ,SW DC1 CODE15 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 20.--23. " SW_DC1_CODE14_CNT ,SW DC1 CODE14 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 16.--19. " SW_DC1_CODE13_CNT ,SW DC1 CODE13 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 12.--15. " SW_DC1_CODE12_CNT ,SW DC1 CODE12 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8.--11. " SW_DC1_CODE11_CNT ,SW DC1 CODE11 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 4.--7. " SW_DC1_CODE10_CNT ,SW DC1 CODE10 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " SW_DC1_CODE9_CNT ,SW DC1 CODE9 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SWREG25,Base Address For Reference Picture Index 11" bitfld.long 0x0C 28.--31. " SW_DC2_CODE8_CNT ,SW DC2 CODE8 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 24.--27. " SW_DC2_CODE7_CNT ,SW DC2 CODE7 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 20.--23. " SW_DC2_CODE6_CNT ,SW DC2 CODE6 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0C 16.--19. " SW_DC2_CODE5_CNT ,SW DC2 CODE5 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 12.--15. " SW_DC2_CODE4_CNT ,SW DC2 CODE4 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 8.--11. " SW_DC2_CODE3_CNT ,SW DC2 CODE3 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0C 4.--6. " SW_DC2_CODE2_CNT ,SW DC2 CODE2 CNT" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--1. " SW_DC2_CODE1_CNT ,SW DC2 CODE1 CNT" "0,1,2,3" line.long 0x10 "SWREG26,Base Address For Reference Picture Index 12" bitfld.long 0x10 28.--31. " SW_DC2_CODE16_CNT ,SW DC2 CODE16 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. " SW_DC2_CODE15_CNT ,SW DC2 CODE15 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 20.--23. " SW_DC2_CODE14_CNT ,SW DC2 CODE14 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 16.--19. " SW_DC2_CODE13_CNT ,SW DC2 CODE13 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 12.--15. " SW_DC2_CODE12_CNT ,SW DC2 CODE12 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. " SW_DC2_CODE11_CNT ,SW DC2 CODE11 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 4.--7. " SW_DC2_CODE10_CNT ,SW DC2 CODE10 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. " SW_DC2_CODE9_CNT ,SW DC2 CODE9 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x70000000)) group.long 0x58++0x13 line.long 0x00 "SWREG22,Base Address For Reference Picture Index 8" bitfld.long 0x00 24.--29. " SW_SCAN_MAP_16 ,SW scan map 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " SW_SCAN_MAP_17 ,SW scan map 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " SW_SCAN_MAP_18 ,SW scan map 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6.--11. " SW_SCAN_MAP_19 ,SW scan map 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " SW_SCAN_MAP_20 ,SW scan map 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "SWREG23,Base Address For Reference Picture Index 9" bitfld.long 0x04 24.--29. " SW_SCAN_MAP_21 ,SW scan map 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 18.--23. " SW_SCAN_MAP_22 ,SW scan map 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 12.--17. " SW_SCAN_MAP_23 ,SW scan map 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 6.--11. " SW_SCAN_MAP_24 ,SW scan map 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " SW_SCAN_MAP_25 ,SW scan map 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "SWREG24,Base Address For Reference Picture Index 10" bitfld.long 0x08 24.--29. " SW_SCAN_MAP_26 ,SW scan map 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 18.--23. " SW_SCAN_MAP_27 ,SW scan map 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 12.--17. " SW_SCAN_MAP_28 ,SW scan map 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x08 6.--11. " SW_SCAN_MAP_29 ,SW scan map 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " SW_SCAN_MAP_30 ,SW scan map 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "SWREG25,Base Address For Reference Picture Index 11" bitfld.long 0x0C 24.--29. " SW_SCAN_MAP_31 ,SW scan map 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 18.--23. " SW_SCAN_MAP_32 ,SW scan map 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 12.--17. " SW_SCAN_MAP_33 ,SW scan map 33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0C 6.--11. " SW_SCAN_MAP_34 ,SW scan map 34" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " SW_SCAN_MAP_35 ,SW scan map 35" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "SWREG26,Base Address For Reference Picture Index 12" bitfld.long 0x10 24.--29. " SW_SCAN_MAP_36 ,SW scan map 36" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 18.--23. " SW_SCAN_MAP_37 ,SW scan map 37" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 12.--17. " SW_SCAN_MAP_38 ,SW scan map 38" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x10 6.--11. " SW_SCAN_MAP_39 ,SW scan map 39" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 0.--5. " SW_SCAN_MAP_40 ,SW scan map 40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0x58++0x13 line.long 0x00 "SWREG22,Base Address For Reference Picture Index 8" hexmask.long 0x00 2.--31. 0x04 " SW_DCT_STRM1_BASE ,SW DCT STRM1 base" line.long 0x04 "SWREG23,Base Address For Reference Picture Index 9" hexmask.long 0x04 2.--31. 0x04 " SW_DCT_STRM2_BASE ,SW DCT STRM2 base" line.long 0x08 "SWREG24,Base Address For Reference Picture Index 10" hexmask.long 0x08 2.--31. 0x04 " SW_DCT_STRM3_BASE ,SW DCT STRM3 base" line.long 0x0C "SWREG25,Base Address For Reference Picture Index 11" hexmask.long 0x0C 2.--31. 0x04 " SW_DCT_STRM4_BASE ,SW DCT STRM4 base" line.long 0x10 "SWREG26,Base Address For Reference Picture Index 12" hexmask.long 0x10 2.--31. 0x04 " SW_DCT_STRM5_BASE ,SW DCT STRM5 base" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0x6C++0x03 line.long 0x00 "SWREG27,Base Address For Reference Picture Index 13" hexmask.long 0x00 2.--31. 0x04 " SW_REFER13_BASE ,Base address for reference picture index 13" bitfld.long 0x00 1. " SW_REFER13_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x00 0. " SW_REFER13_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x30000000)) group.long 0x6C++0x03 line.long 0x00 "SWREG27,Base Address For Reference Picture Index 13" bitfld.long 0x00 28.--31. " SW_DC3_CODE8_CNT ,SW DC3 CODE8 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SW_DC3_CODE7_CNT ,SW DC3 CODE7 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SW_DC3_CODE6_CNT ,SW DC3 CODE6 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. " SW_DC3_CODE5_CNT ,SW DC3 CODE5 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " SW_DC3_CODE4_CNT ,SW DC3 CODE4 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " SW_DC3_CODE3_CNT ,SW DC3 CODE3 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--6. " SW_DC3_CODE2_CNT ,SW DC3 CODE2 CNT" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " SW_DC3_CODE1_CNT ,SW DC3 CODE1 CNT" "0,1,2,3" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x40000000||0x70000000||0x90000000||0xA0000000))) group.long 0x6C++0x03 line.long 0x00 "SWREG27,Base Address For Reference Picture Index 13" hexmask.long 0x00 2.--31. 0x04 " SW_BITPL_CTRL_BASE ,SW BITPL CTRL base" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0x70++0x07 line.long 0x00 "SWREG28,Base Address For Reference Picture Index 14" hexmask.long 0x00 2.--31. 0x04 " SW_REFER14_BASE ,Base address for reference picture index 14" bitfld.long 0x00 1. " SW_REFER14_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x00 0. " SW_REFER14_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" line.long 0x04 "SWREG29,Base Address For Reference Picture Index 15" hexmask.long 0x04 2.--31. 0x04 " SW_REFER15_BASE ,Base address for reference picture index 15" bitfld.long 0x04 1. " SW_REFER15_FIELD_E ,Refer picture consist of single fields or frame" "Frame,Fields" bitfld.long 0x04 0. " SW_REFER15_TOPC_E ,Reference picture closer to current picture" "Bottom field,Top field" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x30000000)) group.long 0x70++0x03 line.long 0x00 "SWREG28,Base Address For Reference Picture Index 14" bitfld.long 0x00 28.--31. " SW_DC3_CODE16_CNT ,SW DC3 CODE16 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SW_DC3_CODE15_CNT ,SW DC3 CODE15 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SW_DC3_CODE14_CNT ,SW DC3 CODE14 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. " SW_DC3_CODE13_CNT ,SW DC3 CODE13 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " SW_DC3_CODE12_CNT ,SW DC3 CODE12 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " SW_DC3_CODE11_CNT ,SW DC3 CODE11 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " SW_DC3_CODE10_CNT ,SW DC3 CODE10 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " SW_DC3_CODE9_CNT ,SW DC3 CODE9 CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x70000000)) group.long 0x70++0x07 line.long 0x00 "SWREG28,Base Address For Reference Picture Index 14" bitfld.long 0x00 24.--29. " SW_SCAN_MAP_41 ,SW scan map 41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " SW_SCAN_MAP_42 ,SW scan map 42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " SW_SCAN_MAP_43 ,SW scan map 43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6.--11. " SW_SCAN_MAP_44 ,SW scan map 44" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " SW_SCAN_MAP_45 ,SW scan map 45" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "SWREG29,Base Address For Reference Picture Index 15" bitfld.long 0x04 24.--29. " SW_SCAN_MAP_41 ,SW scan map 46" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 18.--23. " SW_SCAN_MAP_42 ,SW scan map 47" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 12.--17. " SW_SCAN_MAP_43 ,SW scan map 48" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 6.--11. " SW_SCAN_MAP_44 ,SW scan map 49" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " SW_SCAN_MAP_45 ,SW scan map 50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0x70++0x07 line.long 0x00 "SWREG28,Base Address For Reference Picture Index 14" hexmask.long 0x00 2.--31. 0x04 " SW_DCT_STRM6_BASE ,SW DCT STRM6 base" line.long 0x04 "SWREG29,Base Address For Reference Picture Index 15" hexmask.long 0x04 2.--31. 0x04 " SW_DCT_STRM7_BASE ,SW DCT STRM7 base" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0xB0000000)) group.long 0x70++0x07 line.long 0x00 "SWREG28,Base Address For Reference Picture Index 14" hexmask.long.word 0x00 16.--31. 1. " SW_REF_INVD_CUR_1 ,SW REF INVD CUR 1" hexmask.long.word 0x00 0.--15. 1. " SW_REF_INVD_CUR_0 ,SW REF INVD CUR 0" line.long 0x04 "SWREG29,Base Address For Reference Picture Index 15" hexmask.long.word 0x04 16.--31. 1. " SW_REF_INVD_CUR_3 ,SW REF INVD CUR 3" hexmask.long.word 0x04 0.--15. 1. " SW_REF_INVD_CUR_2 ,SW REF INVD CUR 2" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0x78++0x03 line.long 0x00 "SWREG30,Reference Picture Numbers For Index 0 And 1" hexmask.long.word 0x00 16.--31. 1. " SW_REFER1_NBR ,Number for reference picture index 1" hexmask.long.word 0x00 0.--15. 1. " SW_REFER0_NBR ,Number for reference picture index 0" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0x78++0x03 line.long 0x00 "SWREG30,Reference Picture Numbers For Index 0 And 1" bitfld.long 0x00 31. " SW_FILT_TYPE ,SW FILT type" "0,1" bitfld.long 0x00 28.--30. " SW_FILT_SHARPNESS ,SW FILT SHARPNESS" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 21.--27. 1. " SW_FILT_MB_ADJ_0 ,SW FILT MB ADJ 0" textline " " hexmask.long.byte 0x00 14.--20. 1. " SW_FILT_MB_ADJ_1 ,SW FILT MB ADJ 1" hexmask.long.byte 0x00 7.--13. 1. " SW_FILT_MB_ADJ_2 ,SW FILT MB ADJ 2" hexmask.long.byte 0x00 0.--6. 1. " SW_FILT_MB_ADJ_3 ,SW FILT MB ADJ 3" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0xB0000000)) group.long 0x78++0x03 line.long 0x00 "SWREG30,Reference Picture Numbers For Index 0 And 1" hexmask.long.word 0x00 16.--31. 1. " SW_REF_DIST_CUR_1 ,SW REF DIST CUR 1" hexmask.long.word 0x00 0.--15. 1. " SW_REF_DIST_CUR_0 ,SW REF DIST CUR 0" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0x7C++0x0B line.long 0x00 "SWREG31,Reference Picture Numbers For Index 2 And 3" hexmask.long.word 0x00 16.--31. 1. " SW_REFER3_NBR ,Number for reference picture index 3" hexmask.long.word 0x00 0.--15. 1. " SW_REFER2_NBR ,Number for reference picture index 2" line.long 0x04 "SWREG32,Reference Picture Numbers For Index 4 And 5" hexmask.long.word 0x04 16.--31. 1. " SW_REFER5_NBR ,Number for reference picture index 5" hexmask.long.word 0x04 0.--15. 1. " SW_REFER4_NBR ,Number for reference picture index 4" line.long 0x08 "SWREG33,Reference Picture Numbers For Index 6 And 7" hexmask.long.word 0x08 16.--31. 1. " SW_REFER7_NBR ,Number for reference picture index 7" hexmask.long.word 0x08 0.--15. 1. " SW_REFER6_NBR ,Number for reference picture index 6" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x70000000)) group.long 0x7C++0x0B line.long 0x00 "SWREG31,Reference Picture Numbers For Index 2 And 3" bitfld.long 0x00 24.--29. " SW_SCAN_MAP_51 ,SW scan map 51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " SW_SCAN_MAP_52 ,SW scan map 52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " SW_SCAN_MAP_53 ,SW scan map 53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6.--11. " SW_SCAN_MAP_54 ,SW scan map 54" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " SW_SCAN_MAP_55 ,SW scan map 55" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "SWREG32,Reference Picture Numbers For Index 4 And 5" bitfld.long 0x04 24.--29. " SW_SCAN_MAP_56 ,SW scan map 56" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 18.--23. " SW_SCAN_MAP_57 ,SW scan map 57" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 12.--17. " SW_SCAN_MAP_58 ,SW scan map 58" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 6.--11. " SW_SCAN_MAP_59 ,SW scan map 59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " SW_SCAN_MAP_60 ,SW scan map 60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "SWREG33,Reference Picture Numbers For Index 6 And 7" bitfld.long 0x08 24.--29. " SW_SCAN_MAP_61 ,SW scan map 61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 18.--23. " SW_SCAN_MAP_62 ,SW scan map 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 12.--17. " SW_SCAN_MAP_63 ,SW scan map 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0x7C++0x0B line.long 0x00 "SWREG31,Reference Picture Numbers For Index 2 And 3" hexmask.long.byte 0x00 21.--27. 1. " SW_FILT_MB_ADJ_0 ,SW FILT MB ADJ 0" hexmask.long.byte 0x00 14.--20. 1. " SW_FILT_MB_ADJ_1 ,SW FILT MB ADJ 1" hexmask.long.byte 0x00 7.--13. 1. " SW_FILT_MB_ADJ_2 ,SW FILT MB ADJ 2" textline " " hexmask.long.byte 0x00 0.--6. 1. " SW_FILT_MB_ADJ_3 ,SW FILT MB ADJ 3" line.long 0x04 "SWREG32,Reference Picture Numbers For Index 4 And 5" bitfld.long 0x04 18.--23. " SW_FILT_LEVEL_0 ,SW FILT level 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 12.--17. " SW_FILT_LEVEL_1 ,SW FILT level 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 6.--11. " SW_FILT_LEVEL_2 ,SW FILT level 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 0.--5. " SW_FILT_LEVEL_3 ,SW FILT level 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "SWREG33,Reference Picture Numbers For Index 6 And 7" bitfld.long 0x08 27.--31. " SW_QUANT_DELTA_0 ,SW QUANT DELTA 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 22.--26. " SW_QUANT_DELTA_1 ,SW QUANT DELTA 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x08 11.--21. 1. " SW_QUANT_0 ,SW QUANT 0" textline " " hexmask.long.word 0x08 0.--10. 1. " SW_QUANT_1 ,SW QUANT 1" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0xB0000000)) group.long 0x7C++0x0B line.long 0x00 "SWREG31,Reference Picture Numbers For Index 2 And 3" hexmask.long.word 0x00 16.--31. 1. " SW_REF_DIST_CUR_3 ,SW REF DIST CUR 3" hexmask.long.word 0x00 0.--15. 1. " SW_REF_DIST_CUR_2 ,SW REF DIST CUR 2" line.long 0x04 "SWREG32,Reference Picture Numbers For Index 4 And 5" hexmask.long.word 0x04 16.--31. 1. " SW_REF_INVD_COL_1 ,SW REF INVD COL 1" hexmask.long.word 0x04 0.--15. 1. " SW_REF_INVD_COL_0 ,SW REF INVD COL 0" line.long 0x08 "SWREG33,Reference Picture Numbers For Index 6 And 7" hexmask.long.word 0x08 16.--31. 1. " SW_REF_INVD_COL_3 ,SW REF INVD COL 3" hexmask.long.word 0x08 0.--15. 1. " SW_REF_INVD_COL_2 ,SW REF INVD COL 2" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0x88++0x07 line.long 0x00 "SWREG34,Reference Picture Numbers For Index 8 And 9" hexmask.long.word 0x00 16.--31. 1. " SW_REFER9_NBR ,Number for reference picture index 9" hexmask.long.word 0x00 0.--15. 1. " SW_REFER8_NBR ,Number for reference picture index 8" line.long 0x04 "SWREG35,Reference Picture Numbers For Index 10 And 11" hexmask.long.word 0x04 16.--31. 1. " SW_REFER11_NBR ,Number for reference picture index 11" hexmask.long.word 0x04 0.--15. 1. " SW_REFER10_NBR ,Number for reference picture index 10" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x20000000)) group.long 0x88++0x03 line.long 0x00 "SWREG34,Reference Picture Numbers For Index 8 And 9" hexmask.long.word 0x00 22.--31. 1. " SW_PRED_BC_TAP_0_3 ,SW PRED BC TAP 0 3" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x40000000||0x70000000||0x80000000||0x90000000||0xA0000000||0xB0000000))) group.long 0x88++0x07 line.long 0x00 "SWREG34,Reference Picture Numbers For Index 8 And 9" hexmask.long.word 0x00 22.--31. 1. " SW_PRED_BC_TAP_0_3 ,SW PRED BC TAP 0 3" hexmask.long.word 0x00 12.--21. 1. " SW_PRED_BC_TAP_1_0 ,SW PRED BC TAP 1 0" hexmask.long.word 0x00 2.--11. 1. " SW_PRED_BC_TAP_1_1 ,SW PRED BC TAP 1 1" line.long 0x04 "SWREG35,Reference Picture Numbers For Index 10 And 11" hexmask.long.word 0x04 22.--31. 1. " SW_PRED_BC_TAP_1_2 ,SW PRED BC TAP 1 2" hexmask.long.word 0x04 12.--21. 1. " SW_PRED_BC_TAP_1_3 ,SW PRED BC TAP 1 3" hexmask.long.word 0x04 2.--11. 1. " SW_PRED_BC_TAP_2_0 ,SW PRED BC TAP 2 0" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0x90++0x03 line.long 0x00 "SWREG36,Reference Picture Numbers For Index 12 And 13" hexmask.long.word 0x00 16.--31. 1. " SW_REFER13_NBR ,Number for reference picture index 13" hexmask.long.word 0x00 0.--15. 1. " SW_REFER12_NBR ,Number for reference picture index 12" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x40000000||0x70000000||0x90000000||0xA0000000||0xB0000000))) group.long 0x90++0x03 line.long 0x00 "SWREG36,Reference Picture Numbers For Index 12 And 13" hexmask.long.word 0x00 22.--31. 1. " SW_PRED_BC_TAP_2_1 ,SW PRED BC TAP 2 1" hexmask.long.word 0x00 12.--21. 1. " SW_PRED_BC_TAP_2_2 ,SW PRED BC TAP 2 2" hexmask.long.word 0x00 2.--11. 1. " SW_PRED_BC_TAP_2_3 ,SW PRED BC TAP 2 3" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0x94++0x0B line.long 0x00 "SWREG37,Reference Picture Numbers For Index 14 And 15" hexmask.long.word 0x00 16.--31. 1. " SW_REFER15_NBR ,Number for reference picture index 15" hexmask.long.word 0x00 0.--15. 1. " SW_REFER14_NBR ,Number for reference picture index 14" line.long 0x04 "SWREG38,Reference Picture Long Term Flags" line.long 0x08 "SWREG39,Reference Picture Valid Flags" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x70000000||0x90000000||0xA0000000))) group.long 0x94++0x0B line.long 0x00 "SWREG37,Reference Picture Numbers For Index 14 And 15" hexmask.long.word 0x00 22.--31. 1. " SW_PRED_BC_TAP_3_0 ,SW PRED BC TAP 3 0" hexmask.long.word 0x00 12.--21. 1. " SW_PRED_BC_TAP_3_1 ,SW PRED BC TAP 3 1" hexmask.long.word 0x00 2.--11. 1. " SW_PRED_BC_TAP_3_2 ,SW PRED BC TAP 3 2" line.long 0x04 "SWREG38,Reference Picture Long Term Flags" line.long 0x08 "SWREG39,Reference Picture Valid Flags" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==((0x00--0x30000000)||(0x50000000--0xA0000000)))) group.long 0xA0++0x03 line.long 0x00 "SWREG40,Base Address For Standard Dependent Tables" hexmask.long 0x00 2.--31. 1. " SW_QTABLE_BASE ,Base address for standard dependent tables" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==((0x00--0x60000000)||(0x80000000--0xB0000000)))) group.long 0xA4++0x03 line.long 0x00 "SWREG41,Base Address For Direct Mode Motion Vectors/Progressive PEG AC/DC Coefficient Read/Write Base" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0xA8++0x0B line.long 0x00 "SWREG42_H264,Bi-Dir Initial Ref Pic List Register (0-2)" bitfld.long 0x00 25.--29. " SW_BINIT_RLIST_B2_H264 ,Initial reference picture list for bi-direct backward picid 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " SW_BINIT_RLIST_F2_H264 ,Initial reference picture list for bi-direct forward picid 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " SW_BINIT_RLIST_B1_H264 ,Initial reference picture list for bi-direct backward picid 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 10.--14. " SW_BINIT_RLIST_F1_H264 ,Initial reference picture list for bi-direct forward picid 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SW_BINIT_RLIST_B0_H264 ,Initial reference picture list for bi-direct backward picid 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " SW_BINIT_RLIST_F0_H264 ,Initial reference picture list for bi-direct forward picid 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "SWREG43_H264,Bi-Dir Initial Ref Pic List Register (3-5)" bitfld.long 0x04 25.--29. " SW_BINIT_RLIST_B5_H264 ,Initial reference picture list for bi-direct backward picid 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 20.--24. " SW_BINIT_RLIST_F5_H264 ,Initial reference picture list for bi-direct forward picid 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15.--19. " SW_BINIT_RLIST_B4_H264 ,Initial reference picture list for bi-direct backward picid 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 10.--14. " SW_BINIT_RLIST_F4_H264 ,Initial reference picture list for bi-direct forward picid 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 5.--9. " SW_BINIT_RLIST_B3_H264 ,Initial reference picture list for bi-direct backward picid 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " SW_BINIT_RLIST_F3_H264 ,Initial reference picture list for bi-direct forward picid 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "SWREG44_H264,Bi-Dir Initial Ref Pic List Register (6-8)" bitfld.long 0x08 25.--29. " SW_BINIT_RLIST_B8_H264 ,Initial reference picture list for bi-direct backward picid 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 20.--24. " SW_BINIT_RLIST_F8_H264 ,Initial reference picture list for bi-direct forward picid 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 15.--19. " SW_BINIT_RLIST_B7_H264 ,Initial reference picture list for bi-direct backward picid 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x08 10.--14. " SW_BINIT_RLIST_F7_H264 ,Initial reference picture list for bi-direct forward picid 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 5.--9. " SW_BINIT_RLIST_B6_H264 ,Initial reference picture list for bi-direct backward picid 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " SW_BINIT_RLIST_F6_H264 ,Initial reference picture list for bi-direct forward picid 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x70000000||0x90000000||0xA0000000))) group.long 0xA8++0x0B line.long 0x00 "SWREG42_H264,Bi-Dir Initial Ref Pic List Register (0-2)" hexmask.long.word 0x00 22.--31. 1. " SW_PRED_BC_TAP_5_1 ,SW PRED BC TAP 5_1" hexmask.long.word 0x00 12.--21. 1. " SW_PRED_BC_TAP_5_2 ,SW PRED BC TAP 5 2" hexmask.long.word 0x00 2.--11. 1. " SW_PRED_BC_TAP_5_3 ,SW PRED BC TAP 5 3" line.long 0x04 "SWREG43_H264,Bi-Dir Initial Ref Pic List Register (3-5)" hexmask.long.word 0x04 22.--31. 1. " SW_PRED_BC_TAP_6_0 ,SW PRED BC TAP 6 0" hexmask.long.word 0x04 12.--21. 1. " SW_PRED_BC_TAP_6_1 ,SW PRED BC TAP 6 1" hexmask.long.word 0x04 2.--11. 1. " SW_PRED_BC_TAP_6_2 ,SW PRED BC TAP 6 2" line.long 0x08 "SWREG44_H264,Bi-Dir Initial Ref Pic List Register (6-8)" hexmask.long.word 0x08 22.--31. 1. " SW_PRED_BC_TAP_6_3 ,SW PRED BC TAP 6 3" hexmask.long.word 0x08 12.--21. 1. " SW_PRED_BC_TAP_7_0 ,SW PRED BC TAP 7 0" hexmask.long.word 0x08 2.--11. 1. " SW_PRED_BC_TAP_7_1 ,SW PRED BC TAP 7 1" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0xB0000000)) group.long 0xA8++0x0B line.long 0x00 "SWREG42_H264,Bi-Dir Initial Ref Pic List Register (0-2)" hexmask.long.byte 0x00 24.--31. 1. " SW_WEIGHT_QP_1 ,SW weight QP 1" bitfld.long 0x00 21.--23. " SW_REF_DELTA_COL_0 ,SW REF DELTA COL 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " SW_REF_DELTA_COL_1 ,SW REF DELTA COL 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15.--17. " SW_REF_DELTA_COL_2 ,SW REF DELTA COL 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " SW_REF_DELTA_COL_3 ,SW REF DELTA COL 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " SW_REF_DELTA_CUR_0 ,SW REF DELTA CUR 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--8. " SW_REF_DELTA_CUR_1 ,SW REF DELTA CUR 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--5. " SW_REF_DELTA_CUR_2 ,SW REF DELTA CUR 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " SW_REF_DELTA_CUR_3 ,SW REF DELTA CUR 3" "0,1,2,3,4,5,6,7" line.long 0x04 "SWREG43_H264,Bi-Dir Initial Ref Pic List Register (3-5)" hexmask.long.byte 0x04 24.--31. 1. " SW_WEIGHT_QP_2 ,SW weight QP 2" hexmask.long.byte 0x04 16.--23. 1. " SW_WEIGHT_QP_3 ,SW weight QP 3" hexmask.long.byte 0x04 8.--15. 1. " SW_WEIGHT_QP_4 ,SW weight QP 4" textline " " hexmask.long.byte 0x04 0.--7. 1. " SW_WEIGHT_QP_5 ,SW weight QP 5" line.long 0x08 "SWREG44_H264,Bi-Dir Initial Ref Pic List Register (6-8)" bitfld.long 0x08 26. " SW_DEC_AVSP_ENA ,SW DEC AVSP enable" "Disabled,Enabled" bitfld.long 0x08 25. " SW_WEIGHT_QP_E ,SW weight QP enable" "Disabled,Enabled" bitfld.long 0x08 23.--24. " SW_WEIGHT_QP_MODEL ,SW weight QP model" "0,1,2,3" textline " " bitfld.long 0x08 22. " SW_AVS_AEC_E ,SW AVS AEC enable" "Disabled,Enabled" bitfld.long 0x08 21. " SW_NO_FWD_REF_E ,SW NO FWD REF enable" "Disabled,Enabled" bitfld.long 0x08 20. " SW_PB_FIELD_ENHANCED_E ,SW PB field enhanced enable" "Disabled,Enabled" textline " " bitfld.long 0x08 14.--19. " SW_QP_DELTA_CB ,SW QP DELTA CB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " SW_QP_DELTA_CR ,SW QP DELTA CR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x08 0.--7. 1. " SW_WEIGHT_QP_0 ,SW weight QP 0" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0xB4++0x03 line.long 0x00 "SWREG45,Bi-Dir Initial Ref Pic List Register (9-11)" bitfld.long 0x00 25.--29. " SW_BINIT_RLIST_B11 ,Initial reference picture list for bi-direct backward picid 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " SW_BINIT_RLIST_F11 ,Initial reference picture list for bi-direct forward picid 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " SW_BINIT_RLIST_B10 ,Initial reference picture list for bi-direct backward picid 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 10.--14. " SW_BINIT_RLIST_F10 ,Initial reference picture list for bi-direct forward picid 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SW_BINIT_RLIST_B9 ,Initial reference picture list for bi-direct backward picid 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " SW_BINIT_RLIST_F9 ,Initial reference picture list for bi-direct forward picid 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x70000000)) group.long 0xB4++0x03 line.long 0x00 "SWREG45,Bi-Dir Initial Ref Pic List Register (9-11)" hexmask.long.word 0x00 22.--31. 1. " SW_PRED_BC_TAP_7_2 ,SW PRED BC TAP 7 2" hexmask.long.word 0x00 12.--21. 1. " SW_PRED_BC_TAP_7_3 ,SW PRED BC TAP 7 3" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0xB4++0x03 line.long 0x00 "SWREG45,Bi-Dir Initial Ref Pic List Register (9-11)" hexmask.long.word 0x00 22.--31. 1. " SW_PRED_BC_TAP_7_2 ,SW PRED BC TAP 7 2" hexmask.long.word 0x00 12.--21. 1. " SW_PRED_BC_TAP_7_3 ,SW PRED BC TAP 7 3" bitfld.long 0x00 10.--11. " SW_PRED_TAP_2_M1 ,SW PRED TAP 2 M1" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " SW_PRED_TAP_2_4 ,SW PRED TAP 2 4" "0,1,2,3" bitfld.long 0x00 6.--7. " SW_PRED_TAP_4_M1 ,SW PRED TAP 4 M1" "0,1,2,3" bitfld.long 0x00 4.--5. " SW_PRED_TAP_4_4 ,SW PRED TAP 4 4" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " SW_PRED_TAP_6_M1 ,SW PRED TAP 6 M1" "0,1,2,3" bitfld.long 0x00 0.--1. " SW_PRED_TAP_6_4 ,SW PRED TAP 6 4" "0,1,2,3" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0xB0000000)) group.long 0xB4++0x03 line.long 0x00 "SWREG45,Bi-Dir Initial Ref Pic List Register (9-11)" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0xB8++0x07 line.long 0x00 "SWREG46,Bi-Dir Initial Ref Pic List Register (12-14)" bitfld.long 0x00 25.--29. " SW_BINIT_RLIST_B14 ,Initial reference picture list for bi-direct backward picid 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " SW_BINIT_RLIST_F14 ,Initial reference picture list for bi-direct forward picid 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " SW_BINIT_RLIST_B13 ,Initial reference picture list for bi-direct backward picid 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 10.--14. " SW_BINIT_RLIST_F13 ,Initial reference picture list for bi-direct forward picid 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SW_BINIT_RLIST_B12 ,Initial reference picture list for bi-direct backward picid 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " SW_BINIT_RLIST_F12 ,Initial reference picture list for bi-direct forward picid 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "SWREG47,Bi-Dir And P Fwd Initial Ref Pic List Register (15 and P 0-3)" bitfld.long 0x04 25.--29. " SW_PINIT_RLIST_F3 ,Initial reference picture list for P forward picid 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 20.--24. " SW_PINIT_RLIST_F2 ,Initial reference picture list for P forward picid 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15.--19. " SW_PINIT_RLIST_F1 ,Initial reference picture list for P forward picid 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 10.--14. " SW_PINIT_RLIST_F0 ,Initial reference picture list for P forward picid 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 5.--9. " SW_BINIT_RLIST_B15 ,Initial reference picture list for bi-direct backward picid 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " SW_BINIT_RLIST_F15 ,Initial reference picture list for bi-direct forward picid 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) group.long 0xB8++0x07 line.long 0x00 "SWREG46,Bi-Dir Initial Ref Pic List Register (12-14)" bitfld.long 0x00 27.--31. " SW_QUANT_DELTA_2 ,SW QUANT DELTA 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 22.--26. " SW_QUANT_DELTA_3 ,SW QUANT DELTA 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 11.--21. 1. " SW_QUANT_2 ,SW QUANT 2" textline " " hexmask.long.word 0x00 0.--10. 1. " SW_QUANT_3 ,SW QUANT 3" line.long 0x04 "SWREG47,Bi-Dir And P Fwd Initial Ref Pic List Register (15 and P 0-3)" bitfld.long 0x04 27.--31. " SW_QUANT_DELTA_4 ,SW QUANT DELTA 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 11.--21. 1. " SW_QUANT_4 ,SW QUANT 4" hexmask.long.word 0x04 0.--10. 1. " SW_QUANT_5 ,SW QUANT 5" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000||0x10000000))) group.long 0xC0++0x03 line.long 0x00 "SWREG48,Error Concealment Register" hexmask.long.word 0x00 23.--31. 1. " SW_STARTMB_X ,Start MB from SW for X dimension" hexmask.long.word 0x00 14.--22. 1. " SW_STARTMB_Y ,Start MB from SW for Y dimension" bitfld.long 0x00 12.--13. " SW_ERROR_CONC_MODE ,Error concealment mode" "Normal,Direct MV usage,?..." endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000||0x20000000||0x40000000||0x70000000||0x80000000||0xB0000000))) group.long 0xC4++0x03 line.long 0x00 "SWREG49,Prediction Filter Tap Register" hexmask.long.word 0x00 22.--31. 1. " SW_PRED_BC_TAP_0_0 ,Prediction filter set 0, tap 0" hexmask.long.word 0x00 12.--21. 1. " SW_PRED_BC_TAP_0_1 ,Prediction filter set 0, tap 1" hexmask.long.word 0x00 2.--11. 1. " SW_PRED_BC_TAP_0_2 ,Prediction filter set 0, tap 2" endif textline " " if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00))) rgroup.long 0xC8++0x03 line.long 0x00 "SWREG50,Synthesis Configuration Register Decoder 0" bitfld.long 0x00 24.--25. " SW_DEC_H264_PROF ,Decoding format support" "Not supported,Supported up to baseline profile,Supported up to high profile (restricted high profile tools),Supported up to high profile" bitfld.long 0x00 21. " SW_DEC_OBUFF_LEVEL ,Decoder output buffer level" "1MB,4MB" textline " " bitfld.long 0x00 20. " SW_REF_BUFF_EXIST ,Reference picture buffer usage" "Not used,Used" bitfld.long 0x00 16.--19. " SW_DEC_BUS_STRD ,Connected to standard bus" "Error,AHB master/AHB slave,OCP master/OCP slave,AXI master/AXI slave,AXI master/APB slave,AXI master/AHB slave,?..." textline " " bitfld.long 0x00 14.--15. " SW_DEC_SYNTH_LAN ,SW_DEC_SYNTH_LAN" "Error,VHDL,Verilog,?..." bitfld.long 0x00 12.--13. " SW_DEC_BUS_WIDTH ,SW_DEC_BUS_WIDTH" "Error,32 bit bus,64 bit bus,128 bit bus" textline " " hexmask.long.word 0x00 0.--10. 1. " SW_DEC_MAX_OWIDTH ,Max configured decoder video resolution that can be decoded" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x20000000||0x10000000))) rgroup.long 0xC8++0x03 line.long 0x00 "SWREG50,Synthesis Configuration Register Decoder 0" bitfld.long 0x00 26.--27. " SW_DEC_MPEG4_PROF ,Decoding format support - MPEG-4 / H.263" "Not supported,Supported up to simple profile,Supported up to advanced simple profile,?..." bitfld.long 0x00 21. " SW_DEC_OBUFF_LEVEL ,Decoder output buffer level" "1MB,4MB" textline " " bitfld.long 0x00 20. " SW_REF_BUFF_EXIST ,Reference picture buffer usage" "Not used,Used" bitfld.long 0x00 16.--19. " SW_DEC_BUS_STRD ,Connected to standard bus" "Error,AHB master/AHB slave,OCP master/OCP slave,AXI master/AXI slave,AXI master/APB slave,AXI master/AHB slave,?..." textline " " bitfld.long 0x00 14.--15. " SW_DEC_SYNTH_LAN ,SW_DEC_SYNTH_LAN" "Error,VHDL,Verilog,?..." bitfld.long 0x00 12.--13. " SW_DEC_BUS_WIDTH ,SW_DEC_BUS_WIDTH" "Error,32 bit bus,64 bit bus,128 bit bus" textline " " bitfld.long 0x00 11. " SW_DEC_SOREN_PROF ,Decoding format support - Sorenson" "Not supported,Supported" hexmask.long.word 0x00 0.--10. 1. " SW_DEC_MAX_OWIDTH ,Max configured decoder video resolution that can be decoded" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x30000000)) rgroup.long 0xC8++0x03 line.long 0x00 "SWREG50,Synthesis Configuration Register Decoder 0" bitfld.long 0x00 28. " SW_DEC_JPEG_PROF ,Decoding format support - JPEG" "Not supported,Supported" bitfld.long 0x00 22. " SW_DEC_PJPEG_EXIST ,Progressive JPEG support" "Not supported,Supported" textline " " bitfld.long 0x00 16.--19. " SW_DEC_BUS_STRD ,Connected to standard bus" "Error,AHB master/AHB slave,OCP master/OCP slave,AXI master/AXI slave,AXI master/APB slave,AXI master/AHB slave,?..." bitfld.long 0x00 14.--15. " SW_DEC_SYNTH_LAN ,SW_DEC_SYNTH_LAN" "Error,VHDL,Verilog,?..." textline " " bitfld.long 0x00 12.--13. " SW_DEC_BUS_WIDTH ,SW_DEC_BUS_WIDTH" "Error,32 bit bus,64 bit bus,128 bit bus" hexmask.long.word 0x00 0.--10. 1. " SW_DEC_MAX_OWIDTH ,Max configured decoder video resolution that can be decoded" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x40000000)) rgroup.long 0xC8++0x03 line.long 0x00 "SWREG50,Synthesis Configuration Register Decoder 0" bitfld.long 0x00 29.--30. " SW_DEC_VC1_PROF ,Decoding format support - VC-1" "Not supported,Supported up to simple profile,Supported up to main profile,Supported up to advanced profile" bitfld.long 0x00 21. " SW_DEC_OBUFF_LEVEL ,Decoder output buffer level" "1MB,4MB" textline " " bitfld.long 0x00 20. " SW_REF_BUFF_EXIST ,Reference picture buffer usage" "Not used,Used" bitfld.long 0x00 16.--19. " SW_DEC_BUS_STRD ,Connected to standard bus" "Error,AHB master/AHB slave,OCP master/OCP slave,AXI master/AXI slave,AXI master/APB slave,AXI master/AHB slave,?..." textline " " bitfld.long 0x00 14.--15. " SW_DEC_SYNTH_LAN ,SW_DEC_SYNTH_LAN" "Error,VHDL,Verilog,?..." bitfld.long 0x00 12.--13. " SW_DEC_BUS_WIDTH ,SW_DEC_BUS_WIDTH" "Error,32 bit bus,64 bit bus,128 bit bus" textline " " hexmask.long.word 0x00 0.--10. 1. " SW_DEC_MAX_OWIDTH ,Max configured decoder video resolution that can be decoded" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x50000000||0x60000000))) rgroup.long 0xC8++0x03 line.long 0x00 "SWREG50,Synthesis Configuration Register Decoder 0" bitfld.long 0x00 31. " SW_DEC_MPEG2_PROF ,Decoding format support - MPEG-2 / MPEG-1" "Not supported,Supported" bitfld.long 0x00 21. " SW_DEC_OBUFF_LEVEL ,Decoder output buffer level" "1MB,4MB" textline " " bitfld.long 0x00 20. " SW_REF_BUFF_EXIST ,Reference picture buffer usage" "Not used,Used" bitfld.long 0x00 16.--19. " SW_DEC_BUS_STRD ,Connected to standard bus" "Error,AHB master/AHB slave,OCP master/OCP slave,AXI master/AXI slave,AXI master/APB slave,AXI master/AHB slave,?..." textline " " bitfld.long 0x00 14.--15. " SW_DEC_SYNTH_LAN ,SW_DEC_SYNTH_LAN" "Error,VHDL,Verilog,?..." bitfld.long 0x00 12.--13. " SW_DEC_BUS_WIDTH ,SW_DEC_BUS_WIDTH" "Error,32 bit bus,64 bit bus,128 bit bus" textline " " hexmask.long.word 0x00 0.--10. 1. " SW_DEC_MAX_OWIDTH ,Max configured decoder video resolution that can be decoded" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x70000000)) rgroup.long 0xC8++0x03 line.long 0x00 "SWREG50,Synthesis Configuration Register Decoder 0" bitfld.long 0x00 23. " SW_DEC_VP6_PROF ,Decoding format support - VP6" "Not supported,Supported" bitfld.long 0x00 21. " SW_DEC_OBUFF_LEVEL ,Decoder output buffer level" "1MB,4MB" textline " " bitfld.long 0x00 20. " SW_REF_BUFF_EXIST ,Reference picture buffer usage" "Not used,Used" bitfld.long 0x00 16.--19. " SW_DEC_BUS_STRD ,Connected to standard bus" "Error,AHB master/AHB slave,OCP master/OCP slave,AXI master/AXI slave,AXI master/APB slave,AXI master/AHB slave,?..." textline " " bitfld.long 0x00 14.--15. " SW_DEC_SYNTH_LAN ,SW_DEC_SYNTH_LAN" "Error,VHDL,Verilog,?..." bitfld.long 0x00 12.--13. " SW_DEC_BUS_WIDTH ,SW_DEC_BUS_WIDTH" "Error,32 bit bus,64 bit bus,128 bit bus" textline " " hexmask.long.word 0x00 0.--10. 1. " SW_DEC_MAX_OWIDTH ,Max configured decoder video resolution that can be decoded" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x80000000||0x90000000||0xA0000000||0xB0000000))) rgroup.long 0xC8++0x03 line.long 0x00 "SWREG50,Synthesis Configuration Register Decoder 0" bitfld.long 0x00 21. " SW_DEC_OBUFF_LEVEL ,Decoder output buffer level" "1MB,4MB" bitfld.long 0x00 20. " SW_REF_BUFF_EXIST ,Reference picture buffer usage" "Not used,Used" textline " " bitfld.long 0x00 16.--19. " SW_DEC_BUS_STRD ,Connected to standard bus" "Error,AHB master/AHB slave,OCP master/OCP slave,AXI master/AXI slave,AXI master/APB slave,AXI master/AHB slave,?..." bitfld.long 0x00 14.--15. " SW_DEC_SYNTH_LAN ,SW_DEC_SYNTH_LAN" "Error,VHDL,Verilog,?..." textline " " bitfld.long 0x00 12.--13. " SW_DEC_BUS_WIDTH ,SW_DEC_BUS_WIDTH" "Error,32 bit bus,64 bit bus,128 bit bus" hexmask.long.word 0x00 0.--10. 1. " SW_DEC_MAX_OWIDTH ,Max configured decoder video resolution that can be decoded" endif textline " " if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==((0x00--0x20000000)||(0x40000000--0xB0000000)))) group.long 0xCC++0x03 line.long 0x00 "SWREG51,Reference Picture Buffer Control Register" bitfld.long 0x00 31. " SW_REFBU_E ,Refer picture buffer enable" "Disabled,Enabled" hexmask.long.word 0x00 19.--30. 1. " SW_REFBU_THR ,Reference buffer disable threshold value" textline " " bitfld.long 0x00 14.--18. " SW_REFBU_PICID ,The used reference picture ID for reference buffer usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 13. " SW_REFBU_EVAL_E ,Enable for HW internal reference ID calculation" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " SW_REFBU_FPARMOD_E ,Field parity mode enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--8. 0x01 " SW_REFBU_Y_OFFSET ,Y offset for reference buffer" rgroup.long 0xD0++0x07 line.long 0x00 "SWREG52,Reference Picture Buffer Information Register 1" hexmask.long.word 0x00 16.--31. 1. " SW_REFBU_HIT_SUM ,Sum of the reference buffer hits of the picture" hexmask.long.word 0x00 0.--15. 1. " SW_REFBU_INTRA_SUM ,Sum of the luminance 8x8 intra partitions of the picture" line.long 0x04 "SWREG53,Reference Picture Buffer Information Register 2" hexmask.long.tbyte 0x04 0.--21. 1. " SW_REFBU_Y_MV_SUM ,Sum of the decoded motion vector y-components of the picture" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) rgroup.long 0xD8++0x03 line.long 0x00 "SWREG54,Synthesis Configuration Register Decoder 1" bitfld.long 0x00 30. " SW_DEC_REFBU_ILACE ,Reference buffer support for interlaced content" "Not supported,Supported" bitfld.long 0x00 20. " SW_DEC_MVC_PROF ,Decoding format support - MVC" "Not supported,Supported" textline " " bitfld.long 0x00 17.--18. " SW_DEC_TILED_L ,Tiled mode support level" "Not supported,Supported with 8x4 progressive,Supported with 8x4 progressive/ilaced,?..." bitfld.long 0x00 14.--15. " SW_DEC_MAX_OW_EXT ,Max configured decoder video resolution that can be decoded" "0,1,2,3" textline " " bitfld.long 0x00 10. " SW_DPB_FIELD_E ,DPB field separate mode support for ilaced content" "Not supported,Supported" bitfld.long 0x00 7.--9. " SW_DEC_CORE_AM ,Decoder core amount" "1,2,3,4,5,6,7,8" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x20000000))) rgroup.long 0xD8++0x03 line.long 0x00 "SWREG54,Synthesis Configuration Register Decoder 1" bitfld.long 0x00 30. " SW_DEC_REFBU_ILACE ,Reference buffer support for interlaced content" "Not supported,Supported" bitfld.long 0x00 29. " SW_DEC_DIVX_PROF ,DIVX support" "Not supported,Supported" textline " " bitfld.long 0x00 25. " SW_DEC_RTL_ROM ,ROM implementation type" "Actual ROM units,RTL" bitfld.long 0x00 17.--18. " SW_DEC_TILED_L ,Tiled mode support level" "Not supported,Supported with 8x4 progressive,Supported with 8x4 progressive/ilaced,?..." textline " " bitfld.long 0x00 14.--15. " SW_DEC_MAX_OW_EXT ,Max configured decoder video resolution that can be decoded" "0,1,2,3" bitfld.long 0x00 10. " SW_DPB_FIELD_E ,DPB field separate mode support for ilaced content" "Not supported,Supported" textline " " bitfld.long 0x00 7.--9. " SW_DEC_CORE_AM ,Decoder core amount" "1,2,3,4,5,6,7,8" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x30000000))) rgroup.long 0xD8++0x03 line.long 0x00 "SWREG54,Synthesis Configuration Register Decoder 1" bitfld.long 0x00 31. " SW_DEC_JPEG_EXTENS ,JPEG sampling support extension for 411 and 444 samplings and support for bigger max resolution than 16 Mpix" "Not supported,Supported" bitfld.long 0x00 10. " SW_DPB_FIELD_E ,DPB field separate mode support for ilaced content" "Not supported,Supported" textline " " bitfld.long 0x00 7.--9. " SW_DEC_CORE_AM ,Decoder core amount" "1,2,3,4,5,6,7,8" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x40000000))) rgroup.long 0xD8++0x03 line.long 0x00 "SWREG54,Synthesis Configuration Register Decoder 1" bitfld.long 0x00 30. " SW_DEC_REFBU_ILACE ,Reference buffer support for interlaced content" "Not supported,Supported" bitfld.long 0x00 25. " SW_DEC_RTL_ROM ,ROM implementation type" "Actual ROM units,RTL" textline " " bitfld.long 0x00 17.--18. " SW_DEC_TILED_L ,Tiled mode support level" "Not supported,Supported with 8x4 progressive,Supported with 8x4 progressive/ilaced,?..." bitfld.long 0x00 14.--15. " SW_DEC_MAX_OW_EXT ,Max configured decoder video resolution that can be decoded" "0,1,2,3" textline " " bitfld.long 0x00 10. " SW_DPB_FIELD_E ,DPB field separate mode support for ilaced content" "Not supported,Supported" bitfld.long 0x00 7.--9. " SW_DEC_CORE_AM ,Decoder core amount" "1,2,3,4,5,6,7,8" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x50000000||0x60000000))) rgroup.long 0xD8++0x03 line.long 0x00 "SWREG54,Synthesis Configuration Register Decoder 1" bitfld.long 0x00 30. " SW_DEC_REFBU_ILACE ,Reference buffer support for interlaced content" "Not supported,Supported" bitfld.long 0x00 17.--18. " SW_DEC_TILED_L ,Tiled mode support level" "Not supported,Supported with 8x4 progressive,Supported with 8x4 progressive/ilaced,?..." textline " " bitfld.long 0x00 14.--15. " SW_DEC_MAX_OW_EXT ,Max configured decoder video resolution that can be decoded" "0,1,2,3" bitfld.long 0x00 10. " SW_DPB_FIELD_E ,DPB field separate mode support for ilaced content" "Not supported,Supported" textline " " bitfld.long 0x00 7.--9. " SW_DEC_CORE_AM ,Decoder core amount" "1,2,3,4,5,6,7,8" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x70000000)) rgroup.long 0xD8++0x03 line.long 0x00 "SWREG54,Synthesis Configuration Register Decoder 1" bitfld.long 0x00 17.--18. " SW_DEC_TILED_L ,Tiled mode support level" "Not supported,Supported with 8x4 progressive,Supported with 8x4 progressive/ilaced,?..." bitfld.long 0x00 14.--15. " SW_DEC_MAX_OW_EXT ,Max configured decoder video resolution that can be decoded" "0,1,2,3" textline " " bitfld.long 0x00 10. " SW_DPB_FIELD_E ,DPB field separate mode support for ilaced content" "Not supported,Supported" bitfld.long 0x00 7.--9. " SW_DEC_CORE_AM ,Decoder core amount" "1,2,3,4,5,6,7,8" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x80000000)) rgroup.long 0xD8++0x03 line.long 0x00 "SWREG54,Synthesis Configuration Register Decoder 1" bitfld.long 0x00 26.--27. " SW_DEC_RV_PROF ,Decoding format support - RV" "Not supported,Supported,?..." bitfld.long 0x00 25. " SW_DEC_RTL_ROM ,ROM implementation type" "Actual ROM units,RTL" textline " " bitfld.long 0x00 17.--18. " SW_DEC_TILED_L ,Tiled mode support level" "Not supported,Supported with 8x4 progressive,Supported with 8x4 progressive/ilaced,?..." bitfld.long 0x00 14.--15. " SW_DEC_MAX_OW_EXT ,Max configured decoder video resolution that can be decoded" "0,1,2,3" textline " " bitfld.long 0x00 10. " SW_DPB_FIELD_E ,DPB field separate mode support for ilaced content" "Not supported,Supported" bitfld.long 0x00 7.--9. " SW_DEC_CORE_AM ,Decoder core amount" "1,2,3,4,5,6,7,8" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x90000000||0xA0000000))) rgroup.long 0xD8++0x03 line.long 0x00 "SWREG54,Synthesis Configuration Register Decoder 1" bitfld.long 0x00 24. " SW_DEC_VP7_PROF ,Decoding format support - VP7" "Not supported,Supported" bitfld.long 0x00 23. " SW_DEC_VP8_PROF ,Decoding format support - VP7" "Not supported,Supported" textline " " bitfld.long 0x00 19. " SW_DEC_WEBP_E ,Decoding format support - Web-p" "Not supported,Supported" bitfld.long 0x00 17.--18. " SW_DEC_TILED_L ,Tiled mode support level" "Not supported,Supported with 8x4 progressive,Supported with 8x4 progressive/ilaced,?..." textline " " bitfld.long 0x00 16. " SW_DEC_VP8S_ARCH ,VP8 architecture type (for prediction)" "Same prediction arch as for other,Dedicated small arch" bitfld.long 0x00 14.--15. " SW_DEC_MAX_OW_EXT ,Max configured decoder video resolution that can be decoded" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " SW_DEC_ERRCO_LEVEL ,Decoder error concealment support level" "Not supported,VP8 direct mode motion vector,?..." bitfld.long 0x00 11. " SW_VP8_STRIDE_E ,Decoder output stride support for VP8" "Not supported,Supported" textline " " bitfld.long 0x00 10. " SW_DPB_FIELD_E ,DPB field separate mode support for ilaced content" "Not supported,Supported" bitfld.long 0x00 7.--9. " SW_DEC_CORE_AM ,Decoder core amount" "1,2,3,4,5,6,7,8" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0xB0000000)) rgroup.long 0xD8++0x03 line.long 0x00 "SWREG54,Synthesis Configuration Register Decoder 1" bitfld.long 0x00 22. " SW_DEC_VP8_PROF ,Decoding format support - AVS" "Not supported,Supported" bitfld.long 0x00 17.--18. " SW_DEC_TILED_L ,Tiled mode support level" "Not supported,Supported with 8x4 progressive,Supported with 8x4 progressive/ilaced,?..." textline " " bitfld.long 0x00 14.--15. " SW_DEC_MAX_OW_EXT ,Max configured decoder video resolution that can be decoded" "0,1,2,3" bitfld.long 0x00 10. " SW_DPB_FIELD_E ,DPB field separate mode support for ilaced content" "Not supported,Supported" textline " " bitfld.long 0x00 7.--9. " SW_DEC_CORE_AM ,Decoder core amount" "1,2,3,4,5,6,7,8" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==((0x00--0x20000000)||(0x40000000--0xB0000000)))) group.long 0xDC++0x03 line.long 0x00 "SWREG55,Reference Picture Buffer 2 / Advanced Prefetch Control Register" bitfld.long 0x00 31. " SW_REFBU2_BUF_E ,Refer picture buffer 2 enable" "Disabled,Enabled" hexmask.long.word 0x00 19.--30. 1. " SW_REFBU2_THR ,Reference buffer disable threshold value" textline " " bitfld.long 0x00 14.--18. " SW_REFBU2_PICID ,The used reference picture ID for reference buffer usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--13. 1. " SW_APF_THRESHOLD ,Advanced prefetch threshold value" rgroup.long 0xE0++0x03 line.long 0x00 "SWREG56,Reference Buffer Information Register 3" hexmask.long.word 0x00 16.--31. 1. " SW_REFBU_TOP_SUM ,The sum of the top partitions of the picture" hexmask.long.word 0x00 0.--15. 1. " SW_REFBU_BOT_SUM ,The sum of the bottom partitions of the picture" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00))) rgroup.long 0xE4++0x03 line.long 0x00 "SWREG57,Decoder Fuse Register" bitfld.long 0x00 31. " FUSE_DEC_H264 ,H.264 enable" "Disabled,Enabled" bitfld.long 0x00 18. " FUSE_DEC_MVC ,MVC enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " FUSE_DEC_MAXW_4K ,Max video width up to 4096 pixels enable" "Disabled,Enabled" bitfld.long 0x00 15. " FUSE_DEC_MAXW_1920 ,Max video width up to 1920 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " FUSE_DEC_MAXW_1280 ,Max video width up to 1280 pixels enable" "Disabled,Enabled" bitfld.long 0x00 13. " FUSE_DEC_MAXW_720 ,Max video width up to 720 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " FUSE_DEC_MAXW_352 ,Max video width up to 352 pixels enable" "Disabled,Enabled" bitfld.long 0x00 7. " FUSE_DEC_REFBUFFER ,Reference buffer enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x20000000||0x10000000))) if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x10000000))) rgroup.long 0xE4++0x03 line.long 0x00 "SWREG57,Decoder Fuse Register" bitfld.long 0x00 30. " FUSE_DEC_MPEG4 ,H.263/MPEG-4 enable" "Disabled,Enabled" bitfld.long 0x00 28. " FUSE_DEC_SORENSON ,Sorenson enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " FUSE_DEC_DIVX ,DIVX enable" "Disabled,Enabled" bitfld.long 0x00 16. " FUSE_DEC_MAXW_4K ,Max video width up to 4096 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FUSE_DEC_MAXW_1920 ,Max video width up to 1920 pixels enable" "Disabled,Enabled" bitfld.long 0x00 14. " FUSE_DEC_MAXW_1280 ,Max video width up to 1280 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " FUSE_DEC_MAXW_720 ,Max video width up to 720 pixels enable" "Disabled,Enabled" bitfld.long 0x00 12. " FUSE_DEC_MAXW_352 ,Max video width up to 352 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FUSE_DEC_REFBUFFER ,Reference buffer enable" "Disabled,Enabled" else rgroup.long 0xE4++0x03 line.long 0x00 "SWREG57,Decoder Fuse Register" bitfld.long 0x00 30. " FUSE_DEC_MPEG4 ,H.263/MPEG-4 enable" "Disabled,Enabled" bitfld.long 0x00 16. " FUSE_DEC_MAXW_4K ,Max video width up to 4096 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FUSE_DEC_MAXW_1920 ,Max video width up to 1920 pixels enable" "Disabled,Enabled" bitfld.long 0x00 14. " FUSE_DEC_MAXW_1280 ,Max video width up to 1280 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " FUSE_DEC_MAXW_720 ,Max video width up to 720 pixels enable" "Disabled,Enabled" bitfld.long 0x00 12. " FUSE_DEC_MAXW_352 ,Max video width up to 352 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FUSE_DEC_REFBUFFER ,Reference buffer enable" "Disabled,Enabled" endif elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x30000000))) rgroup.long 0xE4++0x03 line.long 0x00 "SWREG57,Decoder Fuse Register" bitfld.long 0x00 27. " FUSE_DEC_JPEG ,JPEG enable" "Disabled,Enabled" bitfld.long 0x00 24. " FUSE_DEC_PJPEG ,Progressive JPEG enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x40000000))) rgroup.long 0xE4++0x03 line.long 0x00 "SWREG57,Decoder Fuse Register" bitfld.long 0x00 25. " FUSE_DEC_VC1 ,VC1 enable" "Disabled,Enabled" bitfld.long 0x00 16. " FUSE_DEC_MAXW_4K ,Max video width up to 4096 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FUSE_DEC_MAXW_1920 ,Max video width up to 1920 pixels enable" "Disabled,Enabled" bitfld.long 0x00 14. " FUSE_DEC_MAXW_1280 ,Max video width up to 1280 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " FUSE_DEC_MAXW_720 ,Max video width up to 720 pixels enable" "Disabled,Enabled" bitfld.long 0x00 12. " FUSE_DEC_MAXW_352 ,Max video width up to 352 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FUSE_DEC_REFBUFFER ,Reference buffer enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x50000000||0x60000000))) rgroup.long 0xE4++0x03 line.long 0x00 "SWREG57,Decoder Fuse Register" bitfld.long 0x00 29. " FUSE_DEC_MPEG2 ,MPEG-2/MPEG-1 enable" "Disabled,Enabled" bitfld.long 0x00 16. " FUSE_DEC_MAXW_4K ,Max video width up to 4096 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FUSE_DEC_MAXW_1920 ,Max video width up to 1920 pixels enable" "Disabled,Enabled" bitfld.long 0x00 14. " FUSE_DEC_MAXW_1280 ,Max video width up to 1280 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " FUSE_DEC_MAXW_720 ,Max video width up to 720 pixels enable" "Disabled,Enabled" bitfld.long 0x00 12. " FUSE_DEC_MAXW_352 ,Max video width up to 352 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FUSE_DEC_REFBUFFER ,Reference buffer enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x70000000)) rgroup.long 0xE4++0x03 line.long 0x00 "SWREG57,Decoder Fuse Register" bitfld.long 0x00 26. " FUSE_DEC_VP6 ,VP6 enable" "Disabled,Enabled" bitfld.long 0x00 16. " FUSE_DEC_MAXW_4K ,Max video width up to 4096 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FUSE_DEC_MAXW_1920 ,Max video width up to 1920 pixels enable" "Disabled,Enabled" bitfld.long 0x00 14. " FUSE_DEC_MAXW_1280 ,Max video width up to 1280 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " FUSE_DEC_MAXW_720 ,Max video width up to 720 pixels enable" "Disabled,Enabled" bitfld.long 0x00 12. " FUSE_DEC_MAXW_352 ,Max video width up to 352 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FUSE_DEC_REFBUFFER ,Reference buffer enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x80000000)) rgroup.long 0xE4++0x03 line.long 0x00 "SWREG57,Decoder Fuse Register" bitfld.long 0x00 22. " FUSE_DEC_RV ,RV enable" "Disabled,Enabled" bitfld.long 0x00 16. " FUSE_DEC_MAXW_4K ,Max video width up to 4096 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FUSE_DEC_MAXW_1920 ,Max video width up to 1920 pixels enable" "Disabled,Enabled" bitfld.long 0x00 14. " FUSE_DEC_MAXW_1280 ,Max video width up to 1280 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " FUSE_DEC_MAXW_720 ,Max video width up to 720 pixels enable" "Disabled,Enabled" bitfld.long 0x00 12. " FUSE_DEC_MAXW_352 ,Max video width up to 352 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FUSE_DEC_REFBUFFER ,Reference buffer enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0x90000000)) rgroup.long 0xE4++0x03 line.long 0x00 "SWREG57,Decoder Fuse Register" bitfld.long 0x00 21. " FUSE_DEC_VP7 ,VP7 enable" "Disabled,Enabled" bitfld.long 0x00 16. " FUSE_DEC_MAXW_4K ,Max video width up to 4096 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FUSE_DEC_MAXW_1920 ,Max video width up to 1920 pixels enable" "Disabled,Enabled" bitfld.long 0x00 14. " FUSE_DEC_MAXW_1280 ,Max video width up to 1280 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " FUSE_DEC_MAXW_720 ,Max video width up to 720 pixels enable" "Disabled,Enabled" bitfld.long 0x00 12. " FUSE_DEC_MAXW_352 ,Max video width up to 352 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FUSE_DEC_REFBUFFER ,Reference buffer enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0xA0000000)) rgroup.long 0xE4++0x03 line.long 0x00 "SWREG57,Decoder Fuse Register" bitfld.long 0x00 20. " FUSE_DEC_VP8 ,VP8 enable" "Disabled,Enabled" bitfld.long 0x00 16. " FUSE_DEC_MAXW_4K ,Max video width up to 4096 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FUSE_DEC_MAXW_1920 ,Max video width up to 1920 pixels enable" "Disabled,Enabled" bitfld.long 0x00 14. " FUSE_DEC_MAXW_1280 ,Max video width up to 1280 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " FUSE_DEC_MAXW_720 ,Max video width up to 720 pixels enable" "Disabled,Enabled" bitfld.long 0x00 12. " FUSE_DEC_MAXW_352 ,Max video width up to 352 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FUSE_DEC_REFBUFFER ,Reference buffer enable" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==0xB0000000)) rgroup.long 0xE4++0x03 line.long 0x00 "SWREG57,Decoder Fuse Register" bitfld.long 0x00 19. " FUSE_DEC_AVS ,AVS enable" "Disabled,Enabled" bitfld.long 0x00 16. " FUSE_DEC_MAXW_4K ,Max video width up to 4096 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FUSE_DEC_MAXW_1920 ,Max video width up to 1920 pixels enable" "Disabled,Enabled" bitfld.long 0x00 14. " FUSE_DEC_MAXW_1280 ,Max video width up to 1280 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " FUSE_DEC_MAXW_720 ,Max video width up to 720 pixels enable" "Disabled,Enabled" bitfld.long 0x00 12. " FUSE_DEC_MAXW_352 ,Max video width up to 352 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FUSE_DEC_REFBUFFER ,Reference buffer enable" "Disabled,Enabled" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000||0x90000000||0xA0000000))) group.long 0xE8++0x03 line.long 0x00 "SWREG58,Device Configuration Register Decoder 2 + Multi Core Control Register" bitfld.long 0x00 31. " SW_SERV_MERGE_DIS ,Decoder service merge disable" "No,Yes" bitfld.long 0x00 30. " SW_DEC_MULTICORE_E ,Decoder multi core enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " SW_DEC_WRITESTAT_E ,Decoder write status word enable" "Disabled,Enabled" bitfld.long 0x00 27.--28. " SW_DEC_MC_POLLMODE ,Decoder multi core status reading mode" "Internal status polling,Dummy status polling,?..." textline " " hexmask.long.word 0x00 17.--26. 1. " SW_DEC_MC_POLLTIME ,Sw_dec_mc_polltime" elif (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x20000000||0x30000000||0x40000000||0x50000000||0x60000000||0x70000000||0x80000000||0xB0000000))) group.long 0xE8++0x03 line.long 0x00 "SWREG58,Device Configuration Register Decoder 2 + Multi Core Control Register" bitfld.long 0x00 31. " SW_SERV_MERGE_DIS ,Decoder service merge disable" "No,Yes" endif if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000))) group.long 0xEC++0x03 line.long 0x00 "SWREG59,H264 Chrominance 8 Pixel Interleaved Data Base" hexmask.long 0x00 2.--31. 1. " SW_DEC_CH8PIX_BASE ,Base address for additional chrominance data format where chrominance is interleaved in group of 8 pixels" endif textline " " if (((per.l(ad:0x38300000+0xF0)&0x02)==0x02)) group.long 0xF0++0x03 line.long 0x00 "SWREG60,Interrupt Register Post-Processor" bitfld.long 0x00 4. " SW_PP_IRQ_DIS ,Post-processor IRQ disable" "No,Yes" bitfld.long 0x00 1. " SW_PP_PIPELINE_E ,Decoder post-processing pipeline enable" "Disabled,Enabled" else group.long 0xF0++0x03 line.long 0x00 "SWREG60,Interrupt Register Post-Processor" bitfld.long 0x00 13. " SW_PP_BUS_INT ,Interrupt status bit bus" "No interrupt,Interrupt" bitfld.long 0x00 12. " SW_PP_RDY_INT ,Interrupt status bit pp" "No interrupt,Interrupt" bitfld.long 0x00 8. " SW_PP_IRQ ,Post-processor IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " SW_PP_IRQ_DIS ,Post-processor IRQ disable" "No,Yes" bitfld.long 0x00 1. " SW_PP_PIPELINE_E ,Decoder post-processing pipeline enable" "Disabled,Enabled" bitfld.long 0x00 0. " SW_PP_E ,External mode post-processing enable" "Disabled,Enabled" endif group.long 0xF4++0x37 line.long 0x00 "SWREG61,Device Configuration Register Post-Processor" hexmask.long.byte 0x00 24.--31. 1. " SW_PP_AXI_RD_ID ,Read ID used for AXI PP read services 8190_decoder" hexmask.long.byte 0x00 16.--23. 1. " SW_PP_AXI_WR_ID ,Write ID used for AXI PP write services 8190_decoder" bitfld.long 0x00 15. " SW_PP_AHB_HLOCK_E ,AHB master HLOCK enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " SW_PP_SCMD_DIS ,AXI single command multiple data disable" "No,Yes" bitfld.long 0x00 13. " SW_PP_IN_A2_ENDSEL ,Endian/swap select for alpha blend input source 2" "PP,Ablend" bitfld.long 0x00 12. " SW_PP_IN_A1_SWAP32 ,Alpha blend source 1 input 32bit data swap" "Not swapped,Swapped" textline " " bitfld.long 0x00 11. " SW_PP_IN_A1_ENDIAN ,Alpha blend source 1 input data byte endian mode" "Big endian,Little endian" bitfld.long 0x00 10. " SW_PP_IN_SWAP32_E ,PP input 32bit data swap" "Not swapped,Swapped" bitfld.long 0x00 9. " SW_PP_DATA_DISC_E ,PP data discard enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " SW_PP_CLK_GATE_E ,PP dynamic clock gating enable" "Disabled,Enabled" bitfld.long 0x00 7. " SW_PP_IN_ENDIAN ,PP input picture byte endian mode" "Big endian,Little endian" bitfld.long 0x00 6. " SW_PP_OUT_ENDIAN ,PP output picture endian mode for YCbCr data or for any data if config value" "Big endian,Little endian" textline " " bitfld.long 0x00 5. " SW_PP_OUT_SWAP32_E ,PP output data word swap" "Not swapped,Swapped" bitfld.long 0x00 0.--4. " SW_PP_MAX_BURST ,Maximum burst length for PP bus transactions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "SWREG62,Deinterlace Control Register" bitfld.long 0x04 31. " SW_DEINT_E ,De-interlace enable" "Disabled,Enabled" hexmask.long.word 0x04 16.--29. 1. " SW_DEINT_THRESHOLD ,Threshold value used in deinterlacing" bitfld.long 0x04 15. " SW_DEINT_BLEND_E ,Blend enable for de-interlacing" "Disabled,Enabled" textline " " hexmask.long.word 0x04 0.--14. 1. " SW_DEINT_EDGE_DET ,Edge detect value used for deinterlacing" line.long 0x08 "SWREG63,Base Address For Reading Post-Processing Input Picture Luminance (Top field/Frame)" hexmask.long 0x08 2.--31. 1. " SW_PP_IN_LU_BASE ,Base address for post-processing input luminance picture" line.long 0x0C "SWREG64,Base Address For Reading Post-Processing Input Picture Cb/Ch" hexmask.long 0x0C 2.--31. 1. " SW_PP_IN_CB_BASE ,Base address for post-processing input Cb picture or for both chrominance pictures" line.long 0x10 "SWREG65,Base Address For Reading Post-Processing Input Picture Cr" hexmask.long 0x10 2.--31. 1. " SW_PP_IN_CR_BASE ,Base address for post-processing input cr picture" line.long 0x14 "SWREG66,Base Address For Writing Post-Processed Picture Luminance/RGB" line.long 0x18 "SWREG67,Base Address For Writing Post-Processed Picture Ch" line.long 0x1C "SWREG68,Register For Contrast Adjusting" hexmask.long.byte 0x1C 24.--31. 1. " SW_CONTRAST_THR1 ,Threshold value 1 used with contrast adjusting" hexmask.long.word 0x1C 10.--19. 0x04 " SW_CONTRAST_OFF2 ,Offset value 2 used with contrast adjusting" line.long 0x20 "SWREG69,Register For Colour Conversion And Contrast Adjusting/8190 YUYV 422 Channel Orders" bitfld.long 0x20 31. " SW_PP_IN_START_CH ,YUYV 422 input format channel order enabled for start_with_chrominance" "Y0CbY0Cr||Y0CrY0Cb,CbY0CrY0||CrY0CbY0" bitfld.long 0x20 30. " SW_PP_IN_CR_FIRST ,YUYV 422 input format channel order enabled for Cr first (before Cb)" "Y0CbY0Cr||CbY0CrY0,Y0CrY0Cb||CrY0CbY0" bitfld.long 0x20 29. " SW_PP_OUT_START_CH ,YUYV 422 output format channel order enabled for start_with_chrominance" "Y0CbY0Cr||Y0CrY0Cb,CbY0CrY0||CrY0CbY0" textline " " bitfld.long 0x20 28. " SW_PP_IN_CR_FIRST ,YUYV 422 output format channel order enabled for Cr first (before Cb)" "Y0CbY0Cr||CbY0CrY0,Y0CrY0Cb||CrY0CbY0" hexmask.long.word 0x20 18.--27. 1. " SW_COLOR_COEFFA2 ,Coefficient a2 used with Y pixel to calculate all color components" hexmask.long.word 0x20 8.--17. 1. " SW_COLOR_COEFFA1 ,Coefficient a1 used with Y pixel to calculate all color components" textline " " hexmask.long.byte 0x20 0.--7. 1. " SW_CONTRAST_THR2 ,Threshold value 2 used with contrast adjusting" line.long 0x24 "SWREG70,Register For Colour Conversion 0" bitfld.long 0x24 30.--31. " SW_PP_OUT_H_EXT ,Extended output height for 4k resolution" "0,1,2,3" hexmask.long.word 0x24 20.--29. 1. " SW_COLOR_COEFFD ,Coefficient d used with Cb to calculate green component value" hexmask.long.word 0x24 10.--19. 1. " SW_COLOR_COEFFC ,Coefficient c used with Cr to calculate green component value" textline " " hexmask.long.word 0x24 0.--9. 1. " SW_COLOR_COEFFB ,Coefficient b used with Cr to calculate red component value" line.long 0x28 "SWREG71,Register For Colour Conversion 1 + Rotation Mode" bitfld.long 0x28 30.--31. " SW_PP_OUT_W_EXT ,Extended output width for 4k resolution" "0,1,2,3" hexmask.long.word 0x28 21.--29. 1. " SW_CROP_STARTX ,Start coordinate x for the cropped area in macro blocks" bitfld.long 0x28 18.--20. " SW_ROTATION_MODE ,Rotation mode" "Disabled,Rotate + 90,Rotate - 90,Horizontal flip,Vertical flip,Rotate 180,?..." textline " " hexmask.long.byte 0x28 10.--17. 1. " SW_COLOR_COEFFF ,Coefficient f used with Y to adjust brightness" hexmask.long.word 0x28 0.--9. 1. " SW_COLOR_COEFFE ,Coefficient e used with Cb to calculate blue component value" line.long 0x2C "SWREG72,PP Input Size And - Cropping Register" hexmask.long.byte 0x2C 24.--31. 1. " SW_CROP_STARTY ,Start coordinate y for the cropped area in macro blocks" bitfld.long 0x2C 18.--22. " SW_RANGEMAP_COEF_Y ,Range map value for Y component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x2C 9.--16. 1. " SW_PP_IN_HEIGHT ,PP input picture height in MBs" textline " " hexmask.long.word 0x2C 0.--8. 1. " SW_PP_IN_WIDTH ,PP input picture width in MBs" line.long 0x30 "SWREG73,PP Input Picture Base Address For Y Bottom Field" hexmask.long 0x30 2.--31. 1. " SW_PP_BOT_YIN_BASE ,PP input Y base for bottom field" line.long 0x34 "SWREG74,PP Input Picture Base For Ch Bottom Field" hexmask.long 0x34 2.--31. 1. " SW_PP_BOT_CIN_BASE ,PP input C base for bottom field" if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x40000000))) group.long 0x13C++0x03 line.long 0x00 "SWREG79,Scaling Register 0 Ratio And Padding For R And G" bitfld.long 0x00 31. " SW_RANGEMAP_Y_E ,Range expansion enable" "Disabled,Enabled" bitfld.long 0x00 30. " RANGE_MAPUV_FLAG ,Range map enable for chrominance component" "Disabled,Enabled" bitfld.long 0x00 29. " SW_YCBCR_RANGE ,Defines the YCbCr range in RGB conversion" "16...235 for Y|16...240 for Chrominance,0...255" textline " " bitfld.long 0x00 28. " SW_RGB_PIX_IN32 ,RGB pixel amount/ 32 bit word" "1 RGB pixel/32 bit,2 RGB pixels/32 bit" bitfld.long 0x00 23.--27. " SW_RGB_R_PADD ,Amount of ones that will be padded in front of the R-component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18.--22. " SW_RGB_G_PADD ,Amount of ones that will be padded in front of the G-component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x00 0.--17. 1. " SW_SCALE_WRATIO ,Scaling ratio for width (outputw-1/inputw-1)" else group.long 0x13C++0x03 line.long 0x00 "SWREG79,Scaling Register 0 Ratio And Padding For R And G" bitfld.long 0x00 31. " SW_RANGEMAP_Y_E ,Range map enable for Y component" "Disabled,Enabled" bitfld.long 0x00 30. " SW_RANGEMAP_C_E ,Range map enable for chrominance component" "Disabled,Enabled" bitfld.long 0x00 29. " SW_YCBCR_RANGE ,Defines the YCbCr range in RGB conversion" "16...235 for Y|16...240 for Chrominance,0...255" textline " " bitfld.long 0x00 28. " SW_RGB_PIX_IN32 ,RGB pixel amount/ 32 bit word" "1 RGB pixel/32 bit,2 RGB pixels/32 bit" bitfld.long 0x00 23.--27. " SW_RGB_R_PADD ,Amount of ones that will be padded in front of the R-component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18.--22. " SW_RGB_G_PADD ,Amount of ones that will be padded in front of the G-component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x00 0.--17. 1. " SW_SCALE_WRATIO ,Scaling ratio for width (outputw-1/inputw-1)" endif group.long 0x140++0x13 line.long 0x00 "SWREG80,Scaling Ratio Register 1 And Padding For B" bitfld.long 0x00 30. " SW_PP_FAST_SCALE_E ,Fast downscaling enable" "Disabled,Enabled" bitfld.long 0x00 27.--29. " SW_PP_IN_STRUCT ,PP input data picture structure" "Top field/Progressive frame,Bottom field,Interlaced field,Interlaced frame,Ripped top field,Ripped bottom field,?..." bitfld.long 0x00 25.--26. " SW_HOR_SCALE_MODE ,Horizontal scaling mode" "Off,Upscale,Downscale,?..." textline " " bitfld.long 0x00 23.--24. " SW_VER_SCALE_MODE ,Vertical scaling mode" "Off,Upscale,Downscale,?..." bitfld.long 0x00 18.--22. " SW_RGB_B_PADD ,Amount of ones that will be padded in front of the B-component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 0.--17. 1. " SW_SCALE_HRATIO ,Scaling ratio for height (outputh-1/inputh-1)" line.long 0x04 "SWREG81,Scaling Ratio Register 2" hexmask.long.word 0x04 16.--31. 1. " SW_WSCALE_INVRA ,Inverse scaling ratio for width or ch (inputw-1 / outputw-1)" hexmask.long.word 0x04 0.--15. 1. " SW_HSCALE_INVRA ,Inverse scaling ratio for height or cv (inputh-1 / outputh-1)" line.long 0x08 "SWREG82,Rmask Register" line.long 0x0C "SWREG83,Gmask Register" line.long 0x10 "SWREG84,Bmask Register" textline " " if (((per.l(ad:0x38300000+0xF0)&0x03)==0x01)) group.long 0x154++0x03 line.long 0x00 "SWREG85,Post-Processor Control Register" bitfld.long 0x00 29.--31. " SW_PP_IN_FORMAT ,PP input picture data format" "YUYV 4:2:2 interleaved,YCbCr 4:2:0 Semi-planar in linear raster-scan format,YCbCr 4:2:0 planar,,,YCbCr 4:2:0 Semi-planar in tiled format,,Escape pp input data format" bitfld.long 0x00 26.--28. " SW_PP_OUT_FORMAT ,PP output picture data format" "RGB,YCbCr 4:2:0 planar,YCbCr 4:2:2 planar,YUYV 4:2:2 interleaved,YCbCr 4:4:4 planar,YCh 4:2:0 chrominance interleaved,YCh 4:2:2,YCh 4:4:4" textline " " hexmask.long.word 0x00 15.--25. 1. " SW_PP_OUT_HEIGHT ,Scaled picture height in pixels" hexmask.long.word 0x00 4.--14. 1. " SW_PP_OUT_WIDTH ,Scaled picture width in pixels" textline " " bitfld.long 0x00 3. " SW_PP_OUT_TILED_E ,Tiled mode enable for PP output" "Disabled,Enabled" bitfld.long 0x00 2. " SW_PP_OUT_SWAP16_E ,PP output swap 16 swaps 16 bit half's inside of 32 bit word" "Not swapped,Swapped" textline " " bitfld.long 0x00 1. " SW_PP_CROP8_R_E ,PP input picture width is not 16 pixels multiple" "Disabled,Enabled" bitfld.long 0x00 0. " SW_PP_CROP8_D_E ,PP input picture height is not 16 pixels multiple" "Disabled,Enabled" elif (((per.l(ad:0x38300000+0xF0)&0x03)==0x02)) if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x30000000))) group.long 0x154++0x03 line.long 0x00 "SWREG85,Post-Processor Control Register" bitfld.long 0x00 29.--31. " SW_PP_IN_FORMAT ,PP input picture data format" ",YCbCr 4:2:0 Semi-planar in linear raster-scan format,,YCbCr 4:0:0,YCbCr 4:2:2 Semi-planar,,YCbCr 4:4:0 Semi-planar,Escape pp input data format" bitfld.long 0x00 26.--28. " SW_PP_OUT_FORMAT ,PP output picture data format" "RGB,YCbCr 4:2:0 planar,YCbCr 4:2:2 planar,YUYV 4:2:2 interleaved,YCbCr 4:4:4 planar,YCh 4:2:0 chrominance interleaved,YCh 4:2:2,YCh 4:4:4" textline " " hexmask.long.word 0x00 15.--25. 1. " SW_PP_OUT_HEIGHT ,Scaled picture height in pixels" hexmask.long.word 0x00 4.--14. 1. " SW_PP_OUT_WIDTH ,Scaled picture width in pixels" textline " " bitfld.long 0x00 3. " SW_PP_OUT_TILED_E ,Tiled mode enable for PP output" "Disabled,Enabled" bitfld.long 0x00 2. " SW_PP_OUT_SWAP16_E ,PP output swap 16 swaps 16 bit half's inside of 32 bit word" "Not swapped,Swapped" textline " " bitfld.long 0x00 1. " SW_PP_CROP8_R_E ,PP input picture width is not 16 pixels multiple" "Disabled,Enabled" bitfld.long 0x00 0. " SW_PP_CROP8_D_E ,PP input picture height is not 16 pixels multiple" "Disabled,Enabled" else group.long 0x154++0x03 line.long 0x00 "SWREG85,Post-Processor Control Register" bitfld.long 0x00 29.--31. " SW_PP_IN_FORMAT ,PP input picture data format" ",YCbCr 4:2:0 Semi-planar in linear raster-scan format,,YCbCr 4:0:0,YCbCr 4:2:2 Semi-planar,,,Escape pp input data format" bitfld.long 0x00 26.--28. " SW_PP_OUT_FORMAT ,PP output picture data format" "RGB,YCbCr 4:2:0 planar,YCbCr 4:2:2 planar,YUYV 4:2:2 interleaved,YCbCr 4:4:4 planar,YCh 4:2:0 chrominance interleaved,YCh 4:2:2,YCh 4:4:4" textline " " hexmask.long.word 0x00 15.--25. 1. " SW_PP_OUT_HEIGHT ,Scaled picture height in pixels" hexmask.long.word 0x00 4.--14. 1. " SW_PP_OUT_WIDTH ,Scaled picture width in pixels" textline " " bitfld.long 0x00 3. " SW_PP_OUT_TILED_E ,Tiled mode enable for PP output" "Disabled,Enabled" bitfld.long 0x00 2. " SW_PP_OUT_SWAP16_E ,PP output swap 16 swaps 16 bit half's inside of 32 bit word" "Not swapped,Swapped" textline " " bitfld.long 0x00 1. " SW_PP_CROP8_R_E ,PP input picture width is not 16 pixels multiple" "Disabled,Enabled" bitfld.long 0x00 0. " SW_PP_CROP8_D_E ,PP input picture height is not 16 pixels multiple" "Disabled,Enabled" endif elif (((per.l(ad:0x38300000+0xF0)&0x03)==0x03)) if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x30000000))) group.long 0x154++0x03 line.long 0x00 "SWREG85,Post-Processor Control Register" bitfld.long 0x00 29.--31. " SW_PP_IN_FORMAT ,PP input picture data format" "YUYV 4:2:2 interleaved,YCbCr 4:2:0 Semi-planar in linear raster-scan format,YCbCr 4:2:0 planar,YCbCr 4:0:0,YCbCr 4:2:2 Semi-planar,YCbCr 4:2:0 Semi-planar in tiled format,YCbCr 4:4:0 Semi-planar,Escape pp input data format" bitfld.long 0x00 26.--28. " SW_PP_OUT_FORMAT ,PP output picture data format" "RGB,YCbCr 4:2:0 planar,YCbCr 4:2:2 planar,YUYV 4:2:2 interleaved,YCbCr 4:4:4 planar,YCh 4:2:0 chrominance interleaved,YCh 4:2:2,YCh 4:4:4" textline " " hexmask.long.word 0x00 15.--25. 1. " SW_PP_OUT_HEIGHT ,Scaled picture height in pixels" hexmask.long.word 0x00 4.--14. 1. " SW_PP_OUT_WIDTH ,Scaled picture width in pixels" textline " " bitfld.long 0x00 3. " SW_PP_OUT_TILED_E ,Tiled mode enable for PP output" "Disabled,Enabled" bitfld.long 0x00 2. " SW_PP_OUT_SWAP16_E ,PP output swap 16 swaps 16 bit half's inside of 32 bit word" "Not swapped,Swapped" textline " " bitfld.long 0x00 1. " SW_PP_CROP8_R_E ,PP input picture width is not 16 pixels multiple" "Disabled,Enabled" bitfld.long 0x00 0. " SW_PP_CROP8_D_E ,PP input picture height is not 16 pixels multiple" "Disabled,Enabled" else group.long 0x154++0x03 line.long 0x00 "SWREG85,Post-Processor Control Register" bitfld.long 0x00 29.--31. " SW_PP_IN_FORMAT ,PP input picture data format" "YUYV 4:2:2 interleaved,YCbCr 4:2:0 Semi-planar in linear raster-scan format,YCbCr 4:2:0 planar,YCbCr 4:0:0,YCbCr 4:2:2 Semi-planar,YCbCr 4:2:0 Semi-planar in tiled format,,Escape pp input data format" bitfld.long 0x00 26.--28. " SW_PP_OUT_FORMAT ,PP output picture data format" "RGB,YCbCr 4:2:0 planar,YCbCr 4:2:2 planar,YUYV 4:2:2 interleaved,YCbCr 4:4:4 planar,YCh 4:2:0 chrominance interleaved,YCh 4:2:2,YCh 4:4:4" textline " " hexmask.long.word 0x00 15.--25. 1. " SW_PP_OUT_HEIGHT ,Scaled picture height in pixels" hexmask.long.word 0x00 4.--14. 1. " SW_PP_OUT_WIDTH ,Scaled picture width in pixels" textline " " bitfld.long 0x00 3. " SW_PP_OUT_TILED_E ,Tiled mode enable for PP output" "Disabled,Enabled" bitfld.long 0x00 2. " SW_PP_OUT_SWAP16_E ,PP output swap 16 swaps 16 bit half's inside of 32 bit word" "Not swapped,Swapped" textline " " bitfld.long 0x00 1. " SW_PP_CROP8_R_E ,PP input picture width is not 16 pixels multiple" "Disabled,Enabled" bitfld.long 0x00 0. " SW_PP_CROP8_D_E ,PP input picture height is not 16 pixels multiple" "Disabled,Enabled" endif else group.long 0x154++0x03 line.long 0x00 "SWREG85,Post-Processor Control Register" bitfld.long 0x00 29.--31. " SW_PP_IN_FORMAT ,PP input picture data format" ",YCbCr 4:2:0 Semi-planar in linear raster-scan format,,,,,,Escape pp input data format" bitfld.long 0x00 26.--28. " SW_PP_OUT_FORMAT ,PP output picture data format" "RGB,YCbCr 4:2:0 planar,YCbCr 4:2:2 planar,YUYV 4:2:2 interleaved,YCbCr 4:4:4 planar,YCh 4:2:0 chrominance interleaved,YCh 4:2:2,YCh 4:4:4" textline " " hexmask.long.word 0x00 15.--25. 1. " SW_PP_OUT_HEIGHT ,Scaled picture height in pixels" hexmask.long.word 0x00 4.--14. 1. " SW_PP_OUT_WIDTH ,Scaled picture width in pixels" textline " " bitfld.long 0x00 3. " SW_PP_OUT_TILED_E ,Tiled mode enable for PP output" "Disabled,Enabled" bitfld.long 0x00 2. " SW_PP_OUT_SWAP16_E ,PP output swap 16 swaps 16 bit half's inside of 32 bit word" "Not swapped,Swapped" textline " " bitfld.long 0x00 1. " SW_PP_CROP8_R_E ,PP input picture width is not 16 pixels multiple" "Disabled,Enabled" bitfld.long 0x00 0. " SW_PP_CROP8_D_E ,PP input picture height is not 16 pixels multiple" "Disabled,Enabled" endif textline " " group.long 0x158++0x13 line.long 0x00 "SWREG86,Mask 1 Start Coordinate Register" bitfld.long 0x00 29.--31. " SW_PP_IN_FORMAT_ES ,Escape PP in format" "YCbCr 4:4:4,YCbCr 4:1:1,?..." bitfld.long 0x00 28. " SW_PP_VC1_ADV_E ,VC1 advanced profile enable" "Disabled,Enabled" bitfld.long 0x00 23.--27. " SW_RANGEMAP_COEF_C ,Range map value for chrominance component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 22. " SW_MASK1_ABLEND_E ,Mask 1 alpha blending enable" "Disabled,Enabled" hexmask.long.word 0x00 11.--21. 1. " SW_MASK1_STARTY ,Vertical start pixel for mask area 1" hexmask.long.word 0x00 0.--10. 1. " SW_MASK1_STARTX ,Horizontal start pixel for mask area 1" line.long 0x04 "SWREG87,Mask 2 Start Coordinate Register + Mask Extensions" bitfld.long 0x04 29.--30. " SW_MASK1_STARTX_EXT ,Extended coordinate up to 4k resolution" "0,1,2,3" bitfld.long 0x04 27.--28. " SW_MASK1_STARTY_EXT ,Extended coordinate up to 4k resolution" "0,1,2,3" bitfld.long 0x04 25.--26. " SW_MASK2_STARTX_EXT ,Extended coordinate up to 4k resolution" "0,1,2,3" textline " " bitfld.long 0x04 23.--24. " SW_MASK2_STARTY_EXT ,Extended coordinate up to 4k resolution" "0,1,2,3" bitfld.long 0x04 22. " SW_MASK2_ABLEND_E ,Mask 2 alpha blending enable" "Disabled,Enabled" hexmask.long.word 0x04 11.--21. 1. " SW_MASK2_STARTY ,Vertical start pixel for mask area 2" textline " " hexmask.long.word 0x04 0.--10. 1. " SW_MASK2_STARTX ,Horizontal start pixel for mask area 2" line.long 0x08 "SWREG88,Mask 1 Size And PP Original Width Register" hexmask.long.word 0x08 23.--31. 1. " SW_EXT_ORIG_WIDTH ,PP input picture original width in macro blocks" bitfld.long 0x08 22. " SW_MASK1_E ,Mask 1 enable" "Disabled,Enabled" hexmask.long.word 0x08 11.--21. 1. " SW_MASK1_ENDY ,Mask 1 end coordinate y in pixels" textline " " hexmask.long.word 0x08 0.--10. 1. " SW_MASK1_ENDX ,Mask 1 end coordinate x in pixels" line.long 0x0C "SWREG89,Mask 2 Size Register + Mask Extensions" bitfld.long 0x0C 29.--30. " SW_MASK1_ENDX_EXT ,Extended coordinate up to 4k resolution" "0,1,2,3" bitfld.long 0x0C 27.--28. " SW_MASK1_ENDY_EXT ,Extended coordinate up to 4k resolution" "0,1,2,3" bitfld.long 0x0C 25.--26. " SW_MASK2_ENDX_EXT ,Extended coordinate up to 4k resolution" "0,1,2,3" textline " " bitfld.long 0x0C 23.--24. " SW_MASK2_ENDY_EXT ,Extended coordinate up to 4k resolution" "0,1,2,3" bitfld.long 0x0C 22. " SW_MASK2_E ,Mask 2 enable" "Disabled,Enabled" hexmask.long.word 0x0C 11.--21. 1. " SW_MASK2_ENDY ,Mask 2 end coordinate y in pixels" textline " " hexmask.long.word 0x0C 0.--10. 1. " SW_MASK2_ENDX ,Mask 2 end coordinate x in pixels" line.long 0x10 "SWREG90,PiP Register 0" bitfld.long 0x10 29. " SW_RIGHT_CROSS_E ,Right side over-cross enable" "Disabled,Enabled" bitfld.long 0x10 28. " SW_LEFT_CROSS_E ,Left side over-cross enable" "Disabled,Enabled" bitfld.long 0x10 27. " SW_UP_CROSS_E ,Upward over-cross enable" "Disabled,Enabled" textline " " bitfld.long 0x10 26. " SW_DOWN_CROSS_E ,Downward over-cross enable" "Disabled,Enabled" hexmask.long.word 0x10 15.--25. 1. " SW_UP_CROSS ,Amount of upward over-cross" bitfld.long 0x10 11.--12. " SW_DOWN_CROSS_EXT ,Extended coordinate for 4k resolution" "0,1,2,3" textline " " hexmask.long.word 0x10 0.--10. 1. " SW_DOWN_CROSS ,Amount of downward over-cross" if (((per.l(ad:0x38300000+0xF0)&0x03)==(0x01||0x02||0x03))) group.long 0x16C++0x03 line.long 0x00 "SWREG91,PiP Register 1 And Dithering Control" bitfld.long 0x00 30.--31. " SW_DITHER_SELECT_R ,Dithering control for R channel" "Disabled,Four-bit dither matrix,Five-bit dither matrix,Six-bit dither matrix" bitfld.long 0x00 28.--29. " SW_DITHER_SELECT_G ,Dithering control for G channel" "Disabled,Four-bit dither matrix,Five-bit dither matrix,Six-bit dither matrix" bitfld.long 0x00 26.--27. " SW_DITHER_SELECT_B ,Dithering control for B channel" "Disabled,Four-bit dither matrix,Five-bit dither matrix,Six-bit dither matrix" textline " " bitfld.long 0x00 22.--23. " SW_PP_TILED_MODE ,Input data is in tiled mode" "Disabled,Enabled,?..." hexmask.long.word 0x00 11.--21. 1. " SW_RIGHT_CROSS ,Amount of right side over-cross" hexmask.long.word 0x00 0.--10. 1. " SW_LEFT_CROSS ,Amount of left side over-cross" else group.long 0x16C++0x03 line.long 0x00 "SWREG91,PiP Register 1 And Dithering Control" bitfld.long 0x00 30.--31. " SW_DITHER_SELECT_R ,Dithering control for R channel" "Disabled,Four-bit dither matrix,Five-bit dither matrix,Six-bit dither matrix" bitfld.long 0x00 28.--29. " SW_DITHER_SELECT_G ,Dithering control for G channel" "Disabled,Four-bit dither matrix,Five-bit dither matrix,Six-bit dither matrix" bitfld.long 0x00 26.--27. " SW_DITHER_SELECT_B ,Dithering control for B channel" "Disabled,Four-bit dither matrix,Five-bit dither matrix,Six-bit dither matrix" textline " " hexmask.long.word 0x00 11.--21. 1. " SW_RIGHT_CROSS ,Amount of right side over-cross" hexmask.long.word 0x00 0.--10. 1. " SW_LEFT_CROSS ,Amount of left side over-cross" endif group.long 0x170++0x0F line.long 0x00 "SWREG92,Display Width And PP Input Size Extension Register" bitfld.long 0x00 29.--31. " SW_PP_IN_H_EXT ,Extended PP input height" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. " SW_PP_IN_W_EXT ,Extended PP input width" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. " SW_CROP_STARTY_EXT ,Extended PP input crop start coordinate x" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20.--22. " SW_CROP_STARTX_EXT ,Extended PP input crop start coordinate y" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " SW_RIGHT_CROSS_EXT ,Extended coordinate for 4k resolution" "0,1,2,3" bitfld.long 0x00 16.--17. " SW_LEFT_CROSS_EXT ,Extended coordinate for 4k resolution" "0,1,2,3" textline " " bitfld.long 0x00 14.--15. " SW_UP_CROSS_EXT ,Extended coordinate for 4k resolution" "0,1,2,3" hexmask.long.word 0x00 0.--12. 1. " SW_DISPLAY_WIDTH ,Width of the display in pixels" line.long 0x04 "SWREG93,Base Address For Alpha Blend 1 Gui Component" line.long 0x08 "SWREG94,Base Address For Alpha Blend 2 Gui Component" line.long 0x0C "SWREG95,Alpha Blend Input Cropping Register" hexmask.long.word 0x0C 13.--25. 1. " SW_ABLEND2_SCANL ,Scan line width in pixels for Ablend 2" hexmask.long.word 0x0C 0.--12. 1. " SW_ABLEND1_SCANL ,Scan line width in pixels for Ablend 1" textline " " rgroup.long 0x18C++0x07 line.long 0x00 "SWREG99,PP Fuse Register" bitfld.long 0x00 31. " FUSE_PP_PP ,PP enable" "Disabled,Enabled" bitfld.long 0x00 30. " FUSE_PP_DEINT ,De-interlacing enable" "Disabled,Enabled" bitfld.long 0x00 29. " FUSE_PP_ABLEND ,Alpha blending enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " FUSE_PP_MAXW_4K ,Max PP output width up to 4096 pixels enable" "Disabled,Enabled" bitfld.long 0x00 15. " FUSE_PP_MAXW_1920 ,Max PP output width up to 1920 pixels enable" "Disabled,Enabled" bitfld.long 0x00 14. " FUSE_PP_MAXW_1280 ,Max PP output width up to 1280 pixels enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " FUSE_PP_MAXW_720 ,Max PP output width up to 720 pixels enable" "Disabled,Enabled" bitfld.long 0x00 12. " FUSE_PP_MAXW_352 ,Max PP output width up to 352 pixels enable" "Disabled,Enabled" textline " " line.long 0x04 "SWREG100,Synthesis Configuration Register Post-Processor" bitfld.long 0x04 31. " SW_ABLEND_CROP_E ,Alpha blending support for input cropping" "Not supported,Supported" bitfld.long 0x04 30. " SW_PPD_PIXAC_E ,Scaling and masks value of adjusted steps" "8pix(width)||2pix(height),1pix for RGB && 2pix for subsampled chroma formats" textline " " bitfld.long 0x04 29. " SW_PPD_TILED_EXIST ,PP output YCbYCr 422 tiled support" "Not supported,Supported" bitfld.long 0x04 28. " SW_PPD_DITH_EXIST ,Dithering exists" "Not exist,Exist" textline " " bitfld.long 0x04 26.--27. " SW_PPD_SCALE_LEVEL ,Scaling support" "Disabled,With low performance architecture,With high performance architecture,With high performance architecture + fast downscaling" bitfld.long 0x04 25. " SW_PPD_DEINT_EXIST ,De-interlacing exits" "Not exist,Exist" textline " " bitfld.long 0x04 24. " SW_PPD_BLEND_EXIST ,Alpha blending exists" "Not exist,Exist" bitfld.long 0x04 23. " SW_PPD_IBUFF_LEVEL ,PP input buffering level" "1MB,4MB" textline " " bitfld.long 0x04 18. " SW_PPD_OEN_VERSION ,PP output endian version" "Endian for other than RGB,Endian for any output format" bitfld.long 0x04 17. " SW_PPD_OBUFF_LEVEL ,PP output buffering level" "1 unit,4 unit" textline " " bitfld.long 0x04 16. " SW_PPD_PP_EXIST ,PPD exists" "Not exist,Exist" bitfld.long 0x04 14.--15. " SW_PPD_IN_TILED_L ,PPD input tiled mode support level" "Not supported,8x4 tile size supported,?..." textline " " hexmask.long.word 0x04 0.--12. 1. " SW_PPD_MAX_OWIDTH ,Max supported PP output width in pixels" textline " " if (((per.l(ad:0x38300000+0x0C)&0xF0000000)==(0x00||0x10000000||0xB0000000))) group.long 0x198++0x03 line.long 0x00 "SWREG102,Base Address For H264 And AVS Decoded Chroma Picture" hexmask.long 0x00 2.--31. 1. " SW_DEC_CH_BASE ,Base address for decoder output chroma picture" bitfld.long 0x00 0. " SW_CH_BASE_E ,Chroma address separate mode enable" "Disabled,Enabled" group.long 0x19C++0x03 line.long 0x00 "SWREG103,Base Address For Reference Chroma Picture Index 0" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 0" group.long 0x1A0++0x03 line.long 0x00 "SWREG104,Base Address For Reference Chroma Picture Index 1" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 1" group.long 0x1A4++0x03 line.long 0x00 "SWREG105,Base Address For Reference Chroma Picture Index 2" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 2" group.long 0x1A8++0x03 line.long 0x00 "SWREG106,Base Address For Reference Chroma Picture Index 3" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 3" group.long 0x1AC++0x03 line.long 0x00 "SWREG107,Base Address For Reference Chroma Picture Index 4" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 4" group.long 0x1B0++0x03 line.long 0x00 "SWREG108,Base Address For Reference Chroma Picture Index 5" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 5" group.long 0x1B4++0x03 line.long 0x00 "SWREG109,Base Address For Reference Chroma Picture Index 6" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 6" group.long 0x1B8++0x03 line.long 0x00 "SWREG110,Base Address For Reference Chroma Picture Index 7" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 7" group.long 0x1BC++0x03 line.long 0x00 "SWREG111,Base Address For Reference Chroma Picture Index 8" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 8" group.long 0x1C0++0x03 line.long 0x00 "SWREG112,Base Address For Reference Chroma Picture Index 9" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 9" group.long 0x1C4++0x03 line.long 0x00 "SWREG113,Base Address For Reference Chroma Picture Index 10" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 10" group.long 0x1C8++0x03 line.long 0x00 "SWREG114,Base Address For Reference Chroma Picture Index 11" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 11" group.long 0x1CC++0x03 line.long 0x00 "SWREG115,Base Address For Reference Chroma Picture Index 12" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 12" group.long 0x1D0++0x03 line.long 0x00 "SWREG116,Base Address For Reference Chroma Picture Index 13" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 13" group.long 0x1D4++0x03 line.long 0x00 "SWREG117,Base Address For Reference Chroma Picture Index 14" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 14" group.long 0x1D8++0x03 line.long 0x00 "SWREG118,Base Address For Reference Chroma Picture Index 15" hexmask.long 0x00 2.--31. 1. " SW_REFER0_CH_BASE ,Base address for reference chroma picture index 15" endif width 0x0B tree.end tree "VPU_G2" base ad:0x38310000 width 10. rgroup.long 0x00++0x03 line.long 0x00 "SWREG0,ID Register" hexmask.long.word 0x00 16.--31. 1. " SW_PRODUCT_NUMBER ,Product number" bitfld.long 0x00 12.--15. " SW_MAJOR_VERSION ,Major version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 4.--11. 1. " SW_MINOR_VERSION ,Minor version" bitfld.long 0x00 3. " SW_PRODUCT_ID_EN ,ASCII type product ID enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--2. " SW_BUILD_VERSION ,Build version" "0,1,2,3,4,5,6,7" group.long 0x04++0x2F line.long 0x00 "SWREG1,Interrupt Register Decoder" bitfld.long 0x00 18. " SW_DEC_TIMEOUT ,Interrupt status bit decoder timeout" "No interrupt,Interrupt" bitfld.long 0x00 16. " SW_DEC_ERROR_INT ,Interrupt status bit input stream error" "No interrupt,Interrupt" bitfld.long 0x00 14. " SW_DEC_BUFFER_INT ,Interrupt status bit input buffer empty" "No interrupt,Interrupt" bitfld.long 0x00 13. " SW_DEC_BUS_INT ,Interrupt status bit bus" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " SW_DEC_RDY_INT ,Interrupt status bit decoder" "No interrupt,Interrupt" bitfld.long 0x00 11. " SW_DEC_ABORT_INT ,Interrupt status bit decoding aborted" "No interrupt,Interrupt" bitfld.long 0x00 8. " SW_DEC_IRQ ,Decoder IRQ" "No interrupt,Interrupt" bitfld.long 0x00 5. " SW_DEC_ABORT_E ,Abort decoding enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SW_DEC_IRQ_DIS ,Decoder IRQ disable" "No,Yes" bitfld.long 0x00 0. " SW_DEC_E ,Decoder enable" "Disabled,Enabled" textline " " line.long 0x04 "SWREG2,Data Configuration Register Decoder" bitfld.long 0x04 28.--31. " SW_DEC_STRM_SWAP ,Byte swap configuration for stream data 4 Bit byte order vector to control byte locations inside HW internal 128 bit data vector" "0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15,1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14,2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13,3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12,4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11,,,7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8,8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7,,,,,,,15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0" bitfld.long 0x04 24.--27. " SW_DEC_PIC_SWAP ,Byte swap configuration for decoder reference output picture data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 20.--23. " SW_DEC_DIRMV_SWAP ,Byte swap configuration for direct mode MV data (read/write)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " SW_DEC_TAB0_SWAP ,Byte swap configuration for VP9 stream probability tables" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 12.--15. " SW_DEC_TAB1_SWAP ,Byte swap configuration for HEVC scaling lists" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " SW_DEC_TAB2_SWAP ,Byte swap configuration for VP9 CTX counter values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 4.--7. " SW_DEC_TAB3_SWAP ,Byte swap configuration for tile sizes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " SW_DEC_RSCAN_SWAP ,Byte swap for raster scan output picture data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " line.long 0x08 "SWREG3,Decoder Control Register 0" bitfld.long 0x08 27.--31. " SW_DEC_MODE ,Decoding mode" ",,,,,,,,,,,,HEVC,VP9,?..." bitfld.long 0x08 20.--23. " SW_DEC_COMP_TABLE_SWAP ,Byte swap configuration for compress table data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 17. " SW_DEC_OUT_EC_BYPASS ,Compress bypass" "Not compressed,Compressed" textline " " bitfld.long 0x08 16. " SW_DEC_OUT_RS_E ,Raster scan output enable" "Disabled,Enabled" bitfld.long 0x08 15. " SW_DEC_OUT_DIS ,Disable decoder output picture writing" "No,Yes" bitfld.long 0x08 14. " SW_FILTERING_DIS ,De-block filtering disable" "No,Yes" textline " " bitfld.long 0x08 12. " SW_WRITE_MVS_E ,Direct mode motion vector write enable for current picture" "Disabled,Enabled" bitfld.long 0x08 11. " SW_APF_ONE_PID ,Prefetch partitions that have the same pic_id together" "Not prefetched,Prefetched" line.long 0x0C "SWREG4,Decoder Control Register 1" hexmask.long.word 0x0C 19.--31. 1. " SW_PIC_WIDTH_IN_CBS ,Picture width in min coded blocks" hexmask.long.word 0x0C 6.--18. 1. " SW_PIC_HEIGHT_IN_CBS ,Picture height in min coded blocks" bitfld.long 0x0C 0.--4. " SW_REF_FRAMES ,Num_ref_frames maximum number of short and long term reference frames in decoded picture buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "SWREG5,Decoder Control Register 2" hexmask.long.byte 0x10 25.--31. 1. " SW_STRM_START_BIT ,Exact bit of stream start word where decoding can be started" bitfld.long 0x10 24. " SW_SCALING_LIST_E ,Scaling matrix enable" "Disabled,Enabled" hexmask.long.byte 0x10 19.--23. 0x08 " SW_CH_QP_OFFSET ,Chroma Qp filter offset" textline " " hexmask.long.byte 0x10 14.--18. 0x40 " SW_CH_QP_OFFSET2 ,Chroma Qp filter offset for cr type" bitfld.long 0x10 12. " SW_SIGN_DATA_HIDE ,Flag for stream decoding" "Not occurred,Occurred" bitfld.long 0x10 11. " SW_TEMPOR_MVP_E ,Temporal mvp enable" "Disabled,Enabled" textline " " bitfld.long 0x10 5.--10. " SW_MAX_CU_QPD_DEPTH ,Max CU qp delta depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 4. " SW_CU_QPD_E ,CU qp delta enable" "Disabled,Enabled" line.long 0x14 "SWREG6,Decoder Control Register 3" line.long 0x18 "SWREG7,Decoder Control Register 4" bitfld.long 0x18 31. " SW_CABAC_INIT_PRESENT ,CABAC init present enable for stream decoding" "Disabled,Enabled" bitfld.long 0x18 30. " SW_BLACKWHITE_E ,Sampling format" "4:2:0,4:0:0" bitfld.long 0x18 28. " SW_WEIGHT_PRED_E ,Weighted prediction enable for P slices" "Disabled,Enabled" textline " " bitfld.long 0x18 26.--27. " SW_WEIGHT_BIPR_IDC ,Weighted prediction specification" "Default,Explicit,?..." bitfld.long 0x18 25. " SW_FILT_SLICE_BORDER ,Filter enable over slice border" "Disabled,Enabled" bitfld.long 0x18 24. " SW_FILT_TILE_BORDER ,Filter enable over tile border" "Disabled,Enabled" textline " " bitfld.long 0x18 23. " SW_ASYM_PRED_E ,Asymmetric prediction flag for stream decoding" "Disabled,Enabled" bitfld.long 0x18 22. " SW_SAO_E ,Sample adaptive offset enable for stream decoding" "Disabled,Enabled" bitfld.long 0x18 21. " SW_PCM_FILT_DISABLE ,Disable for PCM loop filtering" "No,Yes" textline " " bitfld.long 0x18 20. " SW_SLICE_CHQP_FLAG ,Slice header flag for chroma QP present" "Not occurred,Occurred" bitfld.long 0x18 19. " SW_DEPEND_SLICE_E ,Dependent slice enable" "Disabled,Enabled" bitfld.long 0x18 18. " SW_FILT_OVERRIDE_E ,Filter override enable" "Disabled,Enabled" textline " " bitfld.long 0x18 17. " SW_STRONG_SMOOTH_E ,Strong smoothing enable" "Disabled,Enabled" hexmask.long.byte 0x18 12.--16. 0x10 " SW_FILT_OFFSET_BETA ,Filter beta offset" hexmask.long.byte 0x18 7.--11. 0x80 " SW_FILT_OFFSET_TC ,Filter tc offset" textline " " bitfld.long 0x18 6. " SW_SLICE_HDR_EXT_E ,Slice header externsion enable" "Disabled,Enabled" bitfld.long 0x18 3.--5. " SW_SLICE_HDR_EBITS ,Number of extra slice header bits" "0,1,2,3,4,5,6,7" line.long 0x1C "SWREG8,Decoder Control Register 5" bitfld.long 0x1C 31. " SW_CONST_INTRA_E ,Intra prediction use only neighbouring intra macroblocks in prediction enable" "Disabled,Enabled" bitfld.long 0x1C 30. " SW_FILT_CTRL_PRES ,Extra variables controlling characteristics of the deblocking filter are present in the slice header" "Not present,Present" bitfld.long 0x1C 16. " SW_IDR_PIC_E ,IDR picture flag" "Not occurred,Occurred" textline " " bitfld.long 0x1C 12.--15. " SW_PCM_BITDEPTH_Y ,Bit depth for PCM Y data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 8.--11. " SW_PCM_BITDEPTH_C ,Bit depth for PCM C data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 6.--7. " SW_BIT_DEPTH_Y_MINUS8 ,Bit depth of luma samples minus 8" "0,1,2,3" textline " " bitfld.long 0x1C 4.--5. " SW_BIT_DEPTH_C_MINUS8 ,Bit depth of chroma samples minus 8" "0,1,2,3" bitfld.long 0x1C 3. " SW_OUTPUT_8_BITS ,Enable rasterscan output force to 8 bit" "Disabled,Enabled" bitfld.long 0x1C 0.--2. " SW_OUTPUT_FORMAT ,Raster scan and down scale output data format" "0,1,2,3,4,5,6,7" line.long 0x20 "SWREG9,Decoder Control Register 6" bitfld.long 0x20 19.--23. " SW_REFIDX1_ACTIVE ,Maximum reference index that can be used while decoding inter predicted macro blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 14.--18. " SW_REFIDX0_ACTIVE ,Maximum reference index that can be used while decoding inter predicted macro blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x20 0.--13. 1. " SW_HDR_SKIP_LENGTH ,Length of slice header skip length" line.long 0x24 "SWREG10,Decoder Control Register 7" bitfld.long 0x24 31. " SW_START_CODE_E ,Stream start code existence indicator" "Not contains,Contains" hexmask.long.byte 0x24 24.--30. 1. " SW_INIT_QP ,Initial value for quantization parameter" bitfld.long 0x24 19.--23. " SW_NUM_TILE_COLS ,Number of tile columns in picture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x24 14.--18. " SW_NUM_TILE_ROWS ,Number of tile rows in picture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 1. " SW_TILE_ENABLE ,Tile enable" "Disabled,Enabled" bitfld.long 0x24 0. " SW_ENTR_CODE_SYNCH_E ,Entropy coding synchronization enable" "Disabled,Enabled" line.long 0x28 "SWREG11,Decoder Control Register 8" bitfld.long 0x28 27.--29. " SW_TRANSFORM_MODE ,Tranform modes" "4x4,8x8,16x16,32x32,TX mode,?..." bitfld.long 0x28 21.--23. " SW_FILT_SHARPNESS ,Filter sharpness value" "0,1,2,3,4,5,6,7" bitfld.long 0x28 19. " SW_FILT_TYPE ,Filter type" "0,1" textline " " bitfld.long 0x28 8.--10. " SW_MCOMP_FILT_TYPE ,Inter prediction filter type to stream decoder" "Eight tap smooth,Eight tap,Eight tap sharp,Bilinear,Switchable,?..." bitfld.long 0x28 7. " SW_HIGH_PREC_MV_E ,High precision MV prediction enable" "Disabled,Enabled" bitfld.long 0x28 4.--5. " SW_COMP_PRED_MODE ,Prediction comp type" "Single prediction,COMP prediction,Hybrid prediction,?..." textline " " bitfld.long 0x28 2. " SW_GREF_SIGN_BIAS ,Golden reference picture sign bias used for motion vector decoding" "Disabled,Enabled" bitfld.long 0x28 0. " SW_AREF_SIGN_BIAS ,Alternate reference picture sign bias used for motion vector decoding" "Disabled,Enabled" line.long 0x2C "SWREG12,Decoder Control Register 9" hexmask.long.word 0x2C 16.--31. 1. " SW_REFER_LTERM_E ,Long term flag for reference picture index definition" bitfld.long 0x2C 13.--15. " SW_MIN_CB_SIZE ,CodedBlock min size 2^N" ",,,8 pix,16 pix,32 pix,64 pix,?..." bitfld.long 0x2C 10.--12. " SW_MAX_CB_SIZE ,CodedBlock min size 2^N" ",,,8 pix,16 pix,32 pix,64 pix,?..." textline " " bitfld.long 0x2C 7.--9. " SW_MIN_PCM_SIZE ,PCM min size 2^N" ",,,8 pix,16 pix,32 pix,64 pix,?..." bitfld.long 0x2C 4.--6. " SW_MAX_PCM_SIZE ,PCM min size 2^N" ",,,8 pix,16 pix,32 pix,64 pix,?..." bitfld.long 0x2C 3. " SW_PCM_E ,IPCM MBs flag" "Not occurred,Occurred" textline " " bitfld.long 0x2C 2. " SW_TRANSFORM_SKIP_E ,Transform skipping flag" "Not occurred,Occurred" bitfld.long 0x2C 1. " SW_TRANSQ_BYPASS_E ,Transform bypass flag" "Not occurred,Occurred" bitfld.long 0x2C 0. " SW_REFPICLIST_MOD_E ,Refpic list reordering flag" "Not occurred,Occurred" if (((per.l(ad:0x38310000+0x0C)&0xF8000000)==0x60000000)) group.long 0x34++0x1B line.long 0x00 "SWREG13,Decoder Control Register 10" bitfld.long 0x00 13.--15. " SW_MIN_TRB_SIZE ,Transform block min size 2^N" ",,,8 pix,16 pix,32 pix,64 pix,?..." bitfld.long 0x00 10.--12. " SW_MAX_TRB_SIZE ,Transform block max size 2^N" ",,,8 pix,16 pix,32 pix,64 pix,?..." bitfld.long 0x00 7.--9. " SW_MAX_INTRA_HIERDEPTH ,Intra max hierarchy dept" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--6. " SW_MAX_INTER_HIERDEPTH ,Intra max hierarchy dept" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " SW_PARALLEL_MERGE ,Information about differential MV exist inside of coded block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SWREG14,Initial Ref Pic List Register (0-2)" bitfld.long 0x04 25.--29. " SW_INIT_RLIST_B2 ,Initial reference picture list for backward picid 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 20.--24. " SW_INIT_RLIST_F2 ,Initial reference picture list for forward picid 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15.--19. " SW_INIT_RLIST_B1 ,Initial reference picture list for backward picid 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 10.--14. " SW_INIT_RLIST_F1 ,Initial reference picture list for forward picid 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 5.--9. " SW_INIT_RLIST_B0 ,Initial reference picture list for backward picid 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " SW_INIT_RLIST_F0 ,Initial reference picture list for forward picid 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "SWREG15,Initial Ref Pic List Register (3-5)" bitfld.long 0x08 25.--29. " SW_INIT_RLIST_B5 ,Initial reference picture list for backward picid 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 20.--24. " SW_INIT_RLIST_F5 ,Initial reference picture list for forward picid 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 15.--19. " SW_INIT_RLIST_B4 ,Initial reference picture list for backward picid 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x08 10.--14. " SW_INIT_RLIST_F4 ,Initial reference picture list for forward picid 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 5.--9. " SW_INIT_RLIST_B3 ,Initial reference picture list for backward picid 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " SW_INIT_RLIST_F3 ,Initial reference picture list for forward picid 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "SWREG16,Initial Ref Pic List Register (6-8)" bitfld.long 0x0C 25.--29. " SW_INIT_RLIST_B8 ,Initial reference picture list for backward picid 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 20.--24. " SW_INIT_RLIST_F8 ,Initial reference picture list for forward picid 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 15.--19. " SW_INIT_RLIST_B7 ,Initial reference picture list for backward picid 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0C 10.--14. " SW_INIT_RLIST_F7 ,Initial reference picture list for forward picid 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 5.--9. " SW_INIT_RLIST_B6 ,Initial reference picture list for backward picid 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 0.--4. " SW_INIT_RLIST_F6 ,Initial reference picture list for forward picid 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "SWREG17,Initial Ref Pic List Register (9-11)" bitfld.long 0x10 25.--29. " SW_INIT_RLIST_B11 ,Initial reference picture list for backward picid 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 20.--24. " SW_INIT_RLIST_F11 ,Initial reference picture list for forward picid 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 15.--19. " SW_INIT_RLIST_B10 ,Initial reference picture list for backward picid 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x10 10.--14. " SW_INIT_RLIST_F10 ,Initial reference picture list for forward picid 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 5.--9. " SW_INIT_RLIST_B9 ,Initial reference picture list for backward picid 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 0.--4. " SW_INIT_RLIST_F9 ,Initial reference picture list for forward picid 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "SWREG18,Initial Ref Pic List Register (12-14)" bitfld.long 0x14 25.--29. " SW_INIT_RLIST_B14 ,Initial reference picture list for backward picid 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 20.--24. " SW_INIT_RLIST_F14 ,Initial reference picture list for forward picid 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 15.--19. " SW_INIT_RLIST_B13 ,Initial reference picture list for backward picid 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x14 10.--14. " SW_INIT_RLIST_F13 ,Initial reference picture list for forward picid 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 5.--9. " SW_INIT_RLIST_B12 ,Initial reference picture list for backward picid 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 0.--4. " SW_INIT_RLIST_F12 ,Initial reference picture list for forward picid 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "SWREG19,Initial Ref Pic List Register (15 and P 0-3)" bitfld.long 0x18 5.--9. " SW_INIT_RLIST_B15 ,Initial reference picture list for backward picid 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 0.--4. " SW_INIT_RLIST_F15 ,Initial reference picture list for forward picid 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l(ad:0x38310000+0x0C)&0xF8000000)==0x68000000)) group.long 0x34++0x1B line.long 0x00 "SWREG13,Decoder Control Register 10" bitfld.long 0x00 23.--28. " SW_QP_DELTA_Y_DC ,QP delta value for Y DC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 17.--22. " SW_QP_DELTA_CH_DC ,QP delta value for C DC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11.--16. " SW_QP_DELTA_CH_AC ,QP delta value for C AC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 10. " SW_LAST_SIGN_BIAS ,Previous reference picture sign bias for motion vector decoding" "0,1" bitfld.long 0x00 9. " SW_LOSSLESS_E ,Lossless transform enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " SW_COMP_PRED_VAR_REF1 ,Compaund prediction parameter to select correct sign bias from bin decoding" "0,1,2,3" textline " " bitfld.long 0x00 5.--6. " SW_COMP_PRED_VAR_REF0 ,Compaund prediction parameter to select correct sign bias from bin decoding" "0,1,2,3" bitfld.long 0x00 3.--4. " SW_COMP_PRED_FIXED_REF ,Compaund prediction parameter to select last picture sign bias" "0,1,2,3" bitfld.long 0x00 2. " SW_SEGMENT_TEMP_UPD_E ,Temporal segmentation update enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SW_SEGMENT_UPD_E ,Segmentation update enable" "Disabled,Enabled" bitfld.long 0x00 0. " SW_SEGMENT_E ,Segmentation enable" "Disabled,Enabled" line.long 0x04 "SWREG14,Initial Ref Pic List Register (0-2)" bitfld.long 0x04 18.--23. " SW_FILT_LEVEL ,Frame filtering level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 15.--17. " SW_REFPIC_SEG0 ,Segment refer picture" "0,1,2,3,4,5,6,7" bitfld.long 0x04 14. " SW_SKIP_SEG0 ,Segment skip enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8.--13. " SW_FILT_LEVEL_SEG0 ,Segment filter level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 0.--7. 1. " SW_QUANT_SEG0 ,Segment quantization parameter" line.long 0x08 "SWREG15,Initial Ref Pic List Register (3-5)" bitfld.long 0x08 15.--17. " SW_REFPIC_SEG1 ,Segment refer picture" "0,1,2,3,4,5,6,7" bitfld.long 0x08 14. " SW_SKIP_SEG1 ,Segment skip enable" "Disabled,Enabled" bitfld.long 0x08 8.--13. " SW_FILT_LEVEL_SEG1 ,Segment filter level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x08 0.--7. 1. " SW_QUANT_SEG1 ,Segment quantization parameter" line.long 0x0C "SWREG16,Initial Ref Pic List Register (6-8)" bitfld.long 0x0C 15.--17. " SW_REFPIC_SEG2 ,Segment refer picture" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 14. " SW_SKIP_SEG2 ,Segment skip enable" "Disabled,Enabled" bitfld.long 0x0C 8.--13. " SW_FILT_LEVEL_SEG2 ,Segment filter level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x0C 0.--7. 1. " SW_QUANT_SEG2 ,Segment quantization parameter" line.long 0x10 "SWREG17,Initial Ref Pic List Register (9-11)" bitfld.long 0x10 15.--17. " SW_REFPIC_SEG3 ,Segment refer picture" "0,1,2,3,4,5,6,7" bitfld.long 0x10 14. " SW_SKIP_SEG3 ,Segment skip enable" "Disabled,Enabled" bitfld.long 0x10 8.--13. " SW_FILT_LEVEL_SEG3 ,Segment filter level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x10 0.--7. 1. " SW_QUANT_SEG3 ,Segment quantization parameter" line.long 0x14 "SWREG18,Initial Ref Pic List Register (12-14)" bitfld.long 0x14 15.--17. " SW_REFPIC_SEG4 ,Segment refer picture" "0,1,2,3,4,5,6,7" bitfld.long 0x14 14. " SW_SKIP_SEG4 ,Segment skip enable" "Disabled,Enabled" bitfld.long 0x14 8.--13. " SW_FILT_LEVEL_SEG4 ,Segment filter level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x14 0.--7. 1. " SW_QUANT_SEG4 ,Segment quantization parameter" line.long 0x18 "SWREG19,Initial Ref Pic List Register (15 and P 0-3)" bitfld.long 0x18 15.--17. " SW_REFPIC_SEG5 ,Segment refer picture" "0,1,2,3,4,5,6,7" bitfld.long 0x18 14. " SW_SKIP_SEG5 ,Segment skip enable" "Disabled,Enabled" bitfld.long 0x18 8.--13. " SW_FILT_LEVEL_SEG5 ,Segment filter level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x18 0.--7. 1. " SW_QUANT_SEG5 ,Segment quantization parameter" endif group.long 0x50++0x03 line.long 0x00 "SWREG20,Decoder Control Register 11" bitfld.long 0x00 31. " SW_PARTIAL_CTB_X ,Picture width not multiple of CTB size" "0,1" bitfld.long 0x00 30. " SW_PARTIAL_CTB_Y ,Picture height not multiple of CTB size" "0,1" hexmask.long.word 0x00 16.--27. 1. " SW_PIC_WIDTH_4X4 ,Current picture width in 4x4 blocks" textline " " hexmask.long.word 0x00 0.--11. 1. " SW_PIC_HEIGHT_4X4 ,Current picture height in 4x4 blocks" rgroup.long 0x5C++0x03 line.long 0x00 "SWREG23,Decoder Configure Status Register" bitfld.long 0x00 12.--15. " SW_VP9_PROFILE ,VP9 version" "Profile 0,Profile 2-10bits,?..." bitfld.long 0x00 8.--11. " SW_HEVC_VERSION ,HEVC version" "Main8,Main10,?..." bitfld.long 0x00 7. " SW_MULTI_PREFETCH ,Multi-reference blocks prefetch" "Not supported,Supported" textline " " bitfld.long 0x00 6. " SW_DEC_FORMAT_CUSTOMER1_E ,Customized output format support" "Not supported,Supported" bitfld.long 0x00 5. " SW_DEC_FORMAT_P010_E ,P010 output format support" "Not supported,Supported" bitfld.long 0x00 4. " SW_DEC_64BIT_AD_E ,64 bit addressing of master interface support" "Not supported,Supported" textline " " bitfld.long 0x00 3. " SW_DOWN_SUPPORT ,Downscale support" "Not supported,Supported" bitfld.long 0x00 2. " SW_RFC_SUPPORT ,RFC support" "Not supported,Supported" bitfld.long 0x00 1. " SW_VP9_SUPPORT ,VP9 support" "Not supported,Supported" textline " " bitfld.long 0x00 0. " SW_HEVC_SUPPORT ,HEVC support" "Not supported,Supported" if (((per.l(ad:0x38310000+0x0C)&0xF8000000)==0x68000000)) group.long 0x7C++0x1F line.long 0x00 "SWREG31,VP9 Segmentation Values" bitfld.long 0x00 15.--17. " SW_REFPIC_SEG6 ,Segment refer picture" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14. " SW_SKIP_SEG6 ,Segment skip enable" "Disabled,Enabled" bitfld.long 0x00 8.--13. " SW_FILT_LEVEL_SEG6 ,Segment filter level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x00 0.--7. 1. " SW_QUANT_SEG6 ,Segment quantization parameter" line.long 0x04 "SWREG32,VP9 Segmentation Values" bitfld.long 0x04 15.--17. " SW_REFPIC_SEG7 ,Segment refer picture" "0,1,2,3,4,5,6,7" bitfld.long 0x04 14. " SW_SKIP_SEG7 ,Segment skip enable" "Disabled,Enabled" bitfld.long 0x04 8.--13. " SW_FILT_LEVEL_SEG7 ,Segment filter level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x04 0.--7. 1. " SW_QUANT_SEG7 ,Segment quantization parameter" line.long 0x08 "SWREG33,VP9 Reference Picture Scaling Register 0" hexmask.long.word 0x08 16.--31. 1. " SW_LREF_WIDTH ,Accurate width of last (previous) reference picture in pixels" hexmask.long.word 0x08 0.--15. 1. " SW_LREF_HEIGHT ,Accurate height of last (previous) reference picture in pixels" line.long 0x0C "SWREG34,VP9 Reference Picture Scaling Register 1" hexmask.long.word 0x0C 16.--31. 1. " SW_GREF_WIDTH ,Accurate width of golden reference picture in pixels" hexmask.long.word 0x0C 0.--15. 1. " SW_GREF_HEIGHT ,Accurate height of golden reference picture in pixels" line.long 0x10 "SWREG35,VP9 Reference Picture Scaling Register 2" hexmask.long.word 0x10 16.--31. 1. " SW_AREF_WIDTH ,Accurate width of alternate reference picture in pixels" hexmask.long.word 0x10 0.--15. 1. " SW_AREF_HEIGHT ,Accurate height of alternate reference picture in pixels" line.long 0x14 "SWREG36,VP9 Reference Picture Scaling Register 3" hexmask.long.word 0x14 16.--31. 1. " SW_LREF_HOR_SCALE ,Horizontal scaling factor for last (previous) reference picture" hexmask.long.word 0x14 0.--15. 1. " SW_LREF_VER_SCALE ,Vertical scaling factor for last (previous) reference picture" line.long 0x18 "SWREG37,VP9 Reference Picture Scaling Register 4" hexmask.long.word 0x18 16.--31. 1. " SW_GREF_HOR_SCALE ,Horizontal scaling factor for golden reference picture" hexmask.long.word 0x18 0.--15. 1. " SW_GREF_VER_SCALE ,Vertical scaling factor for golden reference picture" line.long 0x1C "SWREG38,VP9 Reference Picture Scaling Register 5" hexmask.long.word 0x1C 16.--31. 1. " SW_AREF_HOR_SCALE ,Horizontal scaling factor for alternalte reference picture" hexmask.long.word 0x1C 0.--15. 1. " SW_AREF_VER_SCALE ,Vertical scaling factor for alternate reference picture" endif group.long 0xB4++0x03 line.long 0x00 "SWREG45,Timeout Control Register" bitfld.long 0x00 31. " SW_TIMEOUT_OVERRIDE_E ,Enable for SW controlled timeout" "Disabled,Enabled" hexmask.long 0x00 0.--30. 1. " SW_TIMEOUT_CYCLES ,Amount of clock cycles to trigger timeout interrupt if no external master activity acwknowledged" if (((per.l(ad:0x38310000+0x0C)&0xF8000000)==0x60000000)) group.long 0xB8++0x07 line.long 0x00 "SWREG46,Picture Order Count From Current Pictures For Index 0-3" hexmask.long.byte 0x00 24.--31. 1. " SW_CUR_POC_00 ,Picture order count from current picture 0" hexmask.long.byte 0x00 16.--23. 1. " SW_CUR_POC_01 ,Picture order count from current picture 1" hexmask.long.byte 0x00 8.--15. 1. " SW_CUR_POC_02 ,Picture order count from current picture 2" textline " " hexmask.long.byte 0x00 0.--7. 1. " SW_CUR_POC_02 ,Picture order count from current picture 2" line.long 0x04 "SWREG47,Picture Order Count From Current Pictures For Index 4-7" hexmask.long.byte 0x04 24.--31. 1. " SW_CUR_POC_04 ,Picture order count from current picture 4" hexmask.long.byte 0x04 16.--23. 1. " SW_CUR_POC_05 ,Picture order count from current picture 5" hexmask.long.byte 0x04 8.--15. 1. " SW_CUR_POC_06 ,Picture order count from current picture 6" textline " " hexmask.long.byte 0x04 0.--7. 1. " SW_CUR_POC_07 ,Picture order count from current picture 7" elif (((per.l(ad:0x38310000+0x0C)&0xF8000000)==0x68000000)) group.long 0xB8++0x07 line.long 0x00 "SWREG46,Picture Order Count From Current Pictures For Index 0-3" hexmask.long.byte 0x00 24.--30. 1. " SW_FILT_REF_ADJ_0 ,Filter level intra adjustment" hexmask.long.byte 0x00 16.--22. 1. " SW_FILT_REF_ADJ_1 ,Filter level last ref pic adjustment" hexmask.long.byte 0x00 8.--14. 1. " SW_FILT_REF_ADJ_2 ,Filter level golden pic adjustment" textline " " hexmask.long.byte 0x00 0.--6. 1. " SW_FILT_REF_ADJ_3 ,Filter level alt ref pic adjustment" line.long 0x04 "SWREG47,Picture Order Count From Current Pictures For Index 4-7" hexmask.long.byte 0x04 24.--30. 1. " SW_FILT_MB_ADJ_0 ,Filter level ZERO mv adjsutment" hexmask.long.byte 0x04 16.--22. 1. " SW_FILT_MB_ADJ_1 ,Filter level adjustment" hexmask.long.byte 0x04 8.--14. 1. " SW_FILT_MB_ADJ_2 ,Filter level adjustment" textline " " hexmask.long.byte 0x04 0.--6. 1. " SW_FILT_MB_ADJ_3 ,Filter level adjustment" endif group.long 0xC0++0x07 line.long 0x00 "SWREG48,Picture Order Count From Current Pictures For Index 8-11" hexmask.long.byte 0x00 24.--31. 1. " SW_CUR_POC_08 ,Picture order count from current picture 8" hexmask.long.byte 0x00 16.--23. 1. " SW_CUR_POC_09 ,Picture order count from current picture 9" hexmask.long.byte 0x00 8.--15. 1. " SW_CUR_POC_10 ,Picture order count from current picture 10" textline " " hexmask.long.byte 0x00 0.--7. 1. " SW_CUR_POC_11 ,Picture order count from current picture 11" line.long 0x04 "SWREG49,Picture Order Count From Current Pictures For Index 12-15" hexmask.long.byte 0x04 24.--31. 1. " SW_CUR_POC_12 ,Picture order count from current picture 12" hexmask.long.byte 0x04 16.--23. 1. " SW_CUR_POC_13 ,Picture order count from current picture 13" hexmask.long.byte 0x04 8.--15. 1. " SW_CUR_POC_14 ,Picture order count from current picture 14" textline " " hexmask.long.byte 0x04 0.--7. 1. " SW_CUR_POC_15 ,Picture order count from current picture 15" rgroup.long 0xC8++0x03 line.long 0x00 "SWREG50,Synthesis Configuration Register Decoder 0" hexmask.long.word 0x00 0.--10. 1. " SW_DEC_MAX_OWIDTH ,Max configured decoder video resolution that can be decoded" rgroup.long 0xD8++0x03 line.long 0x00 "SWREG54,Synthesis Configuration Register Decoder 1" bitfld.long 0x00 14.--15. " SW_DEC_MAX_OW_EXT ,Max configured decoder video resolution that can be decoded" "0,1,2,3" group.long 0xDC++0x03 line.long 0x00 "SWREG55,Advanced Prefetch Control Register" bitfld.long 0x00 31. " SW_APF_DISABLE ,Advanced prefetch disable" "No,Yes" bitfld.long 0x00 30. " SW_APF_SINGLE_PU_MODE ,APF amount of buffered Bus" "0,1" hexmask.long.word 0x00 0.--15. 1. " SW_APF_THRESHOLD ,Advanced prefetch threshold" rgroup.long 0xE0++0x03 line.long 0x00 "SWREG56,Synthesis Configuration Register Decoder 2" hexmask.long.word 0x00 0.--12. 1. " SW_DEC_MAX_OHEIGHT ,Max supported picture height in pixels" group.long 0xE8++0x07 line.long 0x00 "SWREG58,Device Configuration Register Decoder 2 + Multi Core Control Register" bitfld.long 0x00 17. " SW_DEC_CLK_GATE_IDLE_E ,Clock gating enable for decoder run-time" "Disabled,Enabled" bitfld.long 0x00 16. " SW_DEC_CLK_GATE_E ,Clock gating enable for picture-wise/decoding format clock gating" "Disabled,Enabled" bitfld.long 0x00 15. " SW_DEC_REFER_DOUBLEBUFFER_E ,HW internal doube buffering enable for reference data" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " SW_DEC_AXI_RD_ID_E ,SW axi ID enable" "Disabled,Enabled" bitfld.long 0x00 13. " SW_DEC_AXI_WD_ID_E ,SW axi ID enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " SW_DEC_BUSWIDTH ,Decoder master interface buswidth" "32 bit bus,64 bit bus,128 bit bus,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " SW_DEC_MAX_BURST ,Maximum burst length for decoder bus transactions" line.long 0x04 "SWREG59,Device Configuration Register AXI ID" hexmask.long.word 0x04 16.--31. 1. " SW_DEC_AXI_WR_ID ,Read ID base for HW write accesses" hexmask.long.word 0x04 0.--15. 1. " SW_DEC_AXI_RD_ID ,Write ID base for HW write accesses" rgroup.long 0xF0++0x03 line.long 0x00 "SWREG60,Synthesis Configuration Register Decoder 3 For PP" bitfld.long 0x00 31. " SW_DEC_PP_E ,Decoder include PP" "PP not exist,PP exist" bitfld.long 0x00 30. " SW_DEC_PP_RS_E ,Decoder PP raster scan output support" "Not supported,Supported" group.long 0xF8++0x03 line.long 0x00 "SWREG62,HW Proceed Register (CU location)" hexmask.long.word 0x00 16.--31. 1. " SW_CU_LOCATION_X ,Cu horizontal start location X in pixels" hexmask.long.word 0x00 0.--15. 1. " SW_CU_LOCATION_Y ,Cu horizontal start location Y in pixels" rgroup.long 0xFC++0x03 line.long 0x00 "SWREG63,HW Performance Register (Cycles Running)" group.long 0x100++0x07 line.long 0x00 "SWREG64,Base Address MSB (bits 63:32) For Decoded Luminance Picture" line.long 0x04 "SWREG65,Base Address LSB (bits 31:0) For Decoded Luminance Picture" group.long 0x108++0x07 line.long 0x00 "SWREG66,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 0" line.long 0x04 "SWREG67,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 0" group.long 0x110++0x07 line.long 0x00 "SWREG68,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 1" line.long 0x04 "SWREG69,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 1" group.long 0x118++0x07 line.long 0x00 "SWREG70,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 2" line.long 0x04 "SWREG71,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 2" group.long 0x120++0x07 line.long 0x00 "SWREG72,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 3" line.long 0x04 "SWREG73,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 3" group.long 0x128++0x07 line.long 0x00 "SWREG74,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 4" line.long 0x04 "SWREG75,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 4" group.long 0x130++0x07 line.long 0x00 "SWREG76,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 5" line.long 0x04 "SWREG77,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 5" if (((per.l(ad:0x38310000+0x0C)&0xF8000000)==0x60000000)) group.long 0x138++0x0F line.long 0x00 "SWREG78,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 6" line.long 0x04 "SWREG79,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 6" line.long 0x08 "SWREG80,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 7" line.long 0x0C "SWREG81,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 7" elif (((per.l(ad:0x38310000+0x0C)&0xF8000000)==0x68000000)) group.long 0x138++0x0F line.long 0x00 "SWREG78,VP9 Segment Write Base MSB" line.long 0x04 "SWREG79,VP9 Segment Write Base LSB" line.long 0x08 "SWREG80,VP9 Segment Read Base MSB" line.long 0x0C "SWREG81,VP9 Segment Read Base LSB" endif group.long 0x148++0x07 line.long 0x00 "SWREG82,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 8" line.long 0x04 "SWREG83,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 8" group.long 0x150++0x07 line.long 0x00 "SWREG84,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 9" line.long 0x04 "SWREG85,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 9" group.long 0x158++0x07 line.long 0x00 "SWREG86,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 10" line.long 0x04 "SWREG87,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 10" group.long 0x160++0x07 line.long 0x00 "SWREG88,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 11" line.long 0x04 "SWREG89,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 11" group.long 0x168++0x07 line.long 0x00 "SWREG90,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 12" line.long 0x04 "SWREG91,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 12" group.long 0x170++0x07 line.long 0x00 "SWREG92,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 13" line.long 0x04 "SWREG93,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 13" group.long 0x178++0x07 line.long 0x00 "SWREG94,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 14" line.long 0x04 "SWREG95,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 14" group.long 0x180++0x07 line.long 0x00 "SWREG96,Base Address MSB (bits 63:32) For Reference Luminance Picture Index 15" line.long 0x04 "SWREG97,Base Address LSB (bits 31:0) For Reference Luminance Picture Index 15" group.long 0x188++0x07 line.long 0x00 "SWREG98,Base Address MSB (bits 63:32) For Decoded Chrominance Picture" line.long 0x04 "SWREG99,Base Address LSB (bits 31:0) For Decoded Chrominance Picture" group.long 0x190++0x07 line.long 0x00 "SWREG100,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 0" line.long 0x04 "SWREG101,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 0" group.long 0x198++0x07 line.long 0x00 "SWREG102,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 1" line.long 0x04 "SWREG103,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 1" group.long 0x1A0++0x07 line.long 0x00 "SWREG104,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 2" line.long 0x04 "SWREG105,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 2" group.long 0x1A8++0x07 line.long 0x00 "SWREG106,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 3" line.long 0x04 "SWREG107,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 3" group.long 0x1B0++0x07 line.long 0x00 "SWREG108,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 4" line.long 0x04 "SWREG109,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 4" group.long 0x1B8++0x07 line.long 0x00 "SWREG110,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 5" line.long 0x04 "SWREG111,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 5" group.long 0x1C0++0x07 line.long 0x00 "SWREG112,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 6" line.long 0x04 "SWREG113,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 6" group.long 0x1C8++0x07 line.long 0x00 "SWREG114,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 7" line.long 0x04 "SWREG115,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 7" group.long 0x1D0++0x07 line.long 0x00 "SWREG116,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 8" line.long 0x04 "SWREG117,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 8" group.long 0x1D8++0x07 line.long 0x00 "SWREG118,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 9" line.long 0x04 "SWREG119,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 9" group.long 0x1E0++0x07 line.long 0x00 "SWREG120,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 10" line.long 0x04 "SWREG121,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 10" group.long 0x1E8++0x07 line.long 0x00 "SWREG122,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 11" line.long 0x04 "SWREG123,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 11" group.long 0x1F0++0x07 line.long 0x00 "SWREG124,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 12" line.long 0x04 "SWREG125,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 12" group.long 0x1F8++0x07 line.long 0x00 "SWREG126,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 13" line.long 0x04 "SWREG127,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 13" group.long 0x200++0x07 line.long 0x00 "SWREG128,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 14" line.long 0x04 "SWREG129,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 14" group.long 0x208++0x07 line.long 0x00 "SWREG130,Base Address MSB (bits 63:32) For Reference Chrominance Picture Index 15" line.long 0x04 "SWREG131,Base Address LSB (bits 31:0) For Reference Chrominance Picture Index 15" group.long 0x210++0x07 line.long 0x00 "SWREG132,Base Address MSB (bits 63:32) For Decoded Direct Mode MVS" line.long 0x04 "SWREG133,Base Address LSB (bits 31:0) For Decoded Direct Mode MVS" group.long 0x218++0x07 line.long 0x00 "SWREG134,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 0" line.long 0x04 "SWREG135,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 0" group.long 0x220++0x07 line.long 0x00 "SWREG136,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 1" line.long 0x04 "SWREG137,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 1" group.long 0x228++0x07 line.long 0x00 "SWREG138,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 2" line.long 0x04 "SWREG139,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 2" group.long 0x230++0x07 line.long 0x00 "SWREG140,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 3" line.long 0x04 "SWREG141,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 3" group.long 0x238++0x07 line.long 0x00 "SWREG142,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 4" line.long 0x04 "SWREG143,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 4" group.long 0x240++0x07 line.long 0x00 "SWREG144,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 5" line.long 0x04 "SWREG145,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 5" group.long 0x248++0x07 line.long 0x00 "SWREG146,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 6" line.long 0x04 "SWREG147,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 6" group.long 0x250++0x07 line.long 0x00 "SWREG148,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 7" line.long 0x04 "SWREG149,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 7" group.long 0x258++0x07 line.long 0x00 "SWREG150,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 8" line.long 0x04 "SWREG151,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 8" group.long 0x260++0x07 line.long 0x00 "SWREG152,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 9" line.long 0x04 "SWREG153,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 9" group.long 0x268++0x07 line.long 0x00 "SWREG154,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 10" line.long 0x04 "SWREG155,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 10" group.long 0x270++0x07 line.long 0x00 "SWREG156,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 11" line.long 0x04 "SWREG157,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 11" group.long 0x278++0x07 line.long 0x00 "SWREG158,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 12" line.long 0x04 "SWREG159,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 12" group.long 0x280++0x07 line.long 0x00 "SWREG160,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 13" line.long 0x04 "SWREG161,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 13" group.long 0x288++0x07 line.long 0x00 "SWREG162,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 14" line.long 0x04 "SWREG163,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 14" group.long 0x290++0x07 line.long 0x00 "SWREG164,Base Address MSB (bits 63:32) For Reference Direct Mode MVS Index 15" line.long 0x04 "SWREG165,Base Address LSB (bits 31:0) For Reference Direct Mode MVS Index 15" group.long 0x298++0x0F line.long 0x00 "SWREG166,Base Address MSB (bits 63:32) For Tile Sizes" line.long 0x04 "SWREG167,Base Address LSB (bits 31:0) For Tile Sizes" line.long 0x08 "SWREG168,Base Address MSB (bits 63:32) For / Stream Start Address/Decoded End Addr Register" line.long 0x0C "SWREG169,Base Address LSB (bits 31:0) For / Stream Start Address/Decoded End Addr Register" if (((per.l(ad:0x38310000+0x0C)&0xF8000000)==0x60000000)) group.long 0x2A8++0x07 line.long 0x00 "SWREG170,Base Address MSB (bits 63:32) For Scaling Lists" line.long 0x04 "SWREG171,Base Address LSB (bits 31:0) For Scaling Lists" elif (((per.l(ad:0x38310000+0x0C)&0xF8000000)==0x68000000)) group.long 0x2A8++0x07 line.long 0x00 "SWREG170,VP9 CTX Counter Values" line.long 0x04 "SWREG171,VP9 CTX Counter Values" endif group.long 0x2B0++0x4B line.long 0x00 "SWREG172,Base Address MSB (bits 63:32) For Stream Probability Tables" line.long 0x04 "SWREG173,Base Address LSB (bits 31:0) For Stream Probability Tables" line.long 0x08 "SWREG174,Base Address MSB (bits 63:32) For Decoder Output Raster Scan Y Picture" line.long 0x0C "SWREG175,Base Address LSB (bits 31:0) For Decoder Output Raster Scan Y Picture" line.long 0x10 "SWREG176,Base Address MSB (bits 63:32) For Decoder Output Raster Scan C Picture" line.long 0x14 "SWREG177,Base Address LSB (bits 31:0) For Decoder Output Raster Scan C Picture" line.long 0x18 "SWREG178,Base Address MSB (bits 63:32) For Tile Border Coeffients Of Filter" line.long 0x1C "SWREG179,Base Address LSB (bits 31:0) For Tile Border Coeffients Of Filter" line.long 0x20 "SWREG180,Base Address MSB (bits 63:32) For Tile Border Coeffients Of Sao" line.long 0x24 "SWREG181,Base Address LSB (bits 31:0) For Tile Border Coeffients Of Sao" line.long 0x28 "SWREG182,Base Address MSB (bits 63:32) For Tile Border Bsd Control Data" line.long 0x2C "SWREG183,Base Address LSB (bits 31:0) For Tile Border Bsd Control Data" line.long 0x30 "SWREG184,Raster Scan Down Scale Control Register MSM" bitfld.long 0x30 7. " SW_DEC_DS_E ,Raster scan down scale enable" "Disabled,Enabled" bitfld.long 0x30 2.--3. " SW_DEC_DS_Y ,Y coordinate down scale times for raster scan output picture data" "1/2,1/4,1/8,?..." bitfld.long 0x30 0.--1. " SW_DEC_DS_X ,X coordinate down scale times for raster scan output picture data" "1/2,1/4,1/8,?..." line.long 0x34 "SWREG185,Base Address MSB (bits 63:32) For Decoder Output Raster Scan Down Scale Y Picture" line.long 0x38 "SWREG186,Base Address LSB (bits 31:0) For Decoder Output Raster Scan Down Scale Y Picture" line.long 0x3C "SWREG187,Base Address MSB (bits 63:32) For Decoder Output Raster Scan Down Scale C Picture" line.long 0x40 "SWREG188,Base Address LSB (bits 31:0) For Decoder Output Raster Scan Down Scale C Picture" line.long 0x44 "SWREG189,Base Address MSB (bits 63:32) For Decoder Output Compress Luminance Table" line.long 0x48 "SWREG190,Base Address LSB (bits 31:0) For Decoder Output Compress Luminance Table" group.long 0x2FC++0x07 line.long 0x00 "SWREG191,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 0" line.long 0x04 "SWREG192,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 0" group.long 0x304++0x07 line.long 0x00 "SWREG193,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 1" line.long 0x04 "SWREG194,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 1" group.long 0x30C++0x07 line.long 0x00 "SWREG195,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 2" line.long 0x04 "SWREG196,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 2" group.long 0x314++0x07 line.long 0x00 "SWREG197,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 3" line.long 0x04 "SWREG198,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 3" group.long 0x31C++0x07 line.long 0x00 "SWREG199,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 4" line.long 0x04 "SWREG200,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 4" group.long 0x324++0x07 line.long 0x00 "SWREG201,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 5" line.long 0x04 "SWREG202,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 5" group.long 0x32C++0x07 line.long 0x00 "SWREG203,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 6" line.long 0x04 "SWREG204,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 6" group.long 0x334++0x07 line.long 0x00 "SWREG205,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 7" line.long 0x04 "SWREG206,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 7" group.long 0x33C++0x07 line.long 0x00 "SWREG207,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 8" line.long 0x04 "SWREG208,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 8" group.long 0x344++0x07 line.long 0x00 "SWREG209,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 9" line.long 0x04 "SWREG210,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 9" group.long 0x34C++0x07 line.long 0x00 "SWREG211,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 10" line.long 0x04 "SWREG212,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 10" group.long 0x354++0x07 line.long 0x00 "SWREG213,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 11" line.long 0x04 "SWREG214,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 11" group.long 0x35C++0x07 line.long 0x00 "SWREG215,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 12" line.long 0x04 "SWREG216,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 12" group.long 0x364++0x07 line.long 0x00 "SWREG217,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 13" line.long 0x04 "SWREG218,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 13" group.long 0x36C++0x07 line.long 0x00 "SWREG219,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 14" line.long 0x04 "SWREG220,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 14" group.long 0x374++0x07 line.long 0x00 "SWREG221,Base Address MSB (bits 63:32) For Reference Compress Luminance Table Index 15" line.long 0x04 "SWREG222,Base Address LSB (bits 31:0) For Reference Compress Luminance Table Index 15" group.long 0x37C++0x07 line.long 0x00 "SWREG223,Base Address MSB (bits 63:32) For Decoder Output Compress Chrominance Table" line.long 0x04 "SWREG224,Base Address LSB (bits 31:0) For Decoder Output Compress Chrominance Table" group.long 0x384++0x07 line.long 0x00 "SWREG225,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 0" line.long 0x04 "SWREG226,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 0" group.long 0x38C++0x07 line.long 0x00 "SWREG227,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 1" line.long 0x04 "SWREG228,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 1" group.long 0x394++0x07 line.long 0x00 "SWREG229,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 2" line.long 0x04 "SWREG230,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 2" group.long 0x39C++0x07 line.long 0x00 "SWREG231,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 3" line.long 0x04 "SWREG232,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 3" group.long 0x3A4++0x07 line.long 0x00 "SWREG233,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 4" line.long 0x04 "SWREG234,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 4" group.long 0x3AC++0x07 line.long 0x00 "SWREG235,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 5" line.long 0x04 "SWREG236,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 5" group.long 0x3B4++0x07 line.long 0x00 "SWREG237,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 6" line.long 0x04 "SWREG238,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 6" group.long 0x3BC++0x07 line.long 0x00 "SWREG239,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 7" line.long 0x04 "SWREG240,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 7" group.long 0x3C4++0x07 line.long 0x00 "SWREG241,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 8" line.long 0x04 "SWREG242,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 8" group.long 0x3CC++0x07 line.long 0x00 "SWREG243,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 9" line.long 0x04 "SWREG244,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 9" group.long 0x3D4++0x07 line.long 0x00 "SWREG245,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 10" line.long 0x04 "SWREG246,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 10" group.long 0x3DC++0x07 line.long 0x00 "SWREG247,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 11" line.long 0x04 "SWREG248,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 11" group.long 0x3E4++0x07 line.long 0x00 "SWREG249,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 12" line.long 0x04 "SWREG250,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 12" group.long 0x3EC++0x07 line.long 0x00 "SWREG251,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 13" line.long 0x04 "SWREG252,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 13" group.long 0x3F4++0x07 line.long 0x00 "SWREG253,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 14" line.long 0x04 "SWREG254,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 14" group.long 0x3FC++0x07 line.long 0x00 "SWREG255,Base Address MSB (bits 63:32) For Reference Compress Chrominance Table Index 15" line.long 0x04 "SWREG256,Base Address LSB (bits 31:0) For Reference Compress Chrominance Table Index 15" group.long 0x408++0x07 line.long 0x00 "SWREG258,Input Stream Buffer Length" line.long 0x04 "SWREG259,input Stream Buffer Start Offset" width 0x0B tree.end tree.end tree.open "Display Controller Subsystem" tree "BLK_CTL (DCSS Block Control)" base ad:0x0002F000 width 21. group.long 0x00++0x03 line.long 0x00 "RESET_CTRL_SET/CLR,Reset Control Set/Clear" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " SPARE_CLK_RESETN[7] ,Spare clk domain reset [7]" "Reset,No reset" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [6] ,Spare clk domain reset [6]" "Reset,No reset" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [5] ,Spare clk domain reset [5]" "Reset,No reset" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [4] ,Spare clk domain reset [4]" "Reset,No reset" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [3] ,Spare clk domain reset [3]" "Reset,No reset" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [2] ,Spare clk domain reset [2]" "Reset,No reset" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [1] ,Spare clk domain reset [1]" "Reset,No reset" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [0] ,Spare clk domain reset [0]" "Reset,No reset" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RTR_CLK_RESETN ,Rtr_clk domain modules resetn" "Reset,No reset" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " P_CLK_RESETN ,P_clk domain modules resetn" "Reset,No reset" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " APB_CLK_RESETN ,Apb_clk domain modules resetn" "Reset,No reset" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " B_CLK_RESETN ,B_clk domain modules resetn" "Reset,No reset" group.long 0x0C++0x33 line.long 0x00 "RESET_CTRL_TOG,Reset Control Toggle" bitfld.long 0x00 23. " SPARE_CLK_RESETN[7] ,Spare clk domain reset [7]" "Reset,No reset" bitfld.long 0x00 22. " [6] ,Spare clk domain reset [6]" "Reset,No reset" bitfld.long 0x00 21. " [5] ,Spare clk domain reset [5]" "Reset,No reset" bitfld.long 0x00 20. " [4] ,Spare clk domain reset [4]" "Reset,No reset" textline " " bitfld.long 0x00 19. " [3] ,Spare clk domain reset [3]" "Reset,No reset" bitfld.long 0x00 18. " [2] ,Spare clk domain reset [2]" "Reset,No reset" bitfld.long 0x00 17. " [1] ,Spare clk domain reset [1]" "Reset,No reset" bitfld.long 0x00 16. " [0] ,Spare clk domain reset [0]" "Reset,No reset" textline " " bitfld.long 0x00 3. " RTR_CLK_RESETN ,Rtr_clk domain modules resetn" "Reset,No reset" bitfld.long 0x00 2. " P_CLK_RESETN ,P_clk domain modules resetn" "Reset,No reset" bitfld.long 0x00 1. " APB_CLK_RESETN ,Apb_clk domain modules resetn" "Reset,No reset" bitfld.long 0x00 0. " B_CLK_RESETN ,B_clk domain modules resetn" "Reset,No reset" line.long 0x04 "CONTROL0,Control" setclrfld.long 0x04 8. 0x08 8. 0x0C 8. " DISPMIX_PIXCLK_SEL_SET/CLR ,Display subsystem pixel clock select" "Video PLL2 clock,CCM DC pixel clock" bitfld.long 0x04 4.--5. " DISPMIX_REFCLK_SEL ,Reference clock source selection" "27 MHz ORC,Video PLL2 clock,CCM DC pixel clock,?..." line.long 0x08 "CONTROL0_SET,Control Set" bitfld.long 0x08 4.--5. " DISPMIX_REFCLK_SEL ,Reference clock source selection" "27 MHz ORC,Video PLL2 clock,CCM DC pixel clock,?..." line.long 0x0C "CONTROL0_CLR,Control Clear" bitfld.long 0x0C 4.--5. " DISPMIX_REFCLK_SEL ,Reference clock source selection" "27 MHz ORC,Video PLL2 clock,CCM DC pixel clock,?..." line.long 0x10 "CONTROL0_TOG,Control Toggle" bitfld.long 0x10 8. " DISPMIX_PIXCLK_SEL ,Display subsystem pixel clock select" "Video PLL2 clock,CCM DC pixel clock" bitfld.long 0x10 4.--5. " DISPMIX_REFCLK_SEL ,Reference clock source selection" "27 MHz ORC,Video PLL2 clock,CCM DC pixel clock,?..." line.long 0x14 "SPARE_CTRL0,Spare Control0" line.long 0x18 "SPARE_CTRL0_SET,Spare Control0 Set" line.long 0x1C "SPARE_CTRL0_CLR,Spare Control0 Clear" line.long 0x20 "SPARE_CTRL0_TOG,Spare Control0 Toggle" line.long 0x24 "SPARE_CTRL1,Spare Control1" line.long 0x28 "SPARE_CTRL1_SET,Spare Control1 Set" line.long 0x2C "SPARE_CTRL1_CLR,Spare Control1 Clear" line.long 0x30 "SPARE_CTRL1_TOG,Spare Control1 Toggle" rgroup.long 0x40++0x0F line.long 0x00 "SPARE_STATUS0,Spare Status0" line.long 0x04 "SPARE_STATUS0_SET,Spare Status0 Set" line.long 0x08 "SPARE_STATUS0_CLR,Spare Status0 Clear" line.long 0x0C "SPARE_STATUS0_TOG,Spare Status0 Toggle" width 0x0B tree.end tree "DTG (Display Timing Generator)" base ad:0x00020000 width 29. if (((per.l(ad:0x00020000)&0x08)==0x08)) group.long 0x00++0x03 line.long 0x00 "TC_CONTROL_STATUS,Timing Controller Control Register" hexmask.long.byte 0x00 24.--31. 1. " TC_DEFAULT_OVERLAY_ALPHA ,Default alpha foreground used for the active regions where graphics channel does not provide an alpha value" textline " " bitfld.long 0x00 12.--14. " TC_CSS_PIX_COMP_SWAP ,Permutes the pixel conponent ordering into the chroma subsampler (CSS) block" "IPT,ITP,TIP,TPI,PIT,PTI,?..." textline " " bitfld.long 0x00 10. " TC_CH1_PER_PEL_ALPHA_SEL ,Enables per pixel alpha for channel1 (Overlay or Graphics)" "TC_DEFAULT_OVERLAY_ALPHA||Foreground alpha,CH1 Data stream && apply blending per pixel" textline " " bitfld.long 0x00 9. " TC_DOLBY_MODE ,Enables dolby mode" "HDR10,Dolby Processing" textline " " bitfld.long 0x00 8. " TC_GO ,Enable timing controller" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TC_BLENDER_VIDEO_ALPHA_SELECT ,Channel 1 alpha pixel detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " TC_OVERLAY_FIFO_DATA_MODE ,Overlay fifo output data in yuv or RGB mode" "YUV,RGB" textline " " bitfld.long 0x00 2. " TC_OVERLAY_PATH_ENABLE ,Enable channel_1 (Dolby_mode:Overlay /HDR10: (GFX)) processing" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TC_VIDEO_ENH_PATH_ENABLE ,Enable channel_2 (Dolby_mode:Enhancement channel ) processing" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " TC_VIDEO_BASE_PATH_ENABLE ,Enable channel_3 (Dolby_mode:Base Layer channel ) processing" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "TC_CONTROL_STATUS,Timing Controller Control Register" bitfld.long 0x00 12.--14. " TC_CSS_PIX_COMP_SWAP ,Permutes the pixel conponent ordering into the chroma subsampler (CSS) block" "IPT,ITP,TIP,TPI,PIT,PTI,?..." textline " " bitfld.long 0x00 10. " TC_CH1_PER_PEL_ALPHA_SEL ,Enables per pixel alpha for channel1 (Overlay or Graphics)" "TC_DEFAULT_OVERLAY_ALPHA||Foreground alpha,CH1 Data stream && apply blending per pixel" textline " " bitfld.long 0x00 9. " TC_DOLBY_MODE ,Enables dolby mode" "HDR10,Dolby Processing" textline " " bitfld.long 0x00 8. " TC_GO ,Enable timing controller" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TC_BLENDER_VIDEO_ALPHA_SELECT ,Channel 1 alpha pixel detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " TC_OVERLAY_FIFO_DATA_MODE ,Overlay fifo output data in yuv or RGB mode" "YUV,RGB" textline " " bitfld.long 0x00 2. " TC_OVERLAY_PATH_ENABLE ,Enable channel_1 (Dolby_mode:Overlay /HDR10: (GFX)) processing" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TC_VIDEO_ENH_PATH_ENABLE ,Enable channel_2 (Dolby_mode:Enhancement channel ) processing" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " TC_VIDEO_BASE_PATH_ENABLE ,Enable channel_3 (Dolby_mode:Base Layer channel ) processing" "Disabled,Enabled" endif textline " " group.long 0x04++0x2F line.long 0x00 "TC_DTG_REG1,DTG Lower Right Corner Locations" hexmask.long.word 0x00 16.--28. 1. " TC_DTG_LOWER_RIGHT_Y ,Lower right corner Y (vertical) coordinate of the raster table" hexmask.long.word 0x00 0.--12. 1. " TC_DTG_LOWER_RIGHT_X ,Lower right corner X (horizontal) coordinate of the raster table" line.long 0x04 "TC_DISPLAY_REG2,TOP Window Coordinates For Active Display Area" hexmask.long.word 0x04 16.--28. 1. " TC_DISPLAY_UPPER_LEFT_Y ,Upper left corner Y (vertical) coordinate of the active display region" hexmask.long.word 0x04 0.--12. 1. " TC_DISPLAY_UPPER_LEFT_X ,Upper left corner X (horizontal) coordinate of the active display region" line.long 0x08 "TC_DISPLAY_REG3,BOTTOM Window Coordinates For Active Display Area" hexmask.long.word 0x08 16.--28. 1. " TC_DISPLAY_LOWER_RIGHT_Y ,Lower right corner Y (vertical) coordinate of the active display region" hexmask.long.word 0x08 0.--12. 1. " TC_DISPLAY_LOWER_RIGHT_X ,Lower right corner X (horizontal) coordinate of the active display region" line.long 0x0C "TC_CH1_REG4,TOP Window Coordinates For Channel1" hexmask.long.word 0x0C 16.--28. 1. " TC_CHANNEL_1_UPPER_LEFT_Y ,Upper left corner Y (vertical) coordinate of the channel_1 window" hexmask.long.word 0x0C 0.--12. 1. " TC_CHANNEL_1_UPPER_LEFT_X ,Upper left corner X (horizontal) coordinate of the channel_1 window" line.long 0x10 "TC_CH1_REG5,BOTTOM Window Coordinates For Channel_1 Window" hexmask.long.word 0x10 16.--28. 1. " TC_CHANNEL_1_LOWER_RIGHT_Y ,Lower right corner Y (vertical) coordinate of the channel_1 window" hexmask.long.word 0x10 0.--12. 1. " TC_CHANNEL_1_LOWER_RIGHT_X ,Lower right corner X (horizontal) coordinate of the channel_1 window" line.long 0x14 "TC_CH2_REG6,TOP Window Coordinates For Channel_2 Window" hexmask.long.word 0x14 16.--28. 1. " TC_CHANNEL_2_UPPER_LEFT_Y ,Upper left corner Y (vertical) coordinate of the channel_2 window" hexmask.long.word 0x14 0.--12. 1. " TC_CHANNEL_2_UPPER_LEFT_X ,Upper left corner X (horizontal) coordinate of the channel_2 window" line.long 0x18 "TC_CH2_REG7,BOTTOM Window Coordinates For Channel_2 Pixel Window" hexmask.long.word 0x18 16.--28. 1. " TC_CHANNEL_2_LOWER_RIGHT_Y ,Lower right corner Y (vertical) coordinate of the channel_2 window" hexmask.long.word 0x18 0.--12. 1. " TC_CHANNEL_2_LOWER_RIGHT_X ,Lower right corner X (horizontal) coordinate of the channel_2 window" line.long 0x1C "TC_CH3_REG8,TOP Window Coordinates For Channel_3" hexmask.long.word 0x1C 16.--28. 1. " TC_CHANNEL_3_UPPER_LEFT_Y ,Upper left corner Y (vertical) coordinate of the channel_3 window" hexmask.long.word 0x1C 0.--12. 1. " TC_CHANNEL_3_UPPER_LEFT_X ,Upper left corner X (horizontal) coordinate of the channel_3 window" line.long 0x20 "TC_CH3_REG9,BOTTOM Window Coordinates For Channel_3 Pixel Window" hexmask.long.word 0x20 16.--28. 1. " TC_CHANNEL_3_LOWER_RIGHT_Y ,Lower right corner Y (vertical) coordinate of the channel_3 window" hexmask.long.word 0x20 0.--12. 1. " TC_CHANNEL_3_LOWER_RIGHT_X ,Lower right corner X (horizontal) coordinate of the channel_3 window" line.long 0x24 "TC_CTX_LD_REG10,Coordinates In The Raster Table Where The Context Loader Is Started" hexmask.long.word 0x24 16.--28. 1. " TC_CNTXT_SB_LINE_COUNT ,Line count for single buffered (SB) context loading" hexmask.long.word 0x24 0.--12. 1. " TC_CNTXT_DB_LINE_COUNT ,Line count for double buffered (DB) context loading" line.long 0x28 "TC_CH1_BKRND_REG11,Channel_1 Background Pixel Color" hexmask.long.word 0x28 20.--29. 1. " TC_CH1_BKRND_PEL_COMP_1 ,10-bit component ( R or Y )" hexmask.long.word 0x28 10.--19. 1. " TC_CH1_BKRND_PEL_COMP_2 ,10-bit component ( G or Cb )" textline " " hexmask.long.word 0x28 0.--9. 1. " TC_CH1_BKRND_PEL_COMP_3 ,10-bit component ( B or Cr )" line.long 0x2C "TC_CH2_BKRND_REG12,Channel_2 Background Pixel Color" hexmask.long.word 0x2C 20.--29. 1. " TC_CH2_BKRND_PEL_COMP_1 ,10-bit component ( R or Y )" hexmask.long.word 0x2C 10.--19. 1. " TC_CH2_BKRND_PEL_COMP_2 ,10-bit component ( G or Cb )" textline " " hexmask.long.word 0x2C 0.--9. 1. " TC_CH2_BKRND_PEL_COMP_3 ,10-bit component ( B or Cr )" group.long 0x38++0x23 line.long 0x00 "BLENDER_DBY_EOTF_RANGEINV,DBY MODE Blender Control" hexmask.long.tbyte 0x00 0.--16. 1. " BLENDER_EOTF_RANGEINV ,Eotf_rangeInv parameter for DBY blender" line.long 0x04 "BLENDER_DBY_EOTF_RANGEMIN,DBY MODE Blender Control" hexmask.long.tbyte 0x04 0.--16. 1. " BLENDER_EOTF_RANGEMIN ,Eotf_rangeMin parameter for DBY blender" line.long 0x08 "BLENDER_DBY_BDP,DBY MODE Blender Control" bitfld.long 0x08 0.--4. " BLENDER_BDP ,BitDepth parameter in DBY blender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "BLENDER_BKRND_I_GRAPHICS,Background Pixel Color Component Sent To Blender" hexmask.long 0x0C 0.--27. 1. " BLENDER_BCKRND_I_COMP ,28-bit component I component in DBY mode R/Y component in HDR10 MODE" line.long 0x10 "BLENDER_BKRND_P_GRAPHICS,Background Pixel Color Component Sent To Blender" hexmask.long 0x10 0.--27. 1. " BLENDER_BCKRND_P_COMP ,28-bit component P component in DBY mode G/Cb component in HDR10 MODE" line.long 0x14 "BLENDER_BKRND_T_GRAPHICS,Background Pixel Color Component Sent To Blender" hexmask.long 0x14 0.--27. 1. " BLENDER_BCKRND_T_COMP ,28-bit component T component in DBY mode B/Cr component in HDR10 MODE" line.long 0x18 "TC_LINE1_INT_REG13,LINE1 Interrupt Control" hexmask.long.word 0x18 16.--28. 1. " TC_LINE1_INT_Y ,Y (vertical) coordinate for line1 interrupt" hexmask.long.word 0x18 0.--12. 1. " TC_LINE1_INT_X ,X (horizontal) coordinate for line1 interrupt" line.long 0x1C "TC_LINE2_INT_REG14,LINE2 Interrupt Control" hexmask.long.word 0x1C 16.--28. 1. " TC_LINE2_INT_Y ,Y (vertical) coordinate for line2 interrupt" hexmask.long.word 0x1C 0.--12. 1. " TC_LINE2_INT_X ,X (horizontal) coordinate for line2 interrupt" line.long 0x20 "TC_ALPHA_DEFAULT_REG15,Default alpha" hexmask.long.byte 0x20 0.--7. 1. " TC_ALPHA_DEF ,Default background alpha value" rgroup.long 0x5C++0x03 line.long 0x00 "TC_INTERRUPT_STATUS,Timing Controller Interrupt Status" bitfld.long 0x00 6. " TC_RTRAM_CH3_PANIC_INTERRUPT ,Panic interrupt is asserted by the scaler for channel3" "No interrupt,Interrupt" bitfld.long 0x00 5. " TC_RTRAM_CH2_PANIC_INTERRUPT ,Panic interrupt is asserted by the scaler for channel2" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " TC_RTRAM_CH1_PANIC_INTERRUPT ,Panic interrupt is asserted by the scaler for channel1" "No interrupt,Interrupt" bitfld.long 0x00 3. " TC_LINE3_INTERRUPT ,LINE3 interrupt status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " TC_LINE2_INTERRUPT ,LINE2 interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 1. " TC_LINE1_INTERRUPT ,LINE1 interrupt status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " TC_LINE0_INTERRUPT ,LINE0 interrupt status" "No interrupt,Interrupt" group.long 0x60++0x13 line.long 0x00 "TC_INTRERRUPT_CONTROL_REG17,Timing Controller Interrupt Control" bitfld.long 0x00 6. " TC_RTRAM_CH3_PANIC_INTERRUPT_CLR ,Panic interrupt for channel3 clear" "No effect,Clear" bitfld.long 0x00 5. " TC_RTRAM_CH2_PANIC_INTERRUPT_CLR ,Panic interrupt for channel2 clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " TC_RTRAM_CH1_PANIC_INTERRUPT_CLR ,Panic interrupt for channel1 clear" "No effect,Clear" bitfld.long 0x00 3. " TC_LINE3_INTERRUPT_CLR ,LINE3 interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 2. " TC_LINE2_INTERRUPT_CLR ,LINE2 interrupt clear" "No effect,Clear" bitfld.long 0x00 1. " TC_LINE1_INTERRUPT_CLR ,LINE1 interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 0. " TC_LINE0_INTERRUPT_CLR ,LINE0 interrupt clear" "No effect,Clear" line.long 0x04 "TC_CH3_BKRND_REG18,Channel_3 Background Pixel Color" hexmask.long.word 0x04 20.--29. 1. " TC_CH3_BKRND_PEL_COMP_1 ,10-bit component ( R or Y )" hexmask.long.word 0x04 10.--19. 1. " TC_CH3_BKRND_PEL_COMP_2 ,10-bit component ( G or Cb )" textline " " hexmask.long.word 0x04 0.--9. 1. " TC_CH3_BKRND_PEL_COMP_3 ,10-bit component ( B or Cr )" line.long 0x08 "TC_INTRERRUPT_MASK,Timing Controller Interrupt Masks" bitfld.long 0x08 6. " TC_RTRAM_CH3_PANIC_INTERRUPT_MASK ,Panic interrupt mask for channel3" "Not masked,Masked" bitfld.long 0x08 5. " TC_RTRAM_CH2_PANIC_INTERRUPT_MASK ,Panic interrupt mask for channel2" "Not masked,Masked" textline " " bitfld.long 0x08 4. " TC_RTRAM_CH1_PANIC_INTERRUPT_MASK ,Panic interrupt mask for channel1" "Not masked,Masked" bitfld.long 0x08 3. " TC_LINE3_INTERRUPT_MASK ,LINE3 interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x08 2. " TC_LINE2_INTERRUPT_MASK ,LINE2 interrupt mask" "Not masked,Masked" bitfld.long 0x08 1. " TC_LINE1_INTERRUPT_MASK ,LINE1 interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x08 0. " TC_LINE0_INTERRUPT_MASK ,LINE0 interrupt mask" "Not masked,Masked" line.long 0x0C "TC_LINE3_INT_REG,LINE3 Interrupt Control" hexmask.long.word 0x0C 16.--28. 1. " TC_LINE3_INT_Y ,Y (vertical) coordinate for line3 interrupt" hexmask.long.word 0x0C 0.--12. 1. " TC_LINE3_INT_X ,X (horizontal) coordinate for line3 interrupt" line.long 0x10 "TC_LINE4_INT_REG,LINE4 Interrupt Control" hexmask.long.word 0x10 16.--28. 1. " TC_LINE4_INT_Y ,Y (vertical) coordinate for line4 interrupt" hexmask.long.word 0x10 0.--12. 1. " TC_LINE4_INT_X ,X (horizontal) coordinate for line4 interrupt" if (((per.l(ad:0x00020000)&0x200)==0x200)) group.long 0x74++0x0B line.long 0x00 "TC_OL_DE_CONTROL_REG,Controls The Assertion And De-assertion DE Signal (Overlay Channel)" bitfld.long 0x00 31. " TC_INVERT_DE_X ,DE signal invert" "Not inverted,Inverted" hexmask.long.word 0x00 16.--28. 1. " TC_DE_SET_HIGH_X ,X (horizontal) coordinate where DE control signal is set to 1 in a line" textline " " hexmask.long.word 0x00 0.--12. 1. " TC_DE_SET_LOW_X ,X (horizontal) coordinate where DE control signal is set to 0 in a line" line.long 0x04 "TC_BL_DE_CONTROL_REG,Controls The Assertion And De-assertion DE Signal (Base layer (BL) channel)" bitfld.long 0x04 31. " TC_INVERT_DE_X ,DE signal invert" "Not inverted,Inverted" hexmask.long.word 0x04 16.--28. 1. " TC_DE_SET_HIGH_X ,X (horizontal) coordinate where DE control signal is set to 1 in a line" textline " " hexmask.long.word 0x04 0.--12. 1. " TC_DE_SET_LOW_X ,X (horizontal) coordinate where DE control signal is set to 0 in a line" line.long 0x08 "TC_EL_DE_CONTROL_REG,Controls The Assertion And De-assertion DE Signal (Enhancement Layer (EL) Channel)" bitfld.long 0x08 31. " TC_INVERT_DE_X ,DE signal invert" "Not inverted,Inverted" hexmask.long.word 0x08 16.--28. 1. " TC_DE_SET_HIGH_X ,X (horizontal) coordinate where DE control signal is set to 1 in a line" textline " " hexmask.long.word 0x08 0.--12. 1. " TC_DE_SET_LOW_X ,X (horizontal) coordinate where DE control signal is set to 0 in a line" endif width 0x0B tree.end tree "CTX_LD (Context Load)" base ad:0x00023000 width 21. group.long 0x00++0x03 line.long 0x00 "CTRL_STATUS_SET/CLR,Control Status Register For Context Loader Set/Clear" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " AHB_ERR ,AHB error" "No error,Error" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " SB_PEND_DISP_ACTIVE ,Single/active region overlap" "Not occurred,Occurred" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " DB_PEND_SB_REC ,Double/single region overlap" "Not occurred,Occurred" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " SB_LP_COMP ,Single buffer low priority region loading complete IRQ enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 18. 0x04 18. 0x08 18. " SB_HP_COMP ,Single buffer high priority region loading complete" "Not completed,Completed" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DB_COMP ,Double buffer region loading complete" "Not completed,Completed" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " RD_ERR ,AXI read error" "No error,Error" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AHB_ERR_EN ,AHB error IRQ enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SB_PEND_DISP_ACTIVE_EN ,Single/active region overlap interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DB_PEND_SB_REC_EN ,Double/single region overlap interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SB_LP_COMP_EN ,Single buffer low priority region loading complete IRQ enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SB_HP_COMP_EN ,Single buffer high priority region loading complete IRQ enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DB_COMP_EN ,Double buffer region loading complete IRQ enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " RD_ERR_EN ,AXI read error IRQ enable" "Disabled,Enabled" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " ARB_SEL ,Arbitration select" "Round robin,CTX_LD" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ENABLE ,Enable bit for the context loader" "Disabled,Enabled" group.long 0x0C++0x13 line.long 0x00 "CTRL_STATUS_TOG,Control Status Register For Context Loader Toggle" eventfld.long 0x00 22. " AHB_ERR ,AHB error" "No error,Error" eventfld.long 0x00 21. " SB_PEND_DISP_ACTIVE ,Single/active region overlap" "Not occurred,Occurred" eventfld.long 0x00 20. " DB_PEND_SB_REC ,Double/single region overlap" "Not occurred,Occurred" eventfld.long 0x00 19. " SB_LP_COMP ,Single buffer low priority region loading complete IRQ enable" "Disabled,Enabled" textline " " eventfld.long 0x00 18. " SB_HP_COMP ,Single buffer high priority region loading complete" "Not completed,Completed" eventfld.long 0x00 17. " DB_COMP ,Double buffer region loading complete" "Not completed,Completed" eventfld.long 0x00 16. " RD_ERR ,AXI read error" "No error,Error" bitfld.long 0x00 8. " AHB_ERR_EN ,AHB error IRQ enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SB_PEND_DISP_ACTIVE_EN ,Single/active region overlap interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " DB_PEND_SB_REC_EN ,Double/single region overlap interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SB_LP_COMP_EN ,Single buffer low priority region loading complete IRQ enable" "Disabled,Enabled" bitfld.long 0x00 4. " SB_HP_COMP_EN ,Single buffer high priority region loading complete IRQ enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DB_COMP_EN ,Double buffer region loading complete IRQ enable" "Disabled,Enabled" bitfld.long 0x00 2. " RD_ERR_EN ,AXI read error IRQ enable" "Disabled,Enabled" bitfld.long 0x00 1. " ARB_SEL ,Arbitration select" "Round robin,CTX_LD" bitfld.long 0x00 0. " ENABLE ,Enable bit for the context loader" "Disabled,Enabled" line.long 0x04 "DB_BASE_ADDR,DRAM Addr For Double Buffered Register Fetch" line.long 0x08 "DB_COUNT,Double Buffer Register Count" hexmask.long.word 0x08 0.--15. 1. " DB_COUNT ,Double buffered region fetch count" line.long 0x0C "SB_BASE_ADDR,DRAM Addr For Single Buffered Registers" line.long 0x10 "SB_COUNT,Single Buffer Register Count" hexmask.long.word 0x10 16.--31. 1. " LP_COUNT ,Single buffered low priority region fetch count" hexmask.long.word 0x10 0.--15. 1. " HP_COUNT ,Single buffered high priority region fetch count" rgroup.long 0x20++0x03 line.long 0x00 "AHB_ERR_ADDR,AHB Address With Error Response" width 0x0B tree.end tree "DEC400D (Graphics Decompression)" base ad:0x00015000 width 31. rgroup.long 0x24++0x07 line.long 0x00 "GCCHIPREV,Revision ID" line.long 0x04 "GCCHIPDATE,Release Date" rgroup.long 0x98++0x03 line.long 0x00 "GCREGHICHIPPATCHREV,Patch Revision" rgroup.long 0xA8++0x03 line.long 0x00 "GCPRODUCTID,Product ID" group.long 0x800++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG0,Decode Read Configuration 0" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x800+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE0,Decode Read Buffer Base 0" group.long (0x800+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE0,Decode Read Cache Base 0" group.long 0x804++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG1,Decode Read Configuration 1" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x804+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE1,Decode Read Buffer Base 1" group.long (0x804+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE1,Decode Read Cache Base 1" group.long 0x808++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG2,Decode Read Configuration 2" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x808+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE2,Decode Read Buffer Base 2" group.long (0x808+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE2,Decode Read Cache Base 2" group.long 0x80C++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG3,Decode Read Configuration 3" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x80C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE3,Decode Read Buffer Base 3" group.long (0x80C+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE3,Decode Read Cache Base 3" group.long 0x810++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG4,Decode Read Configuration 4" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x810+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE4,Decode Read Buffer Base 4" group.long (0x810+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE4,Decode Read Cache Base 4" group.long 0x814++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG5,Decode Read Configuration 5" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x814+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE5,Decode Read Buffer Base 5" group.long (0x814+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE5,Decode Read Cache Base 5" group.long 0x818++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG6,Decode Read Configuration 6" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x818+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE6,Decode Read Buffer Base 6" group.long (0x818+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE6,Decode Read Cache Base 6" group.long 0x81C++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG7,Decode Read Configuration 7" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x81C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE7,Decode Read Buffer Base 7" group.long (0x81C+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE7,Decode Read Cache Base 7" group.long 0x820++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG8,Decode Read Configuration 8" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x820+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE8,Decode Read Buffer Base 8" group.long (0x820+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE8,Decode Read Cache Base 8" group.long 0x824++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG9,Decode Read Configuration 9" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x824+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE9,Decode Read Buffer Base 9" group.long (0x824+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE9,Decode Read Cache Base 9" group.long 0x828++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG10,Decode Read Configuration 10" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x828+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE10,Decode Read Buffer Base 10" group.long (0x828+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE10,Decode Read Cache Base 10" group.long 0x82C++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG11,Decode Read Configuration 11" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x82C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE11,Decode Read Buffer Base 11" group.long (0x82C+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE11,Decode Read Cache Base 11" group.long 0x830++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG12,Decode Read Configuration 12" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x830+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE12,Decode Read Buffer Base 12" group.long (0x830+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE12,Decode Read Cache Base 12" group.long 0x834++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG13,Decode Read Configuration 13" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x834+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE13,Decode Read Buffer Base 13" group.long (0x834+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE13,Decode Read Cache Base 13" group.long 0x838++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG14,Decode Read Configuration 14" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x838+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE14,Decode Read Buffer Base 14" group.long (0x838+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE14,Decode Read Cache Base 14" group.long 0x83C++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG15,Decode Read Configuration 15" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x83C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE15,Decode Read Buffer Base 15" group.long (0x83C+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE15,Decode Read Cache Base 15" group.long 0x840++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG16,Decode Read Configuration 16" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x840+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE16,Decode Read Buffer Base 16" group.long (0x840+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE16,Decode Read Cache Base 16" group.long 0x844++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG17,Decode Read Configuration 17" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x844+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE17,Decode Read Buffer Base 17" group.long (0x844+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE17,Decode Read Cache Base 17" group.long 0x848++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG18,Decode Read Configuration 18" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x848+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE18,Decode Read Buffer Base 18" group.long (0x848+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE18,Decode Read Cache Base 18" group.long 0x84C++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG19,Decode Read Configuration 19" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x84C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE19,Decode Read Buffer Base 19" group.long (0x84C+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE19,Decode Read Cache Base 19" group.long 0x850++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG20,Decode Read Configuration 20" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x850+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE20,Decode Read Buffer Base 20" group.long (0x850+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE20,Decode Read Cache Base 20" group.long 0x854++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG21,Decode Read Configuration 21" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x854+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE21,Decode Read Buffer Base 21" group.long (0x854+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE21,Decode Read Cache Base 21" group.long 0x858++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG22,Decode Read Configuration 22" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x858+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE22,Decode Read Buffer Base 22" group.long (0x858+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE22,Decode Read Cache Base 22" group.long 0x85C++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG23,Decode Read Configuration 23" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x85C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE23,Decode Read Buffer Base 23" group.long (0x85C+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE23,Decode Read Cache Base 23" group.long 0x860++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG24,Decode Read Configuration 24" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x860+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE24,Decode Read Buffer Base 24" group.long (0x860+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE24,Decode Read Cache Base 24" group.long 0x864++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG25,Decode Read Configuration 25" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x864+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE25,Decode Read Buffer Base 25" group.long (0x864+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE25,Decode Read Cache Base 25" group.long 0x868++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG26,Decode Read Configuration 26" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x868+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE26,Decode Read Buffer Base 26" group.long (0x868+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE26,Decode Read Cache Base 26" group.long 0x86C++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG27,Decode Read Configuration 27" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x86C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE27,Decode Read Buffer Base 27" group.long (0x86C+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE27,Decode Read Cache Base 27" group.long 0x870++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG28,Decode Read Configuration 28" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x870+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE28,Decode Read Buffer Base 28" group.long (0x870+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE28,Decode Read Cache Base 28" group.long 0x874++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG29,Decode Read Configuration 29" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x874+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE29,Decode Read Buffer Base 29" group.long (0x874+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE29,Decode Read Cache Base 29" group.long 0x878++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG30,Decode Read Configuration 30" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x878+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE30,Decode Read Buffer Base 30" group.long (0x878+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE30,Decode Read Cache Base 30" group.long 0x87C++0x03 line.long 0x00 "GCREGAHBDECREADCONFIG31,Decode Read Configuration 31" bitfld.long 0x00 25.--29. " TILE_MODE ,Tile mode" "TILE8X8_XMAJOR,TILE8X8_YMAJOR,TILE16X4,TILE8X4,TILE4X8,TILE4X4,RASTER16X4,TILE64X4,TILE32X4,RASTER256X1,RASTER128X1,RASTER64X4,RASTER256X2,RASTER128X2,RASTER128X4,RASTER64X1,?..." bitfld.long 0x00 22.--24. " TILE_ALIGN_MODE ,Tile align mode" "TILE1_ALIGN,TILE2_ALIGN,TILE4_ALIGN,CBSR_ALIGN,?..." bitfld.long 0x00 16.--17. " COMPRESSION_ALIGN_MODE ,Compression align mode" "ALIGN1_BYTE,ALIGN16_BYTE,ALIGN32_BYTE,ALIGN64_BYTE" textline " " bitfld.long 0x00 3.--7. " COMPRESSION_FORMAT ,Compression format" "ARGB8,?..." bitfld.long 0x00 0. " COMPRESSION_ENABLE ,Compression enable" "Disabled,Enabled" group.long (0x87C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFERBASE31,Decode Read Buffer Base 31" group.long (0x87C+0x180)++0x03 line.long 0x00 "GCREGAHBDECREADCACHEBASE31,Decode Read Cache Base 31" textline " " group.long 0xB00++0x03 line.long 0x00 "GCREGAHBDECCONTROL,Dec400D Control" bitfld.long 0x00 30. " DISABLE_MODULE_CLOCK_GATING ,Disable clock gating for sub modules" "Disabled,Enabled" bitfld.long 0x00 23. " SW_FLUSH_ID[1] ,ID of tile status flush (Request type)" "Read,Write" bitfld.long 0x00 18.--22. " SW_FLUSH_ID[0] ,ID of tile status flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 17. " CLK_DIS ,Disable clock" "No,Yes" textline " " bitfld.long 0x00 16. " DISABLE_HW_FLUSH ,Tile status cache flush through frame end pin is disabled" "Disabled,Enabled" bitfld.long 0x00 6.--10. " TILE_STATUS_READ_ID ,Tile status cache's AXI read ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " SOFT_RESET ,Soft reset the Dec400D" "No reset,Reset" bitfld.long 0x00 3. " DISABLE_DEBUG_REGISTERS ,Disable debug registers" "No,Yes" textline " " bitfld.long 0x00 2. " DISABLE_RAM_CLOCK_GATING ,Disable clock gating for RAMs" "No,Yes" bitfld.long 0x00 1. " DISABLE_COMPRESSION ,Bypass compression for all streams enable" "Disabled,Enabled" bitfld.long 0x00 0. " FLUSH ,Flush tile status cache enable" "Disabled,Enabled" textline " " rgroup.long 0xB04++0x03 line.long 0x00 "GCREGAHBDECINTRACKNOWLEDGE,Interrupt Acknowledge" bitfld.long 0x00 31. " INTR_VEC[31] ,AXI bus error interrupt acknowledge" "Clear,Interrupt" bitfld.long 0x00 30. " [30] ,Tile status flush done interrupt for write stream acknowledge [30]" "Clear,Interrupt" bitfld.long 0x00 29. " [29] ,Tile status flush done interrupt for write stream acknowledge [29]" "Clear,Interrupt" bitfld.long 0x00 28. " [28] ,Tile status flush done interrupt for write stream acknowledge [28]" "Clear,Interrupt" textline " " bitfld.long 0x00 27. " [27] ,Tile status flush done interrupt for write stream acknowledge [27]" "Clear,Interrupt" bitfld.long 0x00 26. " [26] ,Tile status flush done interrupt for write stream acknowledge [26]" "Clear,Interrupt" bitfld.long 0x00 25. " [25] ,Tile status flush done interrupt for write stream acknowledge [25]" "Clear,Interrupt" bitfld.long 0x00 24. " [24] ,Tile status flush done interrupt for write stream acknowledge [24]" "Clear,Interrupt" textline " " bitfld.long 0x00 23. " [23] ,Tile status flush done interrupt for write stream acknowledge [23]" "Clear,Interrupt" bitfld.long 0x00 22. " [22] ,Tile status flush done interrupt for write stream acknowledge [22]" "Clear,Interrupt" bitfld.long 0x00 21. " [21] ,Tile status flush done interrupt for write stream acknowledge [21]" "Clear,Interrupt" bitfld.long 0x00 20. " [20] ,Tile status flush done interrupt for write stream acknowledge [20]" "Clear,Interrupt" textline " " bitfld.long 0x00 19. " [19] ,Tile status flush done interrupt for write stream acknowledge [19]" "Clear,Interrupt" bitfld.long 0x00 18. " [18] ,Tile status flush done interrupt for write stream acknowledge [18]" "Clear,Interrupt" bitfld.long 0x00 17. " [17] ,Tile status flush done interrupt for write stream acknowledge [17]" "Clear,Interrupt" bitfld.long 0x00 16. " [16] ,Tile status flush done interrupt for write stream acknowledge [16]" "Clear,Interrupt" textline " " bitfld.long 0x00 15. " [15] ,Tile status flush done interrupt for write stream acknowledge [15]" "Clear,Interrupt" bitfld.long 0x00 14. " [14] ,Tile status flush done interrupt for write stream acknowledge [14]" "Clear,Interrupt" bitfld.long 0x00 13. " [13] ,Tile status flush done interrupt for write stream acknowledge [13]" "Clear,Interrupt" bitfld.long 0x00 12. " [12] ,Tile status flush done interrupt for write stream acknowledge [12]" "Clear,Interrupt" textline " " bitfld.long 0x00 11. " [11] ,Tile status flush done interrupt for write stream acknowledge [11]" "Clear,Interrupt" bitfld.long 0x00 10. " [10] ,Tile status flush done interrupt for write stream acknowledge [10]" "Clear,Interrupt" bitfld.long 0x00 9. " [9] ,Tile status flush done interrupt for write stream acknowledge [9]" "Clear,Interrupt" bitfld.long 0x00 8. " [8] ,Tile status flush done interrupt for write stream acknowledge [8]" "Clear,Interrupt" textline " " bitfld.long 0x00 7. " [7] ,Tile status flush done interrupt for write stream acknowledge [7]" "Clear,Interrupt" bitfld.long 0x00 6. " [6] ,Tile status flush done interrupt for write stream acknowledge [6]" "Clear,Interrupt" bitfld.long 0x00 5. " [5] ,Tile status flush done interrupt for write stream acknowledge [5]" "Clear,Interrupt" bitfld.long 0x00 4. " [4] ,Tile status flush done interrupt for write stream acknowledge [4]" "Clear,Interrupt" textline " " bitfld.long 0x00 3. " [3] ,Tile status flush done interrupt for write stream acknowledge [3]" "Clear,Interrupt" bitfld.long 0x00 2. " [2] ,Tile status flush done interrupt for write stream acknowledge [2]" "Clear,Interrupt" bitfld.long 0x00 1. " [1] ,Tile status flush done interrupt for write stream acknowledge [1]" "Clear,Interrupt" bitfld.long 0x00 0. " [0] ,Tile status flush done interrupt for write stream acknowledge [0]" "Clear,Interrupt" group.long 0xB08++0x03 line.long 0x00 "GCREGAHBDECINTRENBL,Interrupt Enable" bitfld.long 0x00 31. " INTR_VEC[31] ,AXI bus error interrupt enable [31]" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Tile status flush done interrupt for write stream enable [30]" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Tile status flush done interrupt for write stream enable [29]" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Tile status flush done interrupt for write stream enable [28]" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " [27] ,Tile status flush done interrupt for write stream enable [27]" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Tile status flush done interrupt for write stream enable [26]" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Tile status flush done interrupt for write stream enable [25]" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Tile status flush done interrupt for write stream enable [24]" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Tile status flush done interrupt for write stream enable [23]" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Tile status flush done interrupt for write stream enable [22]" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Tile status flush done interrupt for write stream enable [21]" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Tile status flush done interrupt for write stream enable [20]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [19] ,Tile status flush done interrupt for write stream enable [19]" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Tile status flush done interrupt for write stream enable [18]" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Tile status flush done interrupt for write stream enable [17]" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Tile status flush done interrupt for write stream enable [16]" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Tile status flush done interrupt for write stream enable [15]" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Tile status flush done interrupt for write stream enable [14]" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Tile status flush done interrupt for write stream enable [13]" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Tile status flush done interrupt for write stream enable [12]" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [11] ,Tile status flush done interrupt for write stream enable [11]" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Tile status flush done interrupt for write stream enable [10]" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Tile status flush done interrupt for write stream enable [9]" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Tile status flush done interrupt for write stream enable [8]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Tile status flush done interrupt for write stream enable [7]" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Tile status flush done interrupt for write stream enable [6]" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Tile status flush done interrupt for write stream enable [5]" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Tile status flush done interrupt for write stream enable [4]" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,Tile status flush done interrupt for write stream enable [3]" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Tile status flush done interrupt for write stream enable [2]" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Tile status flush done interrupt for write stream enable [1]" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Tile status flush done interrupt for write stream enable [0]" "Disabled,Enabled" rgroup.long 0xB0C++0x03 line.long 0x00 "GCREGAHBDECTILESTATUSDEBUG,Tile Status Module Debug" rgroup.long 0xB14++0x07 line.long 0x00 "GCREGAHBDECDECODERDEBUG,Decompression Module Debug" line.long 0x04 "GCREGAHBDECTOTALREADSIN,Total Reads In" rgroup.long 0xB20++0x03 line.long 0x00 "GCREGAHBDECTOTALREADBURSTSIN,Total Read Data Count" rgroup.long 0xB28++0x03 line.long 0x00 "GCREGAHBDECTOTALREADREQIN,Total Read Request In" rgroup.long 0xB30++0x03 line.long 0x00 "GCREGAHBDECTOTALREADLASTSIN,Total Input Read Last Number" rgroup.long 0xB38++0x03 line.long 0x00 "GCREGAHBDECTOTALREADSOUT,Total Reads Out" rgroup.long 0xB40++0x03 line.long 0x00 "GCREGAHBDECTOTALREADBURSTSOUT,Total Read Bursts Out" rgroup.long 0xB48++0x03 line.long 0x00 "GCREGAHBDECTOTALREADREQOUT,Total Read Request Out" rgroup.long 0xB50++0x03 line.long 0x00 "GCREGAHBDECTOTALREADLASTSOUT,Total Read Last Out" rgroup.long 0xB58++0x0F line.long 0x00 "GCREGAHBDECDEBUG0,Debug Register 0" line.long 0x04 "GCREGAHBDECDEBUG1,Debug Register 1" line.long 0x08 "GCREGAHBDECDEBUG2,Debug register 2" line.long 0x0C "GCREGAHBDECDEBUG3,Debug Register 3" group.long 0xB68++0x07 line.long 0x00 "GCREGAHBDECCONTROLEX,GCREGAHBDECCONTROLEX" line.long 0x04 "GCREGAHBDECSTATECOMMIT,GCREGAHBDECSTATECOMMIT" rgroup.long 0xB70++0x03 line.long 0x00 "GCREGAHBDECSTATELOCK,GCREGAHBDECSTATELOCK" textline " " group.long 0xC00++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG0,Decode Read Extra Configuration 0" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC00+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE0,Decoder Read Stride 0" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC00+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND0,Decoder Read Buffer End 0" group.long 0xC04++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG1,Decode Read Extra Configuration 1" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC04+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE1,Decoder Read Stride 1" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC04+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND1,Decoder Read Buffer End 1" group.long 0xC08++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG2,Decode Read Extra Configuration 2" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC08+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE2,Decoder Read Stride 2" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC08+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND2,Decoder Read Buffer End 2" group.long 0xC0C++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG3,Decode Read Extra Configuration 3" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC0C+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE3,Decoder Read Stride 3" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC0C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND3,Decoder Read Buffer End 3" group.long 0xC10++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG4,Decode Read Extra Configuration 4" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC10+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE4,Decoder Read Stride 4" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC10+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND4,Decoder Read Buffer End 4" group.long 0xC14++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG5,Decode Read Extra Configuration 5" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC14+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE5,Decoder Read Stride 5" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC14+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND5,Decoder Read Buffer End 5" group.long 0xC18++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG6,Decode Read Extra Configuration 6" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC18+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE6,Decoder Read Stride 6" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC18+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND6,Decoder Read Buffer End 6" group.long 0xC1C++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG7,Decode Read Extra Configuration 7" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC1C+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE7,Decoder Read Stride 7" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC1C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND7,Decoder Read Buffer End 7" group.long 0xC20++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG8,Decode Read Extra Configuration 8" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC20+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE8,Decoder Read Stride 8" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC20+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND8,Decoder Read Buffer End 8" group.long 0xC24++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG9,Decode Read Extra Configuration 9" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC24+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE9,Decoder Read Stride 9" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC24+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND9,Decoder Read Buffer End 9" group.long 0xC28++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG10,Decode Read Extra Configuration 10" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC28+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE10,Decoder Read Stride 10" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC28+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND10,Decoder Read Buffer End 10" group.long 0xC2C++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG11,Decode Read Extra Configuration 11" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC2C+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE11,Decoder Read Stride 11" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC2C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND11,Decoder Read Buffer End 11" group.long 0xC30++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG12,Decode Read Extra Configuration 12" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC30+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE12,Decoder Read Stride 12" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC30+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND12,Decoder Read Buffer End 12" group.long 0xC34++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG13,Decode Read Extra Configuration 13" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC34+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE13,Decoder Read Stride 13" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC34+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND13,Decoder Read Buffer End 13" group.long 0xC38++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG14,Decode Read Extra Configuration 14" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC38+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE14,Decoder Read Stride 14" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC38+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND14,Decoder Read Buffer End 14" group.long 0xC3C++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG15,Decode Read Extra Configuration 15" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC3C+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE15,Decoder Read Stride 15" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC3C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND15,Decoder Read Buffer End 15" group.long 0xC40++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG16,Decode Read Extra Configuration 16" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC40+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE16,Decoder Read Stride 16" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC40+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND16,Decoder Read Buffer End 16" group.long 0xC44++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG17,Decode Read Extra Configuration 17" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC44+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE17,Decoder Read Stride 17" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC44+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND17,Decoder Read Buffer End 17" group.long 0xC48++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG18,Decode Read Extra Configuration 18" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC48+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE18,Decoder Read Stride 18" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC48+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND18,Decoder Read Buffer End 18" group.long 0xC4C++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG19,Decode Read Extra Configuration 19" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC4C+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE19,Decoder Read Stride 19" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC4C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND19,Decoder Read Buffer End 19" group.long 0xC50++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG20,Decode Read Extra Configuration 20" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC50+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE20,Decoder Read Stride 20" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC50+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND20,Decoder Read Buffer End 20" group.long 0xC54++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG21,Decode Read Extra Configuration 21" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC54+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE21,Decoder Read Stride 21" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC54+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND21,Decoder Read Buffer End 21" group.long 0xC58++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG22,Decode Read Extra Configuration 22" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC58+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE22,Decoder Read Stride 22" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC58+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND22,Decoder Read Buffer End 22" group.long 0xC5C++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG23,Decode Read Extra Configuration 23" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC5C+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE23,Decoder Read Stride 23" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC5C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND23,Decoder Read Buffer End 23" group.long 0xC60++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG24,Decode Read Extra Configuration 24" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC60+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE24,Decoder Read Stride 24" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC60+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND24,Decoder Read Buffer End 24" group.long 0xC64++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG25,Decode Read Extra Configuration 25" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC64+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE25,Decoder Read Stride 25" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC64+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND25,Decoder Read Buffer End 25" group.long 0xC68++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG26,Decode Read Extra Configuration 26" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC68+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE26,Decoder Read Stride 26" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC68+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND26,Decoder Read Buffer End 26" group.long 0xC6C++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG27,Decode Read Extra Configuration 27" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC6C+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE27,Decoder Read Stride 27" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC6C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND27,Decoder Read Buffer End 27" group.long 0xC70++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG28,Decode Read Extra Configuration 28" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC70+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE28,Decoder Read Stride 28" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC70+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND28,Decoder Read Buffer End 28" group.long 0xC74++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG29,Decode Read Extra Configuration 29" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC74+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE29,Decoder Read Stride 29" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC74+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND29,Decoder Read Buffer End 29" group.long 0xC78++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG30,Decode Read Extra Configuration 30" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC78+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE30,Decoder Read Stride 30" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC78+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND30,Decoder Read Buffer End 30" group.long 0xC7C++0x03 line.long 0x00 "GCREGAHBDECREADEXCONFIG31,Decode Read Extra Configuration 31" bitfld.long 0x00 29. " TS_CACHE_REPLACEMENT ,TS cache replacement" "LRU,FIFO" bitfld.long 0x00 28. " INTEL_P010 ,Intels P010 format for 10 bit" "Disabled,Enabled" bitfld.long 0x00 27. " PIXEL_CACHE_REPLACEMENT ,Pixel cache replacement" "LRU,FIFO" bitfld.long 0x00 26. " TS_CACHE_READ_MODE ,TS cache read mode" "Disabled,Enabled" textline " " bitfld.long 0x00 20.--24. " STREAM_MODE ,Stream mode" ",ISA_STREAM0,ISA_STREAM1,ISA_STREAM2,ISA_STREAM3,TNR_STREAM_Y,TNR_STREAM_UV,GDC_STREAM_Y,GDC_STREAM_U,GDC_STREAM_V,VPU_SRC_Y,VPR_SRC_UV,VPU_REF_Y,VPU_REF_UV,XYZ_STREAM_AY,XYZ_STREAM_AU,XYZ_STREAM_AV,XYZ_STREAM_BY,XYZ_STREAM_BU,XYZ_STREAM_BV,?..." bitfld.long 0x00 19. " TILE_Y ,Memory layout tileY" "Disabled,Enabled" bitfld.long 0x00 16.--18. " BIT_DEPTH ,Bit depth" "8 bit,10 bit,12 bit,16 bit,?..." hexmask.long.word 0x00 3.--15. 1. " CBSR_WIDTH ,CBSR width" group.long (0xC7C+0x80)++0x03 line.long 0x00 "GCREGAHBDECREADSTRIDE31,Decoder Read Stride 31" hexmask.long.tbyte 0x00 0.--17. 1. " STRIDE ,Surface stride" group.long (0xC7C+0x100)++0x03 line.long 0x00 "GCREGAHBDECREADBUFFEREND31,Decoder Read Buffer End 31" width 0x0B tree.end tree.open "DTRC (Decompression and Tile to Raster Conversion)" tree "DTRC_CHAN2" base ad:0x00016000 width 13. if (((per.l(ad:0x00016000+0xC8)&0x80000000)==0x00)) group.long 0x00++0x07 line.long 0x00 "F0DYDSADDR,Luma Video Data Start Address" line.long 0x04 "F0DCDSADDR,Chroma Video Data Start Address" if (((per.l(ad:0x00016000+0x2C)&0x20000)==0x00)) group.long 0x08++0x07 line.long 0x00 "F0DYTSADDR,Luma Table Data Start Address" line.long 0x04 "F0DCTSADDR,Chroma Table Data Start Address" endif group.long 0x10++0x1F line.long 0x00 "F0SIZE,Frame Size" hexmask.long.word 0x00 16.--25. 1. " F0HEIGHT ,Frame height" hexmask.long.word 0x00 0.--9. 1. " F0WIDTH ,Frame width" line.long 0x04 "F0SYSSA,Luma Data Slave Start Address" hexmask.long 0x04 4.--31. 0x10 " F0SYSSA ,Luma data slave start address" bitfld.long 0x04 0. " F0YSTRBYPASS ,Luma start tile to raster scan bypass" "No bypass,Bypass" line.long 0x08 "F0SYSEA,Luma Data Slave End Address" hexmask.long 0x08 4.--31. 0x10 " F0SYSEA ,Luma data slave end address" bitfld.long 0x08 0. " F0YETRBYPASS ,End tile to raster scan bypass" "No bypass,Bypass" line.long 0x0C "F0SUVSSA,Chroma Data Slave Start Address" hexmask.long 0x0C 4.--31. 0x10 " F0SUVSSA ,Chroma data slave start address" bitfld.long 0x0C 0. " F0CSTRBYPASS ,Chroma start tile to raster scan bypass" "No bypass,Bypass" line.long 0x10 "F0SUVSEA,Chroma Data Slave End Address" hexmask.long 0x10 4.--31. 0x10 " F0SUVSEA ,Chroma data slave end address" bitfld.long 0x10 0. " F0CETRBYPASS ,End tile to raster scan bypass" "No bypass,Bypass" line.long 0x14 "F0CROPORIG,Cropped Picture Origin" hexmask.long.word 0x14 16.--28. 1. " F0CROPORIGY ,Cropped picture y origin" hexmask.long.word 0x14 0.--12. 1. " F0CROPORIGX ,Cropped picture x origin" line.long 0x18 "F0CROPSIZE,Cropped Picture Size" hexmask.long.word 0x18 16.--28. 1. " F0CROPHEIGHT ,Cropped picture height" hexmask.long.word 0x18 0.--12. 1. " F0CROPWIDTH ,Cropped picture width" line.long 0x1C "F0DCTL,Frame Data Control" bitfld.long 0x1C 18. " F0CROPENABLE ,Cropped enable" "Disabled,Enabled" bitfld.long 0x1C 17. " F0DECOMPRESS ,Decompress bypass" "G2 compressed,G2/G1 not compressed" bitfld.long 0x1C 1. " F0PIXELBITDEPTH ,Pixel bit depth" "10 bit,8 bit" bitfld.long 0x1C 0. " F0FRAMECFG ,Frame configuration ready" "Not ready,Ready" else group.long 0x60++0x07 line.long 0x00 "F1DYDSADDR,Luma Video Data Start Address" line.long 0x04 "F1DCDSADDR,Chroma Video Data Start Address" if (((per.l(ad:0x00016000+0x8C)&0x20000)==0x00)) group.long 0x68++0x07 line.long 0x00 "F1DYTSADDR,Luma Table Data Start Address" line.long 0x04 "F1DCTSADDR,Chroma Table Data Start Address" endif group.long 0x70++0x1F line.long 0x00 "F1SIZE,Frame Size" hexmask.long.word 0x00 16.--25. 1. " F1HEIGHT ,Frame height" hexmask.long.word 0x00 0.--9. 1. " F1WIDTH ,Frame width" line.long 0x04 "F1SYSSA,Luma Data Slave Start Address" hexmask.long 0x04 4.--31. 0x10 " F1SYSSA ,Luma data slave start address" bitfld.long 0x04 0. " F1YSTRBYPASS ,Luma start tile to raster scan bypass" "No bypass,Bypass" line.long 0x08 "F1SYSEA,Luma Data Slave End Address" hexmask.long 0x08 4.--31. 0x10 " F1SYSEA ,Luma data slave end address" bitfld.long 0x08 0. " F1YETRBYPASS ,End tile to raster scan bypass" "No bypass,Bypass" line.long 0x0C "F1SUVSSA,Chroma Data Slave Start Address" hexmask.long 0x0C 4.--31. 0x10 " F1SUVSSA ,Chroma data slave start address" bitfld.long 0x0C 0. " F1CSTRBYPASS ,Chroma start tile to raster scan bypass" "No bypass,Bypass" line.long 0x10 "F1SUVSEA,Chroma Data Slave End Address" hexmask.long 0x10 4.--31. 0x10 " F1SUVSEA ,Chroma data slave end address" bitfld.long 0x10 0. " F1CETRBYPASS ,End tile to raster scan bypass" "No bypass,Bypass" line.long 0x14 "F1CROPORIG,Cropped Picture Origin" hexmask.long.word 0x14 16.--28. 1. " F1CROPORIGY ,Cropped picture y origin" hexmask.long.word 0x14 0.--12. 1. " F1CROPORIGX ,Cropped picture x origin" line.long 0x18 "F1CROPSIZE,Cropped Picture Size" hexmask.long.word 0x18 16.--28. 1. " F1CROPHEIGHT ,Cropped picture height" hexmask.long.word 0x18 0.--12. 1. " F1CROPWIDTH ,Cropped picture width" line.long 0x1C "F1DCTL,Frame Data Control" bitfld.long 0x1C 18. " F1CROPENABLE ,Cropped enable" "Disabled,Enabled" bitfld.long 0x1C 17. " F1DECOMPRESS ,Decompress bypass" "G2 compressed,G2/G1 not compressed" bitfld.long 0x1C 1. " F1PIXELBITDEPTH ,Pixel bit depth" "10 bit,8 bit" bitfld.long 0x1C 0. " F1FRAMECFG ,Frame configuration ready" "Not ready,Ready" endif group.long 0xC0++0x13 line.long 0x00 "DTRCINTEN,DTRC Interrupt Enables" bitfld.long 0x00 4. " HOTRESETFINISH_EN ,Hot reset finish" "Disabled,Enabled" bitfld.long 0x00 3. " SLFRAMEFETCHDONE_EN ,Slave frame fetch done" "Disabled,Enabled" bitfld.long 0x00 2. " TIMEOUT_EN ,Time out enable" "Disabled,Enabled" bitfld.long 0x00 1. " BUSERROR_EN ,Bus error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRAMEFETCHDONE_EN ,Frame fetch done interrupt enable" "Disabled,Enabled" line.long 0x04 "FDINTR,DTRC Interrupt Requests" bitfld.long 0x04 4. " HOTRESETFINISH ,Hot reset finish interrupt" "No interrupt,Interrupt" bitfld.long 0x04 3. " SLFRAMEFETCHDONE ,Slave frame fetch done interrupt" "No interrupt,Interrupt" bitfld.long 0x04 2. " TIMEOUT ,Time out interrupt" "No interrupt,Interrupt" rbitfld.long 0x04 1. " BUSERROR ,Bus error interrupt" "No interrupt,Interrupt" textline " " rbitfld.long 0x04 0. " FRAMEFETCHDONE ,Frame fetch done interrupt" "No interrupt,Interrupt" textline " " line.long 0x08 "DTCTRL,DTRC Control" rbitfld.long 0x08 31. " FRBUFF_PTR ,Frame buffer configure pointer" "Frame 0,Frame 1" textline " " bitfld.long 0x08 30. " ADDR_ARID ,Bypass tile-to-rasterscan by address or AXI ID" "ARID,ARADDR" textline " " bitfld.long 0x08 29. " RAST_ENDIAN ,Raster endian mode" "Little-endian,Big-endian" textline " " bitfld.long 0x08 28. " MERGEG1G2_ARIDEN ,Merge G2/G1 ARID enable" "Disabled,Enabled" textline " " bitfld.long 0x08 24.--27. " BYTESWAP_M_NONG1G2 ,Byte swap mode for master interface non-G1/G2 data" "0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15,1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14,2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13,3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12,4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11,5-4-7-6-1-0-3-2-13-12-15-14-9-8-11-10,6-7-4-5-2-3-0-1-14-15-12-13-10-11-8-9,7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8,8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7,9-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6,10-11-8-9-14-15-12-13-2-3-0-1-6-7-4-5,11-10-9-8-15-14-13-12-3-2-1-0-7-6-5-4,12-13-14-15-8-9-10-11-4-5-6-7-0-1-2-3,13-12-15-14-9-8-11-10-5-4-7-6-1-0-3-2,14-15-12-13-10-11-8-9-6-7-4-5-2-3-0-1,15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0" textline " " bitfld.long 0x08 20.--23. " BYTESWAP_MTABLE ,Byte swap mode for master interface table data" "0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15,1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14,2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13,3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12,4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11,5-4-7-6-1-0-3-2-13-12-15-14-9-8-11-10,6-7-4-5-2-3-0-1-14-15-12-13-10-11-8-9,7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8,8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7,9-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6,10-11-8-9-14-15-12-13-2-3-0-1-6-7-4-5,11-10-9-8-15-14-13-12-3-2-1-0-7-6-5-4,12-13-14-15-8-9-10-11-4-5-6-7-0-1-2-3,13-12-15-14-9-8-11-10-5-4-7-6-1-0-3-2,14-15-12-13-10-11-8-9-6-7-4-5-2-3-0-1,15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0" textline " " bitfld.long 0x08 16.--19. " BYTESWAP_MCOMPTILE ,Byte swap mode for master interface compressed data and tiled data" "0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15,1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14,2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13,3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12,4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11,5-4-7-6-1-0-3-2-13-12-15-14-9-8-11-10,6-7-4-5-2-3-0-1-14-15-12-13-10-11-8-9,7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8,8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7,9-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6,10-11-8-9-14-15-12-13-2-3-0-1-6-7-4-5,11-10-9-8-15-14-13-12-3-2-1-0-7-6-5-4,12-13-14-15-8-9-10-11-4-5-6-7-0-1-2-3,13-12-15-14-9-8-11-10-5-4-7-6-1-0-3-2,14-15-12-13-10-11-8-9-6-7-4-5-2-3-0-1,15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0" textline " " bitfld.long 0x08 12.--15. " BYTESWAP_SLRAST ,Byte swap mode for slave interface raster scan data" "0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15,1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14,2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13,3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12,4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11,5-4-7-6-1-0-3-2-13-12-15-14-9-8-11-10,6-7-4-5-2-3-0-1-14-15-12-13-10-11-8-9,7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8,8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7,9-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6,10-11-8-9-14-15-12-13-2-3-0-1-6-7-4-5,11-10-9-8-15-14-13-12-3-2-1-0-7-6-5-4,12-13-14-15-8-9-10-11-4-5-6-7-0-1-2-3,13-12-15-14-9-8-11-10-5-4-7-6-1-0-3-2,14-15-12-13-10-11-8-9-6-7-4-5-2-3-0-1,15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0" textline " " hexmask.long.byte 0x08 4.--11. 1. " AXIMAXBURSTL ,Maximum burst length of AXI master port" textline " " bitfld.long 0x08 3. " G1G2DATA ,G2 or G1 source data" "G2,G1" textline " " bitfld.long 0x08 2. " HOTRESETTRIG ,Hot reset trigger" "Not triggered,Triggered" textline " " bitfld.long 0x08 0.--1. " ARIDRCFG ,ARIDR configuration" "All ARID de-tiled,ARID in ARIDR de-tiled,ARID in ARIDR bypass de-tile,ARID in ARIDR de-tiled" textline " " line.long 0x0C "ARIDR,ARIDR" line.long 0x10 "DTID2DDR,DTID2DDR" hexmask.long.byte 0x10 8.--15. 1. " ARID_TABLE ,ARID of table fetching/ARID of chroma data" hexmask.long.byte 0x10 0.--7. 1. " ARID_COMPR ,ARID of compressed data fetching/ARID of luma data" rgroup.long 0xD4++0x07 line.long 0x00 "DTRCCONFIG,DTRCCONFIG" bitfld.long 0x00 4.--5. " MAX_PIC_WIDTH ,Maximum supported picture width" "4096,1920,?..." bitfld.long 0x00 3. " G1TILE_INPUT ,G1 tile input support" "Not supported,Supported" bitfld.long 0x00 2. " AXI_MAXBURSTL ,Maximum burst length of AXI master port" "Not supported,Supported" bitfld.long 0x00 1. " G1G2_KEEPORDER ,Keep the order between g1/g2 transactions and non-g1/g2 transactions at AXI slave interface" "Not supported,Supported" textline " " line.long 0x04 "DTRCVERSION,DTRC Version" bitfld.long 0x04 10.--15. " MAJOR ,Major version" "G2 tile + G2 compressed,G1 tile + G2 tile + G2 compressed,?..." textline " " bitfld.long 0x04 4.--9. " MINOR ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 0.--3. " CUST_VERSION ,Customer version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group.long 0xF0++0x0B line.long 0x00 "PFCTRL,Performance Counter Control" bitfld.long 0x00 0. " PFC_EN ,Performance counter enable" "Disabled,Enabled" line.long 0x04 "PFCR,Performance Counter" line.long 0x08 "TOCR,Time Out Cycles" width 0x0B tree.end tree "DTRC_CHAN3" base ad:0x00017000 width 13. if (((per.l(ad:0x00017000+0xC8)&0x80000000)==0x00)) group.long 0x00++0x07 line.long 0x00 "F0DYDSADDR,Luma Video Data Start Address" line.long 0x04 "F0DCDSADDR,Chroma Video Data Start Address" if (((per.l(ad:0x00017000+0x2C)&0x20000)==0x00)) group.long 0x08++0x07 line.long 0x00 "F0DYTSADDR,Luma Table Data Start Address" line.long 0x04 "F0DCTSADDR,Chroma Table Data Start Address" endif group.long 0x10++0x1F line.long 0x00 "F0SIZE,Frame Size" hexmask.long.word 0x00 16.--25. 1. " F0HEIGHT ,Frame height" hexmask.long.word 0x00 0.--9. 1. " F0WIDTH ,Frame width" line.long 0x04 "F0SYSSA,Luma Data Slave Start Address" hexmask.long 0x04 4.--31. 0x10 " F0SYSSA ,Luma data slave start address" bitfld.long 0x04 0. " F0YSTRBYPASS ,Luma start tile to raster scan bypass" "No bypass,Bypass" line.long 0x08 "F0SYSEA,Luma Data Slave End Address" hexmask.long 0x08 4.--31. 0x10 " F0SYSEA ,Luma data slave end address" bitfld.long 0x08 0. " F0YETRBYPASS ,End tile to raster scan bypass" "No bypass,Bypass" line.long 0x0C "F0SUVSSA,Chroma Data Slave Start Address" hexmask.long 0x0C 4.--31. 0x10 " F0SUVSSA ,Chroma data slave start address" bitfld.long 0x0C 0. " F0CSTRBYPASS ,Chroma start tile to raster scan bypass" "No bypass,Bypass" line.long 0x10 "F0SUVSEA,Chroma Data Slave End Address" hexmask.long 0x10 4.--31. 0x10 " F0SUVSEA ,Chroma data slave end address" bitfld.long 0x10 0. " F0CETRBYPASS ,End tile to raster scan bypass" "No bypass,Bypass" line.long 0x14 "F0CROPORIG,Cropped Picture Origin" hexmask.long.word 0x14 16.--28. 1. " F0CROPORIGY ,Cropped picture y origin" hexmask.long.word 0x14 0.--12. 1. " F0CROPORIGX ,Cropped picture x origin" line.long 0x18 "F0CROPSIZE,Cropped Picture Size" hexmask.long.word 0x18 16.--28. 1. " F0CROPHEIGHT ,Cropped picture height" hexmask.long.word 0x18 0.--12. 1. " F0CROPWIDTH ,Cropped picture width" line.long 0x1C "F0DCTL,Frame Data Control" bitfld.long 0x1C 18. " F0CROPENABLE ,Cropped enable" "Disabled,Enabled" bitfld.long 0x1C 17. " F0DECOMPRESS ,Decompress bypass" "G2 compressed,G2/G1 not compressed" bitfld.long 0x1C 1. " F0PIXELBITDEPTH ,Pixel bit depth" "10 bit,8 bit" bitfld.long 0x1C 0. " F0FRAMECFG ,Frame configuration ready" "Not ready,Ready" else group.long 0x60++0x07 line.long 0x00 "F1DYDSADDR,Luma Video Data Start Address" line.long 0x04 "F1DCDSADDR,Chroma Video Data Start Address" if (((per.l(ad:0x00017000+0x8C)&0x20000)==0x00)) group.long 0x68++0x07 line.long 0x00 "F1DYTSADDR,Luma Table Data Start Address" line.long 0x04 "F1DCTSADDR,Chroma Table Data Start Address" endif group.long 0x70++0x1F line.long 0x00 "F1SIZE,Frame Size" hexmask.long.word 0x00 16.--25. 1. " F1HEIGHT ,Frame height" hexmask.long.word 0x00 0.--9. 1. " F1WIDTH ,Frame width" line.long 0x04 "F1SYSSA,Luma Data Slave Start Address" hexmask.long 0x04 4.--31. 0x10 " F1SYSSA ,Luma data slave start address" bitfld.long 0x04 0. " F1YSTRBYPASS ,Luma start tile to raster scan bypass" "No bypass,Bypass" line.long 0x08 "F1SYSEA,Luma Data Slave End Address" hexmask.long 0x08 4.--31. 0x10 " F1SYSEA ,Luma data slave end address" bitfld.long 0x08 0. " F1YETRBYPASS ,End tile to raster scan bypass" "No bypass,Bypass" line.long 0x0C "F1SUVSSA,Chroma Data Slave Start Address" hexmask.long 0x0C 4.--31. 0x10 " F1SUVSSA ,Chroma data slave start address" bitfld.long 0x0C 0. " F1CSTRBYPASS ,Chroma start tile to raster scan bypass" "No bypass,Bypass" line.long 0x10 "F1SUVSEA,Chroma Data Slave End Address" hexmask.long 0x10 4.--31. 0x10 " F1SUVSEA ,Chroma data slave end address" bitfld.long 0x10 0. " F1CETRBYPASS ,End tile to raster scan bypass" "No bypass,Bypass" line.long 0x14 "F1CROPORIG,Cropped Picture Origin" hexmask.long.word 0x14 16.--28. 1. " F1CROPORIGY ,Cropped picture y origin" hexmask.long.word 0x14 0.--12. 1. " F1CROPORIGX ,Cropped picture x origin" line.long 0x18 "F1CROPSIZE,Cropped Picture Size" hexmask.long.word 0x18 16.--28. 1. " F1CROPHEIGHT ,Cropped picture height" hexmask.long.word 0x18 0.--12. 1. " F1CROPWIDTH ,Cropped picture width" line.long 0x1C "F1DCTL,Frame Data Control" bitfld.long 0x1C 18. " F1CROPENABLE ,Cropped enable" "Disabled,Enabled" bitfld.long 0x1C 17. " F1DECOMPRESS ,Decompress bypass" "G2 compressed,G2/G1 not compressed" bitfld.long 0x1C 1. " F1PIXELBITDEPTH ,Pixel bit depth" "10 bit,8 bit" bitfld.long 0x1C 0. " F1FRAMECFG ,Frame configuration ready" "Not ready,Ready" endif group.long 0xC0++0x13 line.long 0x00 "DTRCINTEN,DTRC Interrupt Enables" bitfld.long 0x00 4. " HOTRESETFINISH_EN ,Hot reset finish" "Disabled,Enabled" bitfld.long 0x00 3. " SLFRAMEFETCHDONE_EN ,Slave frame fetch done" "Disabled,Enabled" bitfld.long 0x00 2. " TIMEOUT_EN ,Time out enable" "Disabled,Enabled" bitfld.long 0x00 1. " BUSERROR_EN ,Bus error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FRAMEFETCHDONE_EN ,Frame fetch done interrupt enable" "Disabled,Enabled" line.long 0x04 "FDINTR,DTRC Interrupt Requests" bitfld.long 0x04 4. " HOTRESETFINISH ,Hot reset finish interrupt" "No interrupt,Interrupt" bitfld.long 0x04 3. " SLFRAMEFETCHDONE ,Slave frame fetch done interrupt" "No interrupt,Interrupt" bitfld.long 0x04 2. " TIMEOUT ,Time out interrupt" "No interrupt,Interrupt" rbitfld.long 0x04 1. " BUSERROR ,Bus error interrupt" "No interrupt,Interrupt" textline " " rbitfld.long 0x04 0. " FRAMEFETCHDONE ,Frame fetch done interrupt" "No interrupt,Interrupt" textline " " line.long 0x08 "DTCTRL,DTRC Control" rbitfld.long 0x08 31. " FRBUFF_PTR ,Frame buffer configure pointer" "Frame 0,Frame 1" textline " " bitfld.long 0x08 30. " ADDR_ARID ,Bypass tile-to-rasterscan by address or AXI ID" "ARID,ARADDR" textline " " bitfld.long 0x08 29. " RAST_ENDIAN ,Raster endian mode" "Little-endian,Big-endian" textline " " bitfld.long 0x08 28. " MERGEG1G2_ARIDEN ,Merge G2/G1 ARID enable" "Disabled,Enabled" textline " " bitfld.long 0x08 24.--27. " BYTESWAP_M_NONG1G2 ,Byte swap mode for master interface non-G1/G2 data" "0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15,1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14,2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13,3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12,4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11,5-4-7-6-1-0-3-2-13-12-15-14-9-8-11-10,6-7-4-5-2-3-0-1-14-15-12-13-10-11-8-9,7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8,8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7,9-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6,10-11-8-9-14-15-12-13-2-3-0-1-6-7-4-5,11-10-9-8-15-14-13-12-3-2-1-0-7-6-5-4,12-13-14-15-8-9-10-11-4-5-6-7-0-1-2-3,13-12-15-14-9-8-11-10-5-4-7-6-1-0-3-2,14-15-12-13-10-11-8-9-6-7-4-5-2-3-0-1,15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0" textline " " bitfld.long 0x08 20.--23. " BYTESWAP_MTABLE ,Byte swap mode for master interface table data" "0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15,1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14,2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13,3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12,4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11,5-4-7-6-1-0-3-2-13-12-15-14-9-8-11-10,6-7-4-5-2-3-0-1-14-15-12-13-10-11-8-9,7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8,8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7,9-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6,10-11-8-9-14-15-12-13-2-3-0-1-6-7-4-5,11-10-9-8-15-14-13-12-3-2-1-0-7-6-5-4,12-13-14-15-8-9-10-11-4-5-6-7-0-1-2-3,13-12-15-14-9-8-11-10-5-4-7-6-1-0-3-2,14-15-12-13-10-11-8-9-6-7-4-5-2-3-0-1,15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0" textline " " bitfld.long 0x08 16.--19. " BYTESWAP_MCOMPTILE ,Byte swap mode for master interface compressed data and tiled data" "0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15,1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14,2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13,3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12,4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11,5-4-7-6-1-0-3-2-13-12-15-14-9-8-11-10,6-7-4-5-2-3-0-1-14-15-12-13-10-11-8-9,7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8,8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7,9-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6,10-11-8-9-14-15-12-13-2-3-0-1-6-7-4-5,11-10-9-8-15-14-13-12-3-2-1-0-7-6-5-4,12-13-14-15-8-9-10-11-4-5-6-7-0-1-2-3,13-12-15-14-9-8-11-10-5-4-7-6-1-0-3-2,14-15-12-13-10-11-8-9-6-7-4-5-2-3-0-1,15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0" textline " " bitfld.long 0x08 12.--15. " BYTESWAP_SLRAST ,Byte swap mode for slave interface raster scan data" "0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15,1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14,2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13,3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12,4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11,5-4-7-6-1-0-3-2-13-12-15-14-9-8-11-10,6-7-4-5-2-3-0-1-14-15-12-13-10-11-8-9,7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8,8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7,9-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6,10-11-8-9-14-15-12-13-2-3-0-1-6-7-4-5,11-10-9-8-15-14-13-12-3-2-1-0-7-6-5-4,12-13-14-15-8-9-10-11-4-5-6-7-0-1-2-3,13-12-15-14-9-8-11-10-5-4-7-6-1-0-3-2,14-15-12-13-10-11-8-9-6-7-4-5-2-3-0-1,15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0" textline " " hexmask.long.byte 0x08 4.--11. 1. " AXIMAXBURSTL ,Maximum burst length of AXI master port" textline " " bitfld.long 0x08 3. " G1G2DATA ,G2 or G1 source data" "G2,G1" textline " " bitfld.long 0x08 2. " HOTRESETTRIG ,Hot reset trigger" "Not triggered,Triggered" textline " " bitfld.long 0x08 0.--1. " ARIDRCFG ,ARIDR configuration" "All ARID de-tiled,ARID in ARIDR de-tiled,ARID in ARIDR bypass de-tile,ARID in ARIDR de-tiled" textline " " line.long 0x0C "ARIDR,ARIDR" line.long 0x10 "DTID2DDR,DTID2DDR" hexmask.long.byte 0x10 8.--15. 1. " ARID_TABLE ,ARID of table fetching/ARID of chroma data" hexmask.long.byte 0x10 0.--7. 1. " ARID_COMPR ,ARID of compressed data fetching/ARID of luma data" rgroup.long 0xD4++0x07 line.long 0x00 "DTRCCONFIG,DTRCCONFIG" bitfld.long 0x00 4.--5. " MAX_PIC_WIDTH ,Maximum supported picture width" "4096,1920,?..." bitfld.long 0x00 3. " G1TILE_INPUT ,G1 tile input support" "Not supported,Supported" bitfld.long 0x00 2. " AXI_MAXBURSTL ,Maximum burst length of AXI master port" "Not supported,Supported" bitfld.long 0x00 1. " G1G2_KEEPORDER ,Keep the order between g1/g2 transactions and non-g1/g2 transactions at AXI slave interface" "Not supported,Supported" textline " " line.long 0x04 "DTRCVERSION,DTRC Version" bitfld.long 0x04 10.--15. " MAJOR ,Major version" "G2 tile + G2 compressed,G1 tile + G2 tile + G2 compressed,?..." textline " " bitfld.long 0x04 4.--9. " MINOR ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 0.--3. " CUST_VERSION ,Customer version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group.long 0xF0++0x0B line.long 0x00 "PFCTRL,Performance Counter Control" bitfld.long 0x00 0. " PFC_EN ,Performance counter enable" "Disabled,Enabled" line.long 0x04 "PFCR,Performance Counter" line.long 0x08 "TOCR,Time Out Cycles" width 0x0B tree.end tree.end tree.open "DPR (Display Prefetch and Resolve)" tree "DPR1" base ad:0x00018000 width 30. group.long 0x00++0x03 line.long 0x00 "SYSTEM_CTRL0_SET/CLR,System Control 0 Set/Clear" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " BCMD2AXI_MSTR_ID_CTRL ,Buscmd to AXI master ID control" "Unique,Same" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Subystem hardware signal,SHADOW_LOAD_EN" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x04 2. 0x08 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SOFT_RESET ,Soft reset" "No reset,Reset" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_EN ,Run enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "SYSTEM_CTRL0_TOG,System Control 0 Toggle" bitfld.long 0x00 16. " BCMD2AXI_MSTR_ID_CTRL ,Buscmd to AXI master ID control" "Assigned unique AXI ID,Assigned same AXI ID" bitfld.long 0x00 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Subystem hardware signal,SHADOW_LOAD_EN" bitfld.long 0x00 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" bitfld.long 0x00 1. " SOFT_RESET ,Soft reset" "No reset,Reset" bitfld.long 0x00 0. " RUN_EN ,Run enable" "Disabled,Enabled" textline " " group.long 0x20++0x03 line.long 0x00 "IRQ_MASK_SET/CLR,Interrupt Mask Set/Clear" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer ready IRQ error mask" "Not masked,Masked" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer ready IRQ error mask" "Not masked,Masked" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow IRQ mask" "Not masked,Masked" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow IRQ mask" "Not masked,Masked" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "Not masked,Masked" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "Not masked,Masked" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "Not masked,Masked" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "Not masked,Masked" group.long 0x2C++0x07 line.long 0x00 "IRQ_MASK_TOG,Interrupt Mask Toggle" bitfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer ready IRQ error mask" "Not masked,Masked" bitfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer ready IRQ error mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow IRQ mask" "Not masked,Masked" bitfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow IRQ mask" "Not masked,Masked" textline " " bitfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "Not masked,Masked" bitfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "Not masked,Masked" textline " " bitfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "Not masked,Masked" bitfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "Not masked,Masked" line.long 0x04 "IRQ_MASK_STATUS_SET/CLR,Status Register of Masked IRQ Set/Clear" setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer error masked IRQ" "Not masked,Masked" setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer error masked IRQ" "Not masked,Masked" textline " " setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow masked IRQ" "Not masked,Masked" setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow masked IRQ" "Not masked,Masked" textline " " setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "Not masked,Masked" setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "Not masked,Masked" textline " " setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "Not masked,Masked" setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "Not masked,Masked" group.long 0x3C++0x07 line.long 0x00 "IRQ_MASK_STATUS_TOG,Status Register of Masked IRQ" bitfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer error masked IRQ" "Not masked,Masked" bitfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer error masked IRQ" "Not masked,Masked" textline " " bitfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow masked IRQ" "Not masked,Masked" bitfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow masked IRQ" "Not masked,Masked" textline " " bitfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "Not masked,Masked" bitfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "Not masked,Masked" textline " " bitfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "Not masked,Masked" bitfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "Not masked,Masked" line.long 0x04 "IRQ_NONMASK_STATUS_SET/CLR,Status of Non-Masked IRQ Set/Clear" setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow non-masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow non-masked IRQ" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" group.long 0x4C++0x13 line.long 0x00 "IRQ_NONMASK_STATUS_TOG,Status of Non-Masked IRQ Toggle" eventfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow non-masked IRQ" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" textline " " line.long 0x04 "MODE_CTRL0,Mode Control 0" bitfld.long 0x04 18.--19. " A_COMP_SEL ,Alpha component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x04 16.--17. " R_COMP_SEL ,Red component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x04 14.--15. " G_COMP_SEL ,Green component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x04 12.--13. " B_COMP_SEL ,Blue component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " setclrfld.long 0x04 11. 0x08 11. 0x0C 11. " PIX_UV_SWAP_SET/CLR ,Pixel UV swap" "Not swapped,Swapped" setclrfld.long 0x04 10. 0x08 10. 0x0C 10. " PIX_LUMA_UV_SWAP_SET/CLR ,Pixel luma/UV position swap" "YUYV,UYVY" textline " " bitfld.long 0x04 8.--9. " PIX_SIZE ,Pixel size" "8 bits,16 bits,32 bits,?..." setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " COMP_2PLANE_EN_SET/CLR ,Component 2-plane enable" "Disabled,Enabled" textline " " setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " YUV_EN_SET/CLR ,YUV enable" "Disabled,Enabled" bitfld.long 0x04 2.--4. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU 2PYUV420,VPU 2-Plane VP9,?..." textline " " setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " RTR_4LINE_BUF_EN_SET/CLR ,RTRAM lines per buffer" "8 RTRAM,4 RTRAM" setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " RTR_3BUF_EN_SET/CLR ,RTRAM buffer implementation" "2 RTRAM,3 RTRAM" line.long 0x08 "MODE_CTRL0_SET,Mode Control 0 Set" bitfld.long 0x08 18.--19. " A_COMP_SEL ,Alpha component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x08 16.--17. " R_COMP_SEL ,Red component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x08 14.--15. " G_COMP_SEL ,Green component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x08 12.--13. " B_COMP_SEL ,Blue component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x08 8.--9. " PIX_SIZE ,Pixel size" "8 bits,16 bits,32 bits,?..." bitfld.long 0x08 2.--4. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU 2PYUV420,VPU 2-Plane VP9,?..." line.long 0x0C "MODE_CTRL0_CLR,Mode Control 0 Clear" bitfld.long 0x0C 18.--19. " A_COMP_SEL ,Alpha component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x0C 16.--17. " R_COMP_SEL ,Red component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x0C 14.--15. " G_COMP_SEL ,Green component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x0C 12.--13. " B_COMP_SEL ,Blue component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x0C 8.--9. " PIX_SIZE ,Pixel size" "8 bits,16 bits,32 bits,?..." bitfld.long 0x0C 2.--4. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU 2PYUV420,VPU 2-Plane VP9,?..." line.long 0x10 "MODE_CTRL0_TOG,Mode Control 0 Toggle" bitfld.long 0x10 18.--19. " A_COMP_SEL ,Alpha component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x10 16.--17. " R_COMP_SEL ,Red component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x10 14.--15. " G_COMP_SEL ,Green component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x10 12.--13. " B_COMP_SEL ,Blue component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x10 11. " PIX_UV_SWAP ,Pixel UV swap" "Not swapped,Swapped" bitfld.long 0x10 10. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" textline " " bitfld.long 0x10 8.--9. " PIX_SIZE ,Pixel size" "8 bits,16 bits,32 bits,?..." bitfld.long 0x10 7. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" textline " " bitfld.long 0x10 6. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x10 2.--4. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU 2PYUV420,VPU 2-Plane VP9,?..." textline " " bitfld.long 0x10 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8 RTRAM,4 RTRAM" bitfld.long 0x10 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2 RTRAM,3 RTRAM" group.long 0x70++0x0F line.long 0x00 "FRAME_CTRL0,Frame Control 0" hexmask.long.word 0x00 16.--31. 1. " PITCH ,Image Pitch" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " ROT_FLIP_ORDER_EN ,Rotation flip order" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " ROT_ENC ,Encoded rotation" "0,90,180,270" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x04 "FRAME_CTRL0_SET,Frame Control 0 Set" hexmask.long.word 0x04 16.--31. 1. " PITCH ,Image Pitch" bitfld.long 0x04 2.--3. " ROT_ENC ,Encoded rotation" "0 degrees,90 degrees counter clock wise,180 degrees counter clock wise,270 degrees counter clock wise" line.long 0x08 "FRAME_CTRL0_CLR,Frame Control 0 Clear" hexmask.long.word 0x08 16.--31. 1. " PITCH ,Image Pitch" bitfld.long 0x08 2.--3. " ROT_ENC ,Encoded rotation" "0 degrees,90 degrees counter clock wise,180 degrees counter clock wise,270 degrees counter clock wise" line.long 0x0C "FRAME_CTRL0_TOG,Frame Control 0 Toggle" hexmask.long.word 0x0C 16.--31. 1. " PITCH ,Image Pitch" bitfld.long 0x0C 4. " ROT_FLIP_ORDER_EN ,Rotation flip order" "Rotate/flip,Flip/rotate" textline " " bitfld.long 0x0C 2.--3. " ROT_ENC ,Encoded rotation" "0 degrees,90 degrees counter clock wise,180 degrees counter clock wise,270 degrees counter clock wise" bitfld.long 0x0C 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" textline " " if (((per.l(ad:0x00018000+0x70)&0x0C)==(0x04||0x0C)))||(((per.l(ad:0x00018000+0x50)&0x1C)==(0x0C||0x10)))||(((per.l(ad:0x00018000+0x50)&0x31C)==0x108)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." elif (((per.l(ad:0x00018000+0x50)&0x31C)==0x208)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." else group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" endif group.long 0xA0++0x2F line.long 0x00 "FRAME_1P_PIX_X_CTRL,Frame 1-Plane Pix X Control" hexmask.long.word 0x00 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" hexmask.long.word 0x00 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x04 "FRAME_1P_PIX_X_CTRL_SET,Frame 1-Plane Pix X Control Set" hexmask.long.word 0x04 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" hexmask.long.word 0x04 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x08 "FRAME_1P_PIX_X_CTRL_CLR,Frame 1-Plane Pix X Control Clear" hexmask.long.word 0x08 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" hexmask.long.word 0x08 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x0C "FRAME_1P_PIX_X_CTRL_TOG,Frame 1-Plane Pix X Control Toggle" hexmask.long.word 0x0C 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" hexmask.long.word 0x0C 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x10 "FRAME_1P_PIX_Y_CTRL,Frame 1-Plane Pix Y Control" hexmask.long.word 0x10 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (1-Plane or 2-Plane Luma)" hexmask.long.word 0x10 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x14 "FRAME_1P_PIX_Y_CTRL_SET,Frame 1-Plane Pix Y Control Set" hexmask.long.word 0x14 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (1-Plane or 2-Plane Luma)" hexmask.long.word 0x14 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x18 "FRAME_1P_PIX_Y_CTRL_CLR,Frame 1-Plane Pix Y Control Clear" hexmask.long.word 0x18 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (1-Plane or 2-Plane Luma)" hexmask.long.word 0x18 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x1C "FRAME_1P_PIX_Y_CTRL_TOG,Frame 1-Plane Pix Y Control Toggle" hexmask.long.word 0x1C 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (1-Plane or 2-Plane Luma)" hexmask.long.word 0x1C 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x20 "FRAME_1P_BASE_ADDR_CTRL0,Frame 1-Plane Base Address Control 0" line.long 0x24 "FRAME_1P_BASE_ADDR_CTRL0_SET,Frame 1-Plane Base Address Control 0 Set" line.long 0x28 "FRAME_1P_BASE_ADDR_CTRL0_CLR,Frame 1-Plane Base Address Control 0 Clear" line.long 0x2C "FRAME_1P_BASE_ADDR_CTRL0_TOG,Frame 1-Plane Base Address Control 0 Toggle" if (((per.l(ad:0x00018000+0x70)&0x0C)==(0x04||0x0C)))||(((per.l(ad:0x00018000+0x50)&0x1C)==(0x0C||0x10)))||(((per.l(ad:0x00018000+0x50)&0x31C)==0x108)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." elif (((per.l(ad:0x00018000+0x50)&0x31C)==0x208)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." else group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" endif group.long 0xF0++0x2F line.long 0x00 "FRAME_2P_PIX_X_CTRL,Frame 2-Plane Pix X Control" hexmask.long.word 0x00 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X (2-Plane UV)" hexmask.long.word 0x00 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x04 "FRAME_2P_PIX_X_CTRL_SET,Frame 2-Plane Pix X Control Set" hexmask.long.word 0x04 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X (2-Plane UV)" hexmask.long.word 0x04 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x08 "FRAME_2P_PIX_X_CTRL_CLR,Frame 2-Plane Pix X Control Clear" hexmask.long.word 0x08 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X (2-Plane UV)" hexmask.long.word 0x08 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x0C "FRAME_2P_PIX_X_CTRL_TOG,Frame 2-Plane Pix X Control Toggle" hexmask.long.word 0x0C 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X (2-Plane UV)" hexmask.long.word 0x0C 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x10 "FRAME_2P_PIX_Y_CTRL,Frame 2-Plane Pix Y Control" hexmask.long.word 0x10 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (2-Plane UV)" hexmask.long.word 0x10 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x14 "FRAME_2P_PIX_Y_CTRL_SET,Frame 2-Plane Pix Y Control Set" hexmask.long.word 0x14 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (2-Plane UV)" hexmask.long.word 0x14 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x18 "FRAME_2P_PIX_Y_CTRL_CLR,Frame 2-Plane Pix Y Control Clear" hexmask.long.word 0x18 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (2-Plane UV)" hexmask.long.word 0x18 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x1C "FRAME_2P_PIX_Y_CTRL_TOG,Frame 2-Plane Pix Y Control Toggle" hexmask.long.word 0x1C 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (2-Plane UV)" hexmask.long.word 0x1C 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x20 "FRAME_2P_BASE_ADDR_CTRL0,Frame 2-Plane Base Address Control 0" line.long 0x24 "FRAME_2P_BASE_ADDR_CTRL0_SET,Frame 2-Plane Base Address Control 0 Set" line.long 0x28 "FRAME_2P_BASE_ADDR_CTRL0_CLR,Frame 2-Plane Base Address Control 0 Clear" line.long 0x2C "FRAME_2P_BASE_ADDR_CTRL0_TOG,Frame 2-Plane Base Address Control 0 Toggle" group.long 0x200++0x0F line.long 0x00 "RTRAM_CTRL0,RTRAM Control 0" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x00 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,All rows" line.long 0x04 "RTRAM_CTRL0_SET,RTRAM Control 0 Set" bitfld.long 0x04 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x04 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" line.long 0x08 "RTRAM_CTRL0_CLR,RTRAM Control 0 Clear" bitfld.long 0x08 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x08 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" line.long 0x0C "RTRAM_CTRL0_TOG,RTRAM Control 0 Toggle" bitfld.long 0x0C 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x0C 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,All rows" width 0x0B tree.end tree "DPR2" base ad:0x00019000 width 30. group.long 0x00++0x03 line.long 0x00 "SYSTEM_CTRL0_SET/CLR,System Control 0 Set/Clear" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " BCMD2AXI_MSTR_ID_CTRL ,Buscmd to AXI master ID control" "Unique,Same" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Subystem hardware signal,SHADOW_LOAD_EN" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x04 2. 0x08 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SOFT_RESET ,Soft reset" "No reset,Reset" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_EN ,Run enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "SYSTEM_CTRL0_TOG,System Control 0 Toggle" bitfld.long 0x00 16. " BCMD2AXI_MSTR_ID_CTRL ,Buscmd to AXI master ID control" "Assigned unique AXI ID,Assigned same AXI ID" bitfld.long 0x00 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Subystem hardware signal,SHADOW_LOAD_EN" bitfld.long 0x00 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" bitfld.long 0x00 1. " SOFT_RESET ,Soft reset" "No reset,Reset" bitfld.long 0x00 0. " RUN_EN ,Run enable" "Disabled,Enabled" textline " " group.long 0x20++0x03 line.long 0x00 "IRQ_MASK_SET/CLR,Interrupt Mask Set/Clear" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer ready IRQ error mask" "Not masked,Masked" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer ready IRQ error mask" "Not masked,Masked" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow IRQ mask" "Not masked,Masked" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow IRQ mask" "Not masked,Masked" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "Not masked,Masked" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "Not masked,Masked" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "Not masked,Masked" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "Not masked,Masked" group.long 0x2C++0x07 line.long 0x00 "IRQ_MASK_TOG,Interrupt Mask Toggle" bitfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer ready IRQ error mask" "Not masked,Masked" bitfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer ready IRQ error mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow IRQ mask" "Not masked,Masked" bitfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow IRQ mask" "Not masked,Masked" textline " " bitfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "Not masked,Masked" bitfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "Not masked,Masked" textline " " bitfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "Not masked,Masked" bitfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "Not masked,Masked" line.long 0x04 "IRQ_MASK_STATUS_SET/CLR,Status Register of Masked IRQ Set/Clear" setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer error masked IRQ" "Not masked,Masked" setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer error masked IRQ" "Not masked,Masked" textline " " setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow masked IRQ" "Not masked,Masked" setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow masked IRQ" "Not masked,Masked" textline " " setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "Not masked,Masked" setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "Not masked,Masked" textline " " setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "Not masked,Masked" setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "Not masked,Masked" group.long 0x3C++0x07 line.long 0x00 "IRQ_MASK_STATUS_TOG,Status Register of Masked IRQ" bitfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer error masked IRQ" "Not masked,Masked" bitfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer error masked IRQ" "Not masked,Masked" textline " " bitfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow masked IRQ" "Not masked,Masked" bitfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow masked IRQ" "Not masked,Masked" textline " " bitfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "Not masked,Masked" bitfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "Not masked,Masked" textline " " bitfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "Not masked,Masked" bitfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "Not masked,Masked" line.long 0x04 "IRQ_NONMASK_STATUS_SET/CLR,Status of Non-Masked IRQ Set/Clear" setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow non-masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow non-masked IRQ" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" group.long 0x4C++0x13 line.long 0x00 "IRQ_NONMASK_STATUS_TOG,Status of Non-Masked IRQ Toggle" eventfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow non-masked IRQ" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" textline " " line.long 0x04 "MODE_CTRL0,Mode Control 0" bitfld.long 0x04 18.--19. " A_COMP_SEL ,Alpha component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x04 16.--17. " R_COMP_SEL ,Red component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x04 14.--15. " G_COMP_SEL ,Green component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x04 12.--13. " B_COMP_SEL ,Blue component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " setclrfld.long 0x04 11. 0x08 11. 0x0C 11. " PIX_UV_SWAP_SET/CLR ,Pixel UV swap" "Not swapped,Swapped" setclrfld.long 0x04 10. 0x08 10. 0x0C 10. " PIX_LUMA_UV_SWAP_SET/CLR ,Pixel luma/UV position swap" "YUYV,UYVY" textline " " bitfld.long 0x04 8.--9. " PIX_SIZE ,Pixel size" "8 bits,16 bits,32 bits,?..." setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " COMP_2PLANE_EN_SET/CLR ,Component 2-plane enable" "Disabled,Enabled" textline " " setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " YUV_EN_SET/CLR ,YUV enable" "Disabled,Enabled" bitfld.long 0x04 2.--4. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU 2PYUV420,VPU 2-Plane VP9,?..." textline " " setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " RTR_4LINE_BUF_EN_SET/CLR ,RTRAM lines per buffer" "8 RTRAM,4 RTRAM" setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " RTR_3BUF_EN_SET/CLR ,RTRAM buffer implementation" "2 RTRAM,3 RTRAM" line.long 0x08 "MODE_CTRL0_SET,Mode Control 0 Set" bitfld.long 0x08 18.--19. " A_COMP_SEL ,Alpha component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x08 16.--17. " R_COMP_SEL ,Red component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x08 14.--15. " G_COMP_SEL ,Green component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x08 12.--13. " B_COMP_SEL ,Blue component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x08 8.--9. " PIX_SIZE ,Pixel size" "8 bits,16 bits,32 bits,?..." bitfld.long 0x08 2.--4. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU 2PYUV420,VPU 2-Plane VP9,?..." line.long 0x0C "MODE_CTRL0_CLR,Mode Control 0 Clear" bitfld.long 0x0C 18.--19. " A_COMP_SEL ,Alpha component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x0C 16.--17. " R_COMP_SEL ,Red component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x0C 14.--15. " G_COMP_SEL ,Green component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x0C 12.--13. " B_COMP_SEL ,Blue component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x0C 8.--9. " PIX_SIZE ,Pixel size" "8 bits,16 bits,32 bits,?..." bitfld.long 0x0C 2.--4. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU 2PYUV420,VPU 2-Plane VP9,?..." line.long 0x10 "MODE_CTRL0_TOG,Mode Control 0 Toggle" bitfld.long 0x10 18.--19. " A_COMP_SEL ,Alpha component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x10 16.--17. " R_COMP_SEL ,Red component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x10 14.--15. " G_COMP_SEL ,Green component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x10 12.--13. " B_COMP_SEL ,Blue component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x10 11. " PIX_UV_SWAP ,Pixel UV swap" "Not swapped,Swapped" bitfld.long 0x10 10. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" textline " " bitfld.long 0x10 8.--9. " PIX_SIZE ,Pixel size" "8 bits,16 bits,32 bits,?..." bitfld.long 0x10 7. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" textline " " bitfld.long 0x10 6. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x10 2.--4. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU 2PYUV420,VPU 2-Plane VP9,?..." textline " " bitfld.long 0x10 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8 RTRAM,4 RTRAM" bitfld.long 0x10 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2 RTRAM,3 RTRAM" group.long 0x70++0x0F line.long 0x00 "FRAME_CTRL0,Frame Control 0" hexmask.long.word 0x00 16.--31. 1. " PITCH ,Image Pitch" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " ROT_FLIP_ORDER_EN ,Rotation flip order" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " ROT_ENC ,Encoded rotation" "0,90,180,270" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x04 "FRAME_CTRL0_SET,Frame Control 0 Set" hexmask.long.word 0x04 16.--31. 1. " PITCH ,Image Pitch" bitfld.long 0x04 2.--3. " ROT_ENC ,Encoded rotation" "0 degrees,90 degrees counter clock wise,180 degrees counter clock wise,270 degrees counter clock wise" line.long 0x08 "FRAME_CTRL0_CLR,Frame Control 0 Clear" hexmask.long.word 0x08 16.--31. 1. " PITCH ,Image Pitch" bitfld.long 0x08 2.--3. " ROT_ENC ,Encoded rotation" "0 degrees,90 degrees counter clock wise,180 degrees counter clock wise,270 degrees counter clock wise" line.long 0x0C "FRAME_CTRL0_TOG,Frame Control 0 Toggle" hexmask.long.word 0x0C 16.--31. 1. " PITCH ,Image Pitch" bitfld.long 0x0C 4. " ROT_FLIP_ORDER_EN ,Rotation flip order" "Rotate/flip,Flip/rotate" textline " " bitfld.long 0x0C 2.--3. " ROT_ENC ,Encoded rotation" "0 degrees,90 degrees counter clock wise,180 degrees counter clock wise,270 degrees counter clock wise" bitfld.long 0x0C 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" textline " " if (((per.l(ad:0x00019000+0x70)&0x0C)==(0x04||0x0C)))||(((per.l(ad:0x00019000+0x50)&0x1C)==(0x0C||0x10)))||(((per.l(ad:0x00019000+0x50)&0x31C)==0x108)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." elif (((per.l(ad:0x00019000+0x50)&0x31C)==0x208)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." else group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" endif group.long 0xA0++0x2F line.long 0x00 "FRAME_1P_PIX_X_CTRL,Frame 1-Plane Pix X Control" hexmask.long.word 0x00 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" hexmask.long.word 0x00 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x04 "FRAME_1P_PIX_X_CTRL_SET,Frame 1-Plane Pix X Control Set" hexmask.long.word 0x04 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" hexmask.long.word 0x04 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x08 "FRAME_1P_PIX_X_CTRL_CLR,Frame 1-Plane Pix X Control Clear" hexmask.long.word 0x08 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" hexmask.long.word 0x08 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x0C "FRAME_1P_PIX_X_CTRL_TOG,Frame 1-Plane Pix X Control Toggle" hexmask.long.word 0x0C 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" hexmask.long.word 0x0C 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x10 "FRAME_1P_PIX_Y_CTRL,Frame 1-Plane Pix Y Control" hexmask.long.word 0x10 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (1-Plane or 2-Plane Luma)" hexmask.long.word 0x10 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x14 "FRAME_1P_PIX_Y_CTRL_SET,Frame 1-Plane Pix Y Control Set" hexmask.long.word 0x14 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (1-Plane or 2-Plane Luma)" hexmask.long.word 0x14 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x18 "FRAME_1P_PIX_Y_CTRL_CLR,Frame 1-Plane Pix Y Control Clear" hexmask.long.word 0x18 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (1-Plane or 2-Plane Luma)" hexmask.long.word 0x18 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x1C "FRAME_1P_PIX_Y_CTRL_TOG,Frame 1-Plane Pix Y Control Toggle" hexmask.long.word 0x1C 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (1-Plane or 2-Plane Luma)" hexmask.long.word 0x1C 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x20 "FRAME_1P_BASE_ADDR_CTRL0,Frame 1-Plane Base Address Control 0" line.long 0x24 "FRAME_1P_BASE_ADDR_CTRL0_SET,Frame 1-Plane Base Address Control 0 Set" line.long 0x28 "FRAME_1P_BASE_ADDR_CTRL0_CLR,Frame 1-Plane Base Address Control 0 Clear" line.long 0x2C "FRAME_1P_BASE_ADDR_CTRL0_TOG,Frame 1-Plane Base Address Control 0 Toggle" if (((per.l(ad:0x00019000+0x70)&0x0C)==(0x04||0x0C)))||(((per.l(ad:0x00019000+0x50)&0x1C)==(0x0C||0x10)))||(((per.l(ad:0x00019000+0x50)&0x31C)==0x108)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." elif (((per.l(ad:0x00019000+0x50)&0x31C)==0x208)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." else group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" endif group.long 0xF0++0x2F line.long 0x00 "FRAME_2P_PIX_X_CTRL,Frame 2-Plane Pix X Control" hexmask.long.word 0x00 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X (2-Plane UV)" hexmask.long.word 0x00 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x04 "FRAME_2P_PIX_X_CTRL_SET,Frame 2-Plane Pix X Control Set" hexmask.long.word 0x04 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X (2-Plane UV)" hexmask.long.word 0x04 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x08 "FRAME_2P_PIX_X_CTRL_CLR,Frame 2-Plane Pix X Control Clear" hexmask.long.word 0x08 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X (2-Plane UV)" hexmask.long.word 0x08 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x0C "FRAME_2P_PIX_X_CTRL_TOG,Frame 2-Plane Pix X Control Toggle" hexmask.long.word 0x0C 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X (2-Plane UV)" hexmask.long.word 0x0C 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x10 "FRAME_2P_PIX_Y_CTRL,Frame 2-Plane Pix Y Control" hexmask.long.word 0x10 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (2-Plane UV)" hexmask.long.word 0x10 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x14 "FRAME_2P_PIX_Y_CTRL_SET,Frame 2-Plane Pix Y Control Set" hexmask.long.word 0x14 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (2-Plane UV)" hexmask.long.word 0x14 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x18 "FRAME_2P_PIX_Y_CTRL_CLR,Frame 2-Plane Pix Y Control Clear" hexmask.long.word 0x18 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (2-Plane UV)" hexmask.long.word 0x18 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x1C "FRAME_2P_PIX_Y_CTRL_TOG,Frame 2-Plane Pix Y Control Toggle" hexmask.long.word 0x1C 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (2-Plane UV)" hexmask.long.word 0x1C 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x20 "FRAME_2P_BASE_ADDR_CTRL0,Frame 2-Plane Base Address Control 0" line.long 0x24 "FRAME_2P_BASE_ADDR_CTRL0_SET,Frame 2-Plane Base Address Control 0 Set" line.long 0x28 "FRAME_2P_BASE_ADDR_CTRL0_CLR,Frame 2-Plane Base Address Control 0 Clear" line.long 0x2C "FRAME_2P_BASE_ADDR_CTRL0_TOG,Frame 2-Plane Base Address Control 0 Toggle" group.long 0x200++0x0F line.long 0x00 "RTRAM_CTRL0,RTRAM Control 0" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x00 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,All rows" line.long 0x04 "RTRAM_CTRL0_SET,RTRAM Control 0 Set" bitfld.long 0x04 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x04 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" line.long 0x08 "RTRAM_CTRL0_CLR,RTRAM Control 0 Clear" bitfld.long 0x08 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x08 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" line.long 0x0C "RTRAM_CTRL0_TOG,RTRAM Control 0 Toggle" bitfld.long 0x0C 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x0C 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,All rows" width 0x0B tree.end tree "DPR3" base ad:0x0001A000 width 30. group.long 0x00++0x03 line.long 0x00 "SYSTEM_CTRL0_SET/CLR,System Control 0 Set/Clear" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " BCMD2AXI_MSTR_ID_CTRL ,Buscmd to AXI master ID control" "Unique,Same" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Subystem hardware signal,SHADOW_LOAD_EN" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x04 2. 0x08 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SOFT_RESET ,Soft reset" "No reset,Reset" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_EN ,Run enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "SYSTEM_CTRL0_TOG,System Control 0 Toggle" bitfld.long 0x00 16. " BCMD2AXI_MSTR_ID_CTRL ,Buscmd to AXI master ID control" "Assigned unique AXI ID,Assigned same AXI ID" bitfld.long 0x00 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Subystem hardware signal,SHADOW_LOAD_EN" bitfld.long 0x00 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" bitfld.long 0x00 1. " SOFT_RESET ,Soft reset" "No reset,Reset" bitfld.long 0x00 0. " RUN_EN ,Run enable" "Disabled,Enabled" textline " " group.long 0x20++0x03 line.long 0x00 "IRQ_MASK_SET/CLR,Interrupt Mask Set/Clear" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer ready IRQ error mask" "Not masked,Masked" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer ready IRQ error mask" "Not masked,Masked" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow IRQ mask" "Not masked,Masked" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow IRQ mask" "Not masked,Masked" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "Not masked,Masked" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "Not masked,Masked" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "Not masked,Masked" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "Not masked,Masked" group.long 0x2C++0x07 line.long 0x00 "IRQ_MASK_TOG,Interrupt Mask Toggle" bitfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer ready IRQ error mask" "Not masked,Masked" bitfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer ready IRQ error mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow IRQ mask" "Not masked,Masked" bitfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow IRQ mask" "Not masked,Masked" textline " " bitfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "Not masked,Masked" bitfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "Not masked,Masked" textline " " bitfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "Not masked,Masked" bitfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "Not masked,Masked" line.long 0x04 "IRQ_MASK_STATUS_SET/CLR,Status Register of Masked IRQ Set/Clear" setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer error masked IRQ" "Not masked,Masked" setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer error masked IRQ" "Not masked,Masked" textline " " setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow masked IRQ" "Not masked,Masked" setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow masked IRQ" "Not masked,Masked" textline " " setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "Not masked,Masked" setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "Not masked,Masked" textline " " setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "Not masked,Masked" setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "Not masked,Masked" group.long 0x3C++0x07 line.long 0x00 "IRQ_MASK_STATUS_TOG,Status Register of Masked IRQ" bitfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer error masked IRQ" "Not masked,Masked" bitfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer error masked IRQ" "Not masked,Masked" textline " " bitfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow masked IRQ" "Not masked,Masked" bitfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow masked IRQ" "Not masked,Masked" textline " " bitfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "Not masked,Masked" bitfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "Not masked,Masked" textline " " bitfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "Not masked,Masked" bitfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "Not masked,Masked" line.long 0x04 "IRQ_NONMASK_STATUS_SET/CLR,Status of Non-Masked IRQ Set/Clear" setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow non-masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow non-masked IRQ" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" group.long 0x4C++0x13 line.long 0x00 "IRQ_NONMASK_STATUS_TOG,Status of Non-Masked IRQ Toggle" eventfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM Fifo load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM Fifo load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV Fifo overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB Fifo overflow non-masked IRQ" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" textline " " line.long 0x04 "MODE_CTRL0,Mode Control 0" bitfld.long 0x04 18.--19. " A_COMP_SEL ,Alpha component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x04 16.--17. " R_COMP_SEL ,Red component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x04 14.--15. " G_COMP_SEL ,Green component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x04 12.--13. " B_COMP_SEL ,Blue component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " setclrfld.long 0x04 11. 0x08 11. 0x0C 11. " PIX_UV_SWAP_SET/CLR ,Pixel UV swap" "Not swapped,Swapped" setclrfld.long 0x04 10. 0x08 10. 0x0C 10. " PIX_LUMA_UV_SWAP_SET/CLR ,Pixel luma/UV position swap" "YUYV,UYVY" textline " " bitfld.long 0x04 8.--9. " PIX_SIZE ,Pixel size" "8 bits,16 bits,32 bits,?..." setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " COMP_2PLANE_EN_SET/CLR ,Component 2-plane enable" "Disabled,Enabled" textline " " setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " YUV_EN_SET/CLR ,YUV enable" "Disabled,Enabled" bitfld.long 0x04 2.--4. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU 2PYUV420,VPU 2-Plane VP9,?..." textline " " setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " RTR_4LINE_BUF_EN_SET/CLR ,RTRAM lines per buffer" "8 RTRAM,4 RTRAM" setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " RTR_3BUF_EN_SET/CLR ,RTRAM buffer implementation" "2 RTRAM,3 RTRAM" line.long 0x08 "MODE_CTRL0_SET,Mode Control 0 Set" bitfld.long 0x08 18.--19. " A_COMP_SEL ,Alpha component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x08 16.--17. " R_COMP_SEL ,Red component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x08 14.--15. " G_COMP_SEL ,Green component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x08 12.--13. " B_COMP_SEL ,Blue component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x08 8.--9. " PIX_SIZE ,Pixel size" "8 bits,16 bits,32 bits,?..." bitfld.long 0x08 2.--4. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU 2PYUV420,VPU 2-Plane VP9,?..." line.long 0x0C "MODE_CTRL0_CLR,Mode Control 0 Clear" bitfld.long 0x0C 18.--19. " A_COMP_SEL ,Alpha component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x0C 16.--17. " R_COMP_SEL ,Red component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x0C 14.--15. " G_COMP_SEL ,Green component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x0C 12.--13. " B_COMP_SEL ,Blue component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x0C 8.--9. " PIX_SIZE ,Pixel size" "8 bits,16 bits,32 bits,?..." bitfld.long 0x0C 2.--4. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU 2PYUV420,VPU 2-Plane VP9,?..." line.long 0x10 "MODE_CTRL0_TOG,Mode Control 0 Toggle" bitfld.long 0x10 18.--19. " A_COMP_SEL ,Alpha component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x10 16.--17. " R_COMP_SEL ,Red component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x10 14.--15. " G_COMP_SEL ,Green component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.long 0x10 12.--13. " B_COMP_SEL ,Blue component byte select" "Byte 0,Byte 1,Byte 2,Byte 3" textline " " bitfld.long 0x10 11. " PIX_UV_SWAP ,Pixel UV swap" "Not swapped,Swapped" bitfld.long 0x10 10. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" textline " " bitfld.long 0x10 8.--9. " PIX_SIZE ,Pixel size" "8 bits,16 bits,32 bits,?..." bitfld.long 0x10 7. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" textline " " bitfld.long 0x10 6. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x10 2.--4. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU 2PYUV420,VPU 2-Plane VP9,?..." textline " " bitfld.long 0x10 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8 RTRAM,4 RTRAM" bitfld.long 0x10 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2 RTRAM,3 RTRAM" group.long 0x70++0x0F line.long 0x00 "FRAME_CTRL0,Frame Control 0" hexmask.long.word 0x00 16.--31. 1. " PITCH ,Image Pitch" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " ROT_FLIP_ORDER_EN ,Rotation flip order" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " ROT_ENC ,Encoded rotation" "0,90,180,270" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x04 "FRAME_CTRL0_SET,Frame Control 0 Set" hexmask.long.word 0x04 16.--31. 1. " PITCH ,Image Pitch" bitfld.long 0x04 2.--3. " ROT_ENC ,Encoded rotation" "0 degrees,90 degrees counter clock wise,180 degrees counter clock wise,270 degrees counter clock wise" line.long 0x08 "FRAME_CTRL0_CLR,Frame Control 0 Clear" hexmask.long.word 0x08 16.--31. 1. " PITCH ,Image Pitch" bitfld.long 0x08 2.--3. " ROT_ENC ,Encoded rotation" "0 degrees,90 degrees counter clock wise,180 degrees counter clock wise,270 degrees counter clock wise" line.long 0x0C "FRAME_CTRL0_TOG,Frame Control 0 Toggle" hexmask.long.word 0x0C 16.--31. 1. " PITCH ,Image Pitch" bitfld.long 0x0C 4. " ROT_FLIP_ORDER_EN ,Rotation flip order" "Rotate/flip,Flip/rotate" textline " " bitfld.long 0x0C 2.--3. " ROT_ENC ,Encoded rotation" "0 degrees,90 degrees counter clock wise,180 degrees counter clock wise,270 degrees counter clock wise" bitfld.long 0x0C 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" textline " " if (((per.l(ad:0x0001A000+0x70)&0x0C)==(0x04||0x0C)))||(((per.l(ad:0x0001A000+0x50)&0x1C)==(0x0C||0x10)))||(((per.l(ad:0x0001A000+0x50)&0x31C)==0x108)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." elif (((per.l(ad:0x0001A000+0x50)&0x31C)==0x208)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." else group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" endif group.long 0xA0++0x2F line.long 0x00 "FRAME_1P_PIX_X_CTRL,Frame 1-Plane Pix X Control" hexmask.long.word 0x00 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" hexmask.long.word 0x00 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x04 "FRAME_1P_PIX_X_CTRL_SET,Frame 1-Plane Pix X Control Set" hexmask.long.word 0x04 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" hexmask.long.word 0x04 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x08 "FRAME_1P_PIX_X_CTRL_CLR,Frame 1-Plane Pix X Control Clear" hexmask.long.word 0x08 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" hexmask.long.word 0x08 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x0C "FRAME_1P_PIX_X_CTRL_TOG,Frame 1-Plane Pix X Control Toggle" hexmask.long.word 0x0C 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" hexmask.long.word 0x0C 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x10 "FRAME_1P_PIX_Y_CTRL,Frame 1-Plane Pix Y Control" hexmask.long.word 0x10 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (1-Plane or 2-Plane Luma)" hexmask.long.word 0x10 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x14 "FRAME_1P_PIX_Y_CTRL_SET,Frame 1-Plane Pix Y Control Set" hexmask.long.word 0x14 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (1-Plane or 2-Plane Luma)" hexmask.long.word 0x14 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x18 "FRAME_1P_PIX_Y_CTRL_CLR,Frame 1-Plane Pix Y Control Clear" hexmask.long.word 0x18 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (1-Plane or 2-Plane Luma)" hexmask.long.word 0x18 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x1C "FRAME_1P_PIX_Y_CTRL_TOG,Frame 1-Plane Pix Y Control Toggle" hexmask.long.word 0x1C 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (1-Plane or 2-Plane Luma)" hexmask.long.word 0x1C 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x20 "FRAME_1P_BASE_ADDR_CTRL0,Frame 1-Plane Base Address Control 0" line.long 0x24 "FRAME_1P_BASE_ADDR_CTRL0_SET,Frame 1-Plane Base Address Control 0 Set" line.long 0x28 "FRAME_1P_BASE_ADDR_CTRL0_CLR,Frame 1-Plane Base Address Control 0 Clear" line.long 0x2C "FRAME_1P_BASE_ADDR_CTRL0_TOG,Frame 1-Plane Base Address Control 0 Toggle" if (((per.l(ad:0x0001A000+0x70)&0x0C)==(0x04||0x0C)))||(((per.l(ad:0x0001A000+0x50)&0x1C)==(0x0C||0x10)))||(((per.l(ad:0x0001A000+0x50)&0x31C)==0x108)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,?..." elif (((per.l(ad:0x0001A000+0x50)&0x31C)==0x208)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,?..." else group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control 0" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control 0 Set" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control 0 Clear" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control 0 Toggle" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64 bytes,128 bytes,256 bytes,512 bytes,1K bytes,2K bytes,4K bytes,8K bytes" endif group.long 0xF0++0x2F line.long 0x00 "FRAME_2P_PIX_X_CTRL,Frame 2-Plane Pix X Control" hexmask.long.word 0x00 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X (2-Plane UV)" hexmask.long.word 0x00 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x04 "FRAME_2P_PIX_X_CTRL_SET,Frame 2-Plane Pix X Control Set" hexmask.long.word 0x04 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X (2-Plane UV)" hexmask.long.word 0x04 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x08 "FRAME_2P_PIX_X_CTRL_CLR,Frame 2-Plane Pix X Control Clear" hexmask.long.word 0x08 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X (2-Plane UV)" hexmask.long.word 0x08 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x0C "FRAME_2P_PIX_X_CTRL_TOG,Frame 2-Plane Pix X Control Toggle" hexmask.long.word 0x0C 16.--31. 1. " CROP_ULC_X ,Starting coordinate of cropped image X (2-Plane UV)" hexmask.long.word 0x0C 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x10 "FRAME_2P_PIX_Y_CTRL,Frame 2-Plane Pix Y Control" hexmask.long.word 0x10 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (2-Plane UV)" hexmask.long.word 0x10 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x14 "FRAME_2P_PIX_Y_CTRL_SET,Frame 2-Plane Pix Y Control Set" hexmask.long.word 0x14 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (2-Plane UV)" hexmask.long.word 0x14 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x18 "FRAME_2P_PIX_Y_CTRL_CLR,Frame 2-Plane Pix Y Control Clear" hexmask.long.word 0x18 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (2-Plane UV)" hexmask.long.word 0x18 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x1C "FRAME_2P_PIX_Y_CTRL_TOG,Frame 2-Plane Pix Y Control Toggle" hexmask.long.word 0x1C 16.--31. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y (2-Plane UV)" hexmask.long.word 0x1C 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x20 "FRAME_2P_BASE_ADDR_CTRL0,Frame 2-Plane Base Address Control 0" line.long 0x24 "FRAME_2P_BASE_ADDR_CTRL0_SET,Frame 2-Plane Base Address Control 0 Set" line.long 0x28 "FRAME_2P_BASE_ADDR_CTRL0_CLR,Frame 2-Plane Base Address Control 0 Clear" line.long 0x2C "FRAME_2P_BASE_ADDR_CTRL0_TOG,Frame 2-Plane Base Address Control 0 Toggle" group.long 0x200++0x0F line.long 0x00 "RTRAM_CTRL0,RTRAM Control 0" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x00 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,All rows" line.long 0x04 "RTRAM_CTRL0_SET,RTRAM Control 0 Set" bitfld.long 0x04 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x04 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" line.long 0x08 "RTRAM_CTRL0_CLR,RTRAM Control 0 Clear" bitfld.long 0x08 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x08 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" line.long 0x0C "RTRAM_CTRL0_TOG,RTRAM Control 0 Toggle" bitfld.long 0x0C 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x0C 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,All rows" width 0x0B tree.end tree.end tree "MED_DC_SCALE (Scaler)" base ad:0x0001C000 width 22. group.long 0x00++0x27 line.long 0x00 "SCALE_CTRL,Scale Control Register" bitfld.long 0x00 12. " ENABLE_MEM2OFIFO ,Enable path from external memory to drive the data into the scale output FIFO" "Disabled,Enabled" bitfld.long 0x00 8. " ENABLE_SCALE2MEM ,Enable path from the scaler output back to the system memory" "Disabled,Enabled" bitfld.long 0x00 4. " ENABLE_REPEAT ,Enable scaler to restart processing a frame buffer without receiving a SW kick event using the ENABLE_SCALER control bit" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLE_SCALER ,Enable scaler to begin processing a frame buffer based on all current programmable settings" "Disabled,Enabled" line.long 0x04 "SCALE_OFIFO_CTRL,Scale Output FIFO Control Register" bitfld.long 0x04 31. " ENABLE_HIGH_THRESH_DETECT ,High threshold detection interrupt enable" "Disabled,Enabled" bitfld.long 0x04 30. " ENABLE_LOW_THRESH_DETECT ,Low threshold detection interrupt enable" "Disabled,Enabled" bitfld.long 0x04 29. " ENABLE_UNDERRUN_DETECT ,Underrun on the output FIFO interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CLEAR_HIGH_THRESH_DETECT ,Clear high threshold detect interrupt" "No action,Clear" bitfld.long 0x04 27. " CLEAR_LOW_THRESH_DETECT ,Clear low threshold interrupt detect" "No action,Clear" bitfld.long 0x04 26. " CLEAR_UNDERRUN_DETECT ,Clear underrun interrupt detect" "No action,Clear" textline " " hexmask.long.word 0x04 16.--25. 1. " OFIFO_HIGH_THRESH ,Output FIFO high threshold value" hexmask.long.word 0x04 0.--9. 1. " OFIFO_LOW_THRESH ,Output FIFO low threshold value" line.long 0x08 "SCALE_SRC_DATA_CTRL,Scale Source Data Control Register" bitfld.long 0x08 8.--11. " A2R10G10B10_FORMAT ,Data arrangement in 10 RGB mode" "ARGB,ARBG,AGRB,AGBR,ABRG,ABGR,RGBA,RBGA,GRBA,GBRA,BRGA,BGRA,?..." bitfld.long 0x08 4. " Y_UV_BYTE_SWAP ,Enable swapping of alternate bytes in the incoming data word" "Disabled,Enabled" bitfld.long 0x08 1. " RTRAM_LINES_PER_BANK ,Number of lines that are used in each bank of the RTRAM_CTRL module" "4 lines,8 lines" textline " " bitfld.long 0x08 0. " SRC_SELECT ,Source select" "ARGB||AYUV444,YUV" line.long 0x0C "SCALE_BIT_DEPTH,Scale Bit Depth Control Register" bitfld.long 0x0C 4.--5. " CHROMA_BIT_DEPTH ,Bit depth of the alternate component (UV 2-plane) processing" "8-bit,,10-bit,?..." bitfld.long 0x0C 0.--1. " LUMA_BIT_DEPTH ,Bit depth of the primary component (Y, RGB) processing" "8-bit,,10-bit,?..." line.long 0x10 "SCALE_SRC_FORMAT,Scale Source Format Control Register" bitfld.long 0x10 0.--1. " SRC_FORMAT ,Input buffer format" "YUV420,YUV422,ARGB8888/YUV444,?..." line.long 0x14 "SCALE_DST_FORMAT,Scale Destination Format Control Register" bitfld.long 0x14 0.--1. " DST_FORMAT ,Scaler output format" ",YUV420,RGB888/YUV444,?..." line.long 0x18 "SCALE_SRC_LUMA_RES,Scale Source Luma Resolution Register" hexmask.long.word 0x18 16.--27. 1. " HEIGHT ,Height of the source image in pixels minus 1" hexmask.long.word 0x18 0.--11. 1. " WIDTH ,Width of the source image in pixels minus 1" line.long 0x1C "SCALE_SRC_CHROMA_RES,Scale Source Chroma Resolution Register" hexmask.long.word 0x1C 16.--27. 1. " HEIGHT ,Height of the source image in pixels minus 1" hexmask.long.word 0x1C 0.--11. 1. " WIDTH ,Width of the source image in pixels minus 1" line.long 0x20 "SCALE_DST_LUMA_RES,Scale Destination Luma Resolution Register" hexmask.long.word 0x20 16.--27. 1. " HEIGHT ,Height of the destination image in pixels minus 1" hexmask.long.word 0x20 0.--11. 1. " WIDTH ,Width of the destination image in pixels minus 1" line.long 0x24 "SCALE_DST_CHROMA_RES,Scale Destination Chroma Resolution Register" hexmask.long.word 0x24 0.--11. 1. " WIDTH ,Width of the destination image in pixels minus 1" group.long 0x48++0x1F line.long 0x00 "SCALE_V_LUMA_START,Scale Vertical Luma Start Register" hexmask.long 0x00 0.--25. 1. " V_START ,13 integer and 13 fractional bits to define the vertical offset into the start of the prefetched image" line.long 0x04 "SCALE_V_LUMA_INC,Scale Vertical Luma Increment Register" hexmask.long.tbyte 0x04 0.--19. 1. " V_INC ,Vertical increment value used for scaling the image" line.long 0x08 "SCALE_H_LUMA_START,Scale Horizontal Luma Start Register" hexmask.long 0x08 0.--25. 1. " H_START ,13 integer and 13 fractional bits to define the horizontal offset into the start of the prefetched image" line.long 0x0C "SCALE_H_LUMA_INC,Scale Horizontal Luma Increment Register" hexmask.long.tbyte 0x0C 0.--19. 1. " H_INC ,Horizontal increment value used for scaling the image" line.long 0x10 "SCALE_V_CHROMA_START,Scale Vertical Chroma Start Register" hexmask.long 0x10 0.--25. 1. " V_START ,13 integer and 13 fractional bits to define the vertical offset into the start of the prefetched image" line.long 0x14 "SCALE_V_CHROMA_INC,Scale Vertical Chroma Increment Register" hexmask.long.tbyte 0x14 0.--19. 1. " V_INC ,Vertical increment value used for scaling the image" line.long 0x18 "SCALE_H_CHROMA_START,Scale Horizontal Chroma Start Register" hexmask.long 0x18 0.--25. 1. " H_START ,13 integer and 13 fractional bits to define the horizontal offset into the start of the prefetched image" line.long 0x1C "SCALE_H_CHROMA_INC,Scale Horizontal Chroma Increment Register" hexmask.long.tbyte 0x1C 0.--19. 1. " H_INC ,Horizontal increment value used for scaling the image" group.long 0x80++0x03 line.long 0x00 "SCALE_COEF_ARRAY,Scale Coefficient Memory Array" hexmask.long.word 0x00 0.--11. 1. " COEF ,Coefficient" width 0x0B tree.end tree "LUT_LD (Look Up Table Load)" base ad:0x00024000 width 21. group.long 0x00++0x03 line.long 0x00 "CTRL_STATUS_SET/CLR,Control/Status Register For LUT Loader" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " RD_ERR ,AXI read error" "No error,Error" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " RD_ERR_EN ,AXI read error IRQ enable" "Disabled,Enabled" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " BYTES_PER_REQ ,Bytes per request control" "0 - 256 bytes,1 - 128 bytes" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ENABLE ,Enable LUT_LD" "Disabled,Enabled" group.long 0x0C++0x07 line.long 0x00 "CTRL_STATUS_TOG,Control/Status Register For LUT Loader" eventfld.long 0x00 16. " RD_ERR ,AXI read error" "No error,Error" bitfld.long 0x00 8. " RD_ERR_EN ,AXI read error IRQ enable" "Disabled,Enabled" bitfld.long 0x00 1. " BYTES_PER_REQ ,Bytes per request control" "0 - 256 bytes,1 - 128 bytes" bitfld.long 0x00 0. " ENABLE ,Enable LUT_LD" "Disabled,Enabled" line.long 0x04 "BASE_ADDR,Address For Data Fetch" width 0x0B tree.end tree "MED_HDR10 (HDR10 Image Processing)" base ad:0x0000C000 width 28. group.long 0x0++0x03 line.long 0x00 "PIPE1_A0_LUT,A0 Component Look-Up-Table" hexmask.long.word 0x00 0.--13. 1. " PIPE1_A0_LUT ,LUT entries 14 bits wide" group.long 0x1000++0x03 line.long 0x00 "PIPE1_A1_LUT,A1 Component Look-Up-Table" hexmask.long.word 0x00 0.--13. 1. " PIPE1_A1_LUT ,LUT entries 14 bits wide" group.long 0x2000++0x03 line.long 0x00 "PIPE1_A2_LUT,A2 Component Look-Up-Table" hexmask.long.word 0x00 0.--13. 1. " PIPE1_A2_LUT ,LUT entries 14 bits wide" group.long 0x3000++0x73 line.long 0x00 "HDR_PIPE1_CSCA_CONTROL_REG,Pipe1 Colorspace Converter A Control" bitfld.long 0x00 15. " BYPASS ,Pixels CSC bypass" "No bypass,Bypass" bitfld.long 0x00 1. " ENABLE_FOR_ALL_PELS ,CSC enabled for all pixels" "Blended pixels,All pixels" textline " " bitfld.long 0x00 0. " ENABLE ,CSC enable" "Disabled,Enabled" line.long 0x04 "HDR_PIPE1_CSCA_H00,Pipe1 Colorspace Converter A (CSCA) h(0,0) Matrix Coefficient" hexmask.long.word 0x04 0.--15. 1. " H00 ,h(0.0) 16 bit signed coefficient" line.long 0x08 "HDR_PIPE1_CSCA_H10,Pipe1 Colorspace Converter A (CSCA) h(1,0) Matrix Coefficient" hexmask.long.word 0x08 0.--15. 1. " H10 ,h(1.0) 16 bit signed coefficient" line.long 0x0C "HDR_PIPE1_CSCA_H20,Pipe1 Colorspace Converter A (CSCA) h(2,0) Matrix Coefficient" hexmask.long.word 0x0C 0.--15. 1. " H20 ,h(2.0) 16 bit signed coefficient" line.long 0x10 "HDR_PIPE1_CSCA_H01,Pipe1 Colorspace Converter A (CSCA) h(0,1) Matrix Coefficient" hexmask.long.word 0x10 0.--15. 1. " H01 ,h(0.1) 16 bit signed coefficient" line.long 0x14 "HDR_PIPE1_CSCA_H11,Pipe1 Colorspace Converter A (CSCA) h(1,1) Matrix Coefficient" hexmask.long.word 0x14 0.--15. 1. " H11 ,h(1.1) 16 bit signed coefficient" line.long 0x18 "HDR_PIPE1_CSCA_H21,Pipe1 Colorspace Converter A (CSCA) h(2,1) Matrix Coefficient" hexmask.long.word 0x18 0.--15. 1. " H21 ,h(2.1) 16 bit signed coefficient" line.long 0x1C "HDR_PIPE1_CSCA_H02,Pipe1 Colorspace Converter A (CSCA) h(0,2) Matrix Coefficient" hexmask.long.word 0x1C 0.--15. 1. " H02 ,h(0.2) 16 bit signed coefficient" line.long 0x20 "HDR_PIPE1_CSCA_H12,Pipe1 Colorspace Converter A (CSCA) h(1,2) Matrix Coefficient" hexmask.long.word 0x20 0.--15. 1. " H12 ,h(1.2) 16 bit signed coefficient" line.long 0x24 "HDR_PIPE1_CSCA_H22,Pipe1 Colorspace Converter A (CSCA) h(2,2) Matrix Coefficient" hexmask.long.word 0x24 0.--15. 1. " H22 ,h(2.2) 16 bit signed coefficient" line.long 0x28 "HDR_PIPE1_CSCA_IO_0,Pipe1 Colorspace Converter A (CSCA) Component 0 Pre-Offset" hexmask.long.word 0x28 0.--9. 0x01 " COMPO_PRE_OFFSET ,Offset added to component 0 of the pixel before the color space conversion matrix multiply" line.long 0x2C "HDR_PIPE1_CSCA_IO_1,Pipe1 Colorspace Converter A (CSCA) Component 1 Pre-Offset" hexmask.long.word 0x2C 0.--9. 0x01 " COMP1_PRE_OFFSET ,Offset added to component 1 of the pixel before the color space conversion matrix multiply" line.long 0x30 "HDR_PIPE1_CSCA_IO_2,Pipe1 Colorspace Converter A (CSCA) Component 2 Pre-Offset" hexmask.long.word 0x30 0.--9. 0x01 " COMP2_PRE_OFFSET ,Offset added to component 2 of the pixel before the color space conversion matrix multiply" line.long 0x34 "HDR_PIPE1_CSCA_IO_MIN_0,Pipe1 Colorspace Converter A (CSCA) Component 0 Clip Min" hexmask.long.word 0x34 0.--9. 1. " COMP0_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x38 "HDR_PIPE1_CSCA_IO_MIN_1,Pipe1 Colorspace Converter A (CSCA) Component 1 Clip Min" hexmask.long.word 0x38 0.--9. 1. " COMP1_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x3C "HDR_PIPE1_CSCA_IO_MIN_2,Pipe1 Colorspace Converter A (CSCA) Component 2 Clip Min" hexmask.long.word 0x3C 0.--9. 1. " COMP2_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x40 "HDR_PIPE1_CSCA_IO_MAX_0,Pipe1 Colorspace Converter A (CSCA) Component 0 Clip Max Value" hexmask.long.word 0x40 0.--9. 1. " COMP0_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x44 "HDR_PIPE1_CSCA_IO_MAX_1,Pipe1 Colorspace Converter A (CSCA) Component 1 Clip Max Value" hexmask.long.word 0x44 0.--9. 1. " COMP1_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x48 "HDR_PIPE1_CSCA_IO_MAX_2,Pipe1 Colorspace Converter A (CSCA) Component 2 Clip Max Value" hexmask.long.word 0x48 0.--9. 1. " COMP2_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x4C "HDR_PIPE1_CSCA_NORM,Pipe1 Colorspace Converter A (CSCA) Normalization Factor" bitfld.long 0x4C 0.--4. " CSCA_NORM ,Size of arithmetic shift after matrix multiply" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "HDR_PIPE1_CSCA_OO_0,Pipe1 Colorspace Converter A (CSCA): Post Offset Component 0" hexmask.long 0x50 0.--27. 0x01 " CSCA_OO_0 ,Output offset" line.long 0x54 "HDR_PIPE1_CSCA_OO_1,Pipe1 Colorspace Converter A (CSCA): Post Offset Component 1" hexmask.long 0x54 0.--27. 0x01 " CSCA_OO_1 ,Output offset" line.long 0x58 "HDR_PIPE1_CSCA_OO_2,Pipe1 Colorspace Converter A (CSCA): Post Offset Component 2" hexmask.long 0x58 0.--27. 0x01 " CSCA_OO_2 ,Output offset" line.long 0x5C "HDR_PIPE1_CSCA_OMIN_0,Pipe1 Colorspace Converter A (CSCA): Post Offset Min Clip Value For Component 0" hexmask.long.word 0x5C 0.--9. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x60 "HDR_PIPE1_CSCA_OMIN_1,Pipe1 Colorspace Converter A (CSCA): Post Offset Min Clip Value For Component 1" hexmask.long.word 0x60 0.--9. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x64 "HDR_PIPE1_CSCA_OMIN_2,Pipe1 Colorspace Converter A (CSCA): Post Offset Min Clip Value For Component 2" hexmask.long.word 0x64 0.--9. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x68 "HDR_PIPE1_CSCA_OMAX_0,Pipe1 Colorspace Converter A (CSCA): Post Offset Max Clip Value For Component 0" hexmask.long.word 0x68 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x6C "HDR_PIPE1_CSCA_OMAX_1,Pipe1 Colorspace Converter A (CSCA): Post Offset Max Clip Value For Component 1" hexmask.long.word 0x6C 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x70 "HDR_PIPE1_CSCA_OMAX_2,Pipe1 Colorspace Converter A (CSCA): Post Offset Max Clip Value For Component 2" hexmask.long.word 0x70 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" group.long 0x3080++0x03 line.long 0x00 "HDR_PIPE1_LUT_CONTROL_REG,Pipe1 LUT Control Register" bitfld.long 0x00 15. " BYPASS ,LUT bypass" "No bypass,Bypass" bitfld.long 0x00 1. " ENABLE_FOR_ALL_PELS ,LUT enabled for all pixels" "Blended pixels,All pixels" textline " " bitfld.long 0x00 0. " ENABLE ,LUT enable" "Disabled,Enabled" group.long 0x3800++0x77 line.long 0x00 "HDR_PIPE1_CSCB_CONTROL_REG,Pipe1 Colorspace Converter B Control" bitfld.long 0x00 15. " BYPASS ,CSC bypass" "No bypass,Bypass" bitfld.long 0x00 1. " ENABLE_FOR_ALL_PELS ,CSC enabled for all pixels" "Blended pixels,All pixels" textline " " bitfld.long 0x00 0. " ENABLE ,CSC enable" "Disabled,Enabled" line.long 0x04 "HDR_PIPE1_CSCB_H00,Pipe1 Colorspace Converter B (CSCB) h(0,0) Matrix Coefficient" hexmask.long.word 0x04 0.--15. 1. " H00 ,h(0.0) 16 bit signed coefficient" line.long 0x08 "HDR_PIPE1_CSCB_H10,Pipe1 Colorspace Converter B (CSCB) h(1,0) Matrix Coefficient" hexmask.long.word 0x08 0.--15. 1. " H10 ,h(1.0) 16 bit signed coefficient" line.long 0x0C "HDR_PIPE1_CSCB_H20,Pipe1 Colorspace Converter B (CSCB) h(2,0) Matrix Coefficient" hexmask.long.word 0x0C 0.--15. 1. " H20 ,h(2.0) 16 bit signed coefficient" line.long 0x10 "HDR_PIPE1_CSCB_H01,Pipe1 Colorspace Converter B (CSCB) h(0,1) Matrix Coefficient" hexmask.long.word 0x10 0.--15. 1. " H01 ,h(0.1) 16 bit signed coefficient" line.long 0x14 "HDR_PIPE1_CSCB_H11,Pipe1 Colorspace Converter B (CSCB) h(1,1) Matrix Coefficient" hexmask.long.word 0x14 0.--15. 1. " H11 ,h(1.1) 16 bit signed coefficient" line.long 0x18 "HDR_PIPE1_CSCB_H21,Pipe1 Colorspace Converter B (CSCB) h(2,1) Matrix Coefficient" hexmask.long.word 0x18 0.--15. 1. " H21 ,h(2.1) 16 bit signed coefficient" line.long 0x1C "HDR_PIPE1_CSCB_H02,Pipe1 Colorspace Converter B (CSCB) h(0,2) Matrix Coefficient" hexmask.long.word 0x1C 0.--15. 1. " H02 ,h(0.2) 16 bit signed coefficient" line.long 0x20 "HDR_PIPE1_CSCB_H12,Pipe1 Colorspace Converter B (CSCB) h(1,2) Matrix Coefficient" hexmask.long.word 0x20 0.--15. 1. " H12 ,h(1.2) 16 bit signed coefficient" line.long 0x24 "HDR_PIPE1_CSCB_H22,Pipe1 Colorspace Converter B (CSCB) h(2,2) Matrix Coefficient" hexmask.long.word 0x24 0.--15. 1. " H22 ,h(2.2) 16 bit signed coefficient" line.long 0x28 "HDR_PIPE1_CSCB_IO_0,Pipe1 Colorspace Converter B (CSCB) Component 0 Pre-Offset" hexmask.long.word 0x28 0.--13. 0x01 " COMPO_PRE_OFFSET ,Offset added to component 0 of the pixel before the color space conversion matrix multiply" line.long 0x2C "HDR_PIPE1_CSCB_IO_1,Pipe1 Colorspace Converter B (CSCB) Component 1 Pre-Offset" hexmask.long.word 0x2C 0.--13. 0x01 " COMP1_PRE_OFFSET ,Offset added to component 1 of the pixel before the color space conversion matrix multiply" line.long 0x30 "HDR_PIPE1_CSCB_IO_2,Pipe1 Colorspace Converter B (CSCB) Component 2 Pre-Offset" hexmask.long.word 0x30 0.--13. 0x01 " COMP2_PRE_OFFSET ,Offset added to component 2 of the pixel before the color space conversion matrix multiply" line.long 0x34 "HDR_PIPE1_CSCB_IO_MIN_0,Pipe1 Colorspace Converter B (CSCB) Component 0 Clip Min" hexmask.long.word 0x34 0.--13. 1. " COMP0_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x38 "HDR_PIPE1_CSCB_IO_MIN_1,Pipe1 Colorspace Converter B (CSCB) Component 1 Clip Min" hexmask.long.word 0x38 0.--13. 1. " COMP1_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x3C "HDR_PIPE1_CSCB_IO_MIN_2,Pipe1 Colorspace Converter B (CSCB) Component 2 Clip Min" hexmask.long.word 0x3C 0.--13. 1. " COMP2_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x40 "HDR_PIPE1_CSCB_IO_MAX_0,Pipe1 Colorspace Converter B (CSCB) Component 0 Clip Max Value" hexmask.long.word 0x40 0.--13. 1. " COMP0_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x44 "HDR_PIPE1_CSCB_IO_MAX_1,Pipe1 Colorspace Converter B (CSCB) Component 1 Clip Max Value" hexmask.long.word 0x44 0.--13. 1. " COMP1_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x48 "HDR_PIPE1_CSCB_IO_MAX_2,Pipe1 Colorspace Converter B (CSCB) Component 2 Clip Max Value" hexmask.long.word 0x48 0.--13. 1. " COMP2_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x4C "HDR_PIPE1_CSCB_NORM,Pipe1 Colorspace Converter B (CSCB) Normalization Factor" bitfld.long 0x4C 0.--4. " CSCB_NORM ,Size of arithmetic shift after matrix multiply" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "HDR_PIPE1_CSCB_OO_0,Pipe1 Colorspace Converter B (CSCB): Post Offset Component 0" hexmask.long 0x50 0.--28. 0x01 " CSCB_OO_0 ,Output offset" line.long 0x54 "HDR_PIPE1_CSCB_OO_1,Pipe1 Colorspace Converter B (CSCB): Post Offset Component 1" hexmask.long 0x54 0.--28. 0x01 " CSCB_OO_1 ,Output offset" line.long 0x58 "HDR_PIPE1_CSCB_OO_2,Pipe1 Colorspace Converter B (CSCB): Post Offset Component 2" hexmask.long 0x58 0.--28. 0x01 " CSCB_OO_2 ,Output offset" line.long 0x5C "HDR_PIPE1_CSCB_OMIN_0,Pipe1 Colorspace Converter B (CSCB): Post Offset Min Clip Value For Component 0" hexmask.long 0x5C 0.--27. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x60 "HDR_PIPE1_CSCB_OMIN_1,Pipe1 Colorspace Converter B (CSCB): Post Offset Min Clip Value For Component 1" hexmask.long 0x60 0.--27. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x64 "HDR_PIPE1_CSCB_OMIN_2,Pipe1 Colorspace Converter B (CSCB): Post Offset Min Clip Value For Component 2" hexmask.long 0x64 0.--27. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x68 "HDR_PIPE1_CSCB_OMAX_0,Pipe1 Colorspace Converter B (CSCB): Post Offset Max Clip Value For Component 0" hexmask.long 0x68 0.--27. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x6C "HDR_PIPE1_CSCB_OMAX_1,Pipe1 Colorspace Converter B (CSCB): Post Offset Max Clip Value For Component 1" hexmask.long.word 0x6C 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x70 "HDR_PIPE1_CSCB_OMAX_2,Pipe1 Colorspace Converter B (CSCB): Post Offset Max Clip Value For Component 2" hexmask.long 0x70 0.--27. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x74 "HDR_PIPE1_FL2FX,Pipe1 Floating Point To Fixed Point Control" bitfld.long 0x74 1. " ENABLE_FOR_ALL_PELS ,Float to fixed operation enabled mode" "Blended pixels,All pixels" bitfld.long 0x74 0. " ENABLE ,Float to fixed converter enabled" "Disabled,Enabled" group.long 0x4000++0x03 line.long 0x00 "PIPE2_A0_LUT,A0 Component Look-Up-Table" hexmask.long.word 0x00 0.--13. 1. " PIPE2_A0_LUT ,LUT entries 14 bits wide" group.long 0x5000++0x03 line.long 0x00 "PIPE2_A1_LUT,A1 Component Look-Up-Table" hexmask.long.word 0x00 0.--13. 1. " PIPE2_A1_LUT ,LUT entries 14 bits wide" group.long 0x6000++0x03 line.long 0x00 "PIPE2_A2_LUT,A2 Component Look-Up-Table" hexmask.long.word 0x00 0.--13. 1. " PIPE2_A2_LUT ,LUT entries 14 bits wide" group.long 0x7000++0x73 line.long 0x00 "HDR_PIPE2_CSCA_CONTROL_REG,Pipe2 Colorspace Converter A Control" bitfld.long 0x00 15. " BYPASS ,CSC bypass" "No bypass,Bypass" bitfld.long 0x00 1. " ENABLE_FOR_ALL_PELS ,CSC enabled for all pixels" "Blended pixels,All pixels" textline " " bitfld.long 0x00 0. " ENABLE ,CSC enable" "Disabled,Enabled" line.long 0x04 "HDR_PIPE2_CSCA_H00,Pipe2 Colorspace Converter A (CSCA) h(0,0) Matrix Coefficient" hexmask.long.word 0x04 0.--15. 1. " H00 ,h(0.0) 16 bit signed coefficient" line.long 0x08 "HDR_PIPE2_CSCA_H10,Pipe2 Colorspace Converter A (CSCA) h(1,0) Matrix Coefficient" hexmask.long.word 0x08 0.--15. 1. " H10 ,h(1.0) 16 bit signed coefficient" line.long 0x0C "HDR_PIPE2_CSCA_H20,Pipe2 Colorspace Converter A (CSCA) h(2,0) Matrix Coefficient" hexmask.long.word 0x0C 0.--15. 1. " H20 ,h(2.0) 16 bit signed coefficient" line.long 0x10 "HDR_PIPE2_CSCA_H01,Pipe2 Colorspace Converter A (CSCA) h(0,1) Matrix Coefficient" hexmask.long.word 0x10 0.--15. 1. " H01 ,h(0.1) 16 bit signed coefficient" line.long 0x14 "HDR_PIPE2_CSCA_H11,Pipe2 Colorspace Converter A (CSCA) h(1,1) Matrix Coefficient" hexmask.long.word 0x14 0.--15. 1. " H11 ,h(1.1) 16 bit signed coefficient" line.long 0x18 "HDR_PIPE2_CSCA_H21,Pipe2 Colorspace Converter A (CSCA) h(2,1) Matrix Coefficient" hexmask.long.word 0x18 0.--15. 1. " H21 ,h(2.1) 16 bit signed coefficient" line.long 0x1C "HDR_PIPE2_CSCA_H02,Pipe2 Colorspace Converter A (CSCA) h(0,2) Matrix Coefficient" hexmask.long.word 0x1C 0.--15. 1. " H02 ,h(0.2) 16 bit signed coefficient" line.long 0x20 "HDR_PIPE2_CSCA_H12,Pipe2 Colorspace Converter A (CSCA) h(1,2) Matrix Coefficient" hexmask.long.word 0x20 0.--15. 1. " H12 ,h(1.2) 16 bit signed coefficient" line.long 0x24 "HDR_PIPE2_CSCA_H22,Pipe2 Colorspace Converter A (CSCA) h(2,2) Matrix Coefficient" hexmask.long.word 0x24 0.--15. 1. " H22 ,h(2.2) 16 bit signed coefficient" line.long 0x28 "HDR_PIPE2_CSCA_IO_0,Pipe2 Colorspace Converter A (CSCA) Component 0 Pre-Offset" hexmask.long.word 0x28 0.--9. 0x01 " COMPO_PRE_OFFSET ,Offset added to component 0 of the pixel before the color space conversion matrix multiply" line.long 0x2C "HDR_PIPE2_CSCA_IO_1,Pipe2 Colorspace Converter A (CSCA) Component 1 Pre-Offset" hexmask.long.word 0x2C 0.--9. 0x01 " COMP1_PRE_OFFSET ,Offset added to component 1 of the pixel before the color space conversion matrix multiply" line.long 0x30 "HDR_PIPE2_CSCA_IO_2,Pipe2 Colorspace Converter A (CSCA) Component 2 Pre-Offset" hexmask.long.word 0x30 0.--9. 0x01 " COMP2_PRE_OFFSET ,Offset added to component 2 of the pixel before the color space conversion matrix multiply" line.long 0x34 "HDR_PIPE2_CSCA_IO_MIN_0,Pipe2 Colorspace Converter A (CSCA) Component 0 Clip Min" hexmask.long.word 0x34 0.--9. 1. " COMP0_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x38 "HDR_PIPE2_CSCA_IO_MIN_1,Pipe2 Colorspace Converter A (CSCA) Component 1 Clip Min" hexmask.long.word 0x38 0.--9. 1. " COMP1_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x3C "HDR_PIPE2_CSCA_IO_MIN_2,Pipe2 Colorspace Converter A (CSCA) Component 2 Clip Min" hexmask.long.word 0x3C 0.--9. 1. " COMP2_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x40 "HDR_PIPE2_CSCA_IO_MAX_0,Pipe2 Colorspace Converter A (CSCA) Component 0 Clip Max Value" hexmask.long.word 0x40 0.--9. 1. " COMP0_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x44 "HDR_PIPE2_CSCA_IO_MAX_1,Pipe2 Colorspace Converter A (CSCA) Component 1 Clip Max Value" hexmask.long.word 0x44 0.--9. 1. " COMP1_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x48 "HDR_PIPE2_CSCA_IO_MAX_2,Pipe2 Colorspace Converter A (CSCA) Component 2 Clip Max Value" hexmask.long.word 0x48 0.--9. 1. " COMP2_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x4C "HDR_PIPE2_CSCA_NORM,Pipe2 Colorspace Converter A (CSCA) Normalization Factor" bitfld.long 0x4C 0.--4. " CSCA_NORM ,Size of arithmetic shift after matrix multiply" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "HDR_PIPE2_CSCA_OO_0,Pipe2 Colorspace Converter A (CSCA): Post Offset Component 0" hexmask.long 0x50 0.--27. 0x01 " CSCA_OO_0 ,Output offset" line.long 0x54 "HDR_PIPE2_CSCA_OO_1,Pipe2 Colorspace Converter A (CSCA): Post Offset Component 1" hexmask.long 0x54 0.--27. 0x01 " CSCA_OO_1 ,Output offset" line.long 0x58 "HDR_PIPE2_CSCA_OO_2,Pipe2 Colorspace Converter A (CSCA): Post Offset Component 2" hexmask.long 0x58 0.--27. 0x01 " CSCA_OO_2 ,Output offset" line.long 0x5C "HDR_PIPE2_CSCA_OMIN_0,Pipe2 Colorspace Converter A (CSCA): Post Offset Min Clip Value For Component 0" hexmask.long.word 0x5C 0.--9. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x60 "HDR_PIPE2_CSCA_OMIN_1,Pipe2 Colorspace Converter A (CSCA): Post Offset Min Clip Value For Component 1" hexmask.long.word 0x60 0.--9. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x64 "HDR_PIPE2_CSCA_OMIN_2,Pipe2 Colorspace Converter A (CSCA): Post Offset Min Clip Value For Component 2" hexmask.long.word 0x64 0.--9. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x68 "HDR_PIPE2_CSCA_OMAX_0,Pipe2 Colorspace Converter A (CSCA): Post Offset Max Clip Value For Component 0" hexmask.long.word 0x68 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x6C "HDR_PIPE2_CSCA_OMAX_1,Pipe2 Colorspace Converter A (CSCA): Post Offset Max Clip Value For Component 1" hexmask.long.word 0x6C 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x70 "HDR_PIPE2_CSCA_OMAX_2,Pipe2 Colorspace Converter A (CSCA): Post Offset Max Clip Value For Component 2" hexmask.long.word 0x70 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" group.long 0x7080++0x03 line.long 0x00 "HDR_PIPE2_LUT_CONTROL_REG,Pipe2 LUT Control Register" bitfld.long 0x00 15. " BYPASS ,LUT bypass" "No bypass,Bypass" bitfld.long 0x00 1. " ENABLE_FOR_ALL_PELS ,LUT enabled for all pixels" "Blended pixels,All pixels" textline " " bitfld.long 0x00 0. " ENABLE ,LUT enable" "Disabled,Enabled" group.long 0x7800++0x77 line.long 0x00 "HDR_PIPE2_CSCB_CONTROL_REG,Pipe2 Colorspace Converter B Control" bitfld.long 0x00 15. " BYPASS ,CSC bypass" "No bypass,Bypass" bitfld.long 0x00 1. " ENABLE_FOR_ALL_PELS ,CSC enabled for all pixels" "Blended pixels,All pixels" textline " " bitfld.long 0x00 0. " ENABLE ,CSC enable" "Disabled,Enabled" line.long 0x04 "HDR_PIPE2_CSCB_H00,Pipe2 Colorspace Converter B (CSCB) h(0,0) Matrix Coefficient" hexmask.long.word 0x04 0.--15. 1. " H00 ,h(0.0) 16 bit signed coefficient" line.long 0x08 "HDR_PIPE2_CSCB_H10,Pipe2 Colorspace Converter B (CSCB) h(1,0) Matrix Coefficient" hexmask.long.word 0x08 0.--15. 1. " H10 ,h(1.0) 16 bit signed coefficient" line.long 0x0C "HDR_PIPE2_CSCB_H20,Pipe2 Colorspace Converter B (CSCB) h(2,0) Matrix Coefficient" hexmask.long.word 0x0C 0.--15. 1. " H20 ,h(2.0) 16 bit signed coefficient" line.long 0x10 "HDR_PIPE2_CSCB_H01,Pipe2 Colorspace Converter B (CSCB) h(0,1) Matrix Coefficient" hexmask.long.word 0x10 0.--15. 1. " H01 ,h(0.1) 16 bit signed coefficient" line.long 0x14 "HDR_PIPE2_CSCB_H11,Pipe2 Colorspace Converter B (CSCB) h(1,1) Matrix Coefficient" hexmask.long.word 0x14 0.--15. 1. " H11 ,h(1.1) 16 bit signed coefficient" line.long 0x18 "HDR_PIPE2_CSCB_H21,Pipe2 Colorspace Converter B (CSCB) h(2,1) Matrix Coefficient" hexmask.long.word 0x18 0.--15. 1. " H21 ,h(2.1) 16 bit signed coefficient" line.long 0x1C "HDR_PIPE2_CSCB_H02,Pipe2 Colorspace Converter B (CSCB) h(0,2) Matrix Coefficient" hexmask.long.word 0x1C 0.--15. 1. " H02 ,h(0.2) 16 bit signed coefficient" line.long 0x20 "HDR_PIPE2_CSCB_H12,Pipe2 Colorspace Converter B (CSCB) h(1,2) Matrix Coefficient" hexmask.long.word 0x20 0.--15. 1. " H12 ,h(1.2) 16 bit signed coefficient" line.long 0x24 "HDR_PIPE2_CSCB_H22,Pipe2 Colorspace Converter B (CSCB) h(2,2) Matrix Coefficient" hexmask.long.word 0x24 0.--15. 1. " H22 ,h(2.2) 16 bit signed coefficient" line.long 0x28 "HDR_PIPE2_CSCB_IO_0,Pipe2 Colorspace Converter B (CSCB) Component 0 Pre-Offset" hexmask.long.word 0x28 0.--13. 0x01 " COMPO_PRE_OFFSET ,Offset added to component 0 of the pixel before the color space conversion matrix multiply" line.long 0x2C "HDR_PIPE2_CSCB_IO_1,Pipe2 Colorspace Converter B (CSCB) Component 1 Pre-Offset" hexmask.long.word 0x2C 0.--13. 0x01 " COMP1_PRE_OFFSET ,Offset added to component 1 of the pixel before the color space conversion matrix multiply" line.long 0x30 "HDR_PIPE2_CSCB_IO_2,Pipe2 Colorspace Converter B (CSCB) Component 2 Pre-Offset" hexmask.long.word 0x30 0.--13. 0x01 " COMP2_PRE_OFFSET ,Offset added to component 2 of the pixel before the color space conversion matrix multiply" line.long 0x34 "HDR_PIPE2_CSCB_IO_MIN_0,Pipe2 Colorspace Converter B (CSCB) Component 0 Clip Min" hexmask.long.word 0x34 0.--13. 1. " COMP0_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x38 "HDR_PIPE2_CSCB_IO_MIN_1,Pipe2 Colorspace Converter B (CSCB) Component 1 Clip Min" hexmask.long.word 0x38 0.--13. 1. " COMP1_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x3C "HDR_PIPE2_CSCB_IO_MIN_2,Pipe2 Colorspace Converter B (CSCB) Component 2 Clip Min" hexmask.long.word 0x3C 0.--13. 1. " COMP2_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x40 "HDR_PIPE2_CSCB_IO_MAX_0,Pipe2 Colorspace Converter B (CSCB) Component 0 Clip Max Value" hexmask.long.word 0x40 0.--13. 1. " COMP0_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x44 "HDR_PIPE2_CSCB_IO_MAX_1,Pipe2 Colorspace Converter B (CSCB) Component 1 Clip Max Value" hexmask.long.word 0x44 0.--13. 1. " COMP1_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x48 "HDR_PIPE2_CSCB_IO_MAX_2,Pipe2 Colorspace Converter B (CSCB) Component 2 Clip Max Value" hexmask.long.word 0x48 0.--13. 1. " COMP2_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x4C "HDR_PIPE2_CSCB_NORM,Pipe2 Colorspace Converter B (CSCB) Normalization Factor" bitfld.long 0x4C 0.--4. " CSCB_NORM ,Size of arithmetic shift after matrix multiply" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "HDR_PIPE2_CSCB_OO_0,Pipe2 Colorspace Converter B (CSCB): Post Offset Component 0" hexmask.long 0x50 0.--28. 0x01 " CSCB_OO_0 ,Output offset" line.long 0x54 "HDR_PIPE2_CSCB_OO_1,Pipe2 Colorspace Converter B (CSCB): Post Offset Component 1" hexmask.long 0x54 0.--28. 0x01 " CSCB_OO_1 ,Output offset" line.long 0x58 "HDR_PIPE2_CSCB_OO_2,Pipe2 Colorspace Converter B (CSCB): Post Offset Component 2" hexmask.long 0x58 0.--28. 0x01 " CSCB_OO_2 ,Output offset" line.long 0x5C "HDR_PIPE2_CSCB_OMIN_0,Pipe2 Colorspace Converter B (CSCB): Post Offset Min Clip Value For Component 0" hexmask.long 0x5C 0.--27. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x60 "HDR_PIPE2_CSCB_OMIN_1,Pipe2 Colorspace Converter B (CSCB): Post Offset Min Clip Value For Component 1" hexmask.long 0x60 0.--27. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x64 "HDR_PIPE2_CSCB_OMIN_2,Pipe2 Colorspace Converter B (CSCB): Post Offset Min Clip Value For Component 2" hexmask.long 0x64 0.--27. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x68 "HDR_PIPE2_CSCB_OMAX_0,Pipe2 Colorspace Converter B (CSCB): Post Offset Max Clip Value For Component 0" hexmask.long 0x68 0.--27. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x6C "HDR_PIPE2_CSCB_OMAX_1,Pipe2 Colorspace Converter B (CSCB): Post Offset Max Clip Value For Component 1" hexmask.long.word 0x6C 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x70 "HDR_PIPE2_CSCB_OMAX_2,Pipe2 Colorspace Converter B (CSCB): Post Offset Max Clip Value For Component 2" hexmask.long 0x70 0.--27. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x74 "HDR_PIPE2_FL2FX,Pipe2 Floating Point To Fixed Point Control" bitfld.long 0x74 1. " ENABLE_FOR_ALL_PELS ,Float to fixed operation enabled mode" "Blended pixels,All pixels" bitfld.long 0x74 0. " ENABLE ,Float to fixed converter enabled" "Disabled,Enabled" group.long 0x8000++0x03 line.long 0x00 "PIPE3_A0_LUT,A0 Component Look-Up-Table" hexmask.long.word 0x00 0.--13. 1. " PIPE3_A0_LUT ,LUT entries 14 bits wide" group.long 0x9000++0x03 line.long 0x00 "PIPE3_A1_LUT,A1 Component Look-Up-Table" hexmask.long.word 0x00 0.--13. 1. " PIPE3_A1_LUT ,LUT entries 14 bits wide" group.long 0xA000++0x03 line.long 0x00 "PIPE3_A2_LUT,A2 Component Look-Up-Table" hexmask.long.word 0x00 0.--13. 1. " PIPE3_A2_LUT ,LUT entries 14 bits wide" group.long 0xB000++0x73 line.long 0x00 "HDR_PIPE3_CSCA_CONTROL_REG,Pipe3 Colorspace Converter A Control" bitfld.long 0x00 15. " BYPASS ,CSC bypass" "No bypass,Bypass" bitfld.long 0x00 1. " ENABLE_FOR_ALL_PELS ,CSC enabled for all pixels" "Blended pixels,All pixels" textline " " bitfld.long 0x00 0. " ENABLE ,CSC enable" "Disabled,Enabled" line.long 0x04 "HDR_PIPE3_CSCA_H00,Pipe3 Colorspace Converter A (CSCA) h(0,0) Matrix Coefficient" hexmask.long.word 0x04 0.--15. 1. " H00 ,h(0.0) 16 bit signed coefficient" line.long 0x08 "HDR_PIPE3_CSCA_H10,Pipe3 Colorspace Converter A (CSCA) h(1,0) Matrix Coefficient" hexmask.long.word 0x08 0.--15. 1. " H10 ,h(1.0) 16 bit signed coefficient" line.long 0x0C "HDR_PIPE3_CSCA_H20,Pipe3 Colorspace Converter A (CSCA) h(2,0) Matrix Coefficient" hexmask.long.word 0x0C 0.--15. 1. " H20 ,h(2.0) 16 bit signed coefficient" line.long 0x10 "HDR_PIPE3_CSCA_H01,Pipe3 Colorspace Converter A (CSCA) h(0,1) Matrix Coefficient" hexmask.long.word 0x10 0.--15. 1. " H01 ,h(0.1) 16 bit signed coefficient" line.long 0x14 "HDR_PIPE3_CSCA_H11,Pipe3 Colorspace Converter A (CSCA) h(1,1) Matrix Coefficient" hexmask.long.word 0x14 0.--15. 1. " H11 ,h(1.1) 16 bit signed coefficient" line.long 0x18 "HDR_PIPE3_CSCA_H21,Pipe3 Colorspace Converter A (CSCA) h(2,1) Matrix Coefficient" hexmask.long.word 0x18 0.--15. 1. " H21 ,h(2.1) 16 bit signed coefficient" line.long 0x1C "HDR_PIPE3_CSCA_H02,Pipe3 Colorspace Converter A (CSCA) h(0,2) Matrix Coefficient" hexmask.long.word 0x1C 0.--15. 1. " H02 ,h(0.2) 16 bit signed coefficient" line.long 0x20 "HDR_PIPE3_CSCA_H12,Pipe3 Colorspace Converter A (CSCA) h(1,2) Matrix Coefficient" hexmask.long.word 0x20 0.--15. 1. " H12 ,h(1.2) 16 bit signed coefficient" line.long 0x24 "HDR_PIPE3_CSCA_H22,Pipe3 Colorspace Converter A (CSCA) h(2,2) Matrix Coefficient" hexmask.long.word 0x24 0.--15. 1. " H22 ,h(2.2) 16 bit signed coefficient" line.long 0x28 "HDR_PIPE3_CSCA_IO_0,Pipe3 Colorspace Converter A (CSCA) Component 0 Pre-Offset" hexmask.long.word 0x28 0.--9. 0x01 " COMPO_PRE_OFFSET ,Offset added to component 0 of the pixel before the color space conversion matrix multiply" line.long 0x2C "HDR_PIPE3_CSCA_IO_1,Pipe3 Colorspace Converter A (CSCA) Component 1 Pre-Offset" hexmask.long.word 0x2C 0.--9. 0x01 " COMP1_PRE_OFFSET ,Offset added to component 1 of the pixel before the color space conversion matrix multiply" line.long 0x30 "HDR_PIPE3_CSCA_IO_2,Pipe3 Colorspace Converter A (CSCA) Component 2 Pre-Offset" hexmask.long.word 0x30 0.--9. 0x01 " COMP2_PRE_OFFSET ,Offset added to component 2 of the pixel before the color space conversion matrix multiply" line.long 0x34 "HDR_PIPE3_CSCA_IO_MIN_0,Pipe3 Colorspace Converter A (CSCA) Component 0 Clip Min" hexmask.long.word 0x34 0.--9. 1. " COMP0_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x38 "HDR_PIPE3_CSCA_IO_MIN_1,Pipe3 Colorspace Converter A (CSCA) Component 1 Clip Min" hexmask.long.word 0x38 0.--9. 1. " COMP1_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x3C "HDR_PIPE3_CSCA_IO_MIN_2,Pipe3 Colorspace Converter A (CSCA) Component 2 Clip Min" hexmask.long.word 0x3C 0.--9. 1. " COMP2_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x40 "HDR_PIPE3_CSCA_IO_MAX_0,Pipe3 Colorspace Converter A (CSCA) Component 0 Clip Max Value" hexmask.long.word 0x40 0.--9. 1. " COMP0_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x44 "HDR_PIPE3_CSCA_IO_MAX_1,Pipe3 Colorspace Converter A (CSCA) Component 1 Clip Max Value" hexmask.long.word 0x44 0.--9. 1. " COMP1_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x48 "HDR_PIPE3_CSCA_IO_MAX_2,Pipe3 Colorspace Converter A (CSCA) Component 2 Clip Max Value" hexmask.long.word 0x48 0.--9. 1. " COMP2_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x4C "HDR_PIPE3_CSCA_NORM,Pipe3 Colorspace Converter A (CSCA) Normalization Factor" bitfld.long 0x4C 0.--4. " CSCA_NORM ,Size of arithmetic shift after matrix multiply" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "HDR_PIPE3_CSCA_OO_0,Pipe3 Colorspace Converter A (CSCA): Post Offset Component 0" hexmask.long 0x50 0.--27. 0x01 " CSCA_OO_0 ,Output offset" line.long 0x54 "HDR_PIPE3_CSCA_OO_1,Pipe3 Colorspace Converter A (CSCA): Post Offset Component 1" hexmask.long 0x54 0.--27. 0x01 " CSCA_OO_1 ,Output offset" line.long 0x58 "HDR_PIPE3_CSCA_OO_2,Pipe3 Colorspace Converter A (CSCA): Post Offset Component 2" hexmask.long 0x58 0.--27. 0x01 " CSCA_OO_2 ,Output offset" line.long 0x5C "HDR_PIPE3_CSCA_OMIN_0,Pipe3 Colorspace Converter A (CSCA): Post Offset Min Clip Value For Component 0" hexmask.long.word 0x5C 0.--9. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x60 "HDR_PIPE3_CSCA_OMIN_1,Pipe3 Colorspace Converter A (CSCA): Post Offset Min Clip Value For Component 1" hexmask.long.word 0x60 0.--9. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x64 "HDR_PIPE3_CSCA_OMIN_2,Pipe3 Colorspace Converter A (CSCA): Post Offset Min Clip Value For Component 2" hexmask.long.word 0x64 0.--9. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x68 "HDR_PIPE3_CSCA_OMAX_0,Pipe3 Colorspace Converter A (CSCA): Post Offset Max Clip Value For Component 0" hexmask.long.word 0x68 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x6C "HDR_PIPE3_CSCA_OMAX_1,Pipe3 Colorspace Converter A (CSCA): Post Offset Max Clip Value For Component 1" hexmask.long.word 0x6C 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x70 "HDR_PIPE3_CSCA_OMAX_2,Pipe3 Colorspace Converter A (CSCA): Post Offset Max Clip Value For Component 2" hexmask.long.word 0x70 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" group.long 0xB080++0x03 line.long 0x00 "HDR_PIPE3_LUT_CONTROL_REG,Pipe3 LUT Control Register" bitfld.long 0x00 15. " BYPASS ,LUT bypass" "No bypass,Bypass" bitfld.long 0x00 1. " ENABLE_FOR_ALL_PELS ,LUT enabled for all pixels" "Blended pixels,All pixels" textline " " bitfld.long 0x00 0. " ENABLE ,LUT enable" "Disabled,Enabled" group.long 0xB800++0x77 line.long 0x00 "HDR_PIPE3_CSCB_CONTROL_REG,Pipe3 Colorspace Converter B Control" bitfld.long 0x00 15. " BYPASS ,CSC bypass" "No bypass,Bypass" bitfld.long 0x00 1. " ENABLE_FOR_ALL_PELS ,CSC enabled for all pixels" "Blended pixels,All pixels" textline " " bitfld.long 0x00 0. " ENABLE ,CSC enable" "Disabled,Enabled" line.long 0x04 "HDR_PIPE3_CSCB_H00,Pipe3 Colorspace Converter B (CSCB) h(0,0) Matrix Coefficient" hexmask.long.word 0x04 0.--15. 1. " H00 ,h(0.0) 16 bit signed coefficient" line.long 0x08 "HDR_PIPE3_CSCB_H10,Pipe3 Colorspace Converter B (CSCB) h(1,0) Matrix Coefficient" hexmask.long.word 0x08 0.--15. 1. " H10 ,h(1.0) 16 bit signed coefficient" line.long 0x0C "HDR_PIPE3_CSCB_H20,Pipe3 Colorspace Converter B (CSCB) h(2,0) Matrix Coefficient" hexmask.long.word 0x0C 0.--15. 1. " H20 ,h(2.0) 16 bit signed coefficient" line.long 0x10 "HDR_PIPE3_CSCB_H01,Pipe3 Colorspace Converter B (CSCB) h(0,1) Matrix Coefficient" hexmask.long.word 0x10 0.--15. 1. " H01 ,h(0.1) 16 bit signed coefficient" line.long 0x14 "HDR_PIPE3_CSCB_H11,Pipe3 Colorspace Converter B (CSCB) h(1,1) Matrix Coefficient" hexmask.long.word 0x14 0.--15. 1. " H11 ,h(1.1) 16 bit signed coefficient" line.long 0x18 "HDR_PIPE3_CSCB_H21,Pipe3 Colorspace Converter B (CSCB) h(2,1) Matrix Coefficient" hexmask.long.word 0x18 0.--15. 1. " H21 ,h(2.1) 16 bit signed coefficient" line.long 0x1C "HDR_PIPE3_CSCB_H02,Pipe3 Colorspace Converter B (CSCB) h(0,2) Matrix Coefficient" hexmask.long.word 0x1C 0.--15. 1. " H02 ,h(0.2) 16 bit signed coefficient" line.long 0x20 "HDR_PIPE3_CSCB_H12,Pipe3 Colorspace Converter B (CSCB) h(1,2) Matrix Coefficient" hexmask.long.word 0x20 0.--15. 1. " H12 ,h(1.2) 16 bit signed coefficient" line.long 0x24 "HDR_PIPE3_CSCB_H22,Pipe3 Colorspace Converter B (CSCB) h(2,2) Matrix Coefficient" hexmask.long.word 0x24 0.--15. 1. " H22 ,h(2.2) 16 bit signed coefficient" line.long 0x28 "HDR_PIPE3_CSCB_IO_0,Pipe3 Colorspace Converter B (CSCB) Component 0 Pre-Offset" hexmask.long.word 0x28 0.--13. 0x01 " COMPO_PRE_OFFSET ,Offset added to component 0 of the pixel before the color space conversion matrix multiply" line.long 0x2C "HDR_PIPE3_CSCB_IO_1,Pipe3 Colorspace Converter B (CSCB) Component 1 Pre-Offset" hexmask.long.word 0x2C 0.--13. 0x01 " COMP1_PRE_OFFSET ,Offset added to component 1 of the pixel before the color space conversion matrix multiply" line.long 0x30 "HDR_PIPE3_CSCB_IO_2,Pipe3 Colorspace Converter B (CSCB) Component 2 Pre-Offset" hexmask.long.word 0x30 0.--13. 0x01 " COMP2_PRE_OFFSET ,Offset added to component 2 of the pixel before the color space conversion matrix multiply" line.long 0x34 "HDR_PIPE3_CSCB_IO_MIN_0,Pipe3 Colorspace Converter B (CSCB) Component 0 Clip Min" hexmask.long.word 0x34 0.--13. 1. " COMP0_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x38 "HDR_PIPE3_CSCB_IO_MIN_1,Pipe3 Colorspace Converter B (CSCB) Component 1 Clip Min" hexmask.long.word 0x38 0.--13. 1. " COMP1_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x3C "HDR_PIPE3_CSCB_IO_MIN_2,Pipe3 Colorspace Converter B (CSCB) Component 2 Clip Min" hexmask.long.word 0x3C 0.--13. 1. " COMP2_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x40 "HDR_PIPE3_CSCB_IO_MAX_0,Pipe3 Colorspace Converter B (CSCB) Component 0 Clip Max Value" hexmask.long.word 0x40 0.--13. 1. " COMP0_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x44 "HDR_PIPE3_CSCB_IO_MAX_1,Pipe3 Colorspace Converter B (CSCB) Component 1 Clip Max Value" hexmask.long.word 0x44 0.--13. 1. " COMP1_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x48 "HDR_PIPE3_CSCB_IO_MAX_2,Pipe3 Colorspace Converter B (CSCB) Component 2 Clip Max Value" hexmask.long.word 0x48 0.--13. 1. " COMP2_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x4C "HDR_PIPE3_CSCB_NORM,Pipe3 Colorspace Converter B (CSCB) Normalization Factor" bitfld.long 0x4C 0.--4. " CSCB_NORM ,Size of arithmetic shift after matrix multiply" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "HDR_PIPE3_CSCB_OO_0,Pipe3 Colorspace Converter B (CSCB): Post Offset Component 0" hexmask.long 0x50 0.--28. 0x01 " CSCB_OO_0 ,Output offset" line.long 0x54 "HDR_PIPE3_CSCB_OO_1,Pipe3 Colorspace Converter B (CSCB): Post Offset Component 1" hexmask.long 0x54 0.--28. 0x01 " CSCB_OO_1 ,Output offset" line.long 0x58 "HDR_PIPE3_CSCB_OO_2,Pipe3 Colorspace Converter B (CSCB): Post Offset Component 2" hexmask.long 0x58 0.--28. 0x01 " CSCB_OO_2 ,Output offset" line.long 0x5C "HDR_PIPE3_CSCB_OMIN_0,Pipe3 Colorspace Converter B (CSCB): Post Offset Min Clip Value For Component 0" hexmask.long 0x5C 0.--27. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x60 "HDR_PIPE3_CSCB_OMIN_1,Pipe3 Colorspace Converter B (CSCB): Post Offset Min Clip Value For Component 1" hexmask.long 0x60 0.--27. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x64 "HDR_PIPE3_CSCB_OMIN_2,Pipe3 Colorspace Converter B (CSCB): Post Offset Min Clip Value For Component 2" hexmask.long 0x64 0.--27. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x68 "HDR_PIPE3_CSCB_OMAX_0,Pipe3 Colorspace Converter B (CSCB): Post Offset Max Clip Value For Component 0" hexmask.long 0x68 0.--27. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x6C "HDR_PIPE3_CSCB_OMAX_1,Pipe3 Colorspace Converter B (CSCB): Post Offset Max Clip Value For Component 1" hexmask.long.word 0x6C 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x70 "HDR_PIPE3_CSCB_OMAX_2,Pipe3 Colorspace Converter B (CSCB): Post Offset Max Clip Value For Component 2" hexmask.long 0x70 0.--27. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x74 "HDR_PIPE3_FL2FX,Pipe3 Floating Point To Fixed Point Control" bitfld.long 0x74 1. " ENABLE_FOR_ALL_PELS ,Float to fixed operation enabled mode" "Blended pixels,All pixels" bitfld.long 0x74 0. " ENABLE ,Float to fixed converter enabled" "Disabled,Enabled" group.long 0xC000++0x03 line.long 0x00 "OPIPE_A0_TABLE,A0 Component Linear-To-Non-Linear Conversion Table" hexmask.long.word 0x00 0.--13. 1. " OPIPE_A0_TABLE ,TABLE nodes 14 bits wide" group.long 0xD000++0x03 line.long 0x00 "OPIPE_A1_TABLE,A1 Component Linear-To-Non-Linear Conversion Table" hexmask.long.word 0x00 0.--13. 1. " OPIPE_A1_TABLE ,TABLE nodes 14 bits wide" group.long 0xE000++0x03 line.long 0x00 "OPIPE_A2_TABLE,A2 Component Linear-To-Non-Linear Conversion Table" hexmask.long.word 0x00 0.--13. 1. " OPIPE_A2_TABLE ,TABLE nodes 14 bits wide" group.long 0xF000++0x77 line.long 0x00 "HDR_OPIPE_CSC_CONTROL_REG,HDR Output Stage Colorspace Converter (CSCO) Control" bitfld.long 0x00 15. " BYPASS ,CSC bypass" "No bypass,Bypass" bitfld.long 0x00 1. " ENABLE_FOR_ALL_PELS ,CSC enabled for all pixels" "Blended pixels,All pixels" textline " " bitfld.long 0x00 0. " ENABLE ,CSC enable" "Disabled,Enabled" line.long 0x04 "HDR_OPIPE_CSC_H00,OPipe Colorspace Converter (CSC) h(0,0) Matrix Coefficient" hexmask.long.word 0x04 0.--15. 1. " H00 ,h(0.0) 16 bit signed coefficient" line.long 0x08 "HDR_OPIPE_CSC_H10,OPipe Colorspace Converter (CSC) h(1,0) Matrix Coefficient" hexmask.long.word 0x08 0.--15. 1. " H10 ,h(1.0) 16 bit signed coefficient" line.long 0x0C "HDR_OPIPE_CSC_H20,HDR OUTPUT Colorspace Converter (CSCO) h(2,0) Matrix Coefficient" hexmask.long.word 0x0C 0.--15. 1. " H20 ,h(2.0) 16 bit signed coefficient" line.long 0x10 "HDR_OPIPE_CSC_H01,HDR OUTPUT Pipe Colorspace Converter (CSCO) h(0,1) Matrix Coefficient" hexmask.long.word 0x10 0.--15. 1. " H01 ,h(0.1) 16 bit signed coefficient" line.long 0x14 "HDR_OPIPE_CSC_H11,HDR OUTPUT Pipe Colorspace Converter (CSCO) h(1,1) Matrix Coefficient" hexmask.long.word 0x14 0.--15. 1. " H11 ,h(1.1) 16 bit signed coefficient" line.long 0x18 "HDR_OPIPE_CSC_H21,HDR_output Pipe Colorspace Converter (CSCO) h(2,1) Matrix Coefficient" hexmask.long.word 0x18 0.--15. 1. " H21 ,h(2.1) 16 bit signed coefficient" line.long 0x1C "HDR_OPIPE_CSC_H02,HDR OUTPUT Pipe Colorspace Converter (CSCO) h(0,2) Matrix Coefficient" hexmask.long.word 0x1C 0.--15. 1. " H02 ,h(0.2) 16 bit signed coefficient" line.long 0x20 "HDR_OPIPE_CSC_H12,HDR OUPUT Pipe Colorspace Converter (CSCO) h(1,2) Matrix Coefficient" hexmask.long.word 0x20 0.--15. 1. " H12 ,h(1.2) 16 bit signed coefficient" line.long 0x24 "HDR_OPIPE_CSC_H22,HDR OUPUT Pipe Colorspace Converter (CSCO) h(2,2) Matrix Coefficient" hexmask.long.word 0x24 0.--15. 1. " H22 ,h(2.2) 16 bit signed coefficient" line.long 0x28 "HDR_OPIPE_CSC_IO_0,HDR OUTPUT Pipe Colorspace Converter (CSCO) Component 0 Pre-Offset" hexmask.long.word 0x28 0.--9. 0x01 " COMPO_PRE_OFFSET ,Offset added to component 0 of the pixel before the color space conversion matrix multiply" line.long 0x2C "HDR_OPIPE_CSC_IO_1,HDR OUPTUT Pipe Colorspace Converter (CSCO) Component 1 Pre-Offset" hexmask.long.word 0x2C 0.--9. 0x01 " COMP1_PRE_OFFSET ,Offset added to component 1 of the pixel before the color space conversion matrix multiply" line.long 0x30 "HDR_OPIPE_CSC_IO_2,HDR OUPUT Pipe: Colorspace Converter (CSCO) Component 2 Pre-Offset" hexmask.long.word 0x30 0.--9. 0x01 " COMP2_PRE_OFFSET ,Offset added to component 2 of the pixel before the color space conversion matrix multiply" line.long 0x34 "HDR_OPIPE_CSC_IO_MIN_0,HDR OUPTU Pipe Colorspace Converter (CSCO) Component 0 Clip Min" hexmask.long.word 0x34 0.--9. 1. " COMP0_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x38 "HDR_OPIPE_CSC_IO_MIN_1,HDR OUPUT Pipe Colorspace Converter (CSCO) Component 1 Clip Min" hexmask.long.word 0x38 0.--9. 1. " COMP1_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x3C "HDR_OPIPE_CSC_IO_MIN_2,HDR OUPTU Pipe Colorspace Converter (CSCO) Component 2 Clip Min" hexmask.long.word 0x3C 0.--9. 1. " COMP2_CLIP_MIN ,Minimum value of pixel component after the pre-increment" line.long 0x40 "HDR_OPIPE_CSC_IO_MAX_0,HDR OUPTUT Pipe Colorspace Converter O (CSC) Component 0 Clip Max Value" hexmask.long.word 0x40 0.--9. 1. " COMP0_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x44 "HDR_OPIPE_CSC_IO_MAX_1,HDR OUTPUT Pipe Colorspace Converter (CSCO) Component 1 Clip Max Value" hexmask.long.word 0x44 0.--9. 1. " COMP1_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x48 "HDR_OPIPE_CSC_IO_MAX_2,HDR OUTPUT Pipe Colorspace Converter (CSCO) Component 2 Clip Max Value" hexmask.long.word 0x48 0.--9. 1. " COMP2_CLIP_MAX ,Maximum value of pixel component after the pre-increment" line.long 0x4C "HDR_OPIPE_CSC_NORM,HDR OUPUT Pipe Colorspace Converter (CSCO) Normalization Factor" bitfld.long 0x4C 0.--4. " CSCA_NORM ,Size of arithmetic shift after matrix multiply" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "HDR_OPIPE_CSC_OO_0,HDR OUPTUT Pipe Colorspace Converter (CSC): Post Offset Component 0" hexmask.long 0x50 0.--27. 0x01 " CSCA_OO_0 ,Output offset" line.long 0x54 "HDR_OPIPE_CSC_OO_1,HDR OUTPUT Pipe Colorspace Converter (CSC): Post Offset Component 1" hexmask.long 0x54 0.--27. 0x01 " CSCA_OO_1 ,Output offset" line.long 0x58 "HDR_OPIPE_CSC_OO_2,HDR OUPTUT Pipe Colorspace Converter (CSC): Post Offset Component 2" hexmask.long 0x58 0.--27. 0x01 " CSCA_OO_2 ,Output offset" line.long 0x5C "HDR_OPIPE_CSC_OMIN_0,HDR OUTPUT Pipe Colorspace Converter (CSC): Post Offset Min Clip Value For Component 0" hexmask.long.word 0x5C 0.--9. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x60 "HDR_OPIPE_CSC_OMIN_1,HDR OUTPUT Pipe Colorspace Converter (CSC): Post Offset Min Clip Value For Component 1" hexmask.long.word 0x60 0.--9. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x64 "HDR_OPIPE_CSC_OMIN_2,HDR OUTPUT Pipe Colorspace Converter (CSC): Post Offset Min Clip Value For Component 2" hexmask.long.word 0x64 0.--9. 0x01 " POST_OFF_MIN ,Minimum clipped pixel component" line.long 0x68 "HDR_OPIPE_CSC_OMAX_0,HDR OUPTUT Pipe Colorspace Converter (CSC): Post Offset Max Clip Value For Component 0" hexmask.long.word 0x68 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x6C "HDR_OPIPE_CSC_OMAX_1,HDR OUTPUT Pipe Colorspace Converter (CSC): Post Offset Max Clip Value For Component 1" hexmask.long.word 0x6C 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x70 "HDR_OPIPE_CSC_OMAX_2,HDR OUTPUT Pipe Colorspace Converter (CSC): Post Offset Max Clip Value For Component 2" hexmask.long.word 0x70 0.--9. 0x01 " POST_OFF_MAX ,Maximum clipped pixel component" line.long 0x74 "HDR_OPIPE_2NL_CONTROL_REG,HDR OUTPUT-TO NON LINEAR Pipeline Control" bitfld.long 0x74 3. " FIX2FLT_ENABLE_FOR_ALL_PELS ,Fixed to float mode" "Blended pels,All pells" bitfld.long 0x74 2. " LTNL_ENABLE_FOR_ALL_PELS ,Linear to non linear conversion mode" "Blended pels,All pells" textline " " bitfld.long 0x74 1. " DISABLE_FIXED_TO_FLOAT ,Fixed to float disable" "No,Yes" bitfld.long 0x74 0. " PASS_THRU ,Pass through data mode" "Linear to non linear pipeline,Pass through unmodified" width 0x0B tree.end tree "SUBSAM (Color Sub-Sampler)" base ad:0x0001B000 width 23. group.long 0x00++0x03 line.long 0x00 "SS_SYS_CTRL_SET/CLR,SS SYS CTRL Set/Clear" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_EN ,Subsam module ready to be enabled" "Not ready,Ready" group.long 0x0C++0x03 line.long 0x00 "SS_SYS_CTRL_TOG,SS SYS CTRL Toggle" bitfld.long 0x00 0. " RUN_EN ,Subsam module ready to be enabled" "Not ready,Ready" group.long 0x10++0x93 line.long 0x00 "SS_DISPLAY,SS DISPLAY" hexmask.long.word 0x00 16.--28. 1. " LRC_Y ,Lower right corner y coordinate" hexmask.long.word 0x00 0.--12. 1. " LRC_X ,Lower right corner x coordinate" line.long 0x04 "SS_DISPLAY_SET,SS DISPLAY Set" hexmask.long.word 0x04 16.--28. 1. " LRC_Y ,Lower right corner y coordinate" hexmask.long.word 0x04 0.--12. 1. " LRC_X ,Lower right corner x coordinate" line.long 0x08 "SS_DISPLAY_CLR,SS DISPLAY Clear" hexmask.long.word 0x08 16.--28. 1. " LRC_Y ,Lower right corner y coordinate" hexmask.long.word 0x08 0.--12. 1. " LRC_X ,Lower right corner x coordinate" line.long 0x0C "SS_DISPLAY_TOG,SS DISPLAY Toggle" hexmask.long.word 0x0C 16.--28. 1. " LRC_Y ,Lower right corner y coordinate" hexmask.long.word 0x0C 0.--12. 1. " LRC_X ,Lower right corner x coordinate" line.long 0x10 "SS_HSYNC,SS HSYNC" setclrfld.long 0x10 31. 0x14 31. 0x18 31. " POL_SET/CLR ,Polarity of sync signal" "Low,High" hexmask.long.word 0x10 16.--28. 1. " END ,Horizontal sync is de-asserted when horizontal count == END" hexmask.long.word 0x10 0.--12. 1. " START ,Horizontal sync is asserted when horizontal count == START" line.long 0x14 "SS_HSYNC_SET,SS HSYNC Set" hexmask.long.word 0x14 16.--28. 1. " END ,Horizontal sync is de-asserted when horizontal count == END" hexmask.long.word 0x14 0.--12. 1. " START ,Horizontal sync is asserted when horizontal count == START" line.long 0x18 "SS_HSYNC_CLR,SS HSYNC Clear" hexmask.long.word 0x18 16.--28. 1. " END ,Horizontal sync is de-asserted when horizontal count == END" hexmask.long.word 0x18 0.--12. 1. " START ,Horizontal sync is asserted when horizontal count == START" line.long 0x1C "SS_HSYNC_TOG,SS HSYNC Toggle" bitfld.long 0x1C 31. " POL ,Polarity of sync signal" "Low,High" hexmask.long.word 0x1C 16.--28. 1. " END ,Horizontal sync is de-asserted when horizontal count == END" hexmask.long.word 0x1C 0.--12. 1. " START ,Horizontal sync is asserted when horizontal count == START" line.long 0x20 "SS_VSYNC,SS VSYNC" setclrfld.long 0x20 31. 0x24 31. 0x28 31. " POL_SET/CLR ,Polarity of sync signal" "Low,High" hexmask.long.word 0x20 16.--28. 1. " END ,When v_count = END h_count = CSR_SS_LRC_X vsync goes inactive" hexmask.long.word 0x20 0.--12. 1. " START ,When v_count = START and h_count = CSR_SS_LRC_X then vsync goes active" line.long 0x24 "SS_VSYNC_SET,SS VSYNC Set" hexmask.long.word 0x24 16.--28. 1. " END ,When v_count = END h_count = CSR_SS_LRC_X vsync goes inactive" hexmask.long.word 0x24 0.--12. 1. " START ,When v_count = START and h_count = CSR_SS_LRC_X then vsync goes active" line.long 0x28 "SS_VSYNC_CLR,SS VSYNC Clear" hexmask.long.word 0x28 16.--28. 1. " END ,When v_count = END h_count = CSR_SS_LRC_X vsync goes inactive" hexmask.long.word 0x28 0.--12. 1. " START ,When v_count = START and h_count = CSR_SS_LRC_X then vsync goes active" line.long 0x2C "SS_VSYNC_TOG,SS VSYNC Toggle" bitfld.long 0x2C 31. " POL ,Polarity of sync signal" "Low,High" hexmask.long.word 0x2C 16.--28. 1. " END ,When v_count = END h_count = CSR_SS_LRC_X vsync goes inactive" hexmask.long.word 0x2C 0.--12. 1. " START ,When v_count = START and h_count = CSR_SS_LRC_X then vsync goes active" line.long 0x30 "SS_DE_ULC,SS DE ULC" setclrfld.long 0x30 31. 0x34 31. 0x38 31. " POL_SET/CLR ,Polarity of DE signal" "Low,High" hexmask.long.word 0x30 16.--28. 1. " ULC_Y ,Vertical position in the display that determines when the DE goes active" hexmask.long.word 0x30 0.--12. 1. " ULC_X ,Horizontal position in the scan line that determines when DE goes active" line.long 0x34 "SS_DE_ULC_SET,SS DE ULC Set" hexmask.long.word 0x34 16.--28. 1. " ULC_Y ,Vertical position in the display that determines when the DE goes active" hexmask.long.word 0x34 0.--12. 1. " ULC_X ,Horizontal position in the scan line that determines when DE goes active" line.long 0x38 "SS_DE_ULC_CLR,SS DE ULC Clear" hexmask.long.word 0x38 16.--28. 1. " ULC_Y ,Vertical position in the display that determines when the DE goes active" hexmask.long.word 0x38 0.--12. 1. " ULC_X ,Horizontal position in the scan line that determines when DE goes active" line.long 0x3C "SS_DE_ULC_TOG,SS DE ULC Toggle" bitfld.long 0x3C 31. " POL ,Polarity of DE signal" "Low,High" hexmask.long.word 0x3C 16.--28. 1. " ULC_Y ,Vertical position in the display that determines when the DE goes active" hexmask.long.word 0x3C 0.--12. 1. " ULC_X ,Horizontal position in the scan line that determines when DE goes active" line.long 0x40 "SS_DE_LRC,SS DE ULC" hexmask.long.word 0x40 16.--28. 1. " LRC_Y ,Vertical position in the display that determines when the DE goes inactive" hexmask.long.word 0x40 0.--12. 1. " LRC_X ,Horizontal position in the scan line that determines when DE goes inactive" line.long 0x44 "SS_DE_LRC_SET,SS DE LRC Set" hexmask.long.word 0x44 16.--28. 1. " LRC_Y ,Vertical position in the display that determines when the DE goes inactive" hexmask.long.word 0x44 0.--12. 1. " LRC_X ,Horizontal position in the scan line that determines when DE goes inactive" line.long 0x48 "SS_DE_LRC_CLR,SS DE LRC Clear" hexmask.long.word 0x48 16.--28. 1. " LRC_Y ,Vertical position in the display that determines when the DE goes inactive" hexmask.long.word 0x48 0.--12. 1. " LRC_X ,Horizontal position in the scan line that determines when DE goes inactive" line.long 0x4C "SS_DE_LRC_TOG,SS DE LRC Toggle" hexmask.long.word 0x4C 16.--28. 1. " LRC_Y ,Vertical position in the display that determines when the DE goes inactive" hexmask.long.word 0x4C 0.--12. 1. " LRC_X ,Horizontal position in the scan line that determines when DE goes inactive" line.long 0x50 "SS_MODE,SS MODE" bitfld.long 0x50 0.--1. " PIPE_MODE ,Sub-sampler mode" "Bypass,422 subsample,422 subsample,Bypass" line.long 0x54 "SS_MODE_SET,SS MODE Set" bitfld.long 0x54 0.--1. " PIPE_MODE ,Sub-sampler mode" "Bypass,422 subsample,422 subsample,Bypass" line.long 0x58 "SS_MODE_CLR,SS MODE Clear" bitfld.long 0x58 0.--1. " PIPE_MODE ,Sub-sampler mode" "Bypass,422 subsample,422 subsample,Bypass" line.long 0x5C "SS_MODE_TOG,SS MODE Toggle" bitfld.long 0x5C 0.--1. " PIPE_MODE ,Sub-sampler mode" "Bypass,422 subsample,422 subsample,Bypass" line.long 0x60 "SS_COEFF,SS COEFF" bitfld.long 0x60 28.--30. " VERT_NORM ,Vertical filter normalization factor" "0,1,2,3,4,5,6,7" bitfld.long 0x60 24.--27. " VERT_C ,Vertical C coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x60 20.--23. " VERT_B ,Vertical B coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x60 16.--19. " VERT_A ,Vertical A coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x60 12.--14. " HORIZ_NORM ,Horizontal filter normalization factor" "0,1,2,3,4,5,6,7" bitfld.long 0x60 8.--11. " HORIZ_C ,Horizontal C coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x60 4.--7. " HORIZ_B ,Horizontal B coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x60 0.--3. " HORIZ_A ,Horizontal A coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x64 "SS_COEFF_SET,SS COEFF Set" bitfld.long 0x64 28.--30. " VERT_NORM ,Vertical filter normalization factor" "0,1,2,3,4,5,6,7" bitfld.long 0x64 24.--27. " VERT_C ,Vertical C coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x64 20.--23. " VERT_B ,Vertical B coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x64 16.--19. " VERT_A ,Vertical A coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x64 12.--14. " HORIZ_NORM ,Horizontal filter normalization factor" "0,1,2,3,4,5,6,7" bitfld.long 0x64 8.--11. " HORIZ_C ,Horizontal C coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x64 4.--7. " HORIZ_B ,Horizontal B coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x64 0.--3. " HORIZ_A ,Horizontal A coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x68 "SS_COEFF_CLR,SS COEFF Clear" bitfld.long 0x68 28.--30. " VERT_NORM ,Vertical filter normalization factor" "0,1,2,3,4,5,6,7" bitfld.long 0x68 24.--27. " VERT_C ,Vertical C coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x68 20.--23. " VERT_B ,Vertical B coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x68 16.--19. " VERT_A ,Vertical A coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x68 12.--14. " HORIZ_NORM ,Horizontal filter normalization factor" "0,1,2,3,4,5,6,7" bitfld.long 0x68 8.--11. " HORIZ_C ,Horizontal C coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x68 4.--7. " HORIZ_B ,Horizontal B coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x68 0.--3. " HORIZ_A ,Horizontal A coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x6C "SS_COEFF_TOG,SS COEFF Toggle" bitfld.long 0x6C 28.--30. " VERT_NORM ,Vertical filter normalization factor" "0,1,2,3,4,5,6,7" bitfld.long 0x6C 24.--27. " VERT_C ,Vertical C coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x6C 20.--23. " VERT_B ,Vertical B coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x6C 16.--19. " VERT_A ,Vertical A coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x6C 12.--14. " HORIZ_NORM ,Horizontal filter normalization factor" "0,1,2,3,4,5,6,7" bitfld.long 0x6C 8.--11. " HORIZ_C ,Horizontal C coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x6C 4.--7. " HORIZ_B ,Horizontal B coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x6C 0.--3. " HORIZ_A ,Horizontal A coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x70 "SS_CLIP_CB,SS CLIP CB" hexmask.long.word 0x70 16.--25. 1. " MAX ,Maximum value for Cb clipping function" hexmask.long.word 0x70 0.--9. 1. " MIN ,Minimum value for Cb clipping function" line.long 0x74 "SS_CLIP_CB_SET,SS CLIP CB Set" hexmask.long.word 0x74 16.--25. 1. " MAX ,Maximum value for Cb clipping function" hexmask.long.word 0x74 0.--9. 1. " MIN ,Minimum value for Cb clipping function" line.long 0x78 "SS_CLIP_CB_CLR,SS CLIP CB Clear" hexmask.long.word 0x78 16.--25. 1. " MAX ,Maximum value for Cb clipping function" hexmask.long.word 0x78 0.--9. 1. " MIN ,Minimum value for Cb clipping function" line.long 0x7C "SS_CLIP_CB_TOG,SS CLIP CB Toggle" hexmask.long.word 0x7C 16.--25. 1. " MAX ,Maximum value for Cb clipping function" hexmask.long.word 0x7C 0.--9. 1. " MIN ,Minimum value for Cb clipping function" line.long 0x80 "SS_CLIP_CR,SS CLIP CR" hexmask.long.word 0x80 16.--25. 1. " MAX ,Maximum value for Cr clipping function" hexmask.long.word 0x80 0.--9. 1. " MIN ,Minimum value for Cr clipping function" line.long 0x84 "SS_CLIP_CR_SET,SS CLIP CR Set" hexmask.long.word 0x84 16.--25. 1. " MAX ,Maximum value for Cr clipping function" hexmask.long.word 0x84 0.--9. 1. " MIN ,Minimum value for Cr clipping function" line.long 0x88 "SS_CLIP_CR_CLR,SS CLIP CR Clear" hexmask.long.word 0x88 16.--25. 1. " MAX ,Maximum value for Cr clipping function" hexmask.long.word 0x88 0.--9. 1. " MIN ,Minimum value for Cr clipping function" line.long 0x8C "SS_CLIP_CR_TOG,SS CLIP CR Toggle" hexmask.long.word 0x8C 16.--25. 1. " MAX ,Maximum value for Cr clipping function" hexmask.long.word 0x8C 0.--9. 1. " MIN ,Minimum value for Cr clipping function" line.long 0x90 "SS_INTER_MODE_SET/CLR,SS INTER MODE Set/Clear" setclrfld.long 0x90 1. 0x94 1. 0x98 1. " VSYNC_SHIFT ,Vsync shift enable" "Disabled,Enabled" setclrfld.long 0x90 0. 0x94 0. 0x98 0. " INT_EN ,Enable interlaced HDMI timing" "Disabled,Enabled" group.long 0xAC++0x03 line.long 0x00 "SS_INTER_MODE_TOG,SS INTER MODE Toggle" bitfld.long 0x00 1. " VSYNC_SHIFT ,Vsync shift enable" "Disabled,Enabled" bitfld.long 0x00 0. " INT_EN ,Enable interlaced HDMI timing" "Disabled,Enabled" width 0x0B tree.end tree "WR_SCL (Write Scale)" base ad:0x00021000 width 17. group.long 0x00++0x17 line.long 0x00 "CTRL_STATUS,Control Register For Context Loader" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " WR_ERR_SET/CLR ,Write error on the axi interface" "No error,Error" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " WR_ERR_EN_SET/CLR ,Write error IRQ enable" "Disabled,Enabled" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " FRAME_COMP_SET/CLR ,Indicates the current frame being processed has finished" "Not finished,Finished" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " FRAME_COMP_EN_SET/CLR ,Write error IRQ enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 18.--24. 1. " FIFO_SIZE ,Size of FIFO in design" hexmask.long.byte 0x00 10.--17. 1. " P_FREQ ,Payload frequency" bitfld.long 0x00 7.--9. " P_SIZE ,Payload size" "64B,128B,256B,512B,1KB,2KB,4KB,?..." bitfld.long 0x00 5.--6. " T_SIZE ,Transaction size" "64B,128B,256B,512B" textline " " bitfld.long 0x00 2.--4. " BPP ,Bits per pixel" "38bpp,32bpp,32bpp,20bpp,16bpp,?..." setclrfld.long 0x00 1. 0x04 1. 0x08 1. " REPEAT_SET/CLR ,Repeat feature" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ENABLE_SET/CLR ,Enable bit for the write_scalar" "Disabled,Enabled" line.long 0x04 "CTRL_STATUS_SET,Control Register For Context Loader Set" hexmask.long.byte 0x04 18.--24. 1. " FIFO_SIZE ,Size of FIFO in design" hexmask.long.byte 0x04 10.--17. 1. " P_FREQ ,Payload frequency" bitfld.long 0x04 7.--9. " P_SIZE ,Payload size" "64B,128B,256B,512B,1KB,2KB,4KB,?..." bitfld.long 0x04 5.--6. " T_SIZE ,Transaction size" "64B,128B,256B,512B" textline " " bitfld.long 0x04 2.--4. " BPP ,Bits per pixel" "38bpp,32bpp,32bpp,20bpp,16bpp,?..." line.long 0x08 "CTRL_STATUS_CLR,Control Register For Context Loader Clear" hexmask.long.byte 0x08 18.--24. 1. " FIFO_SIZE ,Size of FIFO in design" hexmask.long.byte 0x08 10.--17. 1. " P_FREQ ,Payload frequency" bitfld.long 0x08 7.--9. " P_SIZE ,Payload size" "64B,128B,256B,512B,1KB,2KB,4KB,?..." bitfld.long 0x08 5.--6. " T_SIZE ,Transaction size" "64B,128B,256B,512B" textline " " bitfld.long 0x08 2.--4. " BPP ,Bits per pixel" "38bpp,32bpp,32bpp,20bpp,16bpp,?..." line.long 0x0C "CTRL_STATUS_TOG,Control Register For Context Loader Toggle" eventfld.long 0x0C 31. " WR_ERR ,Write error on the axi interface" "No error,Error" bitfld.long 0x0C 30. " WR_ERR_EN ,Write error IRQ enable" "Disabled,Enabled" eventfld.long 0x0C 29. " FRAME_COMP ,Indicates the current frame being processed has finished" "Not finished,Finished" bitfld.long 0x0C 28. " FRAME_COMP_EN ,Write error IRQ enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x0C 18.--24. 1. " FIFO_SIZE ,Size of FIFO in design" hexmask.long.byte 0x0C 10.--17. 1. " P_FREQ ,Payload frequency" bitfld.long 0x0C 7.--9. " P_SIZE ,Payload size" "64B,128B,256B,512B,1KB,2KB,4KB,?..." bitfld.long 0x0C 5.--6. " T_SIZE ,Transaction size" "64B,128B,256B,512B" textline " " bitfld.long 0x0C 2.--4. " BPP ,Bits per pixel" "38bpp,32bpp,32bpp,20bpp,16bpp,?..." bitfld.long 0x0C 1. " REPEAT ,Repeat feature" "Disabled,Enabled" bitfld.long 0x0C 0. " ENABLE ,Enable bit for the write_scalar" "Disabled,Enabled" line.long 0x10 "BASE_ADDR,Holds The Base Address" line.long 0x14 "PITCH,Pitch" hexmask.long.word 0x14 0.--15. 1. " PITCH ,Vertical pitch for memory address calculation" width 0x0B tree.end tree "RD_SRC (Read Surface)" base ad:0x00022000 width 17. group.long 0x00++0x1F line.long 0x00 "CTRL_STATUS,Control Register For Read Surface" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " RD_ERR_SET/CLR ,AXI read error" "No error,Error" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " FRAME_COMP_SET/CLR ,Frame processing complete" "In progress,Completed" hexmask.long.byte 0x00 16.--22. 1. " FIFO_SIZE ,FIFO size" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " RD_ERR_EN ,AXI read error IRQ enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 14. 0x04 14. 0x08 14. " FRAME_COMP_EN_SET/CLR ,Frame complete IRQ enable" "Disabled,Enabled" bitfld.long 0x00 7.--9. " P_SIZE ,Payload size" "64B,128B,256B,512B,?..." bitfld.long 0x00 5.--6. " T_SIZE ,Transaction size" "64B,128B,256B,512B" bitfld.long 0x00 2.--4. " BPP ,Bits per pixel" "40bpp,32bpp,32bpp,24bpp,16bpp,?..." textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ENABLE_SET/CLR ,Read surface enable" "Disabled,Enabled" line.long 0x04 "CTRL_STATUS_SET,Control Register For Read Surface Set" hexmask.long.byte 0x04 16.--22. 1. " FIFO_SIZE ,FIFO size" bitfld.long 0x04 7.--9. " P_SIZE ,Payload size" "64B,128B,256B,512B,?..." bitfld.long 0x04 5.--6. " T_SIZE ,Transaction size" "64B,128B,256B,512B" bitfld.long 0x04 2.--4. " BPP ,Bits per pixel" "40bpp,32bpp,32bpp,24bpp,16bpp,?..." line.long 0x08 "CTRL_STATUS_CLR,Control Register For Read Surface Clear" hexmask.long.byte 0x08 16.--22. 1. " FIFO_SIZE ,FIFO size" bitfld.long 0x08 7.--9. " P_SIZE ,Payload size" "64B,128B,256B,512B,?..." bitfld.long 0x08 5.--6. " T_SIZE ,Transaction size" "64B,128B,256B,512B" bitfld.long 0x08 2.--4. " BPP ,Bits per pixel" "40bpp,32bpp,32bpp,24bpp,16bpp,?..." line.long 0x0C "CTRL_STATUS_TOG,Control Register For Read Surface Toggle" eventfld.long 0x0C 31. " RD_ERR ,AXI read error" "No error,Error" eventfld.long 0x0C 30. " FRAME_COMP ,Frame processing complete" "In progress,Completed" hexmask.long.byte 0x0C 16.--22. 1. " FIFO_SIZE ,FIFO size" bitfld.long 0x0C 15. " RD_ERR_EN ,AXI read error IRQ enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 14. " FRAME_COMP_EN ,Frame complete IRQ enable" "Disabled,Enabled" bitfld.long 0x0C 7.--9. " P_SIZE ,Payload size" "64B,128B,256B,512B,?..." bitfld.long 0x0C 5.--6. " T_SIZE ,Transaction size" "64B,128B,256B,512B" bitfld.long 0x0C 2.--4. " BPP ,Bits per pixel" "40bpp,32bpp,32bpp,24bpp,16bpp,?..." textline " " bitfld.long 0x0C 0. " ENABLE ,Read surface enable" "Disabled,Enabled" line.long 0x10 "BASE_ADDR,Read Surface Base Address" line.long 0x14 "PITCH,Read Surface Vertical Pitch" hexmask.long.word 0x14 0.--15. 1. " PITCH ,Number of bytes between 2 vertically adjacent pixels in system memory" line.long 0x18 "WIDTH,Source Frame Buffer Width" hexmask.long.word 0x18 0.--15. 1. " WIDTH ,Width (in pixels) of the source frame buffer" line.long 0x1C "HEIGHT,Height Of Frame To Be Read" hexmask.long.word 0x1C 0.--15. 1. " HEIGHT ,Height (in pixels) of the source frame buffer" width 0x0B tree.end tree "IRQ_STEER (Interrupt Request Steering)" base ad:0x0002D000 width 14. group.long 0x00++0x0B line.long 0x00 "CHAN1CTL,Channel 1 Control Register" bitfld.long 0x00 0. " CH0 ,Channel &(1) control" "Disabled,Enabled" line.long 0x04 "CH1_MASK0,Channel 1 Interrupt Mask0 Register" bitfld.long 0x04 31. " MASKFLD[31] ,Mask for interrupt number 511" "Masked,Unmasked" bitfld.long 0x04 30. " [30] ,Mask for interrupt number 510" "Masked,Unmasked" bitfld.long 0x04 29. " [29] ,Mask for interrupt number 509" "Masked,Unmasked" bitfld.long 0x04 28. " [28] ,Mask for interrupt number 508" "Masked,Unmasked" textline " " bitfld.long 0x04 27. " [27] ,Mask for interrupt number 507" "Masked,Unmasked" bitfld.long 0x04 26. " [26] ,Mask for interrupt number 506" "Masked,Unmasked" bitfld.long 0x04 25. " [25] ,Mask for interrupt number 505" "Masked,Unmasked" bitfld.long 0x04 24. " [24] ,Mask for interrupt number 504" "Masked,Unmasked" textline " " bitfld.long 0x04 23. " [23] ,Mask for interrupt number 503" "Masked,Unmasked" bitfld.long 0x04 22. " [22] ,Mask for interrupt number 502" "Masked,Unmasked" bitfld.long 0x04 21. " [21] ,Mask for interrupt number 501" "Masked,Unmasked" bitfld.long 0x04 20. " [20] ,Mask for interrupt number 500" "Masked,Unmasked" textline " " bitfld.long 0x04 19. " [19] ,Mask for interrupt number 499" "Masked,Unmasked" bitfld.long 0x04 18. " [18] ,Mask for interrupt number 498" "Masked,Unmasked" bitfld.long 0x04 17. " [17] ,Mask for interrupt number 497" "Masked,Unmasked" bitfld.long 0x04 16. " [16] ,Mask for interrupt number 496" "Masked,Unmasked" textline " " bitfld.long 0x04 15. " [15] ,Mask for interrupt number 495" "Masked,Unmasked" bitfld.long 0x04 14. " [14] ,Mask for interrupt number 494" "Masked,Unmasked" bitfld.long 0x04 13. " [13] ,Mask for interrupt number 493" "Masked,Unmasked" bitfld.long 0x04 12. " [12] ,Mask for interrupt number 492" "Masked,Unmasked" textline " " bitfld.long 0x04 11. " [11] ,Mask for interrupt number 491" "Masked,Unmasked" bitfld.long 0x04 10. " [10] ,Mask for interrupt number 490" "Masked,Unmasked" bitfld.long 0x04 9. " [9] ,Mask for interrupt number 489" "Masked,Unmasked" bitfld.long 0x04 8. " [8] ,Mask for interrupt number 488" "Masked,Unmasked" textline " " bitfld.long 0x04 7. " [7] ,Mask for interrupt number 487" "Masked,Unmasked" bitfld.long 0x04 6. " [6] ,Mask for interrupt number 486" "Masked,Unmasked" bitfld.long 0x04 5. " [5] ,Mask for interrupt number 485" "Masked,Unmasked" bitfld.long 0x04 4. " [4] ,Mask for interrupt number 484" "Masked,Unmasked" textline " " bitfld.long 0x04 3. " [3] ,Mask for interrupt number 483" "Masked,Unmasked" bitfld.long 0x04 2. " [2] ,Mask for interrupt number 482" "Masked,Unmasked" bitfld.long 0x04 1. " [1] ,Mask for interrupt number 481" "Masked,Unmasked" bitfld.long 0x04 0. " [0] ,Mask for interrupt number 480" "Masked,Unmasked" line.long 0x08 "CH1_MASK1,Channel 1 Interrupt Mask1 Register" bitfld.long 0x08 31. " MASKFLD[31] ,Mask for interrupt number 479" "Masked,Unmasked" bitfld.long 0x08 30. " [30] ,Mask for interrupt number 478" "Masked,Unmasked" bitfld.long 0x08 29. " [29] ,Mask for interrupt number 477" "Masked,Unmasked" bitfld.long 0x08 28. " [28] ,Mask for interrupt number 476" "Masked,Unmasked" textline " " bitfld.long 0x08 27. " [27] ,Mask for interrupt number 475" "Masked,Unmasked" bitfld.long 0x08 26. " [26] ,Mask for interrupt number 474" "Masked,Unmasked" bitfld.long 0x08 25. " [25] ,Mask for interrupt number 473" "Masked,Unmasked" bitfld.long 0x08 24. " [24] ,Mask for interrupt number 472" "Masked,Unmasked" textline " " bitfld.long 0x08 23. " [23] ,Mask for interrupt number 471" "Masked,Unmasked" bitfld.long 0x08 22. " [22] ,Mask for interrupt number 470" "Masked,Unmasked" bitfld.long 0x08 21. " [21] ,Mask for interrupt number 469" "Masked,Unmasked" bitfld.long 0x08 20. " [20] ,Mask for interrupt number 468" "Masked,Unmasked" textline " " bitfld.long 0x08 19. " [19] ,Mask for interrupt number 467" "Masked,Unmasked" bitfld.long 0x08 18. " [18] ,Mask for interrupt number 466" "Masked,Unmasked" bitfld.long 0x08 17. " [17] ,Mask for interrupt number 465" "Masked,Unmasked" bitfld.long 0x08 16. " [16] ,Mask for interrupt number 464" "Masked,Unmasked" textline " " bitfld.long 0x08 15. " [15] ,Mask for interrupt number 463" "Masked,Unmasked" bitfld.long 0x08 14. " [14] ,Mask for interrupt number 462" "Masked,Unmasked" bitfld.long 0x08 13. " [13] ,Mask for interrupt number 461" "Masked,Unmasked" bitfld.long 0x08 12. " [12] ,Mask for interrupt number 460" "Masked,Unmasked" textline " " bitfld.long 0x08 11. " [11] ,Mask for interrupt number 459" "Masked,Unmasked" bitfld.long 0x08 10. " [10] ,Mask for interrupt number 458" "Masked,Unmasked" bitfld.long 0x08 9. " [9] ,Mask for interrupt number 457" "Masked,Unmasked" bitfld.long 0x08 8. " [8] ,Mask for interrupt number 456" "Masked,Unmasked" textline " " bitfld.long 0x08 7. " [7] ,Mask for interrupt number 455" "Masked,Unmasked" bitfld.long 0x08 6. " [6] ,Mask for interrupt number 454" "Masked,Unmasked" bitfld.long 0x08 5. " [5] ,Mask for interrupt number 453" "Masked,Unmasked" bitfld.long 0x08 4. " [4] ,Mask for interrupt number 452" "Masked,Unmasked" textline " " bitfld.long 0x08 3. " [3] ,Mask for interrupt number 451" "Masked,Unmasked" bitfld.long 0x08 2. " [2] ,Mask for interrupt number 450" "Masked,Unmasked" bitfld.long 0x08 1. " [1] ,Mask for interrupt number 449" "Masked,Unmasked" bitfld.long 0x08 0. " [0] ,Mask for interrupt number 448" "Masked,Unmasked" group.long 0x44++0x07 line.long 0x00 "CH1_SET0,Channel 1 Interrupt Set0 Register" bitfld.long 0x00 31. " MASKFLD[31] ,Force interrupt number 511" "Not forced,Forced" bitfld.long 0x00 30. " [30] ,Force interrupt number 510" "Not forced,Forced" bitfld.long 0x00 29. " [29] ,Force interrupt number 509" "Not forced,Forced" bitfld.long 0x00 28. " [28] ,Force interrupt number 508" "Not forced,Forced" textline " " bitfld.long 0x00 27. " [27] ,Force interrupt number 507" "Not forced,Forced" bitfld.long 0x00 26. " [26] ,Force interrupt number 506" "Not forced,Forced" bitfld.long 0x00 25. " [25] ,Force interrupt number 505" "Not forced,Forced" bitfld.long 0x00 24. " [24] ,Force interrupt number 504" "Not forced,Forced" textline " " bitfld.long 0x00 23. " [23] ,Force interrupt number 503" "Not forced,Forced" bitfld.long 0x00 22. " [22] ,Force interrupt number 502" "Not forced,Forced" bitfld.long 0x00 21. " [21] ,Force interrupt number 501" "Not forced,Forced" bitfld.long 0x00 20. " [20] ,Force interrupt number 500" "Not forced,Forced" textline " " bitfld.long 0x00 19. " [19] ,Force interrupt number 499" "Not forced,Forced" bitfld.long 0x00 18. " [18] ,Force interrupt number 498" "Not forced,Forced" bitfld.long 0x00 17. " [17] ,Force interrupt number 497" "Not forced,Forced" bitfld.long 0x00 16. " [16] ,Force interrupt number 496" "Not forced,Forced" textline " " bitfld.long 0x00 15. " [15] ,Force interrupt number 495" "Not forced,Forced" bitfld.long 0x00 14. " [14] ,Force interrupt number 494" "Not forced,Forced" bitfld.long 0x00 13. " [13] ,Force interrupt number 493" "Not forced,Forced" bitfld.long 0x00 12. " [12] ,Force interrupt number 492" "Not forced,Forced" textline " " bitfld.long 0x00 11. " [11] ,Force interrupt number 491" "Not forced,Forced" bitfld.long 0x00 10. " [10] ,Force interrupt number 490" "Not forced,Forced" bitfld.long 0x00 9. " [9] ,Force interrupt number 489" "Not forced,Forced" bitfld.long 0x00 8. " [8] ,Force interrupt number 488" "Not forced,Forced" textline " " bitfld.long 0x00 7. " [7] ,Force interrupt number 487" "Not forced,Forced" bitfld.long 0x00 6. " [6] ,Force interrupt number 486" "Not forced,Forced" bitfld.long 0x00 5. " [5] ,Force interrupt number 485" "Not forced,Forced" bitfld.long 0x00 4. " [4] ,Force interrupt number 484" "Not forced,Forced" textline " " bitfld.long 0x00 3. " [3] ,Force interrupt number 483" "Not forced,Forced" bitfld.long 0x00 2. " [2] ,Force interrupt number 482" "Not forced,Forced" bitfld.long 0x00 1. " [1] ,Force interrupt number 481" "Not forced,Forced" bitfld.long 0x00 0. " [0] ,Force interrupt number 480" "Not forced,Forced" line.long 0x04 "CH1_SET1,Channel 1 Interrupt Set1 Register" bitfld.long 0x04 31. " MASKFLD[31] ,Force interrupt number 479" "Not forced,Forced" bitfld.long 0x04 30. " [30] ,Force interrupt number 478" "Not forced,Forced" bitfld.long 0x04 29. " [29] ,Force interrupt number 477" "Not forced,Forced" bitfld.long 0x04 28. " [28] ,Force interrupt number 476" "Not forced,Forced" textline " " bitfld.long 0x04 27. " [27] ,Force interrupt number 475" "Not forced,Forced" bitfld.long 0x04 26. " [26] ,Force interrupt number 474" "Not forced,Forced" bitfld.long 0x04 25. " [25] ,Force interrupt number 473" "Not forced,Forced" bitfld.long 0x04 24. " [24] ,Force interrupt number 472" "Not forced,Forced" textline " " bitfld.long 0x04 23. " [23] ,Force interrupt number 471" "Not forced,Forced" bitfld.long 0x04 22. " [22] ,Force interrupt number 470" "Not forced,Forced" bitfld.long 0x04 21. " [21] ,Force interrupt number 469" "Not forced,Forced" bitfld.long 0x04 20. " [20] ,Force interrupt number 468" "Not forced,Forced" textline " " bitfld.long 0x04 19. " [19] ,Force interrupt number 467" "Not forced,Forced" bitfld.long 0x04 18. " [18] ,Force interrupt number 466" "Not forced,Forced" bitfld.long 0x04 17. " [17] ,Force interrupt number 465" "Not forced,Forced" bitfld.long 0x04 16. " [16] ,Force interrupt number 464" "Not forced,Forced" textline " " bitfld.long 0x04 15. " [15] ,Force interrupt number 463" "Not forced,Forced" bitfld.long 0x04 14. " [14] ,Force interrupt number 462" "Not forced,Forced" bitfld.long 0x04 13. " [13] ,Force interrupt number 461" "Not forced,Forced" bitfld.long 0x04 12. " [12] ,Force interrupt number 460" "Not forced,Forced" textline " " bitfld.long 0x04 11. " [11] ,Force interrupt number 459" "Not forced,Forced" bitfld.long 0x04 10. " [10] ,Force interrupt number 458" "Not forced,Forced" bitfld.long 0x04 9. " [9] ,Force interrupt number 457" "Not forced,Forced" bitfld.long 0x04 8. " [8] ,Force interrupt number 456" "Not forced,Forced" textline " " bitfld.long 0x04 7. " [7] ,Force interrupt number 455" "Not forced,Forced" bitfld.long 0x04 6. " [6] ,Force interrupt number 454" "Not forced,Forced" bitfld.long 0x04 5. " [5] ,Force interrupt number 453" "Not forced,Forced" bitfld.long 0x04 4. " [4] ,Force interrupt number 452" "Not forced,Forced" textline " " bitfld.long 0x04 3. " [3] ,Force interrupt number 451" "Not forced,Forced" bitfld.long 0x04 2. " [2] ,Force interrupt number 450" "Not forced,Forced" bitfld.long 0x04 1. " [1] ,Force interrupt number 449" "Not forced,Forced" bitfld.long 0x04 0. " [0] ,Force interrupt number 448" "Not forced,Forced" rgroup.long 0x84++0x07 line.long 0x00 "CH1_STATUS0,Channel 1 Interrupt Status0 Register" bitfld.long 0x00 31. " MASKFLD[31] ,Status of interrupt number 511" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Status of interrupt number 510" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Status of interrupt number 509" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Status of interrupt number 508" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " [27] ,Status of interrupt number 507" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Status of interrupt number 506" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Status of interrupt number 505" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Status of interrupt number 504" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " [23] ,Status of interrupt number 503" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Status of interrupt number 502" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Status of interrupt number 501" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Status of interrupt number 500" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " [19] ,Status of interrupt number 499" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Status of interrupt number 498" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Status of interrupt number 497" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Status of interrupt number 496" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " [15] ,Status of interrupt number 495" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Status of interrupt number 494" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Status of interrupt number 493" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Status of interrupt number 492" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " [11] ,Status of interrupt number 491" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Status of interrupt number 490" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Status of interrupt number 489" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Status of interrupt number 488" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " [7] ,Status of interrupt number 487" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Status of interrupt number 486" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Status of interrupt number 485" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Status of interrupt number 484" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " [3] ,Status of interrupt number 483" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Status of interrupt number 482" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Status of interrupt number 481" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Status of interrupt number 480" "No interrupt,Interrupt" line.long 0x04 "CH1_STATUS1,Channel 1 Interrupt Status1 Register" bitfld.long 0x04 31. " MASKFLD[31] ,Status of interrupt number 479" "No interrupt,Interrupt" bitfld.long 0x04 30. " [30] ,Status of interrupt number 478" "No interrupt,Interrupt" bitfld.long 0x04 29. " [29] ,Status of interrupt number 477" "No interrupt,Interrupt" bitfld.long 0x04 28. " [28] ,Status of interrupt number 476" "No interrupt,Interrupt" textline " " bitfld.long 0x04 27. " [27] ,Status of interrupt number 475" "No interrupt,Interrupt" bitfld.long 0x04 26. " [26] ,Status of interrupt number 474" "No interrupt,Interrupt" bitfld.long 0x04 25. " [25] ,Status of interrupt number 473" "No interrupt,Interrupt" bitfld.long 0x04 24. " [24] ,Status of interrupt number 472" "No interrupt,Interrupt" textline " " bitfld.long 0x04 23. " [23] ,Status of interrupt number 471" "No interrupt,Interrupt" bitfld.long 0x04 22. " [22] ,Status of interrupt number 470" "No interrupt,Interrupt" bitfld.long 0x04 21. " [21] ,Status of interrupt number 469" "No interrupt,Interrupt" bitfld.long 0x04 20. " [20] ,Status of interrupt number 468" "No interrupt,Interrupt" textline " " bitfld.long 0x04 19. " [19] ,Status of interrupt number 467" "No interrupt,Interrupt" bitfld.long 0x04 18. " [18] ,Status of interrupt number 466" "No interrupt,Interrupt" bitfld.long 0x04 17. " [17] ,Status of interrupt number 465" "No interrupt,Interrupt" bitfld.long 0x04 16. " [16] ,Status of interrupt number 464" "No interrupt,Interrupt" textline " " bitfld.long 0x04 15. " [15] ,Status of interrupt number 463" "No interrupt,Interrupt" bitfld.long 0x04 14. " [14] ,Status of interrupt number 462" "No interrupt,Interrupt" bitfld.long 0x04 13. " [13] ,Status of interrupt number 461" "No interrupt,Interrupt" bitfld.long 0x04 12. " [12] ,Status of interrupt number 460" "No interrupt,Interrupt" textline " " bitfld.long 0x04 11. " [11] ,Status of interrupt number 459" "No interrupt,Interrupt" bitfld.long 0x04 10. " [10] ,Status of interrupt number 458" "No interrupt,Interrupt" bitfld.long 0x04 9. " [9] ,Status of interrupt number 457" "No interrupt,Interrupt" bitfld.long 0x04 8. " [8] ,Status of interrupt number 456" "No interrupt,Interrupt" textline " " bitfld.long 0x04 7. " [7] ,Status of interrupt number 455" "No interrupt,Interrupt" bitfld.long 0x04 6. " [6] ,Status of interrupt number 454" "No interrupt,Interrupt" bitfld.long 0x04 5. " [5] ,Status of interrupt number 453" "No interrupt,Interrupt" bitfld.long 0x04 4. " [4] ,Status of interrupt number 452" "No interrupt,Interrupt" textline " " bitfld.long 0x04 3. " [3] ,Status of interrupt number 451" "No interrupt,Interrupt" bitfld.long 0x04 2. " [2] ,Status of interrupt number 450" "No interrupt,Interrupt" bitfld.long 0x04 1. " [1] ,Status of interrupt number 449" "No interrupt,Interrupt" bitfld.long 0x04 0. " [0] ,Status of interrupt number 448" "No interrupt,Interrupt" group.long 0xC4++0x03 line.long 0x00 "CH1_MINTDIS,Channel 1 Master Interrupt Disable Register" bitfld.long 0x00 7. " DISABLE ,Disable interrupts from range of 511 - 448" "No,Yes" rgroup.long 0xC8++0x03 line.long 0x00 "CH1_MSTRSTAT,Channel 1 Master Status Register" bitfld.long 0x00 0. " STATUS ,Status of all interrupts" "None interrupt enabled,At least one interrupt enabled" width 0x0B tree.end tree.end tree.open "Low Speed Communication and Interconnects" tree.open "I2C (I2C Controller)" tree "I2C1" base ad:0x30A20000 width 11. group.word 0x00++0x01 line.word 0x00 "I2C1_IADR,I2C1 Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "I2C1_IFDR,I2C1 Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "30,32,36,42,48,52,60,72,80,88,104,128,144,160,192,240,288,320,384,480,576,640,768,960,1152,1280,1536,1920,2304,2560,3072,3840,22,24,26,28,32,36,40,44,48,56,64,72,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024,1280,1536,1792,2048" if (((per.w(ad:0x30A20000+0x08)&0x10)==0x00)) group.word 0x08++0x01 line.word 0x00 "I2C1_I2CR,I2C1 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "I2C1_I2CR,I2C1 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " rbitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" endif group.word 0x0C++0x01 line.word 0x00 "I2C1_I2SR,I2C1 Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "In progress,Completed" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Not addressed,Addressed" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" textline " " rbitfld.word 0x00 2. " SRW ,Slave read/write" "Slave receive/Master write,Slave transmit/Master receive" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "Acknowledged,No acknowledged" hgroup.word 0x10++0x01 hide.word 0x00 "I2C1_I2DR,I2C Data I/O Register" in width 0x0B tree.end tree "I2C2" base ad:0x30A30000 width 11. group.word 0x00++0x01 line.word 0x00 "I2C2_IADR,I2C2 Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "I2C2_IFDR,I2C2 Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "30,32,36,42,48,52,60,72,80,88,104,128,144,160,192,240,288,320,384,480,576,640,768,960,1152,1280,1536,1920,2304,2560,3072,3840,22,24,26,28,32,36,40,44,48,56,64,72,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024,1280,1536,1792,2048" if (((per.w(ad:0x30A30000+0x08)&0x10)==0x00)) group.word 0x08++0x01 line.word 0x00 "I2C2_I2CR,I2C2 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "I2C2_I2CR,I2C2 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " rbitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" endif group.word 0x0C++0x01 line.word 0x00 "I2C2_I2SR,I2C2 Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "In progress,Completed" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Not addressed,Addressed" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" textline " " rbitfld.word 0x00 2. " SRW ,Slave read/write" "Slave receive/Master write,Slave transmit/Master receive" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "Acknowledged,No acknowledged" hgroup.word 0x10++0x01 hide.word 0x00 "I2C2_I2DR,I2C Data I/O Register" in width 0x0B tree.end tree "I2C3" base ad:0x30A40000 width 11. group.word 0x00++0x01 line.word 0x00 "I2C3_IADR,I2C3 Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "I2C3_IFDR,I2C3 Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "30,32,36,42,48,52,60,72,80,88,104,128,144,160,192,240,288,320,384,480,576,640,768,960,1152,1280,1536,1920,2304,2560,3072,3840,22,24,26,28,32,36,40,44,48,56,64,72,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024,1280,1536,1792,2048" if (((per.w(ad:0x30A40000+0x08)&0x10)==0x00)) group.word 0x08++0x01 line.word 0x00 "I2C3_I2CR,I2C3 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "I2C3_I2CR,I2C3 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " rbitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" endif group.word 0x0C++0x01 line.word 0x00 "I2C3_I2SR,I2C3 Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "In progress,Completed" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Not addressed,Addressed" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" textline " " rbitfld.word 0x00 2. " SRW ,Slave read/write" "Slave receive/Master write,Slave transmit/Master receive" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "Acknowledged,No acknowledged" hgroup.word 0x10++0x01 hide.word 0x00 "I2C3_I2DR,I2C Data I/O Register" in width 0x0B tree.end tree "I2C4" base ad:0x30A50000 width 11. group.word 0x00++0x01 line.word 0x00 "I2C4_IADR,I2C4 Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "I2C4_IFDR,I2C4 Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "30,32,36,42,48,52,60,72,80,88,104,128,144,160,192,240,288,320,384,480,576,640,768,960,1152,1280,1536,1920,2304,2560,3072,3840,22,24,26,28,32,36,40,44,48,56,64,72,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024,1280,1536,1792,2048" if (((per.w(ad:0x30A50000+0x08)&0x10)==0x00)) group.word 0x08++0x01 line.word 0x00 "I2C4_I2CR,I2C4 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "I2C4_I2CR,I2C4 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " rbitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" endif group.word 0x0C++0x01 line.word 0x00 "I2C4_I2SR,I2C4 Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "In progress,Completed" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Not addressed,Addressed" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" textline " " rbitfld.word 0x00 2. " SRW ,Slave read/write" "Slave receive/Master write,Slave transmit/Master receive" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "Acknowledged,No acknowledged" hgroup.word 0x10++0x01 hide.word 0x00 "I2C4_I2DR,I2C Data I/O Register" in width 0x0B tree.end tree.end tree.open "UART (Universal Asynchronous Receiver/Transmitter)" tree "UART1" base ad:0x30860000 width 13. if (((per.l(ad:0x30860000+0x80)&0x01)==0x01)) if (((per.l(ad:0x30860000+0xB8)&0x01)==0x00)) rgroup.long 0x00++0x03 line.long 0x00 "UART1_URXD,UART1 Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,Break detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity error flag" "No error,Error" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" else rgroup.long 0x00++0x03 line.long 0x00 "UART1_URXD,UART1 Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,Break detect" "Not detected,Detected" bitfld.long 0x00 10. " NTHB ,Ninth data bit of received 9-bit RS-485 data" "0,1" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" endif wgroup.long 0x40++0x03 line.long 0x00 "UART1_UTXD,UART1 Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data" else hgroup.long 0x00++0x03 hide.long 0x00 "UART1_URXD,UART1 Receiver Register" hgroup.long 0x40++0x03 hide.long 0x00 "UART1_UTXD,UART1 Transmitter Register" endif group.long 0x80++0x03 line.long 0x00 "UART1_UCR1,UART1 Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Number of frames RXD is allowed to be idle before an idle condition is reported" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send break" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled in DOZE state,Disabled in DOZE state" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" if (((per.l(ad:0x30860000+0x84))&0x2010)==0x10) group.long 0x84++0x03 line.long 0x00 "UART1_UCR2,UART1 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "Inactive,Active" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising edge,Falling edge,Any edge,Any edge" bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" textline " " bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" elif (((per.l(ad:0x30860000+0x84))&0x2010)==0x2010) group.long 0x84++0x03 line.long 0x00 "UART1_UCR2,UART1 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising edge,Falling edge,Any edge,Any edge" bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" textline " " bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" elif (((per.l(ad:0x30860000+0x84))&0x2010)==0x2000) group.long 0x84++0x03 line.long 0x00 "UART1_UCR2,UART1 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" textline " " bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" else group.long 0x84++0x03 line.long 0x00 "UART1_UCR2,UART1 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "Inactive,Active" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" textline " " bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" endif textline " " if (((per.l(ad:0x30860000+0xB8)&0x01)==0x00)) if (((per.l(ad:0x30860000+0x80)&0x80)==0x80)) group.long 0x88++0x07 line.long 0x00 "UART1_UCR3,UART1 Control Register 3" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Disables new features of autobaud detection" "No,Yes" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" ",Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level (IrDA mode)" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" line.long 0x04 "UART1_UCR4,UART1 Control Register 4" bitfld.long 0x04 10.--15. " CTSTL ,CTS trigger level (number of characters in the RxFIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 9. " INVR ,Determine RXD input logic level being sampled (IrDA mode)" "Active low,Active high" bitfld.long 0x04 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " IRSC ,IR special case" "Sampling clock,UART reference clock" textline " " bitfld.long 0x04 4. " LPBYP ,Low power bypass disable" "No,Yes" bitfld.long 0x04 3. " TCEN ,TransmitComplete interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " BKEN ,BREAK condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" else group.long 0x88++0x07 line.long 0x00 "UART1_UCR3,UART1 Control Register 3" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Disables new features of autobaud detection" "No,Yes" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" ",Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" line.long 0x04 "UART1_UCR4,UART1 Control Register 4" bitfld.long 0x04 10.--15. " CTSTL ,CTS trigger level (number of characters in the RxFIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x04 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " IRSC ,IR special case" "Sampling clock,UART reference clock" textline " " bitfld.long 0x04 4. " LPBYP ,Low power bypass disable" "No,Yes" bitfld.long 0x04 3. " TCEN ,TransmitComplete interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " BKEN ,BREAK condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif else group.long 0x88++0x07 line.long 0x00 "UART1_UCR3,UART1 Control Register 3" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Disables new features of autobaud detection" "No,Yes" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" ",Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" line.long 0x04 "UART1_UCR4,UART1 Control Register 4" bitfld.long 0x04 10.--15. " CTSTL ,CTS trigger level (number of characters in the RxFIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x04 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " IRSC ,IR special case" "Sampling clock,UART reference clock" textline " " bitfld.long 0x04 4. " LPBYP ,Low power bypass disable" "No,Yes" bitfld.long 0x04 3. " TCEN ,TransmitComplete interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " BKEN ,BREAK condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif group.long 0x90++0x07 line.long 0x00 "UART1_UFCR,UART1 FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32(maximum),?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference frequency divider" "/6,/5,/4,/3,/2,/1,/7,?..." bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" textline " " bitfld.long 0x00 0.--5. " RXTL ,Receiver trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32(maximum),?..." line.long 0x04 "UART1_USR1,UART1 Status Register 1" eventfld.long 0x04 15. " PARITYERR ,Parity error interrupt flag" "No error,Error" rbitfld.long 0x04 14. " RTSS ,RTS_B pin status" "High,Low" rbitfld.long 0x04 13. " TRDY ,Transmitter ready interrupt / DMA flag" "Data not required,Data required" eventfld.long 0x04 12. " RTSD ,RTS_B pin changed state" "Not changed,Changed" textline " " eventfld.long 0x04 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x04 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x04 9. " RRDY ,Receiver ready interrupt / DMA flag" "Not ready,Ready" eventfld.long 0x04 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " rbitfld.long 0x04 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x04 5. " AIRINT ,Asynchronous IR WAKE interrupt flag" "No pulse detected,Pulse detected" eventfld.long 0x04 4. " AWAKE ,Asynchronous WAKE interrupt flag" "No falling edge detected,Falling edge detected" eventfld.long 0x04 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" if (((per.l(ad:0x30860000+0x80)&0x4000)==0x4000)) group.long 0x98++0x03 line.long 0x00 "UART1_USR2,UART1 Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x00 12. " IDLE ,Idle condition detect" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud counter stopped" "Not stopped,Stopped" textline " " eventfld.long 0x00 8. " IRINT ,Serial infrared interrupt flag" "No edge detected,Valid edge detected" eventfld.long 0x00 7. " WAKE ,Start bit is detected" "Not detected,Detected" eventfld.long 0x00 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x00 3. " TXDC ,Transmitter complete" "Incomplete,Complete" textline " " eventfld.long 0x00 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x00 0. " RDR ,Receive data ready" "Not ready,Ready" else group.long 0x98++0x03 line.long 0x00 "UART1_USR2,UART1 Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x00 12. " IDLE ,Idle condition detect" "Not detected,Detected" eventfld.long 0x00 8. " IRINT ,Serial infrared interrupt flag" "No edge detected,Valid edge detected" textline " " eventfld.long 0x00 7. " WAKE ,Start bit detect" "Not detected,Detected" eventfld.long 0x00 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x00 3. " TXDC ,Transmitter complete" "Incomplete,Complete" eventfld.long 0x00 2. " BRCD ,BREAK condition detected" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x00 0. " RDR ,Receive data ready" "Not ready,Ready" endif group.long 0x9C++0x0F line.long 0x00 "UART1_UESC,UART1 Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART escape character" line.long 0x04 "UART1_UTIM,UART1 Escape Timer Register" hexmask.long.word 0x04 0.--11. 1. " TIM ,UART escape timer" line.long 0x08 "UART1_UBIR,UART1 BRM Incremental Register" hexmask.long.word 0x08 0.--15. 1. " INC ,Incremental numerator" line.long 0x0C "UART1_UBMR,UART1 BRM Modulator Register" hexmask.long.word 0x0C 0.--15. 1. " MOD ,Modulator denominator" rgroup.long 0xAC++0x03 line.long 0x00 "UART1_UBRC,UART1 Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,Baud rate count register" group.long 0xB0++0x0B line.long 0x00 "UART1_ONEMS,UART1 One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,One millisecond register" line.long 0x04 "UART1_UTS,UART1 Test Register" bitfld.long 0x04 13. " FRCPERR ,Force parity error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for test" "Disabled,Enabled" bitfld.long 0x04 10. " LOOPIR ,Loop TX and RX for IR test (LOOPIR)" "Disabled,Enabled" bitfld.long 0x04 6. " TXEMPTY ,TxFIFO empty" "Not empty,Empty" textline " " bitfld.long 0x04 5. " RXEMPTY ,RxFIFO empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,TxFIFO full" "Not full,Full" bitfld.long 0x04 3. " RXFULL ,RxFIFO full" "Not full,Full" bitfld.long 0x04 0. " SOFTRST ,Software reset" "No reset,Reset" line.long 0x08 "UART1_UMCR,UART1 RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 0x01 " SLADDR ,RS-485 slave address character" bitfld.long 0x08 3. " SADEN ,RS-485 slave address detected interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" bitfld.long 0x08 1. " SLAM ,RS-485 slave address detect mode selection" "Normal,Automatic" textline " " bitfld.long 0x08 0. " MDEN ,9-bit data or multidrop mode enable" "RS-232||IrDA,RS-485" width 0x0B tree.end tree "UART2" base ad:0x30890000 width 13. if (((per.l(ad:0x30890000+0x80)&0x01)==0x01)) if (((per.l(ad:0x30890000+0xB8)&0x01)==0x00)) rgroup.long 0x00++0x03 line.long 0x00 "UART2_URXD,UART2 Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,Break detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity error flag" "No error,Error" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" else rgroup.long 0x00++0x03 line.long 0x00 "UART2_URXD,UART2 Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,Break detect" "Not detected,Detected" bitfld.long 0x00 10. " NTHB ,Ninth data bit of received 9-bit RS-485 data" "0,1" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" endif wgroup.long 0x40++0x03 line.long 0x00 "UART2_UTXD,UART2 Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data" else hgroup.long 0x00++0x03 hide.long 0x00 "UART2_URXD,UART2 Receiver Register" hgroup.long 0x40++0x03 hide.long 0x00 "UART2_UTXD,UART2 Transmitter Register" endif group.long 0x80++0x03 line.long 0x00 "UART2_UCR1,UART2 Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Number of frames RXD is allowed to be idle before an idle condition is reported" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send break" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled in DOZE state,Disabled in DOZE state" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" if (((per.l(ad:0x30890000+0x84))&0x2010)==0x10) group.long 0x84++0x03 line.long 0x00 "UART2_UCR2,UART2 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "Inactive,Active" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising edge,Falling edge,Any edge,Any edge" bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" textline " " bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" elif (((per.l(ad:0x30890000+0x84))&0x2010)==0x2010) group.long 0x84++0x03 line.long 0x00 "UART2_UCR2,UART2 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising edge,Falling edge,Any edge,Any edge" bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" textline " " bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" elif (((per.l(ad:0x30890000+0x84))&0x2010)==0x2000) group.long 0x84++0x03 line.long 0x00 "UART2_UCR2,UART2 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" textline " " bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" else group.long 0x84++0x03 line.long 0x00 "UART2_UCR2,UART2 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "Inactive,Active" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" textline " " bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" endif textline " " if (((per.l(ad:0x30890000+0xB8)&0x01)==0x00)) if (((per.l(ad:0x30890000+0x80)&0x80)==0x80)) group.long 0x88++0x07 line.long 0x00 "UART2_UCR3,UART2 Control Register 3" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Disables new features of autobaud detection" "No,Yes" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" ",Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level (IrDA mode)" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" line.long 0x04 "UART2_UCR4,UART2 Control Register 4" bitfld.long 0x04 10.--15. " CTSTL ,CTS trigger level (number of characters in the RxFIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 9. " INVR ,Determine RXD input logic level being sampled (IrDA mode)" "Active low,Active high" bitfld.long 0x04 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " IRSC ,IR special case" "Sampling clock,UART reference clock" textline " " bitfld.long 0x04 4. " LPBYP ,Low power bypass disable" "No,Yes" bitfld.long 0x04 3. " TCEN ,TransmitComplete interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " BKEN ,BREAK condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" else group.long 0x88++0x07 line.long 0x00 "UART2_UCR3,UART2 Control Register 3" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Disables new features of autobaud detection" "No,Yes" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" ",Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" line.long 0x04 "UART2_UCR4,UART2 Control Register 4" bitfld.long 0x04 10.--15. " CTSTL ,CTS trigger level (number of characters in the RxFIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x04 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " IRSC ,IR special case" "Sampling clock,UART reference clock" textline " " bitfld.long 0x04 4. " LPBYP ,Low power bypass disable" "No,Yes" bitfld.long 0x04 3. " TCEN ,TransmitComplete interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " BKEN ,BREAK condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif else group.long 0x88++0x07 line.long 0x00 "UART2_UCR3,UART2 Control Register 3" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Disables new features of autobaud detection" "No,Yes" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" ",Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" line.long 0x04 "UART2_UCR4,UART2 Control Register 4" bitfld.long 0x04 10.--15. " CTSTL ,CTS trigger level (number of characters in the RxFIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x04 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " IRSC ,IR special case" "Sampling clock,UART reference clock" textline " " bitfld.long 0x04 4. " LPBYP ,Low power bypass disable" "No,Yes" bitfld.long 0x04 3. " TCEN ,TransmitComplete interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " BKEN ,BREAK condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif group.long 0x90++0x07 line.long 0x00 "UART2_UFCR,UART2 FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32(maximum),?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference frequency divider" "/6,/5,/4,/3,/2,/1,/7,?..." bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" textline " " bitfld.long 0x00 0.--5. " RXTL ,Receiver trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32(maximum),?..." line.long 0x04 "UART2_USR1,UART2 Status Register 1" eventfld.long 0x04 15. " PARITYERR ,Parity error interrupt flag" "No error,Error" rbitfld.long 0x04 14. " RTSS ,RTS_B pin status" "High,Low" rbitfld.long 0x04 13. " TRDY ,Transmitter ready interrupt / DMA flag" "Data not required,Data required" eventfld.long 0x04 12. " RTSD ,RTS_B pin changed state" "Not changed,Changed" textline " " eventfld.long 0x04 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x04 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x04 9. " RRDY ,Receiver ready interrupt / DMA flag" "Not ready,Ready" eventfld.long 0x04 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " rbitfld.long 0x04 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x04 5. " AIRINT ,Asynchronous IR WAKE interrupt flag" "No pulse detected,Pulse detected" eventfld.long 0x04 4. " AWAKE ,Asynchronous WAKE interrupt flag" "No falling edge detected,Falling edge detected" eventfld.long 0x04 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" if (((per.l(ad:0x30890000+0x80)&0x4000)==0x4000)) group.long 0x98++0x03 line.long 0x00 "UART2_USR2,UART2 Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x00 12. " IDLE ,Idle condition detect" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud counter stopped" "Not stopped,Stopped" textline " " eventfld.long 0x00 8. " IRINT ,Serial infrared interrupt flag" "No edge detected,Valid edge detected" eventfld.long 0x00 7. " WAKE ,Start bit is detected" "Not detected,Detected" eventfld.long 0x00 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x00 3. " TXDC ,Transmitter complete" "Incomplete,Complete" textline " " eventfld.long 0x00 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x00 0. " RDR ,Receive data ready" "Not ready,Ready" else group.long 0x98++0x03 line.long 0x00 "UART2_USR2,UART2 Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x00 12. " IDLE ,Idle condition detect" "Not detected,Detected" eventfld.long 0x00 8. " IRINT ,Serial infrared interrupt flag" "No edge detected,Valid edge detected" textline " " eventfld.long 0x00 7. " WAKE ,Start bit detect" "Not detected,Detected" eventfld.long 0x00 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x00 3. " TXDC ,Transmitter complete" "Incomplete,Complete" eventfld.long 0x00 2. " BRCD ,BREAK condition detected" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x00 0. " RDR ,Receive data ready" "Not ready,Ready" endif group.long 0x9C++0x0F line.long 0x00 "UART2_UESC,UART2 Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART escape character" line.long 0x04 "UART2_UTIM,UART2 Escape Timer Register" hexmask.long.word 0x04 0.--11. 1. " TIM ,UART escape timer" line.long 0x08 "UART2_UBIR,UART2 BRM Incremental Register" hexmask.long.word 0x08 0.--15. 1. " INC ,Incremental numerator" line.long 0x0C "UART2_UBMR,UART2 BRM Modulator Register" hexmask.long.word 0x0C 0.--15. 1. " MOD ,Modulator denominator" rgroup.long 0xAC++0x03 line.long 0x00 "UART2_UBRC,UART2 Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,Baud rate count register" group.long 0xB0++0x0B line.long 0x00 "UART2_ONEMS,UART2 One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,One millisecond register" line.long 0x04 "UART2_UTS,UART2 Test Register" bitfld.long 0x04 13. " FRCPERR ,Force parity error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for test" "Disabled,Enabled" bitfld.long 0x04 10. " LOOPIR ,Loop TX and RX for IR test (LOOPIR)" "Disabled,Enabled" bitfld.long 0x04 6. " TXEMPTY ,TxFIFO empty" "Not empty,Empty" textline " " bitfld.long 0x04 5. " RXEMPTY ,RxFIFO empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,TxFIFO full" "Not full,Full" bitfld.long 0x04 3. " RXFULL ,RxFIFO full" "Not full,Full" bitfld.long 0x04 0. " SOFTRST ,Software reset" "No reset,Reset" line.long 0x08 "UART2_UMCR,UART2 RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 0x01 " SLADDR ,RS-485 slave address character" bitfld.long 0x08 3. " SADEN ,RS-485 slave address detected interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" bitfld.long 0x08 1. " SLAM ,RS-485 slave address detect mode selection" "Normal,Automatic" textline " " bitfld.long 0x08 0. " MDEN ,9-bit data or multidrop mode enable" "RS-232||IrDA,RS-485" width 0x0B tree.end tree "UART3" base ad:0x30880000 width 13. if (((per.l(ad:0x30880000+0x80)&0x01)==0x01)) if (((per.l(ad:0x30880000+0xB8)&0x01)==0x00)) rgroup.long 0x00++0x03 line.long 0x00 "UART3_URXD,UART3 Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,Break detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity error flag" "No error,Error" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" else rgroup.long 0x00++0x03 line.long 0x00 "UART3_URXD,UART3 Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,Break detect" "Not detected,Detected" bitfld.long 0x00 10. " NTHB ,Ninth data bit of received 9-bit RS-485 data" "0,1" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" endif wgroup.long 0x40++0x03 line.long 0x00 "UART3_UTXD,UART3 Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data" else hgroup.long 0x00++0x03 hide.long 0x00 "UART3_URXD,UART3 Receiver Register" hgroup.long 0x40++0x03 hide.long 0x00 "UART3_UTXD,UART3 Transmitter Register" endif group.long 0x80++0x03 line.long 0x00 "UART3_UCR1,UART3 Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Number of frames RXD is allowed to be idle before an idle condition is reported" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send break" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled in DOZE state,Disabled in DOZE state" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" if (((per.l(ad:0x30880000+0x84))&0x2010)==0x10) group.long 0x84++0x03 line.long 0x00 "UART3_UCR2,UART3 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "Inactive,Active" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising edge,Falling edge,Any edge,Any edge" bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" textline " " bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" elif (((per.l(ad:0x30880000+0x84))&0x2010)==0x2010) group.long 0x84++0x03 line.long 0x00 "UART3_UCR2,UART3 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising edge,Falling edge,Any edge,Any edge" bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" textline " " bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" elif (((per.l(ad:0x30880000+0x84))&0x2010)==0x2000) group.long 0x84++0x03 line.long 0x00 "UART3_UCR2,UART3 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" textline " " bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" else group.long 0x84++0x03 line.long 0x00 "UART3_UCR2,UART3 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "Inactive,Active" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" textline " " bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" endif textline " " if (((per.l(ad:0x30880000+0xB8)&0x01)==0x00)) if (((per.l(ad:0x30880000+0x80)&0x80)==0x80)) group.long 0x88++0x07 line.long 0x00 "UART3_UCR3,UART3 Control Register 3" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Disables new features of autobaud detection" "No,Yes" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" ",Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level (IrDA mode)" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" line.long 0x04 "UART3_UCR4,UART3 Control Register 4" bitfld.long 0x04 10.--15. " CTSTL ,CTS trigger level (number of characters in the RxFIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 9. " INVR ,Determine RXD input logic level being sampled (IrDA mode)" "Active low,Active high" bitfld.long 0x04 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " IRSC ,IR special case" "Sampling clock,UART reference clock" textline " " bitfld.long 0x04 4. " LPBYP ,Low power bypass disable" "No,Yes" bitfld.long 0x04 3. " TCEN ,TransmitComplete interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " BKEN ,BREAK condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" else group.long 0x88++0x07 line.long 0x00 "UART3_UCR3,UART3 Control Register 3" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Disables new features of autobaud detection" "No,Yes" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" ",Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" line.long 0x04 "UART3_UCR4,UART3 Control Register 4" bitfld.long 0x04 10.--15. " CTSTL ,CTS trigger level (number of characters in the RxFIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x04 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " IRSC ,IR special case" "Sampling clock,UART reference clock" textline " " bitfld.long 0x04 4. " LPBYP ,Low power bypass disable" "No,Yes" bitfld.long 0x04 3. " TCEN ,TransmitComplete interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " BKEN ,BREAK condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif else group.long 0x88++0x07 line.long 0x00 "UART3_UCR3,UART3 Control Register 3" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Disables new features of autobaud detection" "No,Yes" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" ",Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" line.long 0x04 "UART3_UCR4,UART3 Control Register 4" bitfld.long 0x04 10.--15. " CTSTL ,CTS trigger level (number of characters in the RxFIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x04 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " IRSC ,IR special case" "Sampling clock,UART reference clock" textline " " bitfld.long 0x04 4. " LPBYP ,Low power bypass disable" "No,Yes" bitfld.long 0x04 3. " TCEN ,TransmitComplete interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " BKEN ,BREAK condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif group.long 0x90++0x07 line.long 0x00 "UART3_UFCR,UART3 FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32(maximum),?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference frequency divider" "/6,/5,/4,/3,/2,/1,/7,?..." bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" textline " " bitfld.long 0x00 0.--5. " RXTL ,Receiver trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32(maximum),?..." line.long 0x04 "UART3_USR1,UART3 Status Register 1" eventfld.long 0x04 15. " PARITYERR ,Parity error interrupt flag" "No error,Error" rbitfld.long 0x04 14. " RTSS ,RTS_B pin status" "High,Low" rbitfld.long 0x04 13. " TRDY ,Transmitter ready interrupt / DMA flag" "Data not required,Data required" eventfld.long 0x04 12. " RTSD ,RTS_B pin changed state" "Not changed,Changed" textline " " eventfld.long 0x04 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x04 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x04 9. " RRDY ,Receiver ready interrupt / DMA flag" "Not ready,Ready" eventfld.long 0x04 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " rbitfld.long 0x04 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x04 5. " AIRINT ,Asynchronous IR WAKE interrupt flag" "No pulse detected,Pulse detected" eventfld.long 0x04 4. " AWAKE ,Asynchronous WAKE interrupt flag" "No falling edge detected,Falling edge detected" eventfld.long 0x04 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" if (((per.l(ad:0x30880000+0x80)&0x4000)==0x4000)) group.long 0x98++0x03 line.long 0x00 "UART3_USR2,UART3 Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x00 12. " IDLE ,Idle condition detect" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud counter stopped" "Not stopped,Stopped" textline " " eventfld.long 0x00 8. " IRINT ,Serial infrared interrupt flag" "No edge detected,Valid edge detected" eventfld.long 0x00 7. " WAKE ,Start bit is detected" "Not detected,Detected" eventfld.long 0x00 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x00 3. " TXDC ,Transmitter complete" "Incomplete,Complete" textline " " eventfld.long 0x00 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x00 0. " RDR ,Receive data ready" "Not ready,Ready" else group.long 0x98++0x03 line.long 0x00 "UART3_USR2,UART3 Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x00 12. " IDLE ,Idle condition detect" "Not detected,Detected" eventfld.long 0x00 8. " IRINT ,Serial infrared interrupt flag" "No edge detected,Valid edge detected" textline " " eventfld.long 0x00 7. " WAKE ,Start bit detect" "Not detected,Detected" eventfld.long 0x00 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x00 3. " TXDC ,Transmitter complete" "Incomplete,Complete" eventfld.long 0x00 2. " BRCD ,BREAK condition detected" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x00 0. " RDR ,Receive data ready" "Not ready,Ready" endif group.long 0x9C++0x0F line.long 0x00 "UART3_UESC,UART3 Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART escape character" line.long 0x04 "UART3_UTIM,UART3 Escape Timer Register" hexmask.long.word 0x04 0.--11. 1. " TIM ,UART escape timer" line.long 0x08 "UART3_UBIR,UART3 BRM Incremental Register" hexmask.long.word 0x08 0.--15. 1. " INC ,Incremental numerator" line.long 0x0C "UART3_UBMR,UART3 BRM Modulator Register" hexmask.long.word 0x0C 0.--15. 1. " MOD ,Modulator denominator" rgroup.long 0xAC++0x03 line.long 0x00 "UART3_UBRC,UART3 Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,Baud rate count register" group.long 0xB0++0x0B line.long 0x00 "UART3_ONEMS,UART3 One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,One millisecond register" line.long 0x04 "UART3_UTS,UART3 Test Register" bitfld.long 0x04 13. " FRCPERR ,Force parity error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for test" "Disabled,Enabled" bitfld.long 0x04 10. " LOOPIR ,Loop TX and RX for IR test (LOOPIR)" "Disabled,Enabled" bitfld.long 0x04 6. " TXEMPTY ,TxFIFO empty" "Not empty,Empty" textline " " bitfld.long 0x04 5. " RXEMPTY ,RxFIFO empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,TxFIFO full" "Not full,Full" bitfld.long 0x04 3. " RXFULL ,RxFIFO full" "Not full,Full" bitfld.long 0x04 0. " SOFTRST ,Software reset" "No reset,Reset" line.long 0x08 "UART3_UMCR,UART3 RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 0x01 " SLADDR ,RS-485 slave address character" bitfld.long 0x08 3. " SADEN ,RS-485 slave address detected interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" bitfld.long 0x08 1. " SLAM ,RS-485 slave address detect mode selection" "Normal,Automatic" textline " " bitfld.long 0x08 0. " MDEN ,9-bit data or multidrop mode enable" "RS-232||IrDA,RS-485" width 0x0B tree.end tree "UART4" base ad:0x30A60000 width 13. if (((per.l(ad:0x30A60000+0x80)&0x01)==0x01)) if (((per.l(ad:0x30A60000+0xB8)&0x01)==0x00)) rgroup.long 0x00++0x03 line.long 0x00 "UART4_URXD,UART4 Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,Break detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity error flag" "No error,Error" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" else rgroup.long 0x00++0x03 line.long 0x00 "UART4_URXD,UART4 Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,Break detect" "Not detected,Detected" bitfld.long 0x00 10. " NTHB ,Ninth data bit of received 9-bit RS-485 data" "0,1" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" endif wgroup.long 0x40++0x03 line.long 0x00 "UART4_UTXD,UART4 Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data" else hgroup.long 0x00++0x03 hide.long 0x00 "UART4_URXD,UART4 Receiver Register" hgroup.long 0x40++0x03 hide.long 0x00 "UART4_UTXD,UART4 Transmitter Register" endif group.long 0x80++0x03 line.long 0x00 "UART4_UCR1,UART4 Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Number of frames RXD is allowed to be idle before an idle condition is reported" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send break" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled in DOZE state,Disabled in DOZE state" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" if (((per.l(ad:0x30A60000+0x84))&0x2010)==0x10) group.long 0x84++0x03 line.long 0x00 "UART4_UCR2,UART4 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "Inactive,Active" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising edge,Falling edge,Any edge,Any edge" bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" textline " " bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" elif (((per.l(ad:0x30A60000+0x84))&0x2010)==0x2010) group.long 0x84++0x03 line.long 0x00 "UART4_UCR2,UART4 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising edge,Falling edge,Any edge,Any edge" bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" textline " " bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" elif (((per.l(ad:0x30A60000+0x84))&0x2010)==0x2000) group.long 0x84++0x03 line.long 0x00 "UART4_UCR2,UART4 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" textline " " bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" else group.long 0x84++0x03 line.long 0x00 "UART4_UCR2,UART4 Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "By CTS bit,By receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "Inactive,Active" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 8. " PREN ,Parity generator in the transmitter and parity checker in the receiver enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits after a character" "1 stop bit,2 stop bits" textline " " bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" endif textline " " if (((per.l(ad:0x30A60000+0xB8)&0x01)==0x00)) if (((per.l(ad:0x30A60000+0x80)&0x80)==0x80)) group.long 0x88++0x07 line.long 0x00 "UART4_UCR3,UART4 Control Register 3" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Disables new features of autobaud detection" "No,Yes" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" ",Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level (IrDA mode)" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" line.long 0x04 "UART4_UCR4,UART4 Control Register 4" bitfld.long 0x04 10.--15. " CTSTL ,CTS trigger level (number of characters in the RxFIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 9. " INVR ,Determine RXD input logic level being sampled (IrDA mode)" "Active low,Active high" bitfld.long 0x04 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " IRSC ,IR special case" "Sampling clock,UART reference clock" textline " " bitfld.long 0x04 4. " LPBYP ,Low power bypass disable" "No,Yes" bitfld.long 0x04 3. " TCEN ,TransmitComplete interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " BKEN ,BREAK condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" else group.long 0x88++0x07 line.long 0x00 "UART4_UCR3,UART4 Control Register 3" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Disables new features of autobaud detection" "No,Yes" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" ",Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" line.long 0x04 "UART4_UCR4,UART4 Control Register 4" bitfld.long 0x04 10.--15. " CTSTL ,CTS trigger level (number of characters in the RxFIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x04 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " IRSC ,IR special case" "Sampling clock,UART reference clock" textline " " bitfld.long 0x04 4. " LPBYP ,Low power bypass disable" "No,Yes" bitfld.long 0x04 3. " TCEN ,TransmitComplete interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " BKEN ,BREAK condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif else group.long 0x88++0x07 line.long 0x00 "UART4_UCR3,UART4 Control Register 3" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Disables new features of autobaud detection" "No,Yes" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" ",Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" line.long 0x04 "UART4_UCR4,UART4 Control Register 4" bitfld.long 0x04 10.--15. " CTSTL ,CTS trigger level (number of characters in the RxFIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x04 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " IRSC ,IR special case" "Sampling clock,UART reference clock" textline " " bitfld.long 0x04 4. " LPBYP ,Low power bypass disable" "No,Yes" bitfld.long 0x04 3. " TCEN ,TransmitComplete interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " BKEN ,BREAK condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif group.long 0x90++0x07 line.long 0x00 "UART4_UFCR,UART4 FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32(maximum),?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference frequency divider" "/6,/5,/4,/3,/2,/1,/7,?..." bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" textline " " bitfld.long 0x00 0.--5. " RXTL ,Receiver trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32(maximum),?..." line.long 0x04 "UART4_USR1,UART4 Status Register 1" eventfld.long 0x04 15. " PARITYERR ,Parity error interrupt flag" "No error,Error" rbitfld.long 0x04 14. " RTSS ,RTS_B pin status" "High,Low" rbitfld.long 0x04 13. " TRDY ,Transmitter ready interrupt / DMA flag" "Data not required,Data required" eventfld.long 0x04 12. " RTSD ,RTS_B pin changed state" "Not changed,Changed" textline " " eventfld.long 0x04 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x04 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x04 9. " RRDY ,Receiver ready interrupt / DMA flag" "Not ready,Ready" eventfld.long 0x04 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " rbitfld.long 0x04 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x04 5. " AIRINT ,Asynchronous IR WAKE interrupt flag" "No pulse detected,Pulse detected" eventfld.long 0x04 4. " AWAKE ,Asynchronous WAKE interrupt flag" "No falling edge detected,Falling edge detected" eventfld.long 0x04 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" if (((per.l(ad:0x30A60000+0x80)&0x4000)==0x4000)) group.long 0x98++0x03 line.long 0x00 "UART4_USR2,UART4 Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x00 12. " IDLE ,Idle condition detect" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud counter stopped" "Not stopped,Stopped" textline " " eventfld.long 0x00 8. " IRINT ,Serial infrared interrupt flag" "No edge detected,Valid edge detected" eventfld.long 0x00 7. " WAKE ,Start bit is detected" "Not detected,Detected" eventfld.long 0x00 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x00 3. " TXDC ,Transmitter complete" "Incomplete,Complete" textline " " eventfld.long 0x00 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x00 0. " RDR ,Receive data ready" "Not ready,Ready" else group.long 0x98++0x03 line.long 0x00 "UART4_USR2,UART4 Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x00 12. " IDLE ,Idle condition detect" "Not detected,Detected" eventfld.long 0x00 8. " IRINT ,Serial infrared interrupt flag" "No edge detected,Valid edge detected" textline " " eventfld.long 0x00 7. " WAKE ,Start bit detect" "Not detected,Detected" eventfld.long 0x00 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x00 3. " TXDC ,Transmitter complete" "Incomplete,Complete" eventfld.long 0x00 2. " BRCD ,BREAK condition detected" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x00 0. " RDR ,Receive data ready" "Not ready,Ready" endif group.long 0x9C++0x0F line.long 0x00 "UART4_UESC,UART4 Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART escape character" line.long 0x04 "UART4_UTIM,UART4 Escape Timer Register" hexmask.long.word 0x04 0.--11. 1. " TIM ,UART escape timer" line.long 0x08 "UART4_UBIR,UART4 BRM Incremental Register" hexmask.long.word 0x08 0.--15. 1. " INC ,Incremental numerator" line.long 0x0C "UART4_UBMR,UART4 BRM Modulator Register" hexmask.long.word 0x0C 0.--15. 1. " MOD ,Modulator denominator" rgroup.long 0xAC++0x03 line.long 0x00 "UART4_UBRC,UART4 Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,Baud rate count register" group.long 0xB0++0x0B line.long 0x00 "UART4_ONEMS,UART4 One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,One millisecond register" line.long 0x04 "UART4_UTS,UART4 Test Register" bitfld.long 0x04 13. " FRCPERR ,Force parity error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for test" "Disabled,Enabled" bitfld.long 0x04 10. " LOOPIR ,Loop TX and RX for IR test (LOOPIR)" "Disabled,Enabled" bitfld.long 0x04 6. " TXEMPTY ,TxFIFO empty" "Not empty,Empty" textline " " bitfld.long 0x04 5. " RXEMPTY ,RxFIFO empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,TxFIFO full" "Not full,Full" bitfld.long 0x04 3. " RXFULL ,RxFIFO full" "Not full,Full" bitfld.long 0x04 0. " SOFTRST ,Software reset" "No reset,Reset" line.long 0x08 "UART4_UMCR,UART4 RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 0x01 " SLADDR ,RS-485 slave address character" bitfld.long 0x08 3. " SADEN ,RS-485 slave address detected interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" bitfld.long 0x08 1. " SLAM ,RS-485 slave address detect mode selection" "Normal,Automatic" textline " " bitfld.long 0x08 0. " MDEN ,9-bit data or multidrop mode enable" "RS-232||IrDA,RS-485" width 0x0B tree.end tree.end tree.end textline " "